From dbe5c9f5e1c45dd9d23b45abcb280cd594a01a8e Mon Sep 17 00:00:00 2001 From: Paciente8159 Date: Fri, 8 Jul 2022 20:47:43 +0100 Subject: [PATCH 1/6] NXP LPC176x core integration - NXP LPC176x core integration (EEPROM and Analog not implemented yet) --- CHANGELOG.md | 13 + platformio.ini | 34 +- uCNC/src/cnc_build.h | 4 +- uCNC/src/hal/boards/avr/boardmap_rambo14.h | 10 +- uCNC/src/hal/boards/boarddefs.h | 5 + uCNC/src/hal/boards/boards.h | 1 + uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h | 188 + uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp | 11 + uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c | 1278 +++++++ uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h | 3297 +++++++++++++++++ uCNC/src/hal/mcus/mcudefs.h | 7 + uCNC/src/hal/mcus/mcus.h | 1 + uCNC/src/tinyusb/src/class/cdc/cdc.h | 728 ++-- uCNC/src/tinyusb/src/class/cdc/cdc_device.c | 672 ++-- uCNC/src/tinyusb/src/class/cdc/cdc_device.h | 382 +- uCNC/src/tinyusb/src/common/tusb_common.h | 308 +- uCNC/src/tinyusb/src/common/tusb_compiler.h | 331 +- uCNC/src/tinyusb/src/common/tusb_error.h | 42 +- uCNC/src/tinyusb/src/common/tusb_fifo.c | 1251 ++++--- uCNC/src/tinyusb/src/common/tusb_fifo.h | 168 +- uCNC/src/tinyusb/src/common/tusb_timeout.h | 16 +- uCNC/src/tinyusb/src/common/tusb_types.h | 1005 +++-- uCNC/src/tinyusb/src/common/tusb_verify.h | 114 +- uCNC/src/tinyusb/src/device/dcd.h | 238 +- uCNC/src/tinyusb/src/device/dcd_attr.h | 29 +- uCNC/src/tinyusb/src/device/usbd.c | 2004 +++++----- uCNC/src/tinyusb/src/device/usbd.h | 927 +++-- uCNC/src/tinyusb/src/device/usbd_control.c | 236 +- uCNC/src/tinyusb/src/device/usbd_pvt.h | 104 +- uCNC/src/tinyusb/src/osal/osal.h | 52 +- uCNC/src/tinyusb/src/osal/osal_freertos.h | 239 +- uCNC/src/tinyusb/src/osal/osal_mynewt.h | 259 +- uCNC/src/tinyusb/src/osal/osal_none.h | 280 +- uCNC/src/tinyusb/src/osal/osal_pico.h | 268 +- uCNC/src/tinyusb/src/osal/osal_rtthread.h | 178 +- uCNC/src/tinyusb/src/osal/osal_rtx4.h | 170 + .../portable/espressif/esp32sx/dcd_esp32sx.c | 1434 +++---- .../src/portable/microchip/samd/dcd_samd.c | 558 +-- .../src/portable/microchip/samg/dcd_samg.c | 500 --- .../microchip/samx7x/common_usb_regs.h | 2072 ----------- .../portable/microchip/samx7x/dcd_samx7x.c | 794 ---- .../src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 599 +++ .../src/portable/nxp/lpc17_40/dcd_lpc17_40.h | 161 + .../portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 1152 +++--- .../st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h | 555 +-- .../src/portable/st/synopsys/dcd_synopsys.c | 1930 +++++----- .../portable/st/synopsys/synopsys_common.h | 2613 ++++++------- .../src/portable/template/dcd_template.c | 52 +- uCNC/src/tinyusb/src/tusb.c | 299 +- uCNC/src/tinyusb/src/tusb.h | 28 +- uCNC/src/tinyusb/src/tusb_option.h | 261 +- uCNC/src/tinyusb/tusb_config.h | 8 +- uCNC/src/tinyusb/tusb_descriptors.c | 140 +- uCNC/uCNC.ino | 15 +- 54 files changed, 15262 insertions(+), 12759 deletions(-) create mode 100644 uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h create mode 100644 uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp create mode 100644 uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c create mode 100644 uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h create mode 100644 uCNC/src/tinyusb/src/osal/osal_rtx4.h delete mode 100644 uCNC/src/tinyusb/src/portable/microchip/samg/dcd_samg.c delete mode 100644 uCNC/src/tinyusb/src/portable/microchip/samx7x/common_usb_regs.h delete mode 100644 uCNC/src/tinyusb/src/portable/microchip/samx7x/dcd_samx7x.c create mode 100644 uCNC/src/tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.c create mode 100644 uCNC/src/tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.h diff --git a/CHANGELOG.md b/CHANGELOG.md index 5a93799c9..2b6d92d77 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,19 @@ # Changelog +## [1.5.beta] - Unreleased + +### Added + +- added support for NXP LPC176x core (lacks EEPROM and analog) +- updated tinyUSB to version 0.13.0 + +### Changed + + +### Fixed + + ## [1.4.7] - Unreleased ### Added diff --git a/platformio.ini b/platformio.ini index 93a073d8b..2fda2c419 100644 --- a/platformio.ini +++ b/platformio.ini @@ -12,79 +12,93 @@ include_dir=uCNC src_dir=uCNC +[common_Arduino] +monitor_speed = 115200 +framework = arduino + [env:uno] +extends = common_Arduino platform = atmelavr board = uno -framework = arduino build_src_filter = +<*>- build_flags = -D BOARD=BOARD_UNO -ffunction-sections -fdata-sections -mcall-prologues -mrelax -flto -fno-fat-lto-objects -fno-tree-scev-cprop -Wl,--gc-sections -Wl,--relax extra_scripts = avr_compiler.py [env:x_controller] +extends = common_Arduino platform = atmelavr board = uno -framework = arduino build_src_filter = +<*>- build_flags = -D BOARD=BOARD_X_CONTROLLER -ffunction-sections -fdata-sections -mcall-prologues -mrelax -flto -fno-fat-lto-objects -fno-tree-scev-cprop -Wl,--gc-sections -Wl,--relax extra_scripts = avr_compiler.py [env:mks_dlc] +extends = common_Arduino platform = atmelavr board = uno board_build.f_cpu = 20000000UL -framework = arduino build_src_filter = +<*>- build_flags = -D BOARD=BOARD_MKS_DLC -ffunction-sections -fdata-sections -mcall-prologues -mrelax -flto -fno-fat-lto-objects -fno-tree-scev-cprop -Wl,--gc-sections -Wl,--relax extra_scripts = avr_compiler.py [env:ramps14] +extends = common_Arduino platform = atmelavr board = megaatmega2560 -framework = arduino build_src_filter = +<*>- build_flags = -D BOARD=BOARD_RAMPS14 -ffunction-sections -fdata-sections -mcall-prologues -mrelax -flto -fno-fat-lto-objects -fno-tree-scev-cprop -Wl,--gc-sections -Wl,--relax extra_scripts = avr_compiler.py [env:ramps14mirror] +extends = common_Arduino platform = atmelavr board = megaatmega2560 -framework = arduino build_src_filter = +<*>- build_flags = -D BOARD=BOARD_RAMPS14_MIRROR -ffunction-sections -fdata-sections -mcall-prologues -mrelax -flto -fno-fat-lto-objects -fno-tree-scev-cprop -Wl,--gc-sections -Wl,--relax extra_scripts = avr_compiler.py [env:mks_gen_l_v1] +extends = common_Arduino platform = atmelavr board = megaatmega2560 -framework = arduino build_src_filter = +<*>- build_flags = -D BOARD=BOARD_MKS_GEN_L_V1 -ffunction-sections -fdata-sections -mcall-prologues -mrelax -flto -fno-fat-lto-objects -fno-tree-scev-cprop -Wl,--gc-sections -Wl,--relax extra_scripts = avr_compiler.py [env:rambo] +extends = common_Arduino platform = atmelavr board = megaatmega2560 -framework = arduino build_src_filter = +<*>- build_flags = -D BOARD=BOARD_RAMBO14 -ffunction-sections -fdata-sections -mcall-prologues -mrelax -flto -fno-fat-lto-objects -fno-tree-scev-cprop -Wl,--gc-sections -Wl,--relax extra_scripts = avr_compiler.py [env:zeroUSB] +extends = common_Arduino platform = atmelsam board = zeroUSB -framework = arduino build_flags = -D BOARD=BOARD_MZERO -D INTERFACE=1 -fdata-sections -ffunction-sections -nostdlib -fno-exceptions -Wl,--gc-sections [env:bluepill_f103c8] +extends = common_Arduino platform = ststm32 board = bluepill_f103c8 -framework = arduino build_flags = -D BOARD=BOARD_BLUEPILL -D INTERFACE=1 -D HAL_TIM_MODULE_DISABLED -D HAL_EXTI_MODULE_DISABLED -fdata-sections -ffunction-sections -Wl,--gc-sections ;uncomment if it's a bluepill clone ;upload_flags = -c set CPUTAPID 0x2ba01477 [env:blackpill_f401cc] +extends = common_Arduino platform = ststm32 board = blackpill_f401cc -framework = arduino build_flags = -D BOARD=BOARD_BLACKPILL -D INTERFACE=1 -D HAL_TIM_MODULE_DISABLED -D HAL_EXTI_MODULE_DISABLED -fdata-sections -ffunction-sections -Wl,--gc-sections + +[env:re_arm] +extends = common_Arduino +platform = https://github.com/p3p/pio-nxplpc-arduino-lpc176x/archive/0.1.3.zip +platform_packages = p3p/framework-arduino-lpc176x +;Paciente8159/framework-arduino-lpc176x @ https://github.com/Paciente8159/pio-framework-arduino-lpc176x/archive/0.2.10.zip +board = nxp_lpc1768 +lib_ldf_mode = off +lib_compat_mode = strict +build_flags = -D BOARD=BOARD_RE_ARM -D INTERFACE=1 -D NXP_LPC17xx -fdata-sections -ffunction-sections -Wl,--gc-sections diff --git a/uCNC/src/cnc_build.h b/uCNC/src/cnc_build.h index ff16f0bf1..918c705ec 100644 --- a/uCNC/src/cnc_build.h +++ b/uCNC/src/cnc_build.h @@ -24,8 +24,8 @@ extern "C" { #endif -#define CNC_MAJOR_MINOR_VERSION "1.4" -#define CNC_PATCH_VERSION ".6" +#define CNC_MAJOR_MINOR_VERSION "1.5" +#define CNC_PATCH_VERSION ".beta" #define CNC_VERSION CNC_MAJOR_MINOR_VERSION CNC_PATCH_VERSION diff --git a/uCNC/src/hal/boards/avr/boardmap_rambo14.h b/uCNC/src/hal/boards/avr/boardmap_rambo14.h index 8a88a82ed..1cca563f2 100644 --- a/uCNC/src/hal/boards/avr/boardmap_rambo14.h +++ b/uCNC/src/hal/boards/avr/boardmap_rambo14.h @@ -125,6 +125,9 @@ extern "C" #define DOUT31_BIT 7 #define DOUT31_PORT B +#ifndef STEPPER0_HAS_MSTEP +#define STEPPER0_HAS_MSTEP +#endif // STEP0 MICROSTEP #define DOUT23_BIT 1 #define DOUT23_PORT G @@ -156,6 +159,9 @@ extern "C" #define DOUT19_PORT K // stepper current digital potenciometer +#ifndef STEPPER_CURR_DIGIPOT +#define STEPPER_CURR_DIGIPOT +#endif #define DOUT12_BIT 7 #define DOUT12_PORT D #define DOUT13_BIT 2 @@ -165,8 +171,10 @@ extern "C" #define DIN13_BIT 3 #define DIN13_PORT B - // specific rambo settings +// specific rambo settings +#ifndef STEPPER_CURR_DIGIPOT #define STEPPER_CURR_DIGIPOT +#endif #define STEPPER0_HAS_MSTEP #define STEPPER1_HAS_MSTEP #define STEPPER2_HAS_MSTEP diff --git a/uCNC/src/hal/boards/boarddefs.h b/uCNC/src/hal/boards/boarddefs.h index dfe5aa203..f444b4903 100644 --- a/uCNC/src/hal/boards/boarddefs.h +++ b/uCNC/src/hal/boards/boarddefs.h @@ -93,6 +93,11 @@ extern "C" #include "samd21/boardmap_zero.h" #endif +#if (BOARD == BOARD_RE_ARM) +#define MCU MCU_LPC176X +#include "lpc176x/boardmap_re_arm.h" +#endif + #if (BOARD == BOARD_VIRTUAL) #ifndef __linux__ #define MCU MCU_VIRTUAL_WIN diff --git a/uCNC/src/hal/boards/boards.h b/uCNC/src/hal/boards/boards.h index 4c340c684..883e654e0 100644 --- a/uCNC/src/hal/boards/boards.h +++ b/uCNC/src/hal/boards/boards.h @@ -34,6 +34,7 @@ extern "C" #define BOARD_BLACKPILL 11 #define BOARD_MZERO 20 #define BOARD_ZERO 21 +#define BOARD_RE_ARM 30 #define BOARD_VIRTUAL 99 // special purpose board diff --git a/uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h b/uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h new file mode 100644 index 000000000..38f691465 --- /dev/null +++ b/uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h @@ -0,0 +1,188 @@ +/* + Name: boardmap_re_arm.h + Description: Contains all MCU and PIN definitions for Re-Arm Panucatt to run µCNC. + + Copyright: Copyright (c) João Martins + Author: João Martins + Date: 17/06/2022 + + µCNC is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. Please see + + µCNC is distributed WITHOUT ANY WARRANTY; + Also without the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU General Public License for more details. +*/ + +#ifndef BOARDMAP_RE_ARM_H +#define BOARDMAP_RE_ARM_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifndef BOARD_NAME +#define BOARD_NAME "RAMPS 1.4 RE-ARM" +#endif + +// Setup step pins +#define STEP0_BIT 1 // assigns STEP0 pin +#define STEP0_PORT 2 // assigns STEP0 port +#define STEP1_BIT 2 // assigns STEP1 pin +#define STEP1_PORT 2 // assigns STEP1 port +#define STEP2_BIT 3 // assigns STEP2 pin +#define STEP2_PORT 2 // assigns STEP2 port +#define STEP3_BIT 0 // assigns STEP3 pin +#define STEP3_PORT 2 // assigns STEP3 port +#define STEP4_BIT 8 // assigns STEP4 pin +#define STEP4_PORT 2 // assigns STEP4 port + +// Setup dir pins +#define DIR0_BIT 11 // assigns DIR0 pin +#define DIR0_PORT 0 // assigns DIR0 port +#define DIR1_BIT 20 // assigns DIR1 pin +#define DIR1_PORT 0 // assigns DIR1 port +#define DIR2_BIT 22 // assigns DIR2 pin +#define DIR2_PORT 0 // assigns DIR2 port +#define DIR3_BIT 5 // assigns DIR2 pin +#define DIR3_PORT 0 // assigns DIR2 port +#define DIR4_BIT 13 // assigns DIR2 pin +#define DIR4_PORT 2 // assigns DIR2 port + + // Setup limit pins + +#define LIMIT_X_BIT 24 // assigns LIMIT_X pin +#define LIMIT_X_PORT 1 // assigns LIMIT_X port +// #define LIMIT_X_ISR -6 // assigns LIMIT_X ISR +#define LIMIT_X2_BIT 25 // assigns LIMIT_X2 pin +#define LIMIT_X2_PORT 1 // assigns LIMIT_X2 port +// #define LIMIT_X2_ISR -5 // assigns LIMIT_X2 ISR +#define LIMIT_Y_BIT 26 // assigns LIMIT_Y pin +#define LIMIT_Y_PORT 1 // assigns LIMIT_Y port +// #define LIMIT_Y_ISR 1 // assigns LIMIT_Y ISR +#define LIMIT_Y2_BIT 27 // assigns LIMIT_Y2 pin +#define LIMIT_Y2_PORT 1 // assigns LIMIT_Y2 port +// #define LIMIT_Y2_ISR 1 // assigns LIMIT_Y2 ISR +#define LIMIT_Z_BIT 29 // assigns LIMIT_Z pin +#define LIMIT_Z_PORT 1 // assigns LIMIT_Z port +// #define LIMIT_Z_ISR -4 // assigns LIMIT_Z ISR + +// Setup probe pin +#define PROBE_BIT 28 +#define PROBE_PORT 1 +// #define PROBE_ISR -3 + +// Setup com pins +#if (INTERFACE == INTERFACE_UART) +#define RX_BIT 3 +#define TX_BIT 2 +#define RX_PORT 0 +#define TX_PORT 0 +// only uncomment this if other port other then 0 is used +//#define COM_NUMBER 0 +#elif (INTERFACE == INTERFACE_USB) +// PIN A10 is also used because of the USB ID (USB OTG) +#define USB_DM_BIT 30 +#define USB_DM_PORT 0 +#define USB_DP_BIT 29 +#define USB_DP_PORT 0 +#endif + +// // Setup PWM +#define PWM0_BIT 5 // assigns PWM0 pin +#define PWM0_PORT 2 // assigns PWM0 pin +#define PWM0_CHANNEL 6 + +#define PWM1_BIT 4 // assigns PWM1 pin +#define PWM1_PORT 2 // assigns PWM1 pin +#define PWM1_CHANNEL 5 + +// Setup generic IO Pins +// Functionalities are set in config.h file + +// // blink led +#define DOUT31_BIT 28 +#define DOUT31_PORT 4 + +// Stepper enable pin. For Grbl on Uno board a single pin is used +#define STEP0_EN_BIT 10 +#define STEP0_EN_PORT 0 +#define STEP1_EN_BIT 19 +#define STEP1_EN_PORT 0 +#define STEP2_EN_BIT 21 +#define STEP2_EN_PORT 0 +#define STEP3_EN_BIT 4 +#define STEP3_EN_PORT 0 +#define STEP4_EN_BIT 29 +#define STEP4_EN_PORT 4 + + // Setup the Step Timer used has the heartbeat for µCNC + // Timer 1 is used by default + //#define ITP_TIMER 0 + // Setup the RTC Timer used by µCNC to provide an (mostly) accurate time base for all time dependent functions + // Timer 0 is set by default + //#define RTC_TIMER 1 + + // // TMC0 UART + // #define DOUT23_BIT 1 + // #define DOUT23_PORT G + // #define DIN23_BIT 1 + // #define DIN23_PORT K + // #define DIN23_PULLUP + + // // TMC1 UART + // #define DOUT24_BIT 5 + // #define DOUT24_PORT F + // #define DIN24_BIT 2 + // #define DIN24_PORT K + // #define DIN24_PULLUP + + // // TMC2 UART + // #define DOUT25_BIT 7 + // #define DOUT25_PORT L + // #define DIN25_BIT 3 + // #define DIN25_PORT K + // #define DIN25_PULLUP + + // // TMC3 UART + // #define DOUT26_BIT 5 + // #define DOUT26_PORT L + // #define DIN26_BIT 4 + // #define DIN26_PORT K + // #define DIN26_PULLUP + + // // // TMC4 UART + // // #define DOUT27_BIT 3 + // // #define DOUT27_PORT F + // // #define DIN27_BIT 4 + // // #define DIN27_PORT F + // // #define DIN27_PULLUP + + // #define SERVO0_BIT 5 + // #define SERVO0_PORT G + // #define SERVO1_BIT 3 + // #define SERVO1_PORT E + // #define SERVO2_BIT 3 + // #define SERVO2_PORT H + // #define SERVO3_BIT 5 + // #define SERVO3_PORT B + + // // SERVO3 pin supports ISR and can be used as an encoder/counter + // // #define DIN0_BIT 5 + // // #define DIN0_PORT B + // // #define DIN0_ISR 0 + + // // software I2C + // #define DIN20_BIT 1 + // #define DIN20_PORT D + // #define DIN21_BIT 0 + // #define DIN21_PORT D + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp b/uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp new file mode 100644 index 000000000..c271a2dad --- /dev/null +++ b/uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp @@ -0,0 +1,11 @@ +#ifdef ARDUINO_ARCH_LPC176X +#include + +extern "C" +{ + void lpc176x_delay_us(uint32_t delay) + { + LPC176x::delay_us(delay); + } +} +#endif \ No newline at end of file diff --git a/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c new file mode 100644 index 000000000..43eb25b35 --- /dev/null +++ b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c @@ -0,0 +1,1278 @@ +/* + Name: mcu_lpc176x.c + Description: Contains all the function declarations necessary to interact with the MCU. + This provides an intenterface between the µCNC and the MCU unit used to power the µCNC. + + Copyright: Copyright (c) João Martins + Author: João Martins + Date: 07-06-2022 + + µCNC is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. Please see + + µCNC is distributed WITHOUT ANY WARRANTY; + Also without the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU General Public License for more details. +*/ + +#include "../../../cnc.h" + +#if (MCU == MCU_LPC176X) +#include "core_cm3.h" +#include "mcumap_lpc176x.h" +#include +#include +#include +#include "lpc_types.h" +#include "lpc17xx_pinsel.h" +#include "lpc17xx_uart.h" +#include "lpc17xx_clkpwr.h" +#include "lpc17xx_timer.h" +#include "lpc17xx_systick.h" +#include "lpc17xx_pwm.h" +#include "system_LPC17xx.h" + +#if (INTERFACE == INTERFACE_USB) +#ifdef TX +#undef TX +#endif +#ifdef RX +#undef RX +#endif +#include "../../../tinyusb/tusb_config.h" +#include "../../../tinyusb/src/tusb.h" +#endif + +/** + * The internal clock counter + * Increments every millisecond + * Can count up to almost 50 days + **/ +static volatile uint32_t mcu_runtime_ms; +volatile bool lpc_global_isr_enabled; + +#define mcu_config_input_isr(diopin) \ + { \ + SETBIT(LPC_GPIOINT->__indirect__(diopin, RISEREG), __indirect__(diopin, BIT)); \ + SETBIT(LPC_GPIOINT->__indirect__(diopin, FALLREG), __indirect__(diopin, BIT)); \ + NVIC_SetPriority(EINT3_IRQn, 5); \ + NVIC_ClearPendingIRQ(EINT3_IRQn); \ + NVIC_EnableIRQ(EINT3_IRQn); \ + } + +#define mcu_config_pullup(diopin) \ + { \ + LPC_PINCON->__helper__(PINMODE, __indirect__(diopin, PINCON), ) &= ~(3 << (0x1F & (__indirect__(diopin, BIT) << 1))); \ + } + +/* +// #define mcu_config_pwm(diopin) \ +// { \ +// LPC_PINCON->__helper__(PINSEL, __indirect__(diopin, PINCON), ) &= ~(3 << (0x1F & (__indirect__(diopin, BIT) << 1))); \ +// LPC_PINCON->__helper__(PINSEL, __indirect__(diopin, PINCON), ) |= (__indirect__(diopin, PINSEL) << (0x1F & (__indirect__(diopin, BIT) << 1))); \ +// LPC_PWM1->TCR = (1 << 0) | (1 << 2); \ +// LPC_PWM1->MCR = (1 << 1); \ +// LPC_PWM1->MR0 = 255; \ +// LPC_PWM1->LER = (1 << 0) | PWM_LER; \ +// LPC_PWM1->PCR = PWM_ENA & 0x0FE0; \ +// } +*/ + +#define mcu_config_pwm(diopin) \ + { \ + PINSEL_CFG_Type pwm = {__indirect__(diopin, PORT), __indirect__(diopin, BIT), __indirect__(diopin, FUNC), PINSEL_PINMODE_NORMAL}; \ + PINSEL_ConfigPin(&pwm); \ + PWM_TIMERCFG_Type pwmtmr; \ + PWM_ConfigStructInit(PWM_MODE_TIMER, &pwmtmr); \ + pwmtmr.PrescaleValue = 4; \ + PWM_Init(LPC_PWM1, PWM_MODE_TIMER, &pwmtmr); \ + PWM_MATCHCFG_Type pwmconf = {__indirect__(diopin, CHANNEL), DISABLE, DISABLE, ENABLE}; \ + PWM_ConfigMatch(LPC_PWM1, &pwmconf); \ + PWM_ResetCounter(LPC_PWM1); \ + LPC_PWM1->MR0 = 255; \ + mcu_set_pwm(diopin, 0); \ + PWM_Cmd(LPC_PWM1, ENABLE); \ + } + +#define CLOCK_SETUP 1 +#define SCS_Val 0x00000020 +#define CLKSRCSEL_Val 0x00000001 +#define PLL0_SETUP 1 +#define PLL0CFG_Val 0x00050063 +#define PLL1_SETUP 1 +#define PLL1CFG_Val 0x00000023 +#define CCLKCFG_Val 0x00000003 +#define USBCLKCFG_Val 0x00000000 +#define PCLKSEL0_Val 0x00000000 +#define PCLKSEL1_Val 0x00000000 +#define PCONP_Val 0x042887DE +#define CLKOUTCFG_Val 0x00000000 + +void MCU_RTC_ISR(void) +{ + mcu_disable_global_isr(); + uint32_t millis = mcu_runtime_ms; + millis++; + mcu_runtime_ms = millis; + mcu_rtc_cb(millis); + TIM_ClearIntPending(RTC_TIMER_REG, RTC_INT_FLAG); + mcu_enable_global_isr(); +} + +void MCU_ITP_ISR(void) +{ + mcu_disable_global_isr(); + + static bool resetstep = false; + if (TIM_GetIntStatus(ITP_TIMER_REG, ITP_INT_FLAG)) + { + if (!resetstep) + mcu_step_cb(); + else + mcu_step_reset_cb(); + resetstep = !resetstep; + } + TIM_ClearIntPending(ITP_TIMER_REG, ITP_INT_FLAG); + mcu_enable_global_isr(); +} + +void mcu_clocks_init(void) +{ + // disable pullups + LPC_PINCON->PINMODE0 = 0xAAAAAAAA; + LPC_PINCON->PINMODE1 = 0xAAAAAAAA; + LPC_PINCON->PINMODE2 = 0xAAAAAAAA; + LPC_PINCON->PINMODE3 = 0xAAAAAAAA; + LPC_PINCON->PINMODE4 = 0xAAAAAAAA; + LPC_PINCON->PINMODE5 = 0xAAAAAAAA; + LPC_PINCON->PINMODE6 = 0xAAAAAAAA; + LPC_PINCON->PINMODE7 = 0xAAAAAAAA; + LPC_PINCON->PINMODE8 = 0xAAAAAAAA; + LPC_PINCON->PINMODE9 = 0xAAAAAAAA; +} + +/** + * The isr functions + * The respective IRQHandler will execute these functions +// **/ +#if (INTERFACE == INTERFACE_USART) +void MCU_COM_ISR(void) +{ + mcu_disable_global_isr(); + uint32_t irqstatus = UART_GetIntId(COM_USART); + irqstatus &= UART_IIR_INTID_MASK; + + // Receive Line Status + if (irqstatus == UART_IIR_INTID_RLS) + { + uint32_t linestatus = UART_GetLineStatus(COM_USART); + + // Receive Line Status + if (linestatus & (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_RXFE | UART_LSR_BI)) + { + // There are errors or break interrupt + // Read LSR will clear the interrupt + uint8_t dummy = (COM_INREG & UART_RBR_MASKBIT); // Dummy read on RX to clear interrupt, then bail out + return; + } + } + +#ifndef ENABLE_SYNC_RX + if (irqstatus == UART_IIR_INTID_RDA) + { + unsigned char c = (unsigned char)(COM_INREG & UART_RBR_MASKBIT); + mcu_com_rx_cb(c); + } +#endif + +#ifndef ENABLE_SYNC_TX + if (irqstatus == UART_IIR_INTID_THRE) + { + UART_IntConfig(COM_USART, UART_INTCFG_THRE, DISABLE); + mcu_com_tx_cb(); + } +#endif + mcu_enable_global_isr(); +} +#elif (INTERFACE == INTERFACE_USB) +void USB_IRQHandler(void) +{ + mcu_disable_global_isr(); + tud_int_handler(0); + mcu_enable_global_isr(); +} +#endif + +void mcu_usart_init(void) +{ + // LPC_SC->PCONP &= ~((1 << 3) | (1 << 4) | (1 << 24) | (1 << 25) | (1 << 31)); +#if (INTERFACE == INTERFACE_UART) + PINSEL_CFG_Type tx = {TX_PORT, TX_BIT, TX_ALT_FUNC, PINSEL_PINMODE_PULLUP, PINSEL_PINMODE_NORMAL}; + PINSEL_ConfigPin(&tx); + PINSEL_CFG_Type rx = {RX_PORT, RX_BIT, RX_ALT_FUNC, PINSEL_PINMODE_PULLUP, PINSEL_PINMODE_NORMAL}; + PINSEL_ConfigPin(&rx); + + CLKPWR_SetPCLKDiv(COM_PCLK, CLKPWR_PCLKSEL_CCLK_DIV_1); + + UART_CFG_Type conf = {BAUDRATE, UART_PARITY_NONE, UART_DATABIT_8, UART_STOPBIT_1}; + UART_Init(COM_USART, &conf); + + // Enable UART Transmit + UART_TxCmd(COM_USART, ENABLE); + + // Configure Interrupts + UART_IntConfig(COM_USART, UART_INTCFG_RLS, ENABLE); +#ifndef ENABLE_SYNC_RX + UART_IntConfig(COM_USART, UART_INTCFG_RBR, ENABLE); +#endif + +#if (!defined(ENABLE_SYNC_TX) || !defined(ENABLE_SYNC_RX)) + NVIC_SetPriority(COM_IRQ, 3); + NVIC_ClearPendingIRQ(COM_IRQ); + NVIC_EnableIRQ(COM_IRQ); +#endif + +#elif (INTERFACE == INTERFACE_USB) + // // configure USB as Virtual COM port + LPC_PINCON->PINSEL1 &= ~((3 << 26) | (3 << 28)); /* P0.29 D+, P0.30 D- */ + LPC_PINCON->PINSEL1 |= ((1 << 26) | (1 << 28)); /* PINSEL1 26.27, 28.29 = 01 */ + + // todo: VBUS not used by smoothieboard (though spec requires it for self powered devices), pin used for beeper + // todo: Goodlink used for servo4? + // LPC_PINCON->PINSEL3 &= ~((3<< 4)|(3<<28)); /* P1.18 GoodLink, P1.30 VBUS */ + // LPC_PINCON->PINSEL3 |= ((1<< 4)|(2<<28)); /* PINSEL3 4.5 = 01, 28.29 = 10 */ + + LPC_PINCON->PINSEL4 &= ~((3 << 18)); /* P2.9 SoftConnect */ + LPC_PINCON->PINSEL4 |= ((1 << 18)); /* PINSEL4 18.19 = 01 */ + + LPC_SC->PCONP |= (1UL << 31); /* USB PCLK -> enable USB Per. */ + + LPC_USB->USBClkCtrl = 0x1A; /* Dev, PortSel, AHB clock enable */ + while ((LPC_USB->USBClkSt & 0x1A) != 0x1A) + ; + + NVIC_SetPriority(USB_IRQn, 10); + NVIC_ClearPendingIRQ(USB_IRQn); + NVIC_EnableIRQ(USB_IRQn); + + tusb_init(); +#endif +} + +void mcu_rtc_init() +{ + // SysTick->CTRL = 0; + // SysTick->LOAD = ((F_CPU / 1000) - 1); + // SysTick->VAL = 0; + // NVIC_SetPriority(SysTick_IRQn, 10); + // SysTick->CTRL = 3; + + // SYSTICK_InternalInit(1); + // SYSTICK_ClearCounterFlag(); + // NVIC_SetPriority(SysTick_IRQn, 10); + // SYSTICK_IntCmd(ENABLE); + TIM_Cmd(RTC_TIMER_REG, DISABLE); + TIM_TIMERCFG_Type tmrconfig; + TIM_ConfigStructInit(TIM_TIMER_MODE, &tmrconfig); + TIM_Init(RTC_TIMER_REG, TIM_TIMER_MODE, &tmrconfig); + TIM_MATCHCFG_Type tmrmatch; + tmrmatch.MatchChannel = RTC_TIMER; + tmrmatch.IntOnMatch = ENABLE; + tmrmatch.StopOnMatch = DISABLE; + tmrmatch.ResetOnMatch = ENABLE; + tmrmatch.MatchValue = 1000; + TIM_ConfigMatch(RTC_TIMER_REG, &tmrmatch); + NVIC_SetPriority(RTC_TIMER_IRQ, 1); + NVIC_ClearPendingIRQ(RTC_TIMER_IRQ); + NVIC_EnableIRQ(RTC_TIMER_IRQ); + + TIM_Cmd(RTC_TIMER_REG, ENABLE); +} + +/*IO functions*/ + +/** + * initializes the mcu + * this function needs to: + * - configure all IO pins (digital IO, PWM, Analog, etc...) + * - configure all interrupts + * - configure uart or usb + * - start the internal RTC + * */ +void mcu_init(void) +{ + mcu_clocks_init(); + + lpc_global_isr_enabled = false; + +#if STEP0 >= 0 + mcu_config_output(STEP0); +#endif +#if STEP1 >= 0 + mcu_config_output(STEP1); +#endif +#if STEP2 >= 0 + mcu_config_output(STEP2); +#endif +#if STEP3 >= 0 + mcu_config_output(STEP3); +#endif +#if STEP4 >= 0 + mcu_config_output(STEP4); +#endif +#if STEP5 >= 0 + mcu_config_output(STEP5); +#endif +#if STEP6 >= 0 + mcu_config_output(STEP6); +#endif +#if STEP7 >= 0 + mcu_config_output(STEP7); +#endif +#if DIR0 >= 0 + mcu_config_output(DIR0); +#endif +#if DIR1 >= 0 + mcu_config_output(DIR1); +#endif +#if DIR2 >= 0 + mcu_config_output(DIR2); +#endif +#if DIR3 >= 0 + mcu_config_output(DIR3); +#endif +#if DIR4 >= 0 + mcu_config_output(DIR4); +#endif +#if DIR5 >= 0 + mcu_config_output(DIR5); +#endif +#if DIR6 >= 0 + mcu_config_output(DIR6); +#endif +#if DIR7 >= 0 + mcu_config_output(DIR7); +#endif +#if STEP0_EN >= 0 + mcu_config_output(STEP0_EN); +#endif +#if STEP1_EN >= 0 + mcu_config_output(STEP1_EN); +#endif +#if STEP2_EN >= 0 + mcu_config_output(STEP2_EN); +#endif +#if STEP3_EN >= 0 + mcu_config_output(STEP3_EN); +#endif +#if STEP4_EN >= 0 + mcu_config_output(STEP4_EN); +#endif +#if STEP5_EN >= 0 + mcu_config_output(STEP5_EN); +#endif +#if STEP6_EN >= 0 + mcu_config_output(STEP6_EN); +#endif +#if STEP7_EN >= 0 + mcu_config_output(STEP7_EN); +#endif +#if PWM0 >= 0 + mcu_config_pwm(PWM0); +#endif +#if PWM1 >= 0 + mcu_config_pwm(PWM1); +#endif +#if PWM2 >= 0 + mcu_config_pwm(PWM2); +#endif +#if PWM3 >= 0 + mcu_config_pwm(PWM3); +#endif +#if PWM4 >= 0 + mcu_config_pwm(PWM4); +#endif +#if PWM5 >= 0 + mcu_config_pwm(PWM5); +#endif +#if PWM6 >= 0 + mcu_config_pwm(PWM6); +#endif +#if PWM7 >= 0 + mcu_config_pwm(PWM7); +#endif +#if PWM8 >= 0 + mcu_config_pwm(PWM8); +#endif +#if PWM9 >= 0 + mcu_config_pwm(PWM9); +#endif +#if PWM10 >= 0 + mcu_config_pwm(PWM10); +#endif +#if PWM11 >= 0 + mcu_config_pwm(PWM11); +#endif +#if PWM12 >= 0 + mcu_config_pwm(PWM12); +#endif +#if PWM13 >= 0 + mcu_config_pwm(PWM13); +#endif +#if PWM14 >= 0 + mcu_config_pwm(PWM14); +#endif +#if PWM15 >= 0 + mcu_config_pwm(PWM15); +#endif +#if SERVO0 >= 0 + mcu_config_output(SERVO0); +#endif +#if SERVO1 >= 0 + mcu_config_output(SERVO1); +#endif +#if SERVO2 >= 0 + mcu_config_output(SERVO2); +#endif +#if SERVO3 >= 0 + mcu_config_output(SERVO3); +#endif +#if SERVO4 >= 0 + mcu_config_output(SERVO4); +#endif +#if SERVO5 >= 0 + mcu_config_output(SERVO5); +#endif +#if DOUT0 >= 0 + mcu_config_output(DOUT0); +#endif +#if DOUT1 >= 0 + mcu_config_output(DOUT1); +#endif +#if DOUT2 >= 0 + mcu_config_output(DOUT2); +#endif +#if DOUT3 >= 0 + mcu_config_output(DOUT3); +#endif +#if DOUT4 >= 0 + mcu_config_output(DOUT4); +#endif +#if DOUT5 >= 0 + mcu_config_output(DOUT5); +#endif +#if DOUT6 >= 0 + mcu_config_output(DOUT6); +#endif +#if DOUT7 >= 0 + mcu_config_output(DOUT7); +#endif +#if DOUT8 >= 0 + mcu_config_output(DOUT8); +#endif +#if DOUT9 >= 0 + mcu_config_output(DOUT9); +#endif +#if DOUT10 >= 0 + mcu_config_output(DOUT10); +#endif +#if DOUT11 >= 0 + mcu_config_output(DOUT11); +#endif +#if DOUT12 >= 0 + mcu_config_output(DOUT12); +#endif +#if DOUT13 >= 0 + mcu_config_output(DOUT13); +#endif +#if DOUT14 >= 0 + mcu_config_output(DOUT14); +#endif +#if DOUT15 >= 0 + mcu_config_output(DOUT15); +#endif +#if DOUT16 >= 0 + mcu_config_output(DOUT16); +#endif +#if DOUT17 >= 0 + mcu_config_output(DOUT17); +#endif +#if DOUT18 >= 0 + mcu_config_output(DOUT18); +#endif +#if DOUT19 >= 0 + mcu_config_output(DOUT19); +#endif +#if DOUT20 >= 0 + mcu_config_output(DOUT20); +#endif +#if DOUT21 >= 0 + mcu_config_output(DOUT21); +#endif +#if DOUT22 >= 0 + mcu_config_output(DOUT22); +#endif +#if DOUT23 >= 0 + mcu_config_output(DOUT23); +#endif +#if DOUT24 >= 0 + mcu_config_output(DOUT24); +#endif +#if DOUT25 >= 0 + mcu_config_output(DOUT25); +#endif +#if DOUT26 >= 0 + mcu_config_output(DOUT26); +#endif +#if DOUT27 >= 0 + mcu_config_output(DOUT27); +#endif +#if DOUT28 >= 0 + mcu_config_output(DOUT28); +#endif +#if DOUT29 >= 0 + mcu_config_output(DOUT29); +#endif +#if DOUT30 >= 0 + mcu_config_output(DOUT30); +#endif +#if DOUT31 >= 0 + mcu_config_output(DOUT31); +#endif +#if LIMIT_X >= 0 + mcu_config_input(LIMIT_X); +#ifdef LIMIT_X_PULLUP + mcu_config_pullup(LIMIT_X); +#endif +#ifdef LIMIT_X_ISR + mcu_config_input_isr(LIMIT_X); +#endif +#endif +#if LIMIT_Y >= 0 + mcu_config_input(LIMIT_Y); +#ifdef LIMIT_Y_PULLUP + mcu_config_pullup(LIMIT_Y); +#endif +#ifdef LIMIT_Y_ISR + mcu_config_input_isr(LIMIT_Y); +#endif +#endif +#if LIMIT_Z >= 0 + mcu_config_input(LIMIT_Z); +#ifdef LIMIT_Z_PULLUP + mcu_config_pullup(LIMIT_Z); +#endif +#ifdef LIMIT_Z_ISR + mcu_config_input_isr(LIMIT_Z); +#endif +#endif +#if LIMIT_X2 >= 0 + mcu_config_input(LIMIT_X2); +#ifdef LIMIT_X2_PULLUP + mcu_config_pullup(LIMIT_X2); +#endif +#ifdef LIMIT_X2_ISR + mcu_config_input_isr(LIMIT_X2); +#endif +#endif +#if LIMIT_Y2 >= 0 + mcu_config_input(LIMIT_Y2); +#ifdef LIMIT_Y2_PULLUP + mcu_config_pullup(LIMIT_Y2); +#endif +#ifdef LIMIT_Y2_ISR + mcu_config_input_isr(LIMIT_Y2); +#endif +#endif +#if LIMIT_Z2 >= 0 + mcu_config_input(LIMIT_Z2); +#ifdef LIMIT_Z2_PULLUP + mcu_config_pullup(LIMIT_Z2); +#endif +#ifdef LIMIT_Z2_ISR + mcu_config_input_isr(LIMIT_Z2); +#endif +#endif +#if LIMIT_A >= 0 + mcu_config_input(LIMIT_A); +#ifdef LIMIT_A_PULLUP + mcu_config_pullup(LIMIT_A); +#endif +#ifdef LIMIT_A_ISR + mcu_config_input_isr(LIMIT_A); +#endif +#endif +#if LIMIT_B >= 0 + mcu_config_input(LIMIT_B); +#ifdef LIMIT_B_PULLUP + mcu_config_pullup(LIMIT_B); +#endif +#ifdef LIMIT_B_ISR + mcu_config_input_isr(LIMIT_B); +#endif +#endif +#if LIMIT_C >= 0 + mcu_config_input(LIMIT_C); +#ifdef LIMIT_C_PULLUP + mcu_config_pullup(LIMIT_C); +#endif +#ifdef LIMIT_C_ISR + mcu_config_input_isr(LIMIT_C); +#endif +#endif +#if PROBE >= 0 + mcu_config_input(PROBE); +#ifdef PROBE_PULLUP + mcu_config_pullup(PROBE); +#endif +#ifdef PROBE_ISR + mcu_config_input_isr(PROBE); +#endif +#endif +#if ESTOP >= 0 + mcu_config_input(ESTOP); +#ifdef ESTOP_PULLUP + mcu_config_pullup(ESTOP); +#endif +#ifdef ESTOP_ISR + mcu_config_input_isr(ESTOP); +#endif +#endif +#if SAFETY_DOOR >= 0 + mcu_config_input(SAFETY_DOOR); +#ifdef SAFETY_DOOR_PULLUP + mcu_config_pullup(SAFETY_DOOR); +#endif +#ifdef SAFETY_DOOR_ISR + mcu_config_input_isr(SAFETY_DOOR); +#endif +#endif +#if FHOLD >= 0 + mcu_config_input(FHOLD); +#ifdef FHOLD_PULLUP + mcu_config_pullup(FHOLD); +#endif +#ifdef FHOLD_ISR + mcu_config_input_isr(FHOLD); +#endif +#endif +#if CS_RES >= 0 + mcu_config_input(CS_RES); +#ifdef CS_RES_PULLUP + mcu_config_pullup(CS_RES); +#endif +#ifdef CS_RES_ISR + mcu_config_input_isr(CS_RES); +#endif +#endif +#if ANALOG0 >= 0 + mcu_config_input(ANALOG0); +#endif +#if ANALOG1 >= 0 + mcu_config_input(ANALOG1); +#endif +#if ANALOG2 >= 0 + mcu_config_input(ANALOG2); +#endif +#if ANALOG3 >= 0 + mcu_config_input(ANALOG3); +#endif +#if ANALOG4 >= 0 + mcu_config_input(ANALOG4); +#endif +#if ANALOG5 >= 0 + mcu_config_input(ANALOG5); +#endif +#if ANALOG6 >= 0 + mcu_config_input(ANALOG6); +#endif +#if ANALOG7 >= 0 + mcu_config_input(ANALOG7); +#endif +#if ANALOG8 >= 0 + mcu_config_input(ANALOG8); +#endif +#if ANALOG9 >= 0 + mcu_config_input(ANALOG9); +#endif +#if ANALOG10 >= 0 + mcu_config_input(ANALOG10); +#endif +#if ANALOG11 >= 0 + mcu_config_input(ANALOG11); +#endif +#if ANALOG12 >= 0 + mcu_config_input(ANALOG12); +#endif +#if ANALOG13 >= 0 + mcu_config_input(ANALOG13); +#endif +#if ANALOG14 >= 0 + mcu_config_input(ANALOG14); +#endif +#if ANALOG15 >= 0 + mcu_config_input(ANALOG15); +#endif +#if DIN0 >= 0 + mcu_config_input(DIN0); +#ifdef DIN0_PULLUP + mcu_config_pullup(DIN0); +#endif +#ifdef DIN0_ISR + mcu_config_input_isr(DIN0); +#endif +#endif +#if DIN1 >= 0 + mcu_config_input(DIN1); +#ifdef DIN1_PULLUP + mcu_config_pullup(DIN1); +#endif +#ifdef DIN1_ISR + mcu_config_input_isr(DIN1); +#endif +#endif +#if DIN2 >= 0 + mcu_config_input(DIN2); +#ifdef DIN2_PULLUP + mcu_config_pullup(DIN2); +#endif +#ifdef DIN2_ISR + mcu_config_input_isr(DIN2); +#endif +#endif +#if DIN3 >= 0 + mcu_config_input(DIN3); +#ifdef DIN3_PULLUP + mcu_config_pullup(DIN3); +#endif +#ifdef DIN3_ISR + mcu_config_input_isr(DIN3); +#endif +#endif +#if DIN4 >= 0 + mcu_config_input(DIN4); +#ifdef DIN4_PULLUP + mcu_config_pullup(DIN4); +#endif +#ifdef DIN4_ISR + mcu_config_input_isr(DIN4); +#endif +#endif +#if DIN5 >= 0 + mcu_config_input(DIN5); +#ifdef DIN5_PULLUP + mcu_config_pullup(DIN5); +#endif +#ifdef DIN5_ISR + mcu_config_input_isr(DIN5); +#endif +#endif +#if DIN6 >= 0 + mcu_config_input(DIN6); +#ifdef DIN6_PULLUP + mcu_config_pullup(DIN6); +#endif +#ifdef DIN6_ISR + mcu_config_input_isr(DIN6); +#endif +#endif +#if DIN7 >= 0 + mcu_config_input(DIN7); +#ifdef DIN7_PULLUP + mcu_config_pullup(DIN7); +#endif +#ifdef DIN7_ISR + mcu_config_input_isr(DIN7); +#endif +#endif +#if DIN8 >= 0 + mcu_config_input(DIN8); +#ifdef DIN8_PULLUP + mcu_config_pullup(DIN8); +#endif +#endif +#if DIN9 >= 0 + mcu_config_input(DIN9); +#ifdef DIN9_PULLUP + mcu_config_pullup(DIN9); +#endif +#endif +#if DIN10 >= 0 + mcu_config_input(DIN10); +#ifdef DIN10_PULLUP + mcu_config_pullup(DIN10); +#endif +#endif +#if DIN11 >= 0 + mcu_config_input(DIN11); +#ifdef DIN11_PULLUP + mcu_config_pullup(DIN11); +#endif +#endif +#if DIN12 >= 0 + mcu_config_input(DIN12); +#ifdef DIN12_PULLUP + mcu_config_pullup(DIN12); +#endif +#endif +#if DIN13 >= 0 + mcu_config_input(DIN13); +#ifdef DIN13_PULLUP + mcu_config_pullup(DIN13); +#endif +#endif +#if DIN14 >= 0 + mcu_config_input(DIN14); +#ifdef DIN14_PULLUP + mcu_config_pullup(DIN14); +#endif +#endif +#if DIN15 >= 0 + mcu_config_input(DIN15); +#ifdef DIN15_PULLUP + mcu_config_pullup(DIN15); +#endif +#endif +#if DIN16 >= 0 + mcu_config_input(DIN16); +#ifdef DIN16_PULLUP + mcu_config_pullup(DIN16); +#endif +#endif +#if DIN17 >= 0 + mcu_config_input(DIN17); +#ifdef DIN17_PULLUP + mcu_config_pullup(DIN17); +#endif +#endif +#if DIN18 >= 0 + mcu_config_input(DIN18); +#ifdef DIN18_PULLUP + mcu_config_pullup(DIN18); +#endif +#endif +#if DIN19 >= 0 + mcu_config_input(DIN19); +#ifdef DIN19_PULLUP + mcu_config_pullup(DIN19); +#endif +#endif +#if DIN20 >= 0 + mcu_config_input(DIN20); +#ifdef DIN20_PULLUP + mcu_config_pullup(DIN20); +#endif +#endif +#if DIN21 >= 0 + mcu_config_input(DIN21); +#ifdef DIN21_PULLUP + mcu_config_pullup(DIN21); +#endif +#endif +#if DIN22 >= 0 + mcu_config_input(DIN22); +#ifdef DIN22_PULLUP + mcu_config_pullup(DIN22); +#endif +#endif +#if DIN23 >= 0 + mcu_config_input(DIN23); +#ifdef DIN23_PULLUP + mcu_config_pullup(DIN23); +#endif +#endif +#if DIN24 >= 0 + mcu_config_input(DIN24); +#ifdef DIN24_PULLUP + mcu_config_pullup(DIN24); +#endif +#endif +#if DIN25 >= 0 + mcu_config_input(DIN25); +#ifdef DIN25_PULLUP + mcu_config_pullup(DIN25); +#endif +#endif +#if DIN26 >= 0 + mcu_config_input(DIN26); +#ifdef DIN26_PULLUP + mcu_config_pullup(DIN26); +#endif +#endif +#if DIN27 >= 0 + mcu_config_input(DIN27); +#ifdef DIN27_PULLUP + mcu_config_pullup(DIN27); +#endif +#endif +#if DIN28 >= 0 + mcu_config_input(DIN28); +#ifdef DIN28_PULLUP + mcu_config_pullup(DIN28); +#endif +#endif +#if DIN29 >= 0 + mcu_config_input(DIN29); +#ifdef DIN29_PULLUP + mcu_config_pullup(DIN29); +#endif +#endif +#if DIN30 >= 0 + mcu_config_input(DIN30); +#ifdef DIN30_PULLUP + mcu_config_pullup(DIN30); +#endif +#endif +#if DIN31 >= 0 + mcu_config_input(DIN31); +#ifdef DIN31_PULLUP + mcu_config_pullup(DIN31); +#endif +#endif +#if (INTERFACE == INTERFACE_UART) +#if TX >= 0 + mcu_config_output(TX); +#endif +#if RX >= 0 + mcu_config_input(RX); +#ifdef RX_PULLUP + mcu_config_pullup(RX); +#endif +#endif +#endif +#if USB_DM >= 0 + mcu_config_input(USB_DM); +#ifdef USB_DM_PULLUP + mcu_config_pullup(USB_DM); +#endif +#endif +#if USB_DP >= 0 + mcu_config_input(USB_DP); +#ifdef USB_DP_PULLUP + mcu_config_pullup(USB_DP); +#endif +#endif +#if SPI_CLK >= 0 + mcu_config_output(SPI_CLK); +#endif +#if SPI_SDI >= 0 + mcu_config_input(SPI_SDI); +#ifdef SPI_SDI_PULLUP + mcu_config_pullup(SPI_SDI); +#endif +#endif +#if SPI_SDO >= 0 + mcu_config_output(SPI_SDO); +#endif + + mcu_usart_init(); + // SysTick is started by the framework but is not working + // Using timer + mcu_rtc_init(); +#if SERVOS_MASK > 0 + servo_timer_init(); +#endif + mcu_disable_probe_isr(); + mcu_enable_global_isr(); +} + +/** + * enables the pin probe mcu isr on change + * can be defined either as a function or a macro call + * */ +#ifndef mcu_enable_probe_isr +void mcu_enable_probe_isr(void) +{ +} +#endif + +/** + * disables the pin probe mcu isr on change + * can be defined either as a function or a macro call + * */ +#ifndef mcu_disable_probe_isr +void mcu_disable_probe_isr(void) +{ +} +#endif + +/** + * gets the voltage value of a built-in ADC pin + * can be defined either as a function or a macro call + * */ +#ifndef mcu_get_analog +uint8_t mcu_get_analog(uint8_t channel) +{ + return 0; +} +#endif + +/** + * sets the pwm value of a built-in pwm pin + * can be defined either as a function or a macro call + * */ +#ifndef mcu_set_pwm +void mcu_set_pwm(uint8_t pwm, uint8_t value) +{ +} +#endif + +/** + * gets the configured pwm value of a built-in pwm pin + * can be defined either as a function or a macro call + * */ +#ifndef mcu_get_pwm +uint8_t mcu_get_pwm(uint8_t pwm) +{ + return 0; +} +#endif + +/** + * sets the pwm for a servo (50Hz with tON between 1~2ms) + * can be defined either as a function or a macro call + * */ +#define SERVO0_UCNC_INTERNAL_PIN 40 +#ifndef mcu_set_servo +void mcu_set_servo(uint8_t servo, uint8_t value) +{ +} +#endif + +/** + * gets the pwm for a servo (50Hz with tON between 1~2ms) + * can be defined either as a function or a macro call + * */ +#ifndef mcu_get_servo +uint8_t mcu_get_servo(uint8_t servo) +{ + return 0; +} +#endif + +/** + * checks if the serial hardware of the MCU is ready do send the next char + * */ +#ifndef mcu_tx_ready +bool mcu_tx_ready(void) +{ +} +#endif + +/** + * checks if the serial hardware of the MCU has a new char ready to be read + * */ +#ifndef mcu_rx_ready +bool mcu_rx_ready(void) +{ + return true; +} +#endif + +/** + * sends a char either via uart (hardware, software or USB virtual COM port) + * can be defined either as a function or a macro call + * */ +#ifndef mcu_putc +void mcu_putc(char c) +{ +#if !(LED < 0) + mcu_toggle_output(LED); +#endif +#if (INTERFACE == INTERFACE_UART) +#ifdef ENABLE_SYNC_TX + while (!mcu_tx_ready()) + ; +#endif + COM_OUTREG = c; +#ifndef ENABLE_SYNC_TX + UART_IntConfig(COM_USART, UART_INTCFG_THRE, ENABLE); +#endif +#elif (INTERFACE == INTERFACE_USB) + if (c != 0) + { + tud_cdc_write_char(c); + } + if (c == '\r' || c == 0) + { + tud_cdc_write_flush(); + } +#endif +} +#endif + +/** + * gets a char either via uart (hardware, software or USB virtual COM port) + * can be defined either as a function or a macro call + * */ +#ifndef mcu_getc +char mcu_getc(void) +{ +#if !(LED < 0) + mcu_toggle_output(LED); +#endif +#if (INTERFACE == INTERFACE_UART) +#ifdef ENABLE_SYNC_RX + while (!mcu_rx_ready()) + ; +#endif + return (COM_INREG & UART_RBR_MASKBIT); +#elif (INTERFACE == INTERFACE_USB) + while (!tud_cdc_available()) + { + tud_task(); + } + + return (unsigned char)tud_cdc_read_char(); +#endif +} +#endif + +// ISR +/** + * enables global interrupts on the MCU + * can be defined either as a function or a macro call + * */ +#ifndef mcu_enable_global_isr +#error "mcu_enable_global_isr undefined" +#endif +/** + * disables global interrupts on the MCU + * can be defined either as a function or a macro call + * */ +#ifndef mcu_disable_global_isr +#error "mcu_disable_global_isr undefined" +#endif +/** + * gets global interrupts state on the MCU + * can be defined either as a function or a macro call + * */ +#ifndef mcu_get_global_isr +#error "mcu_get_global_isr undefined" +#endif + +// Step interpolator +/** + * convert step rate to clock cycles + * */ +void mcu_freq_to_clocks(float frequency, uint16_t *ticks, uint16_t *prescaller) +{ + // up and down counter (generates half the step rate at each event) + uint32_t totalticks = (uint32_t)((float)(1000000UL >> 1) / frequency); + *prescaller = 0; + *ticks = (uint16_t)totalticks; +} + +/** + * starts the timer interrupt that generates the step pulses for the interpolator + * */ +void mcu_start_itp_isr(uint16_t ticks, uint16_t prescaller) +{ + TIM_Cmd(ITP_TIMER_REG, DISABLE); + TIM_TIMERCFG_Type tmrconfig; + TIM_ConfigStructInit(TIM_TIMER_MODE, &tmrconfig); + TIM_Init(ITP_TIMER_REG, TIM_TIMER_MODE, &tmrconfig); + TIM_MATCHCFG_Type tmrmatch; + tmrmatch.MatchChannel = ITP_TIMER; + tmrmatch.IntOnMatch = ENABLE; + tmrmatch.StopOnMatch = DISABLE; + tmrmatch.ResetOnMatch = ENABLE; + tmrmatch.MatchValue = ticks; + TIM_ConfigMatch(ITP_TIMER_REG, &tmrmatch); + NVIC_SetPriority(ITP_TIMER_IRQ, 1); + NVIC_ClearPendingIRQ(ITP_TIMER_IRQ); + NVIC_EnableIRQ(ITP_TIMER_IRQ); + + TIM_Cmd(ITP_TIMER_REG, ENABLE); +} + +/** + * changes the step rate of the timer interrupt that generates the step pulses for the interpolator + * */ +void mcu_change_itp_isr(uint16_t ticks, uint16_t prescaller) +{ + TIM_UpdateMatchValue(ITP_TIMER_REG, ITP_TIMER, ticks); +} + +/** + * stops the timer interrupt that generates the step pulses for the interpolator + * */ +void mcu_stop_itp_isr(void) +{ + TIM_Cmd(ITP_TIMER_REG, DISABLE); + NVIC_DisableIRQ(ITP_TIMER_IRQ); +} + +/** + * gets the MCU running time in milliseconds. + * the time counting is controled by the internal RTC + * */ +uint32_t mcu_millis() +{ + uint32_t val = mcu_runtime_ms; + return val; +} + +/** + * provides a delay in us (micro seconds) + * the maximum allowed delay is 255 us + * */ +void lpc176x_delay_us(uint32_t delay); +#ifndef mcu_delay_us +void mcu_delay_us(uint8_t delay) +{ + lpc176x_delay_us(delay); +} +#endif + +/** + * runs all internal tasks of the MCU. + * for the moment these are: + * - if USB is enabled and MCU uses tinyUSB framework run tinyUSB tud_task + * - if ENABLE_SYNC_RX is enabled check if there are any chars in the rx transmitter (or the tinyUSB buffer) and read them to the mcu_com_rx_cb + * - if ENABLE_SYNC_TX is enabled check if com_tx_empty is false and run mcu_com_tx_cb + * */ +void mcu_dotasks(void) +{ +#if (INTERFACE == INTERFACE_USB) + tud_cdc_write_flush(); + tud_task(); // tinyusb device task +#endif +#if (defined(ENABLE_SYNC_TX) || defined(ENABLE_SYNC_RX)) + // lpc176x_uart_flush(); +#endif +#ifdef ENABLE_SYNC_RX + while (mcu_rx_ready()) + { + unsigned char c = mcu_getc(); + mcu_com_rx_cb(c); + } +#endif +} + +// Non volatile memory +/** + * gets a byte at the given EEPROM (or other non volatile memory) address of the MCU. + * */ +uint8_t mcu_eeprom_getc(uint16_t address) +{ + return 0; +} + +/** + * sets a byte at the given EEPROM (or other non volatile memory) address of the MCU. + * */ +void mcu_eeprom_putc(uint16_t address, uint8_t value) +{ +} + +/** + * flushes all recorded registers into the eeprom. + * */ +void mcu_eeprom_flush(void) +{ +} + +#endif diff --git a/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h b/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h new file mode 100644 index 000000000..2491ada08 --- /dev/null +++ b/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h @@ -0,0 +1,3297 @@ +/* + Name: mcumap_stm32f10x.h + Description: Contains all MCU and PIN definitions for STM32F10x to run µCNC. + + Copyright: Copyright (c) João Martins + Author: João Martins + Date: 04-02-2020 + + µCNC is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. Please see + + µCNC is distributed WITHOUT ANY WARRANTY; + Also without the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + See the GNU General Public License for more details. +*/ + +#ifndef MCUMAP_LPC176X_H +#define MCUMAP_LPC176X_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* + Generates all the interface definitions. + This creates a middle HAL layer between the board IO pins and the AVR funtionalities +*/ +/* + MCU specific definitions and replacements +*/ +#include "LPC17xx.h" +#include + +// defines the frequency of the mcu +#ifndef F_CPU +#define F_CPU 100000000UL +#endif +// defines the maximum and minimum step rates +#ifndef F_STEP_MAX +#define F_STEP_MAX 200000 +#endif +#ifndef F_STEP_MIN +#define F_STEP_MIN 4 +#endif +// defines special mcu to access flash strings and arrays +#define __rom__ +#define __romstr__ +#define __romarr__ const char +#define rom_strptr * +#define rom_strcpy strcpy +#define rom_strncpy strncpy +#define rom_memcpy memcpy +#define rom_read_byte * + +#if (INTERFACE == INTERFACE_USB) +// if USB VCP is used force RX sync also +#ifndef ENABLE_SYNC_TX +#define ENABLE_SYNC_TX +#endif +#ifndef ENABLE_SYNC_RX +#define ENABLE_SYNC_RX +#endif +#endif + +// Helper macros +#define __helper_ex__(left, mid, right) left##mid##right +#define __helper__(left, mid, right) __helper_ex__(left, mid, right) + +#define __mbedpin_ex__(port, pin) P##port##_##pin +#define __mbedpin__(port, pin) __mbedpin_ex__(port, pin) + +#define __gpioreg__(X) __helper__(LPC_GPIO, X, ) +#define __pinmodereg__(X) __helper__(PINMODE, X, ) + +#define PINCON_0_L 0 +#define PINCON_0_H 1 +#define PINCON_1_L 2 +#define PINCON_1_H 3 +#define PINCON_2_L 4 +#define PINCON_2_H 5 +#define PINCON_3_L 6 +#define PINCON_3_H 7 +#define PINCON_4_L 8 +#define PINCON_4_H 9 +#define __pincon(X, Y) PINCON_##X##_##Y +#define __pincon__(X, Y) __pincon(X, Y) + +#if (defined(STEP0_PORT) && defined(STEP0_BIT)) +#define STEP0 0 +#define STEP0_MBED_PIN __mbedpin__(STEP0_PORT, STEP0_BIT) +#define STEP0_GPIOREG __gpioreg__(STEP0_PORT) +#if (STEP0_BIT < 16) +#define STEP0_PINHALF L +#else +#define STEP0_PINHALF H +#endif +#define STEP0_PINCON __pincon__(STEP0_PORT, STEP0_PINHALF) +#define DIO0 0 +#define DIO0_MBED_PIN STEP0_MBED_PIN +#define DIO0_PORT STEP0_PORT +#define DIO0_BIT STEP0_BIT +#define DIO0_GPIOREG STEP0_GPIOREG +#define DIO0_PINHALF STEP0_PINHALF +#define DIO0_PINCON STEP0_PINCON +#endif +#if (defined(STEP1_PORT) && defined(STEP1_BIT)) +#define STEP1 1 +#define STEP1_MBED_PIN __mbedpin__(STEP1_PORT, STEP1_BIT) +#define STEP1_GPIOREG __gpioreg__(STEP1_PORT) +#if (STEP1_BIT < 16) +#define STEP1_PINHALF L +#else +#define STEP1_PINHALF H +#endif +#define STEP1_PINCON __pincon__(STEP1_PORT, STEP1_PINHALF) +#define DIO1 1 +#define DIO1_MBED_PIN STEP1_MBED_PIN +#define DIO1_PORT STEP1_PORT +#define DIO1_BIT STEP1_BIT +#define DIO1_GPIOREG STEP1_GPIOREG +#define DIO1_PINHALF STEP1_PINHALF +#define DIO1_PINCON STEP1_PINCON +#endif +#if (defined(STEP2_PORT) && defined(STEP2_BIT)) +#define STEP2 2 +#define STEP2_MBED_PIN __mbedpin__(STEP2_PORT, STEP2_BIT) +#define STEP2_GPIOREG __gpioreg__(STEP2_PORT) +#if (STEP2_BIT < 16) +#define STEP2_PINHALF L +#else +#define STEP2_PINHALF H +#endif +#define STEP2_PINCON __pincon__(STEP2_PORT, STEP2_PINHALF) +#define DIO2 2 +#define DIO2_MBED_PIN STEP2_MBED_PIN +#define DIO2_PORT STEP2_PORT +#define DIO2_BIT STEP2_BIT +#define DIO2_GPIOREG STEP2_GPIOREG +#define DIO2_PINHALF STEP2_PINHALF +#define DIO2_PINCON STEP2_PINCON +#endif +#if (defined(STEP3_PORT) && defined(STEP3_BIT)) +#define STEP3 3 +#define STEP3_MBED_PIN __mbedpin__(STEP3_PORT, STEP3_BIT) +#define STEP3_GPIOREG __gpioreg__(STEP3_PORT) +#if (STEP3_BIT < 16) +#define STEP3_PINHALF L +#else +#define STEP3_PINHALF H +#endif +#define STEP3_PINCON __pincon__(STEP3_PORT, STEP3_PINHALF) +#define DIO3 3 +#define DIO3_MBED_PIN STEP3_MBED_PIN +#define DIO3_PORT STEP3_PORT +#define DIO3_BIT STEP3_BIT +#define DIO3_GPIOREG STEP3_GPIOREG +#define DIO3_PINHALF STEP3_PINHALF +#define DIO3_PINCON STEP3_PINCON +#endif +#if (defined(STEP4_PORT) && defined(STEP4_BIT)) +#define STEP4 4 +#define STEP4_MBED_PIN __mbedpin__(STEP4_PORT, STEP4_BIT) +#define STEP4_GPIOREG __gpioreg__(STEP4_PORT) +#if (STEP4_BIT < 16) +#define STEP4_PINHALF L +#else +#define STEP4_PINHALF H +#endif +#define STEP4_PINCON __pincon__(STEP4_PORT, STEP4_PINHALF) +#define DIO4 4 +#define DIO4_MBED_PIN STEP4_MBED_PIN +#define DIO4_PORT STEP4_PORT +#define DIO4_BIT STEP4_BIT +#define DIO4_GPIOREG STEP4_GPIOREG +#define DIO4_PINHALF STEP4_PINHALF +#define DIO4_PINCON STEP4_PINCON +#endif +#if (defined(STEP5_PORT) && defined(STEP5_BIT)) +#define STEP5 5 +#define STEP5_MBED_PIN __mbedpin__(STEP5_PORT, STEP5_BIT) +#define STEP5_GPIOREG __gpioreg__(STEP5_PORT) +#if (STEP5_BIT < 16) +#define STEP5_PINHALF L +#else +#define STEP5_PINHALF H +#endif +#define STEP5_PINCON __pincon__(STEP5_PORT, STEP5_PINHALF) +#define DIO5 5 +#define DIO5_MBED_PIN STEP5_MBED_PIN +#define DIO5_PORT STEP5_PORT +#define DIO5_BIT STEP5_BIT +#define DIO5_GPIOREG STEP5_GPIOREG +#define DIO5_PINHALF STEP5_PINHALF +#define DIO5_PINCON STEP5_PINCON +#endif +#if (defined(STEP6_PORT) && defined(STEP6_BIT)) +#define STEP6 6 +#define STEP6_MBED_PIN __mbedpin__(STEP6_PORT, STEP6_BIT) +#define STEP6_GPIOREG __gpioreg__(STEP6_PORT) +#if (STEP6_BIT < 16) +#define STEP6_PINHALF L +#else +#define STEP6_PINHALF H +#endif +#define STEP6_PINCON __pincon__(STEP6_PORT, STEP6_PINHALF) +#define DIO6 6 +#define DIO6_MBED_PIN STEP6_MBED_PIN +#define DIO6_PORT STEP6_PORT +#define DIO6_BIT STEP6_BIT +#define DIO6_GPIOREG STEP6_GPIOREG +#define DIO6_PINHALF STEP6_PINHALF +#define DIO6_PINCON STEP6_PINCON +#endif +#if (defined(STEP7_PORT) && defined(STEP7_BIT)) +#define STEP7 7 +#define STEP7_MBED_PIN __mbedpin__(STEP7_PORT, STEP7_BIT) +#define STEP7_GPIOREG __gpioreg__(STEP7_PORT) +#if (STEP7_BIT < 16) +#define STEP7_PINHALF L +#else +#define STEP7_PINHALF H +#endif +#define STEP7_PINCON __pincon__(STEP7_PORT, STEP7_PINHALF) +#define DIO7 7 +#define DIO7_MBED_PIN STEP7_MBED_PIN +#define DIO7_PORT STEP7_PORT +#define DIO7_BIT STEP7_BIT +#define DIO7_GPIOREG STEP7_GPIOREG +#define DIO7_PINHALF STEP7_PINHALF +#define DIO7_PINCON STEP7_PINCON +#endif +#if (defined(DIR0_PORT) && defined(DIR0_BIT)) +#define DIR0 8 +#define DIR0_MBED_PIN __mbedpin__(DIR0_PORT, DIR0_BIT) +#define DIR0_GPIOREG __gpioreg__(DIR0_PORT) +#if (DIR0_BIT < 16) +#define DIR0_PINHALF L +#else +#define DIR0_PINHALF H +#endif +#define DIR0_PINCON __pincon__(DIR0_PORT, DIR0_PINHALF) +#define DIO8 8 +#define DIO8_MBED_PIN DIR0_MBED_PIN +#define DIO8_PORT DIR0_PORT +#define DIO8_BIT DIR0_BIT +#define DIO8_GPIOREG DIR0_GPIOREG +#define DIO8_PINHALF DIR0_PINHALF +#define DIO8_PINCON DIR0_PINCON +#endif +#if (defined(DIR1_PORT) && defined(DIR1_BIT)) +#define DIR1 9 +#define DIR1_MBED_PIN __mbedpin__(DIR1_PORT, DIR1_BIT) +#define DIR1_GPIOREG __gpioreg__(DIR1_PORT) +#if (DIR1_BIT < 16) +#define DIR1_PINHALF L +#else +#define DIR1_PINHALF H +#endif +#define DIR1_PINCON __pincon__(DIR1_PORT, DIR1_PINHALF) +#define DIO9 9 +#define DIO9_MBED_PIN DIR1_MBED_PIN +#define DIO9_PORT DIR1_PORT +#define DIO9_BIT DIR1_BIT +#define DIO9_GPIOREG DIR1_GPIOREG +#define DIO9_PINHALF DIR1_PINHALF +#define DIO9_PINCON DIR1_PINCON +#endif +#if (defined(DIR2_PORT) && defined(DIR2_BIT)) +#define DIR2 10 +#define DIR2_MBED_PIN __mbedpin__(DIR2_PORT, DIR2_BIT) +#define DIR2_GPIOREG __gpioreg__(DIR2_PORT) +#if (DIR2_BIT < 16) +#define DIR2_PINHALF L +#else +#define DIR2_PINHALF H +#endif +#define DIR2_PINCON __pincon__(DIR2_PORT, DIR2_PINHALF) +#define DIO10 10 +#define DIO10_MBED_PIN DIR2_MBED_PIN +#define DIO10_PORT DIR2_PORT +#define DIO10_BIT DIR2_BIT +#define DIO10_GPIOREG DIR2_GPIOREG +#define DIO10_PINHALF DIR2_PINHALF +#define DIO10_PINCON DIR2_PINCON +#endif +#if (defined(DIR3_PORT) && defined(DIR3_BIT)) +#define DIR3 11 +#define DIR3_MBED_PIN __mbedpin__(DIR3_PORT, DIR3_BIT) +#define DIR3_GPIOREG __gpioreg__(DIR3_PORT) +#if (DIR3_BIT < 16) +#define DIR3_PINHALF L +#else +#define DIR3_PINHALF H +#endif +#define DIR3_PINCON __pincon__(DIR3_PORT, DIR3_PINHALF) +#define DIO11 11 +#define DIO11_MBED_PIN DIR3_MBED_PIN +#define DIO11_PORT DIR3_PORT +#define DIO11_BIT DIR3_BIT +#define DIO11_GPIOREG DIR3_GPIOREG +#define DIO11_PINHALF DIR3_PINHALF +#define DIO11_PINCON DIR3_PINCON +#endif +#if (defined(DIR4_PORT) && defined(DIR4_BIT)) +#define DIR4 12 +#define DIR4_MBED_PIN __mbedpin__(DIR4_PORT, DIR4_BIT) +#define DIR4_GPIOREG __gpioreg__(DIR4_PORT) +#if (DIR4_BIT < 16) +#define DIR4_PINHALF L +#else +#define DIR4_PINHALF H +#endif +#define DIR4_PINCON __pincon__(DIR4_PORT, DIR4_PINHALF) +#define DIO12 12 +#define DIO12_MBED_PIN DIR4_MBED_PIN +#define DIO12_PORT DIR4_PORT +#define DIO12_BIT DIR4_BIT +#define DIO12_GPIOREG DIR4_GPIOREG +#define DIO12_PINHALF DIR4_PINHALF +#define DIO12_PINCON DIR4_PINCON +#endif +#if (defined(DIR5_PORT) && defined(DIR5_BIT)) +#define DIR5 13 +#define DIR5_MBED_PIN __mbedpin__(DIR5_PORT, DIR5_BIT) +#define DIR5_GPIOREG __gpioreg__(DIR5_PORT) +#if (DIR5_BIT < 16) +#define DIR5_PINHALF L +#else +#define DIR5_PINHALF H +#endif +#define DIR5_PINCON __pincon__(DIR5_PORT, DIR5_PINHALF) +#define DIO13 13 +#define DIO13_MBED_PIN DIR5_MBED_PIN +#define DIO13_PORT DIR5_PORT +#define DIO13_BIT DIR5_BIT +#define DIO13_GPIOREG DIR5_GPIOREG +#define DIO13_PINHALF DIR5_PINHALF +#define DIO13_PINCON DIR5_PINCON +#endif +#if (defined(DIR6_PORT) && defined(DIR6_BIT)) +#define DIR6 14 +#define DIR6_MBED_PIN __mbedpin__(DIR6_PORT, DIR6_BIT) +#define DIR6_GPIOREG __gpioreg__(DIR6_PORT) +#if (DIR6_BIT < 16) +#define DIR6_PINHALF L +#else +#define DIR6_PINHALF H +#endif +#define DIR6_PINCON __pincon__(DIR6_PORT, DIR6_PINHALF) +#define DIO14 14 +#define DIO14_MBED_PIN DIR6_MBED_PIN +#define DIO14_PORT DIR6_PORT +#define DIO14_BIT DIR6_BIT +#define DIO14_GPIOREG DIR6_GPIOREG +#define DIO14_PINHALF DIR6_PINHALF +#define DIO14_PINCON DIR6_PINCON +#endif +#if (defined(DIR7_PORT) && defined(DIR7_BIT)) +#define DIR7 15 +#define DIR7_MBED_PIN __mbedpin__(DIR7_PORT, DIR7_BIT) +#define DIR7_GPIOREG __gpioreg__(DIR7_PORT) +#if (DIR7_BIT < 16) +#define DIR7_PINHALF L +#else +#define DIR7_PINHALF H +#endif +#define DIR7_PINCON __pincon__(DIR7_PORT, DIR7_PINHALF) +#define DIO15 15 +#define DIO15_MBED_PIN DIR7_MBED_PIN +#define DIO15_PORT DIR7_PORT +#define DIO15_BIT DIR7_BIT +#define DIO15_GPIOREG DIR7_GPIOREG +#define DIO15_PINHALF DIR7_PINHALF +#define DIO15_PINCON DIR7_PINCON +#endif +#if (defined(STEP0_EN_PORT) && defined(STEP0_EN_BIT)) +#define STEP0_EN 16 +#define STEP0_EN_MBED_PIN __mbedpin__(STEP0_EN_PORT, STEP0_EN_BIT) +#define STEP0_EN_GPIOREG __gpioreg__(STEP0_EN_PORT) +#if (STEP0_EN_BIT < 16) +#define STEP0_EN_PINHALF L +#else +#define STEP0_EN_PINHALF H +#endif +#define STEP0_EN_PINCON __pincon__(STEP0_EN_PORT, STEP0_EN_PINHALF) +#define DIO16 16 +#define DIO16_MBED_PIN STEP0_EN_MBED_PIN +#define DIO16_PORT STEP0_EN_PORT +#define DIO16_BIT STEP0_EN_BIT +#define DIO16_GPIOREG STEP0_EN_GPIOREG +#define DIO16_PINHALF STEP0_EN_PINHALF +#define DIO16_PINCON STEP0_EN_PINCON +#endif +#if (defined(STEP1_EN_PORT) && defined(STEP1_EN_BIT)) +#define STEP1_EN 17 +#define STEP1_EN_MBED_PIN __mbedpin__(STEP1_EN_PORT, STEP1_EN_BIT) +#define STEP1_EN_GPIOREG __gpioreg__(STEP1_EN_PORT) +#if (STEP1_EN_BIT < 16) +#define STEP1_EN_PINHALF L +#else +#define STEP1_EN_PINHALF H +#endif +#define STEP1_EN_PINCON __pincon__(STEP1_EN_PORT, STEP1_EN_PINHALF) +#define DIO17 17 +#define DIO17_MBED_PIN STEP1_EN_MBED_PIN +#define DIO17_PORT STEP1_EN_PORT +#define DIO17_BIT STEP1_EN_BIT +#define DIO17_GPIOREG STEP1_EN_GPIOREG +#define DIO17_PINHALF STEP1_EN_PINHALF +#define DIO17_PINCON STEP1_EN_PINCON +#endif +#if (defined(STEP2_EN_PORT) && defined(STEP2_EN_BIT)) +#define STEP2_EN 18 +#define STEP2_EN_MBED_PIN __mbedpin__(STEP2_EN_PORT, STEP2_EN_BIT) +#define STEP2_EN_GPIOREG __gpioreg__(STEP2_EN_PORT) +#if (STEP2_EN_BIT < 16) +#define STEP2_EN_PINHALF L +#else +#define STEP2_EN_PINHALF H +#endif +#define STEP2_EN_PINCON __pincon__(STEP2_EN_PORT, STEP2_EN_PINHALF) +#define DIO18 18 +#define DIO18_MBED_PIN STEP2_EN_MBED_PIN +#define DIO18_PORT STEP2_EN_PORT +#define DIO18_BIT STEP2_EN_BIT +#define DIO18_GPIOREG STEP2_EN_GPIOREG +#define DIO18_PINHALF STEP2_EN_PINHALF +#define DIO18_PINCON STEP2_EN_PINCON +#endif +#if (defined(STEP3_EN_PORT) && defined(STEP3_EN_BIT)) +#define STEP3_EN 19 +#define STEP3_EN_MBED_PIN __mbedpin__(STEP3_EN_PORT, STEP3_EN_BIT) +#define STEP3_EN_GPIOREG __gpioreg__(STEP3_EN_PORT) +#if (STEP3_EN_BIT < 16) +#define STEP3_EN_PINHALF L +#else +#define STEP3_EN_PINHALF H +#endif +#define STEP3_EN_PINCON __pincon__(STEP3_EN_PORT, STEP3_EN_PINHALF) +#define DIO19 19 +#define DIO19_MBED_PIN STEP3_EN_MBED_PIN +#define DIO19_PORT STEP3_EN_PORT +#define DIO19_BIT STEP3_EN_BIT +#define DIO19_GPIOREG STEP3_EN_GPIOREG +#define DIO19_PINHALF STEP3_EN_PINHALF +#define DIO19_PINCON STEP3_EN_PINCON +#endif +#if (defined(STEP4_EN_PORT) && defined(STEP4_EN_BIT)) +#define STEP4_EN 20 +#define STEP4_EN_MBED_PIN __mbedpin__(STEP4_EN_PORT, STEP4_EN_BIT) +#define STEP4_EN_GPIOREG __gpioreg__(STEP4_EN_PORT) +#if (STEP4_EN_BIT < 16) +#define STEP4_EN_PINHALF L +#else +#define STEP4_EN_PINHALF H +#endif +#define STEP4_EN_PINCON __pincon__(STEP4_EN_PORT, STEP4_EN_PINHALF) +#define DIO20 20 +#define DIO20_MBED_PIN STEP4_EN_MBED_PIN +#define DIO20_PORT STEP4_EN_PORT +#define DIO20_BIT STEP4_EN_BIT +#define DIO20_GPIOREG STEP4_EN_GPIOREG +#define DIO20_PINHALF STEP4_EN_PINHALF +#define DIO20_PINCON STEP4_EN_PINCON +#endif +#if (defined(STEP5_EN_PORT) && defined(STEP5_EN_BIT)) +#define STEP5_EN 21 +#define STEP5_EN_MBED_PIN __mbedpin__(STEP5_EN_PORT, STEP5_EN_BIT) +#define STEP5_EN_GPIOREG __gpioreg__(STEP5_EN_PORT) +#if (STEP5_EN_BIT < 16) +#define STEP5_EN_PINHALF L +#else +#define STEP5_EN_PINHALF H +#endif +#define STEP5_EN_PINCON __pincon__(STEP5_EN_PORT, STEP5_EN_PINHALF) +#define DIO21 21 +#define DIO21_MBED_PIN STEP5_EN_MBED_PIN +#define DIO21_PORT STEP5_EN_PORT +#define DIO21_BIT STEP5_EN_BIT +#define DIO21_GPIOREG STEP5_EN_GPIOREG +#define DIO21_PINHALF STEP5_EN_PINHALF +#define DIO21_PINCON STEP5_EN_PINCON +#endif +#if (defined(STEP6_EN_PORT) && defined(STEP6_EN_BIT)) +#define STEP6_EN 22 +#define STEP6_EN_MBED_PIN __mbedpin__(STEP6_EN_PORT, STEP6_EN_BIT) +#define STEP6_EN_GPIOREG __gpioreg__(STEP6_EN_PORT) +#if (STEP6_EN_BIT < 16) +#define STEP6_EN_PINHALF L +#else +#define STEP6_EN_PINHALF H +#endif +#define STEP6_EN_PINCON __pincon__(STEP6_EN_PORT, STEP6_EN_PINHALF) +#define DIO22 22 +#define DIO22_MBED_PIN STEP6_EN_MBED_PIN +#define DIO22_PORT STEP6_EN_PORT +#define DIO22_BIT STEP6_EN_BIT +#define DIO22_GPIOREG STEP6_EN_GPIOREG +#define DIO22_PINHALF STEP6_EN_PINHALF +#define DIO22_PINCON STEP6_EN_PINCON +#endif +#if (defined(STEP7_EN_PORT) && defined(STEP7_EN_BIT)) +#define STEP7_EN 23 +#define STEP7_EN_MBED_PIN __mbedpin__(STEP7_EN_PORT, STEP7_EN_BIT) +#define STEP7_EN_GPIOREG __gpioreg__(STEP7_EN_PORT) +#if (STEP7_EN_BIT < 16) +#define STEP7_EN_PINHALF L +#else +#define STEP7_EN_PINHALF H +#endif +#define STEP7_EN_PINCON __pincon__(STEP7_EN_PORT, STEP7_EN_PINHALF) +#define DIO23 23 +#define DIO23_MBED_PIN STEP7_EN_MBED_PIN +#define DIO23_PORT STEP7_EN_PORT +#define DIO23_BIT STEP7_EN_BIT +#define DIO23_GPIOREG STEP7_EN_GPIOREG +#define DIO23_PINHALF STEP7_EN_PINHALF +#define DIO23_PINCON STEP7_EN_PINCON +#endif +#if (defined(PWM0_PORT) && defined(PWM0_BIT)) +#define PWM0 24 +#define PWM0_MBED_PIN __mbedpin__(PWM0_PORT, PWM0_BIT) +#define PWM0_GPIOREG __gpioreg__(PWM0_PORT) +#if (PWM0_BIT < 16) +#define PWM0_PINHALF L +#else +#define PWM0_PINHALF H +#endif +#define PWM0_PINCON __pincon__(PWM0_PORT, PWM0_PINHALF) +#define DIO24 24 +#define DIO24_MBED_PIN PWM0_MBED_PIN +#define DIO24_PORT PWM0_PORT +#define DIO24_BIT PWM0_BIT +#define DIO24_GPIOREG PWM0_GPIOREG +#define DIO24_PINHALF PWM0_PINHALF +#define DIO24_PINCON PWM0_PINCON +#endif +#if (defined(PWM1_PORT) && defined(PWM1_BIT)) +#define PWM1 25 +#define PWM1_MBED_PIN __mbedpin__(PWM1_PORT, PWM1_BIT) +#define PWM1_GPIOREG __gpioreg__(PWM1_PORT) +#if (PWM1_BIT < 16) +#define PWM1_PINHALF L +#else +#define PWM1_PINHALF H +#endif +#define PWM1_PINCON __pincon__(PWM1_PORT, PWM1_PINHALF) +#define DIO25 25 +#define DIO25_MBED_PIN PWM1_MBED_PIN +#define DIO25_PORT PWM1_PORT +#define DIO25_BIT PWM1_BIT +#define DIO25_GPIOREG PWM1_GPIOREG +#define DIO25_PINHALF PWM1_PINHALF +#define DIO25_PINCON PWM1_PINCON +#endif +#if (defined(PWM2_PORT) && defined(PWM2_BIT)) +#define PWM2 26 +#define PWM2_MBED_PIN __mbedpin__(PWM2_PORT, PWM2_BIT) +#define PWM2_GPIOREG __gpioreg__(PWM2_PORT) +#if (PWM2_BIT < 16) +#define PWM2_PINHALF L +#else +#define PWM2_PINHALF H +#endif +#define PWM2_PINCON __pincon__(PWM2_PORT, PWM2_PINHALF) +#define DIO26 26 +#define DIO26_MBED_PIN PWM2_MBED_PIN +#define DIO26_PORT PWM2_PORT +#define DIO26_BIT PWM2_BIT +#define DIO26_GPIOREG PWM2_GPIOREG +#define DIO26_PINHALF PWM2_PINHALF +#define DIO26_PINCON PWM2_PINCON +#endif +#if (defined(PWM3_PORT) && defined(PWM3_BIT)) +#define PWM3 27 +#define PWM3_MBED_PIN __mbedpin__(PWM3_PORT, PWM3_BIT) +#define PWM3_GPIOREG __gpioreg__(PWM3_PORT) +#if (PWM3_BIT < 16) +#define PWM3_PINHALF L +#else +#define PWM3_PINHALF H +#endif +#define PWM3_PINCON __pincon__(PWM3_PORT, PWM3_PINHALF) +#define DIO27 27 +#define DIO27_MBED_PIN PWM3_MBED_PIN +#define DIO27_PORT PWM3_PORT +#define DIO27_BIT PWM3_BIT +#define DIO27_GPIOREG PWM3_GPIOREG +#define DIO27_PINHALF PWM3_PINHALF +#define DIO27_PINCON PWM3_PINCON +#endif +#if (defined(PWM4_PORT) && defined(PWM4_BIT)) +#define PWM4 28 +#define PWM4_MBED_PIN __mbedpin__(PWM4_PORT, PWM4_BIT) +#define PWM4_GPIOREG __gpioreg__(PWM4_PORT) +#if (PWM4_BIT < 16) +#define PWM4_PINHALF L +#else +#define PWM4_PINHALF H +#endif +#define PWM4_PINCON __pincon__(PWM4_PORT, PWM4_PINHALF) +#define DIO28 28 +#define DIO28_MBED_PIN PWM4_MBED_PIN +#define DIO28_PORT PWM4_PORT +#define DIO28_BIT PWM4_BIT +#define DIO28_GPIOREG PWM4_GPIOREG +#define DIO28_PINHALF PWM4_PINHALF +#define DIO28_PINCON PWM4_PINCON +#endif +#if (defined(PWM5_PORT) && defined(PWM5_BIT)) +#define PWM5 29 +#define PWM5_MBED_PIN __mbedpin__(PWM5_PORT, PWM5_BIT) +#define PWM5_GPIOREG __gpioreg__(PWM5_PORT) +#if (PWM5_BIT < 16) +#define PWM5_PINHALF L +#else +#define PWM5_PINHALF H +#endif +#define PWM5_PINCON __pincon__(PWM5_PORT, PWM5_PINHALF) +#define DIO29 29 +#define DIO29_MBED_PIN PWM5_MBED_PIN +#define DIO29_PORT PWM5_PORT +#define DIO29_BIT PWM5_BIT +#define DIO29_GPIOREG PWM5_GPIOREG +#define DIO29_PINHALF PWM5_PINHALF +#define DIO29_PINCON PWM5_PINCON +#endif +#if (defined(PWM6_PORT) && defined(PWM6_BIT)) +#define PWM6 30 +#define PWM6_MBED_PIN __mbedpin__(PWM6_PORT, PWM6_BIT) +#define PWM6_GPIOREG __gpioreg__(PWM6_PORT) +#if (PWM6_BIT < 16) +#define PWM6_PINHALF L +#else +#define PWM6_PINHALF H +#endif +#define PWM6_PINCON __pincon__(PWM6_PORT, PWM6_PINHALF) +#define DIO30 30 +#define DIO30_MBED_PIN PWM6_MBED_PIN +#define DIO30_PORT PWM6_PORT +#define DIO30_BIT PWM6_BIT +#define DIO30_GPIOREG PWM6_GPIOREG +#define DIO30_PINHALF PWM6_PINHALF +#define DIO30_PINCON PWM6_PINCON +#endif +#if (defined(PWM7_PORT) && defined(PWM7_BIT)) +#define PWM7 31 +#define PWM7_MBED_PIN __mbedpin__(PWM7_PORT, PWM7_BIT) +#define PWM7_GPIOREG __gpioreg__(PWM7_PORT) +#if (PWM7_BIT < 16) +#define PWM7_PINHALF L +#else +#define PWM7_PINHALF H +#endif +#define PWM7_PINCON __pincon__(PWM7_PORT, PWM7_PINHALF) +#define DIO31 31 +#define DIO31_MBED_PIN PWM7_MBED_PIN +#define DIO31_PORT PWM7_PORT +#define DIO31_BIT PWM7_BIT +#define DIO31_GPIOREG PWM7_GPIOREG +#define DIO31_PINHALF PWM7_PINHALF +#define DIO31_PINCON PWM7_PINCON +#endif +#if (defined(PWM8_PORT) && defined(PWM8_BIT)) +#define PWM8 32 +#define PWM8_MBED_PIN __mbedpin__(PWM8_PORT, PWM8_BIT) +#define PWM8_GPIOREG __gpioreg__(PWM8_PORT) +#if (PWM8_BIT < 16) +#define PWM8_PINHALF L +#else +#define PWM8_PINHALF H +#endif +#define PWM8_PINCON __pincon__(PWM8_PORT, PWM8_PINHALF) +#define DIO32 32 +#define DIO32_MBED_PIN PWM8_MBED_PIN +#define DIO32_PORT PWM8_PORT +#define DIO32_BIT PWM8_BIT +#define DIO32_GPIOREG PWM8_GPIOREG +#define DIO32_PINHALF PWM8_PINHALF +#define DIO32_PINCON PWM8_PINCON +#endif +#if (defined(PWM9_PORT) && defined(PWM9_BIT)) +#define PWM9 33 +#define PWM9_MBED_PIN __mbedpin__(PWM9_PORT, PWM9_BIT) +#define PWM9_GPIOREG __gpioreg__(PWM9_PORT) +#if (PWM9_BIT < 16) +#define PWM9_PINHALF L +#else +#define PWM9_PINHALF H +#endif +#define PWM9_PINCON __pincon__(PWM9_PORT, PWM9_PINHALF) +#define DIO33 33 +#define DIO33_MBED_PIN PWM9_MBED_PIN +#define DIO33_PORT PWM9_PORT +#define DIO33_BIT PWM9_BIT +#define DIO33_GPIOREG PWM9_GPIOREG +#define DIO33_PINHALF PWM9_PINHALF +#define DIO33_PINCON PWM9_PINCON +#endif +#if (defined(PWM10_PORT) && defined(PWM10_BIT)) +#define PWM10 34 +#define PWM10_MBED_PIN __mbedpin__(PWM10_PORT, PWM10_BIT) +#define PWM10_GPIOREG __gpioreg__(PWM10_PORT) +#if (PWM10_BIT < 16) +#define PWM10_PINHALF L +#else +#define PWM10_PINHALF H +#endif +#define PWM10_PINCON __pincon__(PWM10_PORT, PWM10_PINHALF) +#define DIO34 34 +#define DIO34_MBED_PIN PWM10_MBED_PIN +#define DIO34_PORT PWM10_PORT +#define DIO34_BIT PWM10_BIT +#define DIO34_GPIOREG PWM10_GPIOREG +#define DIO34_PINHALF PWM10_PINHALF +#define DIO34_PINCON PWM10_PINCON +#endif +#if (defined(PWM11_PORT) && defined(PWM11_BIT)) +#define PWM11 35 +#define PWM11_MBED_PIN __mbedpin__(PWM11_PORT, PWM11_BIT) +#define PWM11_GPIOREG __gpioreg__(PWM11_PORT) +#if (PWM11_BIT < 16) +#define PWM11_PINHALF L +#else +#define PWM11_PINHALF H +#endif +#define PWM11_PINCON __pincon__(PWM11_PORT, PWM11_PINHALF) +#define DIO35 35 +#define DIO35_MBED_PIN PWM11_MBED_PIN +#define DIO35_PORT PWM11_PORT +#define DIO35_BIT PWM11_BIT +#define DIO35_GPIOREG PWM11_GPIOREG +#define DIO35_PINHALF PWM11_PINHALF +#define DIO35_PINCON PWM11_PINCON +#endif +#if (defined(PWM12_PORT) && defined(PWM12_BIT)) +#define PWM12 36 +#define PWM12_MBED_PIN __mbedpin__(PWM12_PORT, PWM12_BIT) +#define PWM12_GPIOREG __gpioreg__(PWM12_PORT) +#if (PWM12_BIT < 16) +#define PWM12_PINHALF L +#else +#define PWM12_PINHALF H +#endif +#define PWM12_PINCON __pincon__(PWM12_PORT, PWM12_PINHALF) +#define DIO36 36 +#define DIO36_MBED_PIN PWM12_MBED_PIN +#define DIO36_PORT PWM12_PORT +#define DIO36_BIT PWM12_BIT +#define DIO36_GPIOREG PWM12_GPIOREG +#define DIO36_PINHALF PWM12_PINHALF +#define DIO36_PINCON PWM12_PINCON +#endif +#if (defined(PWM13_PORT) && defined(PWM13_BIT)) +#define PWM13 37 +#define PWM13_MBED_PIN __mbedpin__(PWM13_PORT, PWM13_BIT) +#define PWM13_GPIOREG __gpioreg__(PWM13_PORT) +#if (PWM13_BIT < 16) +#define PWM13_PINHALF L +#else +#define PWM13_PINHALF H +#endif +#define PWM13_PINCON __pincon__(PWM13_PORT, PWM13_PINHALF) +#define DIO37 37 +#define DIO37_MBED_PIN PWM13_MBED_PIN +#define DIO37_PORT PWM13_PORT +#define DIO37_BIT PWM13_BIT +#define DIO37_GPIOREG PWM13_GPIOREG +#define DIO37_PINHALF PWM13_PINHALF +#define DIO37_PINCON PWM13_PINCON +#endif +#if (defined(PWM14_PORT) && defined(PWM14_BIT)) +#define PWM14 38 +#define PWM14_MBED_PIN __mbedpin__(PWM14_PORT, PWM14_BIT) +#define PWM14_GPIOREG __gpioreg__(PWM14_PORT) +#if (PWM14_BIT < 16) +#define PWM14_PINHALF L +#else +#define PWM14_PINHALF H +#endif +#define PWM14_PINCON __pincon__(PWM14_PORT, PWM14_PINHALF) +#define DIO38 38 +#define DIO38_MBED_PIN PWM14_MBED_PIN +#define DIO38_PORT PWM14_PORT +#define DIO38_BIT PWM14_BIT +#define DIO38_GPIOREG PWM14_GPIOREG +#define DIO38_PINHALF PWM14_PINHALF +#define DIO38_PINCON PWM14_PINCON +#endif +#if (defined(PWM15_PORT) && defined(PWM15_BIT)) +#define PWM15 39 +#define PWM15_MBED_PIN __mbedpin__(PWM15_PORT, PWM15_BIT) +#define PWM15_GPIOREG __gpioreg__(PWM15_PORT) +#if (PWM15_BIT < 16) +#define PWM15_PINHALF L +#else +#define PWM15_PINHALF H +#endif +#define PWM15_PINCON __pincon__(PWM15_PORT, PWM15_PINHALF) +#define DIO39 39 +#define DIO39_MBED_PIN PWM15_MBED_PIN +#define DIO39_PORT PWM15_PORT +#define DIO39_BIT PWM15_BIT +#define DIO39_GPIOREG PWM15_GPIOREG +#define DIO39_PINHALF PWM15_PINHALF +#define DIO39_PINCON PWM15_PINCON +#endif +#if (defined(SERVO0_PORT) && defined(SERVO0_BIT)) +#define SERVO0 40 +#define SERVO0_MBED_PIN __mbedpin__(SERVO0_PORT, SERVO0_BIT) +#define SERVO0_GPIOREG __gpioreg__(SERVO0_PORT) +#if (SERVO0_BIT < 16) +#define SERVO0_PINHALF L +#else +#define SERVO0_PINHALF H +#endif +#define SERVO0_PINCON __pincon__(SERVO0_PORT, SERVO0_PINHALF) +#define DIO40 40 +#define DIO40_MBED_PIN SERVO0_MBED_PIN +#define DIO40_PORT SERVO0_PORT +#define DIO40_BIT SERVO0_BIT +#define DIO40_GPIOREG SERVO0_GPIOREG +#define DIO40_PINHALF SERVO0_PINHALF +#define DIO40_PINCON SERVO0_PINCON +#endif +#if (defined(SERVO1_PORT) && defined(SERVO1_BIT)) +#define SERVO1 41 +#define SERVO1_MBED_PIN __mbedpin__(SERVO1_PORT, SERVO1_BIT) +#define SERVO1_GPIOREG __gpioreg__(SERVO1_PORT) +#if (SERVO1_BIT < 16) +#define SERVO1_PINHALF L +#else +#define SERVO1_PINHALF H +#endif +#define SERVO1_PINCON __pincon__(SERVO1_PORT, SERVO1_PINHALF) +#define DIO41 41 +#define DIO41_MBED_PIN SERVO1_MBED_PIN +#define DIO41_PORT SERVO1_PORT +#define DIO41_BIT SERVO1_BIT +#define DIO41_GPIOREG SERVO1_GPIOREG +#define DIO41_PINHALF SERVO1_PINHALF +#define DIO41_PINCON SERVO1_PINCON +#endif +#if (defined(SERVO2_PORT) && defined(SERVO2_BIT)) +#define SERVO2 42 +#define SERVO2_MBED_PIN __mbedpin__(SERVO2_PORT, SERVO2_BIT) +#define SERVO2_GPIOREG __gpioreg__(SERVO2_PORT) +#if (SERVO2_BIT < 16) +#define SERVO2_PINHALF L +#else +#define SERVO2_PINHALF H +#endif +#define SERVO2_PINCON __pincon__(SERVO2_PORT, SERVO2_PINHALF) +#define DIO42 42 +#define DIO42_MBED_PIN SERVO2_MBED_PIN +#define DIO42_PORT SERVO2_PORT +#define DIO42_BIT SERVO2_BIT +#define DIO42_GPIOREG SERVO2_GPIOREG +#define DIO42_PINHALF SERVO2_PINHALF +#define DIO42_PINCON SERVO2_PINCON +#endif +#if (defined(SERVO3_PORT) && defined(SERVO3_BIT)) +#define SERVO3 43 +#define SERVO3_MBED_PIN __mbedpin__(SERVO3_PORT, SERVO3_BIT) +#define SERVO3_GPIOREG __gpioreg__(SERVO3_PORT) +#if (SERVO3_BIT < 16) +#define SERVO3_PINHALF L +#else +#define SERVO3_PINHALF H +#endif +#define SERVO3_PINCON __pincon__(SERVO3_PORT, SERVO3_PINHALF) +#define DIO43 43 +#define DIO43_MBED_PIN SERVO3_MBED_PIN +#define DIO43_PORT SERVO3_PORT +#define DIO43_BIT SERVO3_BIT +#define DIO43_GPIOREG SERVO3_GPIOREG +#define DIO43_PINHALF SERVO3_PINHALF +#define DIO43_PINCON SERVO3_PINCON +#endif +#if (defined(SERVO4_PORT) && defined(SERVO4_BIT)) +#define SERVO4 44 +#define SERVO4_MBED_PIN __mbedpin__(SERVO4_PORT, SERVO4_BIT) +#define SERVO4_GPIOREG __gpioreg__(SERVO4_PORT) +#if (SERVO4_BIT < 16) +#define SERVO4_PINHALF L +#else +#define SERVO4_PINHALF H +#endif +#define SERVO4_PINCON __pincon__(SERVO4_PORT, SERVO4_PINHALF) +#define DIO44 44 +#define DIO44_MBED_PIN SERVO4_MBED_PIN +#define DIO44_PORT SERVO4_PORT +#define DIO44_BIT SERVO4_BIT +#define DIO44_GPIOREG SERVO4_GPIOREG +#define DIO44_PINHALF SERVO4_PINHALF +#define DIO44_PINCON SERVO4_PINCON +#endif +#if (defined(SERVO5_PORT) && defined(SERVO5_BIT)) +#define SERVO5 45 +#define SERVO5_MBED_PIN __mbedpin__(SERVO5_PORT, SERVO5_BIT) +#define SERVO5_GPIOREG __gpioreg__(SERVO5_PORT) +#if (SERVO5_BIT < 16) +#define SERVO5_PINHALF L +#else +#define SERVO5_PINHALF H +#endif +#define SERVO5_PINCON __pincon__(SERVO5_PORT, SERVO5_PINHALF) +#define DIO45 45 +#define DIO45_MBED_PIN SERVO5_MBED_PIN +#define DIO45_PORT SERVO5_PORT +#define DIO45_BIT SERVO5_BIT +#define DIO45_GPIOREG SERVO5_GPIOREG +#define DIO45_PINHALF SERVO5_PINHALF +#define DIO45_PINCON SERVO5_PINCON +#endif +#if (defined(DOUT0_PORT) && defined(DOUT0_BIT)) +#define DOUT0 46 +#define DOUT0_MBED_PIN __mbedpin__(DOUT0_PORT, DOUT0_BIT) +#define DOUT0_GPIOREG __gpioreg__(DOUT0_PORT) +#if (DOUT0_BIT < 16) +#define DOUT0_PINHALF L +#else +#define DOUT0_PINHALF H +#endif +#define DOUT0_PINCON __pincon__(DOUT0_PORT, DOUT0_PINHALF) +#define DIO46 46 +#define DIO46_MBED_PIN DOUT0_MBED_PIN +#define DIO46_PORT DOUT0_PORT +#define DIO46_BIT DOUT0_BIT +#define DIO46_GPIOREG DOUT0_GPIOREG +#define DIO46_PINHALF DOUT0_PINHALF +#define DIO46_PINCON DOUT0_PINCON +#endif +#if (defined(DOUT1_PORT) && defined(DOUT1_BIT)) +#define DOUT1 47 +#define DOUT1_MBED_PIN __mbedpin__(DOUT1_PORT, DOUT1_BIT) +#define DOUT1_GPIOREG __gpioreg__(DOUT1_PORT) +#if (DOUT1_BIT < 16) +#define DOUT1_PINHALF L +#else +#define DOUT1_PINHALF H +#endif +#define DOUT1_PINCON __pincon__(DOUT1_PORT, DOUT1_PINHALF) +#define DIO47 47 +#define DIO47_MBED_PIN DOUT1_MBED_PIN +#define DIO47_PORT DOUT1_PORT +#define DIO47_BIT DOUT1_BIT +#define DIO47_GPIOREG DOUT1_GPIOREG +#define DIO47_PINHALF DOUT1_PINHALF +#define DIO47_PINCON DOUT1_PINCON +#endif +#if (defined(DOUT2_PORT) && defined(DOUT2_BIT)) +#define DOUT2 48 +#define DOUT2_MBED_PIN __mbedpin__(DOUT2_PORT, DOUT2_BIT) +#define DOUT2_GPIOREG __gpioreg__(DOUT2_PORT) +#if (DOUT2_BIT < 16) +#define DOUT2_PINHALF L +#else +#define DOUT2_PINHALF H +#endif +#define DOUT2_PINCON __pincon__(DOUT2_PORT, DOUT2_PINHALF) +#define DIO48 48 +#define DIO48_MBED_PIN DOUT2_MBED_PIN +#define DIO48_PORT DOUT2_PORT +#define DIO48_BIT DOUT2_BIT +#define DIO48_GPIOREG DOUT2_GPIOREG +#define DIO48_PINHALF DOUT2_PINHALF +#define DIO48_PINCON DOUT2_PINCON +#endif +#if (defined(DOUT3_PORT) && defined(DOUT3_BIT)) +#define DOUT3 49 +#define DOUT3_MBED_PIN __mbedpin__(DOUT3_PORT, DOUT3_BIT) +#define DOUT3_GPIOREG __gpioreg__(DOUT3_PORT) +#if (DOUT3_BIT < 16) +#define DOUT3_PINHALF L +#else +#define DOUT3_PINHALF H +#endif +#define DOUT3_PINCON __pincon__(DOUT3_PORT, DOUT3_PINHALF) +#define DIO49 49 +#define DIO49_MBED_PIN DOUT3_MBED_PIN +#define DIO49_PORT DOUT3_PORT +#define DIO49_BIT DOUT3_BIT +#define DIO49_GPIOREG DOUT3_GPIOREG +#define DIO49_PINHALF DOUT3_PINHALF +#define DIO49_PINCON DOUT3_PINCON +#endif +#if (defined(DOUT4_PORT) && defined(DOUT4_BIT)) +#define DOUT4 50 +#define DOUT4_MBED_PIN __mbedpin__(DOUT4_PORT, DOUT4_BIT) +#define DOUT4_GPIOREG __gpioreg__(DOUT4_PORT) +#if (DOUT4_BIT < 16) +#define DOUT4_PINHALF L +#else +#define DOUT4_PINHALF H +#endif +#define DOUT4_PINCON __pincon__(DOUT4_PORT, DOUT4_PINHALF) +#define DIO50 50 +#define DIO50_MBED_PIN DOUT4_MBED_PIN +#define DIO50_PORT DOUT4_PORT +#define DIO50_BIT DOUT4_BIT +#define DIO50_GPIOREG DOUT4_GPIOREG +#define DIO50_PINHALF DOUT4_PINHALF +#define DIO50_PINCON DOUT4_PINCON +#endif +#if (defined(DOUT5_PORT) && defined(DOUT5_BIT)) +#define DOUT5 51 +#define DOUT5_MBED_PIN __mbedpin__(DOUT5_PORT, DOUT5_BIT) +#define DOUT5_GPIOREG __gpioreg__(DOUT5_PORT) +#if (DOUT5_BIT < 16) +#define DOUT5_PINHALF L +#else +#define DOUT5_PINHALF H +#endif +#define DOUT5_PINCON __pincon__(DOUT5_PORT, DOUT5_PINHALF) +#define DIO51 51 +#define DIO51_MBED_PIN DOUT5_MBED_PIN +#define DIO51_PORT DOUT5_PORT +#define DIO51_BIT DOUT5_BIT +#define DIO51_GPIOREG DOUT5_GPIOREG +#define DIO51_PINHALF DOUT5_PINHALF +#define DIO51_PINCON DOUT5_PINCON +#endif +#if (defined(DOUT6_PORT) && defined(DOUT6_BIT)) +#define DOUT6 52 +#define DOUT6_MBED_PIN __mbedpin__(DOUT6_PORT, DOUT6_BIT) +#define DOUT6_GPIOREG __gpioreg__(DOUT6_PORT) +#if (DOUT6_BIT < 16) +#define DOUT6_PINHALF L +#else +#define DOUT6_PINHALF H +#endif +#define DOUT6_PINCON __pincon__(DOUT6_PORT, DOUT6_PINHALF) +#define DIO52 52 +#define DIO52_MBED_PIN DOUT6_MBED_PIN +#define DIO52_PORT DOUT6_PORT +#define DIO52_BIT DOUT6_BIT +#define DIO52_GPIOREG DOUT6_GPIOREG +#define DIO52_PINHALF DOUT6_PINHALF +#define DIO52_PINCON DOUT6_PINCON +#endif +#if (defined(DOUT7_PORT) && defined(DOUT7_BIT)) +#define DOUT7 53 +#define DOUT7_MBED_PIN __mbedpin__(DOUT7_PORT, DOUT7_BIT) +#define DOUT7_GPIOREG __gpioreg__(DOUT7_PORT) +#if (DOUT7_BIT < 16) +#define DOUT7_PINHALF L +#else +#define DOUT7_PINHALF H +#endif +#define DOUT7_PINCON __pincon__(DOUT7_PORT, DOUT7_PINHALF) +#define DIO53 53 +#define DIO53_MBED_PIN DOUT7_MBED_PIN +#define DIO53_PORT DOUT7_PORT +#define DIO53_BIT DOUT7_BIT +#define DIO53_GPIOREG DOUT7_GPIOREG +#define DIO53_PINHALF DOUT7_PINHALF +#define DIO53_PINCON DOUT7_PINCON +#endif +#if (defined(DOUT8_PORT) && defined(DOUT8_BIT)) +#define DOUT8 54 +#define DOUT8_MBED_PIN __mbedpin__(DOUT8_PORT, DOUT8_BIT) +#define DOUT8_GPIOREG __gpioreg__(DOUT8_PORT) +#if (DOUT8_BIT < 16) +#define DOUT8_PINHALF L +#else +#define DOUT8_PINHALF H +#endif +#define DOUT8_PINCON __pincon__(DOUT8_PORT, DOUT8_PINHALF) +#define DIO54 54 +#define DIO54_MBED_PIN DOUT8_MBED_PIN +#define DIO54_PORT DOUT8_PORT +#define DIO54_BIT DOUT8_BIT +#define DIO54_GPIOREG DOUT8_GPIOREG +#define DIO54_PINHALF DOUT8_PINHALF +#define DIO54_PINCON DOUT8_PINCON +#endif +#if (defined(DOUT9_PORT) && defined(DOUT9_BIT)) +#define DOUT9 55 +#define DOUT9_MBED_PIN __mbedpin__(DOUT9_PORT, DOUT9_BIT) +#define DOUT9_GPIOREG __gpioreg__(DOUT9_PORT) +#if (DOUT9_BIT < 16) +#define DOUT9_PINHALF L +#else +#define DOUT9_PINHALF H +#endif +#define DOUT9_PINCON __pincon__(DOUT9_PORT, DOUT9_PINHALF) +#define DIO55 55 +#define DIO55_MBED_PIN DOUT9_MBED_PIN +#define DIO55_PORT DOUT9_PORT +#define DIO55_BIT DOUT9_BIT +#define DIO55_GPIOREG DOUT9_GPIOREG +#define DIO55_PINHALF DOUT9_PINHALF +#define DIO55_PINCON DOUT9_PINCON +#endif +#if (defined(DOUT10_PORT) && defined(DOUT10_BIT)) +#define DOUT10 56 +#define DOUT10_MBED_PIN __mbedpin__(DOUT10_PORT, DOUT10_BIT) +#define DOUT10_GPIOREG __gpioreg__(DOUT10_PORT) +#if (DOUT10_BIT < 16) +#define DOUT10_PINHALF L +#else +#define DOUT10_PINHALF H +#endif +#define DOUT10_PINCON __pincon__(DOUT10_PORT, DOUT10_PINHALF) +#define DIO56 56 +#define DIO56_MBED_PIN DOUT10_MBED_PIN +#define DIO56_PORT DOUT10_PORT +#define DIO56_BIT DOUT10_BIT +#define DIO56_GPIOREG DOUT10_GPIOREG +#define DIO56_PINHALF DOUT10_PINHALF +#define DIO56_PINCON DOUT10_PINCON +#endif +#if (defined(DOUT11_PORT) && defined(DOUT11_BIT)) +#define DOUT11 57 +#define DOUT11_MBED_PIN __mbedpin__(DOUT11_PORT, DOUT11_BIT) +#define DOUT11_GPIOREG __gpioreg__(DOUT11_PORT) +#if (DOUT11_BIT < 16) +#define DOUT11_PINHALF L +#else +#define DOUT11_PINHALF H +#endif +#define DOUT11_PINCON __pincon__(DOUT11_PORT, DOUT11_PINHALF) +#define DIO57 57 +#define DIO57_MBED_PIN DOUT11_MBED_PIN +#define DIO57_PORT DOUT11_PORT +#define DIO57_BIT DOUT11_BIT +#define DIO57_GPIOREG DOUT11_GPIOREG +#define DIO57_PINHALF DOUT11_PINHALF +#define DIO57_PINCON DOUT11_PINCON +#endif +#if (defined(DOUT12_PORT) && defined(DOUT12_BIT)) +#define DOUT12 58 +#define DOUT12_MBED_PIN __mbedpin__(DOUT12_PORT, DOUT12_BIT) +#define DOUT12_GPIOREG __gpioreg__(DOUT12_PORT) +#if (DOUT12_BIT < 16) +#define DOUT12_PINHALF L +#else +#define DOUT12_PINHALF H +#endif +#define DOUT12_PINCON __pincon__(DOUT12_PORT, DOUT12_PINHALF) +#define DIO58 58 +#define DIO58_MBED_PIN DOUT12_MBED_PIN +#define DIO58_PORT DOUT12_PORT +#define DIO58_BIT DOUT12_BIT +#define DIO58_GPIOREG DOUT12_GPIOREG +#define DIO58_PINHALF DOUT12_PINHALF +#define DIO58_PINCON DOUT12_PINCON +#endif +#if (defined(DOUT13_PORT) && defined(DOUT13_BIT)) +#define DOUT13 59 +#define DOUT13_MBED_PIN __mbedpin__(DOUT13_PORT, DOUT13_BIT) +#define DOUT13_GPIOREG __gpioreg__(DOUT13_PORT) +#if (DOUT13_BIT < 16) +#define DOUT13_PINHALF L +#else +#define DOUT13_PINHALF H +#endif +#define DOUT13_PINCON __pincon__(DOUT13_PORT, DOUT13_PINHALF) +#define DIO59 59 +#define DIO59_MBED_PIN DOUT13_MBED_PIN +#define DIO59_PORT DOUT13_PORT +#define DIO59_BIT DOUT13_BIT +#define DIO59_GPIOREG DOUT13_GPIOREG +#define DIO59_PINHALF DOUT13_PINHALF +#define DIO59_PINCON DOUT13_PINCON +#endif +#if (defined(DOUT14_PORT) && defined(DOUT14_BIT)) +#define DOUT14 60 +#define DOUT14_MBED_PIN __mbedpin__(DOUT14_PORT, DOUT14_BIT) +#define DOUT14_GPIOREG __gpioreg__(DOUT14_PORT) +#if (DOUT14_BIT < 16) +#define DOUT14_PINHALF L +#else +#define DOUT14_PINHALF H +#endif +#define DOUT14_PINCON __pincon__(DOUT14_PORT, DOUT14_PINHALF) +#define DIO60 60 +#define DIO60_MBED_PIN DOUT14_MBED_PIN +#define DIO60_PORT DOUT14_PORT +#define DIO60_BIT DOUT14_BIT +#define DIO60_GPIOREG DOUT14_GPIOREG +#define DIO60_PINHALF DOUT14_PINHALF +#define DIO60_PINCON DOUT14_PINCON +#endif +#if (defined(DOUT15_PORT) && defined(DOUT15_BIT)) +#define DOUT15 61 +#define DOUT15_MBED_PIN __mbedpin__(DOUT15_PORT, DOUT15_BIT) +#define DOUT15_GPIOREG __gpioreg__(DOUT15_PORT) +#if (DOUT15_BIT < 16) +#define DOUT15_PINHALF L +#else +#define DOUT15_PINHALF H +#endif +#define DOUT15_PINCON __pincon__(DOUT15_PORT, DOUT15_PINHALF) +#define DIO61 61 +#define DIO61_MBED_PIN DOUT15_MBED_PIN +#define DIO61_PORT DOUT15_PORT +#define DIO61_BIT DOUT15_BIT +#define DIO61_GPIOREG DOUT15_GPIOREG +#define DIO61_PINHALF DOUT15_PINHALF +#define DIO61_PINCON DOUT15_PINCON +#endif +#if (defined(DOUT16_PORT) && defined(DOUT16_BIT)) +#define DOUT16 62 +#define DOUT16_MBED_PIN __mbedpin__(DOUT16_PORT, DOUT16_BIT) +#define DOUT16_GPIOREG __gpioreg__(DOUT16_PORT) +#if (DOUT16_BIT < 16) +#define DOUT16_PINHALF L +#else +#define DOUT16_PINHALF H +#endif +#define DOUT16_PINCON __pincon__(DOUT16_PORT, DOUT16_PINHALF) +#define DIO62 62 +#define DIO62_MBED_PIN DOUT16_MBED_PIN +#define DIO62_PORT DOUT16_PORT +#define DIO62_BIT DOUT16_BIT +#define DIO62_GPIOREG DOUT16_GPIOREG +#define DIO62_PINHALF DOUT16_PINHALF +#define DIO62_PINCON DOUT16_PINCON +#endif +#if (defined(DOUT17_PORT) && defined(DOUT17_BIT)) +#define DOUT17 63 +#define DOUT17_MBED_PIN __mbedpin__(DOUT17_PORT, DOUT17_BIT) +#define DOUT17_GPIOREG __gpioreg__(DOUT17_PORT) +#if (DOUT17_BIT < 16) +#define DOUT17_PINHALF L +#else +#define DOUT17_PINHALF H +#endif +#define DOUT17_PINCON __pincon__(DOUT17_PORT, DOUT17_PINHALF) +#define DIO63 63 +#define DIO63_MBED_PIN DOUT17_MBED_PIN +#define DIO63_PORT DOUT17_PORT +#define DIO63_BIT DOUT17_BIT +#define DIO63_GPIOREG DOUT17_GPIOREG +#define DIO63_PINHALF DOUT17_PINHALF +#define DIO63_PINCON DOUT17_PINCON +#endif +#if (defined(DOUT18_PORT) && defined(DOUT18_BIT)) +#define DOUT18 64 +#define DOUT18_MBED_PIN __mbedpin__(DOUT18_PORT, DOUT18_BIT) +#define DOUT18_GPIOREG __gpioreg__(DOUT18_PORT) +#if (DOUT18_BIT < 16) +#define DOUT18_PINHALF L +#else +#define DOUT18_PINHALF H +#endif +#define DOUT18_PINCON __pincon__(DOUT18_PORT, DOUT18_PINHALF) +#define DIO64 64 +#define DIO64_MBED_PIN DOUT18_MBED_PIN +#define DIO64_PORT DOUT18_PORT +#define DIO64_BIT DOUT18_BIT +#define DIO64_GPIOREG DOUT18_GPIOREG +#define DIO64_PINHALF DOUT18_PINHALF +#define DIO64_PINCON DOUT18_PINCON +#endif +#if (defined(DOUT19_PORT) && defined(DOUT19_BIT)) +#define DOUT19 65 +#define DOUT19_MBED_PIN __mbedpin__(DOUT19_PORT, DOUT19_BIT) +#define DOUT19_GPIOREG __gpioreg__(DOUT19_PORT) +#if (DOUT19_BIT < 16) +#define DOUT19_PINHALF L +#else +#define DOUT19_PINHALF H +#endif +#define DOUT19_PINCON __pincon__(DOUT19_PORT, DOUT19_PINHALF) +#define DIO65 65 +#define DIO65_MBED_PIN DOUT19_MBED_PIN +#define DIO65_PORT DOUT19_PORT +#define DIO65_BIT DOUT19_BIT +#define DIO65_GPIOREG DOUT19_GPIOREG +#define DIO65_PINHALF DOUT19_PINHALF +#define DIO65_PINCON DOUT19_PINCON +#endif +#if (defined(DOUT20_PORT) && defined(DOUT20_BIT)) +#define DOUT20 66 +#define DOUT20_MBED_PIN __mbedpin__(DOUT20_PORT, DOUT20_BIT) +#define DOUT20_GPIOREG __gpioreg__(DOUT20_PORT) +#if (DOUT20_BIT < 16) +#define DOUT20_PINHALF L +#else +#define DOUT20_PINHALF H +#endif +#define DOUT20_PINCON __pincon__(DOUT20_PORT, DOUT20_PINHALF) +#define DIO66 66 +#define DIO66_MBED_PIN DOUT20_MBED_PIN +#define DIO66_PORT DOUT20_PORT +#define DIO66_BIT DOUT20_BIT +#define DIO66_GPIOREG DOUT20_GPIOREG +#define DIO66_PINHALF DOUT20_PINHALF +#define DIO66_PINCON DOUT20_PINCON +#endif +#if (defined(DOUT21_PORT) && defined(DOUT21_BIT)) +#define DOUT21 67 +#define DOUT21_MBED_PIN __mbedpin__(DOUT21_PORT, DOUT21_BIT) +#define DOUT21_GPIOREG __gpioreg__(DOUT21_PORT) +#if (DOUT21_BIT < 16) +#define DOUT21_PINHALF L +#else +#define DOUT21_PINHALF H +#endif +#define DOUT21_PINCON __pincon__(DOUT21_PORT, DOUT21_PINHALF) +#define DIO67 67 +#define DIO67_MBED_PIN DOUT21_MBED_PIN +#define DIO67_PORT DOUT21_PORT +#define DIO67_BIT DOUT21_BIT +#define DIO67_GPIOREG DOUT21_GPIOREG +#define DIO67_PINHALF DOUT21_PINHALF +#define DIO67_PINCON DOUT21_PINCON +#endif +#if (defined(DOUT22_PORT) && defined(DOUT22_BIT)) +#define DOUT22 68 +#define DOUT22_MBED_PIN __mbedpin__(DOUT22_PORT, DOUT22_BIT) +#define DOUT22_GPIOREG __gpioreg__(DOUT22_PORT) +#if (DOUT22_BIT < 16) +#define DOUT22_PINHALF L +#else +#define DOUT22_PINHALF H +#endif +#define DOUT22_PINCON __pincon__(DOUT22_PORT, DOUT22_PINHALF) +#define DIO68 68 +#define DIO68_MBED_PIN DOUT22_MBED_PIN +#define DIO68_PORT DOUT22_PORT +#define DIO68_BIT DOUT22_BIT +#define DIO68_GPIOREG DOUT22_GPIOREG +#define DIO68_PINHALF DOUT22_PINHALF +#define DIO68_PINCON DOUT22_PINCON +#endif +#if (defined(DOUT23_PORT) && defined(DOUT23_BIT)) +#define DOUT23 69 +#define DOUT23_MBED_PIN __mbedpin__(DOUT23_PORT, DOUT23_BIT) +#define DOUT23_GPIOREG __gpioreg__(DOUT23_PORT) +#if (DOUT23_BIT < 16) +#define DOUT23_PINHALF L +#else +#define DOUT23_PINHALF H +#endif +#define DOUT23_PINCON __pincon__(DOUT23_PORT, DOUT23_PINHALF) +#define DIO69 69 +#define DIO69_MBED_PIN DOUT23_MBED_PIN +#define DIO69_PORT DOUT23_PORT +#define DIO69_BIT DOUT23_BIT +#define DIO69_GPIOREG DOUT23_GPIOREG +#define DIO69_PINHALF DOUT23_PINHALF +#define DIO69_PINCON DOUT23_PINCON +#endif +#if (defined(DOUT24_PORT) && defined(DOUT24_BIT)) +#define DOUT24 70 +#define DOUT24_MBED_PIN __mbedpin__(DOUT24_PORT, DOUT24_BIT) +#define DOUT24_GPIOREG __gpioreg__(DOUT24_PORT) +#if (DOUT24_BIT < 16) +#define DOUT24_PINHALF L +#else +#define DOUT24_PINHALF H +#endif +#define DOUT24_PINCON __pincon__(DOUT24_PORT, DOUT24_PINHALF) +#define DIO70 70 +#define DIO70_MBED_PIN DOUT24_MBED_PIN +#define DIO70_PORT DOUT24_PORT +#define DIO70_BIT DOUT24_BIT +#define DIO70_GPIOREG DOUT24_GPIOREG +#define DIO70_PINHALF DOUT24_PINHALF +#define DIO70_PINCON DOUT24_PINCON +#endif +#if (defined(DOUT25_PORT) && defined(DOUT25_BIT)) +#define DOUT25 71 +#define DOUT25_MBED_PIN __mbedpin__(DOUT25_PORT, DOUT25_BIT) +#define DOUT25_GPIOREG __gpioreg__(DOUT25_PORT) +#if (DOUT25_BIT < 16) +#define DOUT25_PINHALF L +#else +#define DOUT25_PINHALF H +#endif +#define DOUT25_PINCON __pincon__(DOUT25_PORT, DOUT25_PINHALF) +#define DIO71 71 +#define DIO71_MBED_PIN DOUT25_MBED_PIN +#define DIO71_PORT DOUT25_PORT +#define DIO71_BIT DOUT25_BIT +#define DIO71_GPIOREG DOUT25_GPIOREG +#define DIO71_PINHALF DOUT25_PINHALF +#define DIO71_PINCON DOUT25_PINCON +#endif +#if (defined(DOUT26_PORT) && defined(DOUT26_BIT)) +#define DOUT26 72 +#define DOUT26_MBED_PIN __mbedpin__(DOUT26_PORT, DOUT26_BIT) +#define DOUT26_GPIOREG __gpioreg__(DOUT26_PORT) +#if (DOUT26_BIT < 16) +#define DOUT26_PINHALF L +#else +#define DOUT26_PINHALF H +#endif +#define DOUT26_PINCON __pincon__(DOUT26_PORT, DOUT26_PINHALF) +#define DIO72 72 +#define DIO72_MBED_PIN DOUT26_MBED_PIN +#define DIO72_PORT DOUT26_PORT +#define DIO72_BIT DOUT26_BIT +#define DIO72_GPIOREG DOUT26_GPIOREG +#define DIO72_PINHALF DOUT26_PINHALF +#define DIO72_PINCON DOUT26_PINCON +#endif +#if (defined(DOUT27_PORT) && defined(DOUT27_BIT)) +#define DOUT27 73 +#define DOUT27_MBED_PIN __mbedpin__(DOUT27_PORT, DOUT27_BIT) +#define DOUT27_GPIOREG __gpioreg__(DOUT27_PORT) +#if (DOUT27_BIT < 16) +#define DOUT27_PINHALF L +#else +#define DOUT27_PINHALF H +#endif +#define DOUT27_PINCON __pincon__(DOUT27_PORT, DOUT27_PINHALF) +#define DIO73 73 +#define DIO73_MBED_PIN DOUT27_MBED_PIN +#define DIO73_PORT DOUT27_PORT +#define DIO73_BIT DOUT27_BIT +#define DIO73_GPIOREG DOUT27_GPIOREG +#define DIO73_PINHALF DOUT27_PINHALF +#define DIO73_PINCON DOUT27_PINCON +#endif +#if (defined(DOUT28_PORT) && defined(DOUT28_BIT)) +#define DOUT28 74 +#define DOUT28_MBED_PIN __mbedpin__(DOUT28_PORT, DOUT28_BIT) +#define DOUT28_GPIOREG __gpioreg__(DOUT28_PORT) +#if (DOUT28_BIT < 16) +#define DOUT28_PINHALF L +#else +#define DOUT28_PINHALF H +#endif +#define DOUT28_PINCON __pincon__(DOUT28_PORT, DOUT28_PINHALF) +#define DIO74 74 +#define DIO74_MBED_PIN DOUT28_MBED_PIN +#define DIO74_PORT DOUT28_PORT +#define DIO74_BIT DOUT28_BIT +#define DIO74_GPIOREG DOUT28_GPIOREG +#define DIO74_PINHALF DOUT28_PINHALF +#define DIO74_PINCON DOUT28_PINCON +#endif +#if (defined(DOUT29_PORT) && defined(DOUT29_BIT)) +#define DOUT29 75 +#define DOUT29_MBED_PIN __mbedpin__(DOUT29_PORT, DOUT29_BIT) +#define DOUT29_GPIOREG __gpioreg__(DOUT29_PORT) +#if (DOUT29_BIT < 16) +#define DOUT29_PINHALF L +#else +#define DOUT29_PINHALF H +#endif +#define DOUT29_PINCON __pincon__(DOUT29_PORT, DOUT29_PINHALF) +#define DIO75 75 +#define DIO75_MBED_PIN DOUT29_MBED_PIN +#define DIO75_PORT DOUT29_PORT +#define DIO75_BIT DOUT29_BIT +#define DIO75_GPIOREG DOUT29_GPIOREG +#define DIO75_PINHALF DOUT29_PINHALF +#define DIO75_PINCON DOUT29_PINCON +#endif +#if (defined(DOUT30_PORT) && defined(DOUT30_BIT)) +#define DOUT30 76 +#define DOUT30_MBED_PIN __mbedpin__(DOUT30_PORT, DOUT30_BIT) +#define DOUT30_GPIOREG __gpioreg__(DOUT30_PORT) +#if (DOUT30_BIT < 16) +#define DOUT30_PINHALF L +#else +#define DOUT30_PINHALF H +#endif +#define DOUT30_PINCON __pincon__(DOUT30_PORT, DOUT30_PINHALF) +#define DIO76 76 +#define DIO76_MBED_PIN DOUT30_MBED_PIN +#define DIO76_PORT DOUT30_PORT +#define DIO76_BIT DOUT30_BIT +#define DIO76_GPIOREG DOUT30_GPIOREG +#define DIO76_PINHALF DOUT30_PINHALF +#define DIO76_PINCON DOUT30_PINCON +#endif +#if (defined(DOUT31_PORT) && defined(DOUT31_BIT)) +#define DOUT31 77 +#define DOUT31_MBED_PIN __mbedpin__(DOUT31_PORT, DOUT31_BIT) +#define DOUT31_GPIOREG __gpioreg__(DOUT31_PORT) +#if (DOUT31_BIT < 16) +#define DOUT31_PINHALF L +#else +#define DOUT31_PINHALF H +#endif +#define DOUT31_PINCON __pincon__(DOUT31_PORT, DOUT31_PINHALF) +#define DIO77 77 +#define DIO77_MBED_PIN DOUT31_MBED_PIN +#define DIO77_PORT DOUT31_PORT +#define DIO77_BIT DOUT31_BIT +#define DIO77_GPIOREG DOUT31_GPIOREG +#define DIO77_PINHALF DOUT31_PINHALF +#define DIO77_PINCON DOUT31_PINCON +#endif +#if (defined(LIMIT_X_PORT) && defined(LIMIT_X_BIT)) +#define LIMIT_X 100 +#define LIMIT_X_MBED_PIN __mbedpin__(LIMIT_X_PORT, LIMIT_X_BIT) +#define LIMIT_X_GPIOREG __gpioreg__(LIMIT_X_PORT) +#if (LIMIT_X_BIT < 16) +#define LIMIT_X_PINHALF L +#else +#define LIMIT_X_PINHALF H +#endif +#define LIMIT_X_PINCON __pincon__(LIMIT_X_PORT, LIMIT_X_PINHALF) +#define DIO100 100 +#define DIO100_MBED_PIN LIMIT_X_MBED_PIN +#define DIO100_PORT LIMIT_X_PORT +#define DIO100_BIT LIMIT_X_BIT +#define DIO100_GPIOREG LIMIT_X_GPIOREG +#define DIO100_PINHALF LIMIT_X_PINHALF +#define DIO100_PINCON LIMIT_X_PINCON +#endif +#if (defined(LIMIT_Y_PORT) && defined(LIMIT_Y_BIT)) +#define LIMIT_Y 101 +#define LIMIT_Y_MBED_PIN __mbedpin__(LIMIT_Y_PORT, LIMIT_Y_BIT) +#define LIMIT_Y_GPIOREG __gpioreg__(LIMIT_Y_PORT) +#if (LIMIT_Y_BIT < 16) +#define LIMIT_Y_PINHALF L +#else +#define LIMIT_Y_PINHALF H +#endif +#define LIMIT_Y_PINCON __pincon__(LIMIT_Y_PORT, LIMIT_Y_PINHALF) +#define DIO101 101 +#define DIO101_MBED_PIN LIMIT_Y_MBED_PIN +#define DIO101_PORT LIMIT_Y_PORT +#define DIO101_BIT LIMIT_Y_BIT +#define DIO101_GPIOREG LIMIT_Y_GPIOREG +#define DIO101_PINHALF LIMIT_Y_PINHALF +#define DIO101_PINCON LIMIT_Y_PINCON +#endif +#if (defined(LIMIT_Z_PORT) && defined(LIMIT_Z_BIT)) +#define LIMIT_Z 102 +#define LIMIT_Z_MBED_PIN __mbedpin__(LIMIT_Z_PORT, LIMIT_Z_BIT) +#define LIMIT_Z_GPIOREG __gpioreg__(LIMIT_Z_PORT) +#if (LIMIT_Z_BIT < 16) +#define LIMIT_Z_PINHALF L +#else +#define LIMIT_Z_PINHALF H +#endif +#define LIMIT_Z_PINCON __pincon__(LIMIT_Z_PORT, LIMIT_Z_PINHALF) +#define DIO102 102 +#define DIO102_MBED_PIN LIMIT_Z_MBED_PIN +#define DIO102_PORT LIMIT_Z_PORT +#define DIO102_BIT LIMIT_Z_BIT +#define DIO102_GPIOREG LIMIT_Z_GPIOREG +#define DIO102_PINHALF LIMIT_Z_PINHALF +#define DIO102_PINCON LIMIT_Z_PINCON +#endif +#if (defined(LIMIT_X2_PORT) && defined(LIMIT_X2_BIT)) +#define LIMIT_X2 103 +#define LIMIT_X2_MBED_PIN __mbedpin__(LIMIT_X2_PORT, LIMIT_X2_BIT) +#define LIMIT_X2_GPIOREG __gpioreg__(LIMIT_X2_PORT) +#if (LIMIT_X2_BIT < 16) +#define LIMIT_X2_PINHALF L +#else +#define LIMIT_X2_PINHALF H +#endif +#define LIMIT_X2_PINCON __pincon__(LIMIT_X2_PORT, LIMIT_X2_PINHALF) +#define DIO103 103 +#define DIO103_MBED_PIN LIMIT_X2_MBED_PIN +#define DIO103_PORT LIMIT_X2_PORT +#define DIO103_BIT LIMIT_X2_BIT +#define DIO103_GPIOREG LIMIT_X2_GPIOREG +#define DIO103_PINHALF LIMIT_X2_PINHALF +#define DIO103_PINCON LIMIT_X2_PINCON +#endif +#if (defined(LIMIT_Y2_PORT) && defined(LIMIT_Y2_BIT)) +#define LIMIT_Y2 104 +#define LIMIT_Y2_MBED_PIN __mbedpin__(LIMIT_Y2_PORT, LIMIT_Y2_BIT) +#define LIMIT_Y2_GPIOREG __gpioreg__(LIMIT_Y2_PORT) +#if (LIMIT_Y2_BIT < 16) +#define LIMIT_Y2_PINHALF L +#else +#define LIMIT_Y2_PINHALF H +#endif +#define LIMIT_Y2_PINCON __pincon__(LIMIT_Y2_PORT, LIMIT_Y2_PINHALF) +#define DIO104 104 +#define DIO104_MBED_PIN LIMIT_Y2_MBED_PIN +#define DIO104_PORT LIMIT_Y2_PORT +#define DIO104_BIT LIMIT_Y2_BIT +#define DIO104_GPIOREG LIMIT_Y2_GPIOREG +#define DIO104_PINHALF LIMIT_Y2_PINHALF +#define DIO104_PINCON LIMIT_Y2_PINCON +#endif +#if (defined(LIMIT_Z2_PORT) && defined(LIMIT_Z2_BIT)) +#define LIMIT_Z2 105 +#define LIMIT_Z2_MBED_PIN __mbedpin__(LIMIT_Z2_PORT, LIMIT_Z2_BIT) +#define LIMIT_Z2_GPIOREG __gpioreg__(LIMIT_Z2_PORT) +#if (LIMIT_Z2_BIT < 16) +#define LIMIT_Z2_PINHALF L +#else +#define LIMIT_Z2_PINHALF H +#endif +#define LIMIT_Z2_PINCON __pincon__(LIMIT_Z2_PORT, LIMIT_Z2_PINHALF) +#define DIO105 105 +#define DIO105_MBED_PIN LIMIT_Z2_MBED_PIN +#define DIO105_PORT LIMIT_Z2_PORT +#define DIO105_BIT LIMIT_Z2_BIT +#define DIO105_GPIOREG LIMIT_Z2_GPIOREG +#define DIO105_PINHALF LIMIT_Z2_PINHALF +#define DIO105_PINCON LIMIT_Z2_PINCON +#endif +#if (defined(LIMIT_A_PORT) && defined(LIMIT_A_BIT)) +#define LIMIT_A 106 +#define LIMIT_A_MBED_PIN __mbedpin__(LIMIT_A_PORT, LIMIT_A_BIT) +#define LIMIT_A_GPIOREG __gpioreg__(LIMIT_A_PORT) +#if (LIMIT_A_BIT < 16) +#define LIMIT_A_PINHALF L +#else +#define LIMIT_A_PINHALF H +#endif +#define LIMIT_A_PINCON __pincon__(LIMIT_A_PORT, LIMIT_A_PINHALF) +#define DIO106 106 +#define DIO106_MBED_PIN LIMIT_A_MBED_PIN +#define DIO106_PORT LIMIT_A_PORT +#define DIO106_BIT LIMIT_A_BIT +#define DIO106_GPIOREG LIMIT_A_GPIOREG +#define DIO106_PINHALF LIMIT_A_PINHALF +#define DIO106_PINCON LIMIT_A_PINCON +#endif +#if (defined(LIMIT_B_PORT) && defined(LIMIT_B_BIT)) +#define LIMIT_B 107 +#define LIMIT_B_MBED_PIN __mbedpin__(LIMIT_B_PORT, LIMIT_B_BIT) +#define LIMIT_B_GPIOREG __gpioreg__(LIMIT_B_PORT) +#if (LIMIT_B_BIT < 16) +#define LIMIT_B_PINHALF L +#else +#define LIMIT_B_PINHALF H +#endif +#define LIMIT_B_PINCON __pincon__(LIMIT_B_PORT, LIMIT_B_PINHALF) +#define DIO107 107 +#define DIO107_MBED_PIN LIMIT_B_MBED_PIN +#define DIO107_PORT LIMIT_B_PORT +#define DIO107_BIT LIMIT_B_BIT +#define DIO107_GPIOREG LIMIT_B_GPIOREG +#define DIO107_PINHALF LIMIT_B_PINHALF +#define DIO107_PINCON LIMIT_B_PINCON +#endif +#if (defined(LIMIT_C_PORT) && defined(LIMIT_C_BIT)) +#define LIMIT_C 108 +#define LIMIT_C_MBED_PIN __mbedpin__(LIMIT_C_PORT, LIMIT_C_BIT) +#define LIMIT_C_GPIOREG __gpioreg__(LIMIT_C_PORT) +#if (LIMIT_C_BIT < 16) +#define LIMIT_C_PINHALF L +#else +#define LIMIT_C_PINHALF H +#endif +#define LIMIT_C_PINCON __pincon__(LIMIT_C_PORT, LIMIT_C_PINHALF) +#define DIO108 108 +#define DIO108_MBED_PIN LIMIT_C_MBED_PIN +#define DIO108_PORT LIMIT_C_PORT +#define DIO108_BIT LIMIT_C_BIT +#define DIO108_GPIOREG LIMIT_C_GPIOREG +#define DIO108_PINHALF LIMIT_C_PINHALF +#define DIO108_PINCON LIMIT_C_PINCON +#endif +#if (defined(PROBE_PORT) && defined(PROBE_BIT)) +#define PROBE 109 +#define PROBE_MBED_PIN __mbedpin__(PROBE_PORT, PROBE_BIT) +#define PROBE_GPIOREG __gpioreg__(PROBE_PORT) +#if (PROBE_BIT < 16) +#define PROBE_PINHALF L +#else +#define PROBE_PINHALF H +#endif +#define PROBE_PINCON __pincon__(PROBE_PORT, PROBE_PINHALF) +#define DIO109 109 +#define DIO109_MBED_PIN PROBE_MBED_PIN +#define DIO109_PORT PROBE_PORT +#define DIO109_BIT PROBE_BIT +#define DIO109_GPIOREG PROBE_GPIOREG +#define DIO109_PINHALF PROBE_PINHALF +#define DIO109_PINCON PROBE_PINCON +#endif +#if (defined(ESTOP_PORT) && defined(ESTOP_BIT)) +#define ESTOP 110 +#define ESTOP_MBED_PIN __mbedpin__(ESTOP_PORT, ESTOP_BIT) +#define ESTOP_GPIOREG __gpioreg__(ESTOP_PORT) +#if (ESTOP_BIT < 16) +#define ESTOP_PINHALF L +#else +#define ESTOP_PINHALF H +#endif +#define ESTOP_PINCON __pincon__(ESTOP_PORT, ESTOP_PINHALF) +#define DIO110 110 +#define DIO110_MBED_PIN ESTOP_MBED_PIN +#define DIO110_PORT ESTOP_PORT +#define DIO110_BIT ESTOP_BIT +#define DIO110_GPIOREG ESTOP_GPIOREG +#define DIO110_PINHALF ESTOP_PINHALF +#define DIO110_PINCON ESTOP_PINCON +#endif +#if (defined(SAFETY_DOOR_PORT) && defined(SAFETY_DOOR_BIT)) +#define SAFETY_DOOR 111 +#define SAFETY_DOOR_MBED_PIN __mbedpin__(SAFETY_DOOR_PORT, SAFETY_DOOR_BIT) +#define SAFETY_DOOR_GPIOREG __gpioreg__(SAFETY_DOOR_PORT) +#if (SAFETY_DOOR_BIT < 16) +#define SAFETY_DOOR_PINHALF L +#else +#define SAFETY_DOOR_PINHALF H +#endif +#define SAFETY_DOOR_PINCON __pincon__(SAFETY_DOOR_PORT, SAFETY_DOOR_PINHALF) +#define DIO111 111 +#define DIO111_MBED_PIN SAFETY_DOOR_MBED_PIN +#define DIO111_PORT SAFETY_DOOR_PORT +#define DIO111_BIT SAFETY_DOOR_BIT +#define DIO111_GPIOREG SAFETY_DOOR_GPIOREG +#define DIO111_PINHALF SAFETY_DOOR_PINHALF +#define DIO111_PINCON SAFETY_DOOR_PINCON +#endif +#if (defined(FHOLD_PORT) && defined(FHOLD_BIT)) +#define FHOLD 112 +#define FHOLD_MBED_PIN __mbedpin__(FHOLD_PORT, FHOLD_BIT) +#define FHOLD_GPIOREG __gpioreg__(FHOLD_PORT) +#if (FHOLD_BIT < 16) +#define FHOLD_PINHALF L +#else +#define FHOLD_PINHALF H +#endif +#define FHOLD_PINCON __pincon__(FHOLD_PORT, FHOLD_PINHALF) +#define DIO112 112 +#define DIO112_MBED_PIN FHOLD_MBED_PIN +#define DIO112_PORT FHOLD_PORT +#define DIO112_BIT FHOLD_BIT +#define DIO112_GPIOREG FHOLD_GPIOREG +#define DIO112_PINHALF FHOLD_PINHALF +#define DIO112_PINCON FHOLD_PINCON +#endif +#if (defined(CS_RES_PORT) && defined(CS_RES_BIT)) +#define CS_RES 113 +#define CS_RES_MBED_PIN __mbedpin__(CS_RES_PORT, CS_RES_BIT) +#define CS_RES_GPIOREG __gpioreg__(CS_RES_PORT) +#if (CS_RES_BIT < 16) +#define CS_RES_PINHALF L +#else +#define CS_RES_PINHALF H +#endif +#define CS_RES_PINCON __pincon__(CS_RES_PORT, CS_RES_PINHALF) +#define DIO113 113 +#define DIO113_MBED_PIN CS_RES_MBED_PIN +#define DIO113_PORT CS_RES_PORT +#define DIO113_BIT CS_RES_BIT +#define DIO113_GPIOREG CS_RES_GPIOREG +#define DIO113_PINHALF CS_RES_PINHALF +#define DIO113_PINCON CS_RES_PINCON +#endif +#if (defined(ANALOG0_PORT) && defined(ANALOG0_BIT)) +#define ANALOG0 114 +#define ANALOG0_MBED_PIN __mbedpin__(ANALOG0_PORT, ANALOG0_BIT) +#define ANALOG0_GPIOREG __gpioreg__(ANALOG0_PORT) +#if (ANALOG0_BIT < 16) +#define ANALOG0_PINHALF L +#else +#define ANALOG0_PINHALF H +#endif +#define ANALOG0_PINCON __pincon__(ANALOG0_PORT, ANALOG0_PINHALF) +#define DIO114 114 +#define DIO114_MBED_PIN ANALOG0_MBED_PIN +#define DIO114_PORT ANALOG0_PORT +#define DIO114_BIT ANALOG0_BIT +#define DIO114_GPIOREG ANALOG0_GPIOREG +#define DIO114_PINHALF ANALOG0_PINHALF +#define DIO114_PINCON ANALOG0_PINCON +#endif +#if (defined(ANALOG1_PORT) && defined(ANALOG1_BIT)) +#define ANALOG1 115 +#define ANALOG1_MBED_PIN __mbedpin__(ANALOG1_PORT, ANALOG1_BIT) +#define ANALOG1_GPIOREG __gpioreg__(ANALOG1_PORT) +#if (ANALOG1_BIT < 16) +#define ANALOG1_PINHALF L +#else +#define ANALOG1_PINHALF H +#endif +#define ANALOG1_PINCON __pincon__(ANALOG1_PORT, ANALOG1_PINHALF) +#define DIO115 115 +#define DIO115_MBED_PIN ANALOG1_MBED_PIN +#define DIO115_PORT ANALOG1_PORT +#define DIO115_BIT ANALOG1_BIT +#define DIO115_GPIOREG ANALOG1_GPIOREG +#define DIO115_PINHALF ANALOG1_PINHALF +#define DIO115_PINCON ANALOG1_PINCON +#endif +#if (defined(ANALOG2_PORT) && defined(ANALOG2_BIT)) +#define ANALOG2 116 +#define ANALOG2_MBED_PIN __mbedpin__(ANALOG2_PORT, ANALOG2_BIT) +#define ANALOG2_GPIOREG __gpioreg__(ANALOG2_PORT) +#if (ANALOG2_BIT < 16) +#define ANALOG2_PINHALF L +#else +#define ANALOG2_PINHALF H +#endif +#define ANALOG2_PINCON __pincon__(ANALOG2_PORT, ANALOG2_PINHALF) +#define DIO116 116 +#define DIO116_MBED_PIN ANALOG2_MBED_PIN +#define DIO116_PORT ANALOG2_PORT +#define DIO116_BIT ANALOG2_BIT +#define DIO116_GPIOREG ANALOG2_GPIOREG +#define DIO116_PINHALF ANALOG2_PINHALF +#define DIO116_PINCON ANALOG2_PINCON +#endif +#if (defined(ANALOG3_PORT) && defined(ANALOG3_BIT)) +#define ANALOG3 117 +#define ANALOG3_MBED_PIN __mbedpin__(ANALOG3_PORT, ANALOG3_BIT) +#define ANALOG3_GPIOREG __gpioreg__(ANALOG3_PORT) +#if (ANALOG3_BIT < 16) +#define ANALOG3_PINHALF L +#else +#define ANALOG3_PINHALF H +#endif +#define ANALOG3_PINCON __pincon__(ANALOG3_PORT, ANALOG3_PINHALF) +#define DIO117 117 +#define DIO117_MBED_PIN ANALOG3_MBED_PIN +#define DIO117_PORT ANALOG3_PORT +#define DIO117_BIT ANALOG3_BIT +#define DIO117_GPIOREG ANALOG3_GPIOREG +#define DIO117_PINHALF ANALOG3_PINHALF +#define DIO117_PINCON ANALOG3_PINCON +#endif +#if (defined(ANALOG4_PORT) && defined(ANALOG4_BIT)) +#define ANALOG4 118 +#define ANALOG4_MBED_PIN __mbedpin__(ANALOG4_PORT, ANALOG4_BIT) +#define ANALOG4_GPIOREG __gpioreg__(ANALOG4_PORT) +#if (ANALOG4_BIT < 16) +#define ANALOG4_PINHALF L +#else +#define ANALOG4_PINHALF H +#endif +#define ANALOG4_PINCON __pincon__(ANALOG4_PORT, ANALOG4_PINHALF) +#define DIO118 118 +#define DIO118_MBED_PIN ANALOG4_MBED_PIN +#define DIO118_PORT ANALOG4_PORT +#define DIO118_BIT ANALOG4_BIT +#define DIO118_GPIOREG ANALOG4_GPIOREG +#define DIO118_PINHALF ANALOG4_PINHALF +#define DIO118_PINCON ANALOG4_PINCON +#endif +#if (defined(ANALOG5_PORT) && defined(ANALOG5_BIT)) +#define ANALOG5 119 +#define ANALOG5_MBED_PIN __mbedpin__(ANALOG5_PORT, ANALOG5_BIT) +#define ANALOG5_GPIOREG __gpioreg__(ANALOG5_PORT) +#if (ANALOG5_BIT < 16) +#define ANALOG5_PINHALF L +#else +#define ANALOG5_PINHALF H +#endif +#define ANALOG5_PINCON __pincon__(ANALOG5_PORT, ANALOG5_PINHALF) +#define DIO119 119 +#define DIO119_MBED_PIN ANALOG5_MBED_PIN +#define DIO119_PORT ANALOG5_PORT +#define DIO119_BIT ANALOG5_BIT +#define DIO119_GPIOREG ANALOG5_GPIOREG +#define DIO119_PINHALF ANALOG5_PINHALF +#define DIO119_PINCON ANALOG5_PINCON +#endif +#if (defined(ANALOG6_PORT) && defined(ANALOG6_BIT)) +#define ANALOG6 120 +#define ANALOG6_MBED_PIN __mbedpin__(ANALOG6_PORT, ANALOG6_BIT) +#define ANALOG6_GPIOREG __gpioreg__(ANALOG6_PORT) +#if (ANALOG6_BIT < 16) +#define ANALOG6_PINHALF L +#else +#define ANALOG6_PINHALF H +#endif +#define ANALOG6_PINCON __pincon__(ANALOG6_PORT, ANALOG6_PINHALF) +#define DIO120 120 +#define DIO120_MBED_PIN ANALOG6_MBED_PIN +#define DIO120_PORT ANALOG6_PORT +#define DIO120_BIT ANALOG6_BIT +#define DIO120_GPIOREG ANALOG6_GPIOREG +#define DIO120_PINHALF ANALOG6_PINHALF +#define DIO120_PINCON ANALOG6_PINCON +#endif +#if (defined(ANALOG7_PORT) && defined(ANALOG7_BIT)) +#define ANALOG7 121 +#define ANALOG7_MBED_PIN __mbedpin__(ANALOG7_PORT, ANALOG7_BIT) +#define ANALOG7_GPIOREG __gpioreg__(ANALOG7_PORT) +#if (ANALOG7_BIT < 16) +#define ANALOG7_PINHALF L +#else +#define ANALOG7_PINHALF H +#endif +#define ANALOG7_PINCON __pincon__(ANALOG7_PORT, ANALOG7_PINHALF) +#define DIO121 121 +#define DIO121_MBED_PIN ANALOG7_MBED_PIN +#define DIO121_PORT ANALOG7_PORT +#define DIO121_BIT ANALOG7_BIT +#define DIO121_GPIOREG ANALOG7_GPIOREG +#define DIO121_PINHALF ANALOG7_PINHALF +#define DIO121_PINCON ANALOG7_PINCON +#endif +#if (defined(ANALOG8_PORT) && defined(ANALOG8_BIT)) +#define ANALOG8 122 +#define ANALOG8_MBED_PIN __mbedpin__(ANALOG8_PORT, ANALOG8_BIT) +#define ANALOG8_GPIOREG __gpioreg__(ANALOG8_PORT) +#if (ANALOG8_BIT < 16) +#define ANALOG8_PINHALF L +#else +#define ANALOG8_PINHALF H +#endif +#define ANALOG8_PINCON __pincon__(ANALOG8_PORT, ANALOG8_PINHALF) +#define DIO122 122 +#define DIO122_MBED_PIN ANALOG8_MBED_PIN +#define DIO122_PORT ANALOG8_PORT +#define DIO122_BIT ANALOG8_BIT +#define DIO122_GPIOREG ANALOG8_GPIOREG +#define DIO122_PINHALF ANALOG8_PINHALF +#define DIO122_PINCON ANALOG8_PINCON +#endif +#if (defined(ANALOG9_PORT) && defined(ANALOG9_BIT)) +#define ANALOG9 123 +#define ANALOG9_MBED_PIN __mbedpin__(ANALOG9_PORT, ANALOG9_BIT) +#define ANALOG9_GPIOREG __gpioreg__(ANALOG9_PORT) +#if (ANALOG9_BIT < 16) +#define ANALOG9_PINHALF L +#else +#define ANALOG9_PINHALF H +#endif +#define ANALOG9_PINCON __pincon__(ANALOG9_PORT, ANALOG9_PINHALF) +#define DIO123 123 +#define DIO123_MBED_PIN ANALOG9_MBED_PIN +#define DIO123_PORT ANALOG9_PORT +#define DIO123_BIT ANALOG9_BIT +#define DIO123_GPIOREG ANALOG9_GPIOREG +#define DIO123_PINHALF ANALOG9_PINHALF +#define DIO123_PINCON ANALOG9_PINCON +#endif +#if (defined(ANALOG10_PORT) && defined(ANALOG10_BIT)) +#define ANALOG10 124 +#define ANALOG10_MBED_PIN __mbedpin__(ANALOG10_PORT, ANALOG10_BIT) +#define ANALOG10_GPIOREG __gpioreg__(ANALOG10_PORT) +#if (ANALOG10_BIT < 16) +#define ANALOG10_PINHALF L +#else +#define ANALOG10_PINHALF H +#endif +#define ANALOG10_PINCON __pincon__(ANALOG10_PORT, ANALOG10_PINHALF) +#define DIO124 124 +#define DIO124_MBED_PIN ANALOG10_MBED_PIN +#define DIO124_PORT ANALOG10_PORT +#define DIO124_BIT ANALOG10_BIT +#define DIO124_GPIOREG ANALOG10_GPIOREG +#define DIO124_PINHALF ANALOG10_PINHALF +#define DIO124_PINCON ANALOG10_PINCON +#endif +#if (defined(ANALOG11_PORT) && defined(ANALOG11_BIT)) +#define ANALOG11 125 +#define ANALOG11_MBED_PIN __mbedpin__(ANALOG11_PORT, ANALOG11_BIT) +#define ANALOG11_GPIOREG __gpioreg__(ANALOG11_PORT) +#if (ANALOG11_BIT < 16) +#define ANALOG11_PINHALF L +#else +#define ANALOG11_PINHALF H +#endif +#define ANALOG11_PINCON __pincon__(ANALOG11_PORT, ANALOG11_PINHALF) +#define DIO125 125 +#define DIO125_MBED_PIN ANALOG11_MBED_PIN +#define DIO125_PORT ANALOG11_PORT +#define DIO125_BIT ANALOG11_BIT +#define DIO125_GPIOREG ANALOG11_GPIOREG +#define DIO125_PINHALF ANALOG11_PINHALF +#define DIO125_PINCON ANALOG11_PINCON +#endif +#if (defined(ANALOG12_PORT) && defined(ANALOG12_BIT)) +#define ANALOG12 126 +#define ANALOG12_MBED_PIN __mbedpin__(ANALOG12_PORT, ANALOG12_BIT) +#define ANALOG12_GPIOREG __gpioreg__(ANALOG12_PORT) +#if (ANALOG12_BIT < 16) +#define ANALOG12_PINHALF L +#else +#define ANALOG12_PINHALF H +#endif +#define ANALOG12_PINCON __pincon__(ANALOG12_PORT, ANALOG12_PINHALF) +#define DIO126 126 +#define DIO126_MBED_PIN ANALOG12_MBED_PIN +#define DIO126_PORT ANALOG12_PORT +#define DIO126_BIT ANALOG12_BIT +#define DIO126_GPIOREG ANALOG12_GPIOREG +#define DIO126_PINHALF ANALOG12_PINHALF +#define DIO126_PINCON ANALOG12_PINCON +#endif +#if (defined(ANALOG13_PORT) && defined(ANALOG13_BIT)) +#define ANALOG13 127 +#define ANALOG13_MBED_PIN __mbedpin__(ANALOG13_PORT, ANALOG13_BIT) +#define ANALOG13_GPIOREG __gpioreg__(ANALOG13_PORT) +#if (ANALOG13_BIT < 16) +#define ANALOG13_PINHALF L +#else +#define ANALOG13_PINHALF H +#endif +#define ANALOG13_PINCON __pincon__(ANALOG13_PORT, ANALOG13_PINHALF) +#define DIO127 127 +#define DIO127_MBED_PIN ANALOG13_MBED_PIN +#define DIO127_PORT ANALOG13_PORT +#define DIO127_BIT ANALOG13_BIT +#define DIO127_GPIOREG ANALOG13_GPIOREG +#define DIO127_PINHALF ANALOG13_PINHALF +#define DIO127_PINCON ANALOG13_PINCON +#endif +#if (defined(ANALOG14_PORT) && defined(ANALOG14_BIT)) +#define ANALOG14 128 +#define ANALOG14_MBED_PIN __mbedpin__(ANALOG14_PORT, ANALOG14_BIT) +#define ANALOG14_GPIOREG __gpioreg__(ANALOG14_PORT) +#if (ANALOG14_BIT < 16) +#define ANALOG14_PINHALF L +#else +#define ANALOG14_PINHALF H +#endif +#define ANALOG14_PINCON __pincon__(ANALOG14_PORT, ANALOG14_PINHALF) +#define DIO128 128 +#define DIO128_MBED_PIN ANALOG14_MBED_PIN +#define DIO128_PORT ANALOG14_PORT +#define DIO128_BIT ANALOG14_BIT +#define DIO128_GPIOREG ANALOG14_GPIOREG +#define DIO128_PINHALF ANALOG14_PINHALF +#define DIO128_PINCON ANALOG14_PINCON +#endif +#if (defined(ANALOG15_PORT) && defined(ANALOG15_BIT)) +#define ANALOG15 129 +#define ANALOG15_MBED_PIN __mbedpin__(ANALOG15_PORT, ANALOG15_BIT) +#define ANALOG15_GPIOREG __gpioreg__(ANALOG15_PORT) +#if (ANALOG15_BIT < 16) +#define ANALOG15_PINHALF L +#else +#define ANALOG15_PINHALF H +#endif +#define ANALOG15_PINCON __pincon__(ANALOG15_PORT, ANALOG15_PINHALF) +#define DIO129 129 +#define DIO129_MBED_PIN ANALOG15_MBED_PIN +#define DIO129_PORT ANALOG15_PORT +#define DIO129_BIT ANALOG15_BIT +#define DIO129_GPIOREG ANALOG15_GPIOREG +#define DIO129_PINHALF ANALOG15_PINHALF +#define DIO129_PINCON ANALOG15_PINCON +#endif +#if (defined(DIN0_PORT) && defined(DIN0_BIT)) +#define DIN0 130 +#define DIN0_MBED_PIN __mbedpin__(DIN0_PORT, DIN0_BIT) +#define DIN0_GPIOREG __gpioreg__(DIN0_PORT) +#if (DIN0_BIT < 16) +#define DIN0_PINHALF L +#else +#define DIN0_PINHALF H +#endif +#define DIN0_PINCON __pincon__(DIN0_PORT, DIN0_PINHALF) +#define DIO130 130 +#define DIO130_MBED_PIN DIN0_MBED_PIN +#define DIO130_PORT DIN0_PORT +#define DIO130_BIT DIN0_BIT +#define DIO130_GPIOREG DIN0_GPIOREG +#define DIO130_PINHALF DIN0_PINHALF +#define DIO130_PINCON DIN0_PINCON +#endif +#if (defined(DIN1_PORT) && defined(DIN1_BIT)) +#define DIN1 131 +#define DIN1_MBED_PIN __mbedpin__(DIN1_PORT, DIN1_BIT) +#define DIN1_GPIOREG __gpioreg__(DIN1_PORT) +#if (DIN1_BIT < 16) +#define DIN1_PINHALF L +#else +#define DIN1_PINHALF H +#endif +#define DIN1_PINCON __pincon__(DIN1_PORT, DIN1_PINHALF) +#define DIO131 131 +#define DIO131_MBED_PIN DIN1_MBED_PIN +#define DIO131_PORT DIN1_PORT +#define DIO131_BIT DIN1_BIT +#define DIO131_GPIOREG DIN1_GPIOREG +#define DIO131_PINHALF DIN1_PINHALF +#define DIO131_PINCON DIN1_PINCON +#endif +#if (defined(DIN2_PORT) && defined(DIN2_BIT)) +#define DIN2 132 +#define DIN2_MBED_PIN __mbedpin__(DIN2_PORT, DIN2_BIT) +#define DIN2_GPIOREG __gpioreg__(DIN2_PORT) +#if (DIN2_BIT < 16) +#define DIN2_PINHALF L +#else +#define DIN2_PINHALF H +#endif +#define DIN2_PINCON __pincon__(DIN2_PORT, DIN2_PINHALF) +#define DIO132 132 +#define DIO132_MBED_PIN DIN2_MBED_PIN +#define DIO132_PORT DIN2_PORT +#define DIO132_BIT DIN2_BIT +#define DIO132_GPIOREG DIN2_GPIOREG +#define DIO132_PINHALF DIN2_PINHALF +#define DIO132_PINCON DIN2_PINCON +#endif +#if (defined(DIN3_PORT) && defined(DIN3_BIT)) +#define DIN3 133 +#define DIN3_MBED_PIN __mbedpin__(DIN3_PORT, DIN3_BIT) +#define DIN3_GPIOREG __gpioreg__(DIN3_PORT) +#if (DIN3_BIT < 16) +#define DIN3_PINHALF L +#else +#define DIN3_PINHALF H +#endif +#define DIN3_PINCON __pincon__(DIN3_PORT, DIN3_PINHALF) +#define DIO133 133 +#define DIO133_MBED_PIN DIN3_MBED_PIN +#define DIO133_PORT DIN3_PORT +#define DIO133_BIT DIN3_BIT +#define DIO133_GPIOREG DIN3_GPIOREG +#define DIO133_PINHALF DIN3_PINHALF +#define DIO133_PINCON DIN3_PINCON +#endif +#if (defined(DIN4_PORT) && defined(DIN4_BIT)) +#define DIN4 134 +#define DIN4_MBED_PIN __mbedpin__(DIN4_PORT, DIN4_BIT) +#define DIN4_GPIOREG __gpioreg__(DIN4_PORT) +#if (DIN4_BIT < 16) +#define DIN4_PINHALF L +#else +#define DIN4_PINHALF H +#endif +#define DIN4_PINCON __pincon__(DIN4_PORT, DIN4_PINHALF) +#define DIO134 134 +#define DIO134_MBED_PIN DIN4_MBED_PIN +#define DIO134_PORT DIN4_PORT +#define DIO134_BIT DIN4_BIT +#define DIO134_GPIOREG DIN4_GPIOREG +#define DIO134_PINHALF DIN4_PINHALF +#define DIO134_PINCON DIN4_PINCON +#endif +#if (defined(DIN5_PORT) && defined(DIN5_BIT)) +#define DIN5 135 +#define DIN5_MBED_PIN __mbedpin__(DIN5_PORT, DIN5_BIT) +#define DIN5_GPIOREG __gpioreg__(DIN5_PORT) +#if (DIN5_BIT < 16) +#define DIN5_PINHALF L +#else +#define DIN5_PINHALF H +#endif +#define DIN5_PINCON __pincon__(DIN5_PORT, DIN5_PINHALF) +#define DIO135 135 +#define DIO135_MBED_PIN DIN5_MBED_PIN +#define DIO135_PORT DIN5_PORT +#define DIO135_BIT DIN5_BIT +#define DIO135_GPIOREG DIN5_GPIOREG +#define DIO135_PINHALF DIN5_PINHALF +#define DIO135_PINCON DIN5_PINCON +#endif +#if (defined(DIN6_PORT) && defined(DIN6_BIT)) +#define DIN6 136 +#define DIN6_MBED_PIN __mbedpin__(DIN6_PORT, DIN6_BIT) +#define DIN6_GPIOREG __gpioreg__(DIN6_PORT) +#if (DIN6_BIT < 16) +#define DIN6_PINHALF L +#else +#define DIN6_PINHALF H +#endif +#define DIN6_PINCON __pincon__(DIN6_PORT, DIN6_PINHALF) +#define DIO136 136 +#define DIO136_MBED_PIN DIN6_MBED_PIN +#define DIO136_PORT DIN6_PORT +#define DIO136_BIT DIN6_BIT +#define DIO136_GPIOREG DIN6_GPIOREG +#define DIO136_PINHALF DIN6_PINHALF +#define DIO136_PINCON DIN6_PINCON +#endif +#if (defined(DIN7_PORT) && defined(DIN7_BIT)) +#define DIN7 137 +#define DIN7_MBED_PIN __mbedpin__(DIN7_PORT, DIN7_BIT) +#define DIN7_GPIOREG __gpioreg__(DIN7_PORT) +#if (DIN7_BIT < 16) +#define DIN7_PINHALF L +#else +#define DIN7_PINHALF H +#endif +#define DIN7_PINCON __pincon__(DIN7_PORT, DIN7_PINHALF) +#define DIO137 137 +#define DIO137_MBED_PIN DIN7_MBED_PIN +#define DIO137_PORT DIN7_PORT +#define DIO137_BIT DIN7_BIT +#define DIO137_GPIOREG DIN7_GPIOREG +#define DIO137_PINHALF DIN7_PINHALF +#define DIO137_PINCON DIN7_PINCON +#endif +#if (defined(DIN8_PORT) && defined(DIN8_BIT)) +#define DIN8 138 +#define DIN8_MBED_PIN __mbedpin__(DIN8_PORT, DIN8_BIT) +#define DIN8_GPIOREG __gpioreg__(DIN8_PORT) +#if (DIN8_BIT < 16) +#define DIN8_PINHALF L +#else +#define DIN8_PINHALF H +#endif +#define DIN8_PINCON __pincon__(DIN8_PORT, DIN8_PINHALF) +#define DIO138 138 +#define DIO138_MBED_PIN DIN8_MBED_PIN +#define DIO138_PORT DIN8_PORT +#define DIO138_BIT DIN8_BIT +#define DIO138_GPIOREG DIN8_GPIOREG +#define DIO138_PINHALF DIN8_PINHALF +#define DIO138_PINCON DIN8_PINCON +#endif +#if (defined(DIN9_PORT) && defined(DIN9_BIT)) +#define DIN9 139 +#define DIN9_MBED_PIN __mbedpin__(DIN9_PORT, DIN9_BIT) +#define DIN9_GPIOREG __gpioreg__(DIN9_PORT) +#if (DIN9_BIT < 16) +#define DIN9_PINHALF L +#else +#define DIN9_PINHALF H +#endif +#define DIN9_PINCON __pincon__(DIN9_PORT, DIN9_PINHALF) +#define DIO139 139 +#define DIO139_MBED_PIN DIN9_MBED_PIN +#define DIO139_PORT DIN9_PORT +#define DIO139_BIT DIN9_BIT +#define DIO139_GPIOREG DIN9_GPIOREG +#define DIO139_PINHALF DIN9_PINHALF +#define DIO139_PINCON DIN9_PINCON +#endif +#if (defined(DIN10_PORT) && defined(DIN10_BIT)) +#define DIN10 140 +#define DIN10_MBED_PIN __mbedpin__(DIN10_PORT, DIN10_BIT) +#define DIN10_GPIOREG __gpioreg__(DIN10_PORT) +#if (DIN10_BIT < 16) +#define DIN10_PINHALF L +#else +#define DIN10_PINHALF H +#endif +#define DIN10_PINCON __pincon__(DIN10_PORT, DIN10_PINHALF) +#define DIO140 140 +#define DIO140_MBED_PIN DIN10_MBED_PIN +#define DIO140_PORT DIN10_PORT +#define DIO140_BIT DIN10_BIT +#define DIO140_GPIOREG DIN10_GPIOREG +#define DIO140_PINHALF DIN10_PINHALF +#define DIO140_PINCON DIN10_PINCON +#endif +#if (defined(DIN11_PORT) && defined(DIN11_BIT)) +#define DIN11 141 +#define DIN11_MBED_PIN __mbedpin__(DIN11_PORT, DIN11_BIT) +#define DIN11_GPIOREG __gpioreg__(DIN11_PORT) +#if (DIN11_BIT < 16) +#define DIN11_PINHALF L +#else +#define DIN11_PINHALF H +#endif +#define DIN11_PINCON __pincon__(DIN11_PORT, DIN11_PINHALF) +#define DIO141 141 +#define DIO141_MBED_PIN DIN11_MBED_PIN +#define DIO141_PORT DIN11_PORT +#define DIO141_BIT DIN11_BIT +#define DIO141_GPIOREG DIN11_GPIOREG +#define DIO141_PINHALF DIN11_PINHALF +#define DIO141_PINCON DIN11_PINCON +#endif +#if (defined(DIN12_PORT) && defined(DIN12_BIT)) +#define DIN12 142 +#define DIN12_MBED_PIN __mbedpin__(DIN12_PORT, DIN12_BIT) +#define DIN12_GPIOREG __gpioreg__(DIN12_PORT) +#if (DIN12_BIT < 16) +#define DIN12_PINHALF L +#else +#define DIN12_PINHALF H +#endif +#define DIN12_PINCON __pincon__(DIN12_PORT, DIN12_PINHALF) +#define DIO142 142 +#define DIO142_MBED_PIN DIN12_MBED_PIN +#define DIO142_PORT DIN12_PORT +#define DIO142_BIT DIN12_BIT +#define DIO142_GPIOREG DIN12_GPIOREG +#define DIO142_PINHALF DIN12_PINHALF +#define DIO142_PINCON DIN12_PINCON +#endif +#if (defined(DIN13_PORT) && defined(DIN13_BIT)) +#define DIN13 143 +#define DIN13_MBED_PIN __mbedpin__(DIN13_PORT, DIN13_BIT) +#define DIN13_GPIOREG __gpioreg__(DIN13_PORT) +#if (DIN13_BIT < 16) +#define DIN13_PINHALF L +#else +#define DIN13_PINHALF H +#endif +#define DIN13_PINCON __pincon__(DIN13_PORT, DIN13_PINHALF) +#define DIO143 143 +#define DIO143_MBED_PIN DIN13_MBED_PIN +#define DIO143_PORT DIN13_PORT +#define DIO143_BIT DIN13_BIT +#define DIO143_GPIOREG DIN13_GPIOREG +#define DIO143_PINHALF DIN13_PINHALF +#define DIO143_PINCON DIN13_PINCON +#endif +#if (defined(DIN14_PORT) && defined(DIN14_BIT)) +#define DIN14 144 +#define DIN14_MBED_PIN __mbedpin__(DIN14_PORT, DIN14_BIT) +#define DIN14_GPIOREG __gpioreg__(DIN14_PORT) +#if (DIN14_BIT < 16) +#define DIN14_PINHALF L +#else +#define DIN14_PINHALF H +#endif +#define DIN14_PINCON __pincon__(DIN14_PORT, DIN14_PINHALF) +#define DIO144 144 +#define DIO144_MBED_PIN DIN14_MBED_PIN +#define DIO144_PORT DIN14_PORT +#define DIO144_BIT DIN14_BIT +#define DIO144_GPIOREG DIN14_GPIOREG +#define DIO144_PINHALF DIN14_PINHALF +#define DIO144_PINCON DIN14_PINCON +#endif +#if (defined(DIN15_PORT) && defined(DIN15_BIT)) +#define DIN15 145 +#define DIN15_MBED_PIN __mbedpin__(DIN15_PORT, DIN15_BIT) +#define DIN15_GPIOREG __gpioreg__(DIN15_PORT) +#if (DIN15_BIT < 16) +#define DIN15_PINHALF L +#else +#define DIN15_PINHALF H +#endif +#define DIN15_PINCON __pincon__(DIN15_PORT, DIN15_PINHALF) +#define DIO145 145 +#define DIO145_MBED_PIN DIN15_MBED_PIN +#define DIO145_PORT DIN15_PORT +#define DIO145_BIT DIN15_BIT +#define DIO145_GPIOREG DIN15_GPIOREG +#define DIO145_PINHALF DIN15_PINHALF +#define DIO145_PINCON DIN15_PINCON +#endif +#if (defined(DIN16_PORT) && defined(DIN16_BIT)) +#define DIN16 146 +#define DIN16_MBED_PIN __mbedpin__(DIN16_PORT, DIN16_BIT) +#define DIN16_GPIOREG __gpioreg__(DIN16_PORT) +#if (DIN16_BIT < 16) +#define DIN16_PINHALF L +#else +#define DIN16_PINHALF H +#endif +#define DIN16_PINCON __pincon__(DIN16_PORT, DIN16_PINHALF) +#define DIO146 146 +#define DIO146_MBED_PIN DIN16_MBED_PIN +#define DIO146_PORT DIN16_PORT +#define DIO146_BIT DIN16_BIT +#define DIO146_GPIOREG DIN16_GPIOREG +#define DIO146_PINHALF DIN16_PINHALF +#define DIO146_PINCON DIN16_PINCON +#endif +#if (defined(DIN17_PORT) && defined(DIN17_BIT)) +#define DIN17 147 +#define DIN17_MBED_PIN __mbedpin__(DIN17_PORT, DIN17_BIT) +#define DIN17_GPIOREG __gpioreg__(DIN17_PORT) +#if (DIN17_BIT < 16) +#define DIN17_PINHALF L +#else +#define DIN17_PINHALF H +#endif +#define DIN17_PINCON __pincon__(DIN17_PORT, DIN17_PINHALF) +#define DIO147 147 +#define DIO147_MBED_PIN DIN17_MBED_PIN +#define DIO147_PORT DIN17_PORT +#define DIO147_BIT DIN17_BIT +#define DIO147_GPIOREG DIN17_GPIOREG +#define DIO147_PINHALF DIN17_PINHALF +#define DIO147_PINCON DIN17_PINCON +#endif +#if (defined(DIN18_PORT) && defined(DIN18_BIT)) +#define DIN18 148 +#define DIN18_MBED_PIN __mbedpin__(DIN18_PORT, DIN18_BIT) +#define DIN18_GPIOREG __gpioreg__(DIN18_PORT) +#if (DIN18_BIT < 16) +#define DIN18_PINHALF L +#else +#define DIN18_PINHALF H +#endif +#define DIN18_PINCON __pincon__(DIN18_PORT, DIN18_PINHALF) +#define DIO148 148 +#define DIO148_MBED_PIN DIN18_MBED_PIN +#define DIO148_PORT DIN18_PORT +#define DIO148_BIT DIN18_BIT +#define DIO148_GPIOREG DIN18_GPIOREG +#define DIO148_PINHALF DIN18_PINHALF +#define DIO148_PINCON DIN18_PINCON +#endif +#if (defined(DIN19_PORT) && defined(DIN19_BIT)) +#define DIN19 149 +#define DIN19_MBED_PIN __mbedpin__(DIN19_PORT, DIN19_BIT) +#define DIN19_GPIOREG __gpioreg__(DIN19_PORT) +#if (DIN19_BIT < 16) +#define DIN19_PINHALF L +#else +#define DIN19_PINHALF H +#endif +#define DIN19_PINCON __pincon__(DIN19_PORT, DIN19_PINHALF) +#define DIO149 149 +#define DIO149_MBED_PIN DIN19_MBED_PIN +#define DIO149_PORT DIN19_PORT +#define DIO149_BIT DIN19_BIT +#define DIO149_GPIOREG DIN19_GPIOREG +#define DIO149_PINHALF DIN19_PINHALF +#define DIO149_PINCON DIN19_PINCON +#endif +#if (defined(DIN20_PORT) && defined(DIN20_BIT)) +#define DIN20 150 +#define DIN20_MBED_PIN __mbedpin__(DIN20_PORT, DIN20_BIT) +#define DIN20_GPIOREG __gpioreg__(DIN20_PORT) +#if (DIN20_BIT < 16) +#define DIN20_PINHALF L +#else +#define DIN20_PINHALF H +#endif +#define DIN20_PINCON __pincon__(DIN20_PORT, DIN20_PINHALF) +#define DIO150 150 +#define DIO150_MBED_PIN DIN20_MBED_PIN +#define DIO150_PORT DIN20_PORT +#define DIO150_BIT DIN20_BIT +#define DIO150_GPIOREG DIN20_GPIOREG +#define DIO150_PINHALF DIN20_PINHALF +#define DIO150_PINCON DIN20_PINCON +#endif +#if (defined(DIN21_PORT) && defined(DIN21_BIT)) +#define DIN21 151 +#define DIN21_MBED_PIN __mbedpin__(DIN21_PORT, DIN21_BIT) +#define DIN21_GPIOREG __gpioreg__(DIN21_PORT) +#if (DIN21_BIT < 16) +#define DIN21_PINHALF L +#else +#define DIN21_PINHALF H +#endif +#define DIN21_PINCON __pincon__(DIN21_PORT, DIN21_PINHALF) +#define DIO151 151 +#define DIO151_MBED_PIN DIN21_MBED_PIN +#define DIO151_PORT DIN21_PORT +#define DIO151_BIT DIN21_BIT +#define DIO151_GPIOREG DIN21_GPIOREG +#define DIO151_PINHALF DIN21_PINHALF +#define DIO151_PINCON DIN21_PINCON +#endif +#if (defined(DIN22_PORT) && defined(DIN22_BIT)) +#define DIN22 152 +#define DIN22_MBED_PIN __mbedpin__(DIN22_PORT, DIN22_BIT) +#define DIN22_GPIOREG __gpioreg__(DIN22_PORT) +#if (DIN22_BIT < 16) +#define DIN22_PINHALF L +#else +#define DIN22_PINHALF H +#endif +#define DIN22_PINCON __pincon__(DIN22_PORT, DIN22_PINHALF) +#define DIO152 152 +#define DIO152_MBED_PIN DIN22_MBED_PIN +#define DIO152_PORT DIN22_PORT +#define DIO152_BIT DIN22_BIT +#define DIO152_GPIOREG DIN22_GPIOREG +#define DIO152_PINHALF DIN22_PINHALF +#define DIO152_PINCON DIN22_PINCON +#endif +#if (defined(DIN23_PORT) && defined(DIN23_BIT)) +#define DIN23 153 +#define DIN23_MBED_PIN __mbedpin__(DIN23_PORT, DIN23_BIT) +#define DIN23_GPIOREG __gpioreg__(DIN23_PORT) +#if (DIN23_BIT < 16) +#define DIN23_PINHALF L +#else +#define DIN23_PINHALF H +#endif +#define DIN23_PINCON __pincon__(DIN23_PORT, DIN23_PINHALF) +#define DIO153 153 +#define DIO153_MBED_PIN DIN23_MBED_PIN +#define DIO153_PORT DIN23_PORT +#define DIO153_BIT DIN23_BIT +#define DIO153_GPIOREG DIN23_GPIOREG +#define DIO153_PINHALF DIN23_PINHALF +#define DIO153_PINCON DIN23_PINCON +#endif +#if (defined(DIN24_PORT) && defined(DIN24_BIT)) +#define DIN24 154 +#define DIN24_MBED_PIN __mbedpin__(DIN24_PORT, DIN24_BIT) +#define DIN24_GPIOREG __gpioreg__(DIN24_PORT) +#if (DIN24_BIT < 16) +#define DIN24_PINHALF L +#else +#define DIN24_PINHALF H +#endif +#define DIN24_PINCON __pincon__(DIN24_PORT, DIN24_PINHALF) +#define DIO154 154 +#define DIO154_MBED_PIN DIN24_MBED_PIN +#define DIO154_PORT DIN24_PORT +#define DIO154_BIT DIN24_BIT +#define DIO154_GPIOREG DIN24_GPIOREG +#define DIO154_PINHALF DIN24_PINHALF +#define DIO154_PINCON DIN24_PINCON +#endif +#if (defined(DIN25_PORT) && defined(DIN25_BIT)) +#define DIN25 155 +#define DIN25_MBED_PIN __mbedpin__(DIN25_PORT, DIN25_BIT) +#define DIN25_GPIOREG __gpioreg__(DIN25_PORT) +#if (DIN25_BIT < 16) +#define DIN25_PINHALF L +#else +#define DIN25_PINHALF H +#endif +#define DIN25_PINCON __pincon__(DIN25_PORT, DIN25_PINHALF) +#define DIO155 155 +#define DIO155_MBED_PIN DIN25_MBED_PIN +#define DIO155_PORT DIN25_PORT +#define DIO155_BIT DIN25_BIT +#define DIO155_GPIOREG DIN25_GPIOREG +#define DIO155_PINHALF DIN25_PINHALF +#define DIO155_PINCON DIN25_PINCON +#endif +#if (defined(DIN26_PORT) && defined(DIN26_BIT)) +#define DIN26 156 +#define DIN26_MBED_PIN __mbedpin__(DIN26_PORT, DIN26_BIT) +#define DIN26_GPIOREG __gpioreg__(DIN26_PORT) +#if (DIN26_BIT < 16) +#define DIN26_PINHALF L +#else +#define DIN26_PINHALF H +#endif +#define DIN26_PINCON __pincon__(DIN26_PORT, DIN26_PINHALF) +#define DIO156 156 +#define DIO156_MBED_PIN DIN26_MBED_PIN +#define DIO156_PORT DIN26_PORT +#define DIO156_BIT DIN26_BIT +#define DIO156_GPIOREG DIN26_GPIOREG +#define DIO156_PINHALF DIN26_PINHALF +#define DIO156_PINCON DIN26_PINCON +#endif +#if (defined(DIN27_PORT) && defined(DIN27_BIT)) +#define DIN27 157 +#define DIN27_MBED_PIN __mbedpin__(DIN27_PORT, DIN27_BIT) +#define DIN27_GPIOREG __gpioreg__(DIN27_PORT) +#if (DIN27_BIT < 16) +#define DIN27_PINHALF L +#else +#define DIN27_PINHALF H +#endif +#define DIN27_PINCON __pincon__(DIN27_PORT, DIN27_PINHALF) +#define DIO157 157 +#define DIO157_MBED_PIN DIN27_MBED_PIN +#define DIO157_PORT DIN27_PORT +#define DIO157_BIT DIN27_BIT +#define DIO157_GPIOREG DIN27_GPIOREG +#define DIO157_PINHALF DIN27_PINHALF +#define DIO157_PINCON DIN27_PINCON +#endif +#if (defined(DIN28_PORT) && defined(DIN28_BIT)) +#define DIN28 158 +#define DIN28_MBED_PIN __mbedpin__(DIN28_PORT, DIN28_BIT) +#define DIN28_GPIOREG __gpioreg__(DIN28_PORT) +#if (DIN28_BIT < 16) +#define DIN28_PINHALF L +#else +#define DIN28_PINHALF H +#endif +#define DIN28_PINCON __pincon__(DIN28_PORT, DIN28_PINHALF) +#define DIO158 158 +#define DIO158_MBED_PIN DIN28_MBED_PIN +#define DIO158_PORT DIN28_PORT +#define DIO158_BIT DIN28_BIT +#define DIO158_GPIOREG DIN28_GPIOREG +#define DIO158_PINHALF DIN28_PINHALF +#define DIO158_PINCON DIN28_PINCON +#endif +#if (defined(DIN29_PORT) && defined(DIN29_BIT)) +#define DIN29 159 +#define DIN29_MBED_PIN __mbedpin__(DIN29_PORT, DIN29_BIT) +#define DIN29_GPIOREG __gpioreg__(DIN29_PORT) +#if (DIN29_BIT < 16) +#define DIN29_PINHALF L +#else +#define DIN29_PINHALF H +#endif +#define DIN29_PINCON __pincon__(DIN29_PORT, DIN29_PINHALF) +#define DIO159 159 +#define DIO159_MBED_PIN DIN29_MBED_PIN +#define DIO159_PORT DIN29_PORT +#define DIO159_BIT DIN29_BIT +#define DIO159_GPIOREG DIN29_GPIOREG +#define DIO159_PINHALF DIN29_PINHALF +#define DIO159_PINCON DIN29_PINCON +#endif +#if (defined(DIN30_PORT) && defined(DIN30_BIT)) +#define DIN30 160 +#define DIN30_MBED_PIN __mbedpin__(DIN30_PORT, DIN30_BIT) +#define DIN30_GPIOREG __gpioreg__(DIN30_PORT) +#if (DIN30_BIT < 16) +#define DIN30_PINHALF L +#else +#define DIN30_PINHALF H +#endif +#define DIN30_PINCON __pincon__(DIN30_PORT, DIN30_PINHALF) +#define DIO160 160 +#define DIO160_MBED_PIN DIN30_MBED_PIN +#define DIO160_PORT DIN30_PORT +#define DIO160_BIT DIN30_BIT +#define DIO160_GPIOREG DIN30_GPIOREG +#define DIO160_PINHALF DIN30_PINHALF +#define DIO160_PINCON DIN30_PINCON +#endif +#if (defined(DIN31_PORT) && defined(DIN31_BIT)) +#define DIN31 161 +#define DIN31_MBED_PIN __mbedpin__(DIN31_PORT, DIN31_BIT) +#define DIN31_GPIOREG __gpioreg__(DIN31_PORT) +#if (DIN31_BIT < 16) +#define DIN31_PINHALF L +#else +#define DIN31_PINHALF H +#endif +#define DIN31_PINCON __pincon__(DIN31_PORT, DIN31_PINHALF) +#define DIO161 161 +#define DIO161_MBED_PIN DIN31_MBED_PIN +#define DIO161_PORT DIN31_PORT +#define DIO161_BIT DIN31_BIT +#define DIO161_GPIOREG DIN31_GPIOREG +#define DIO161_PINHALF DIN31_PINHALF +#define DIO161_PINCON DIN31_PINCON +#endif +#if (defined(TX_PORT) && defined(TX_BIT)) +#define TX 200 +#define TX_MBED_PIN __mbedpin__(TX_PORT, TX_BIT) +#define TX_GPIOREG __gpioreg__(TX_PORT) +#if (TX_BIT < 16) +#define TX_PINHALF L +#else +#define TX_PINHALF H +#endif +#define TX_PINCON __pincon__(TX_PORT, TX_PINHALF) +#define DIO200 200 +#define DIO200_MBED_PIN TX_MBED_PIN +#define DIO200_PORT TX_PORT +#define DIO200_BIT TX_BIT +#define DIO200_GPIOREG TX_GPIOREG +#define DIO200_PINHALF TX_PINHALF +#define DIO200_PINCON TX_PINCON +#endif +#if (defined(RX_PORT) && defined(RX_BIT)) +#define RX 201 +#define RX_MBED_PIN __mbedpin__(RX_PORT, RX_BIT) +#define RX_GPIOREG __gpioreg__(RX_PORT) +#if (RX_BIT < 16) +#define RX_PINHALF L +#else +#define RX_PINHALF H +#endif +#define RX_PINCON __pincon__(RX_PORT, RX_PINHALF) +#define DIO201 201 +#define DIO201_MBED_PIN RX_MBED_PIN +#define DIO201_PORT RX_PORT +#define DIO201_BIT RX_BIT +#define DIO201_GPIOREG RX_GPIOREG +#define DIO201_PINHALF RX_PINHALF +#define DIO201_PINCON RX_PINCON +#endif +#if (defined(USB_DM_PORT) && defined(USB_DM_BIT)) +#define USB_DM 202 +#define USB_DM_MBED_PIN __mbedpin__(USB_DM_PORT, USB_DM_BIT) +#define USB_DM_GPIOREG __gpioreg__(USB_DM_PORT) +#if (USB_DM_BIT < 16) +#define USB_DM_PINHALF L +#else +#define USB_DM_PINHALF H +#endif +#define USB_DM_PINCON __pincon__(USB_DM_PORT, USB_DM_PINHALF) +#define DIO202 202 +#define DIO202_MBED_PIN USB_DM_MBED_PIN +#define DIO202_PORT USB_DM_PORT +#define DIO202_BIT USB_DM_BIT +#define DIO202_GPIOREG USB_DM_GPIOREG +#define DIO202_PINHALF USB_DM_PINHALF +#define DIO202_PINCON USB_DM_PINCON +#endif +#if (defined(USB_DP_PORT) && defined(USB_DP_BIT)) +#define USB_DP 203 +#define USB_DP_MBED_PIN __mbedpin__(USB_DP_PORT, USB_DP_BIT) +#define USB_DP_GPIOREG __gpioreg__(USB_DP_PORT) +#if (USB_DP_BIT < 16) +#define USB_DP_PINHALF L +#else +#define USB_DP_PINHALF H +#endif +#define USB_DP_PINCON __pincon__(USB_DP_PORT, USB_DP_PINHALF) +#define DIO203 203 +#define DIO203_MBED_PIN USB_DP_MBED_PIN +#define DIO203_PORT USB_DP_PORT +#define DIO203_BIT USB_DP_BIT +#define DIO203_GPIOREG USB_DP_GPIOREG +#define DIO203_PINHALF USB_DP_PINHALF +#define DIO203_PINCON USB_DP_PINCON +#endif +#if (defined(SPI_CLK_PORT) && defined(SPI_CLK_BIT)) +#define SPI_CLK 204 +#define SPI_CLK_MBED_PIN __mbedpin__(SPI_CLK_PORT, SPI_CLK_BIT) +#define SPI_CLK_GPIOREG __gpioreg__(SPI_CLK_PORT) +#if (SPI_CLK_BIT < 16) +#define SPI_CLK_PINHALF L +#else +#define SPI_CLK_PINHALF H +#endif +#define SPI_CLK_PINCON __pincon__(SPI_CLK_PORT, SPI_CLK_PINHALF) +#define DIO204 204 +#define DIO204_MBED_PIN SPI_CLK_MBED_PIN +#define DIO204_PORT SPI_CLK_PORT +#define DIO204_BIT SPI_CLK_BIT +#define DIO204_GPIOREG SPI_CLK_GPIOREG +#define DIO204_PINHALF SPI_CLK_PINHALF +#define DIO204_PINCON SPI_CLK_PINCON +#endif +#if (defined(SPI_SDI_PORT) && defined(SPI_SDI_BIT)) +#define SPI_SDI 205 +#define SPI_SDI_MBED_PIN __mbedpin__(SPI_SDI_PORT, SPI_SDI_BIT) +#define SPI_SDI_GPIOREG __gpioreg__(SPI_SDI_PORT) +#if (SPI_SDI_BIT < 16) +#define SPI_SDI_PINHALF L +#else +#define SPI_SDI_PINHALF H +#endif +#define SPI_SDI_PINCON __pincon__(SPI_SDI_PORT, SPI_SDI_PINHALF) +#define DIO205 205 +#define DIO205_MBED_PIN SPI_SDI_MBED_PIN +#define DIO205_PORT SPI_SDI_PORT +#define DIO205_BIT SPI_SDI_BIT +#define DIO205_GPIOREG SPI_SDI_GPIOREG +#define DIO205_PINHALF SPI_SDI_PINHALF +#define DIO205_PINCON SPI_SDI_PINCON +#endif +#if (defined(SPI_SDO_PORT) && defined(SPI_SDO_BIT)) +#define SPI_SDO 206 +#define SPI_SDO_MBED_PIN __mbedpin__(SPI_SDO_PORT, SPI_SDO_BIT) +#define SPI_SDO_GPIOREG __gpioreg__(SPI_SDO_PORT) +#if (SPI_SDO_BIT < 16) +#define SPI_SDO_PINHALF L +#else +#define SPI_SDO_PINHALF H +#endif +#define SPI_SDO_PINCON __pincon__(SPI_SDO_PORT, SPI_SDO_PINHALF) +#define DIO206 206 +#define DIO206_MBED_PIN SPI_SDO_MBED_PIN +#define DIO206_PORT SPI_SDO_PORT +#define DIO206_BIT SPI_SDO_BIT +#define DIO206_GPIOREG SPI_SDO_GPIOREG +#define DIO206_PINHALF SPI_SDO_PINHALF +#define DIO206_PINCON SPI_SDO_PINCON +#endif + +/********************************************** + * ISR on change inputs + **********************************************/ +// ISR on change inputs +#define __risereg__(X) (__helper__(IO, X, IntEnR)) +#if (defined(LIMIT_X_ISR) && defined(LIMIT_X)) +#define LIMIT_X_RISEREG (__risereg__(LIMIT_X_PORT)) +#define LIMIT_X_FALLREG (__fallreg__(LIMIT_X_PORT)) +#define DIO100_ISR (LIMIT_X_ISR) +#define DIO100_RISEREG LIMIT_X_RISEREG +#define DIO100_FALLREG LIMIT_X_FALLREG +#endif +#if (defined(LIMIT_Y_ISR) && defined(LIMIT_Y)) +#define LIMIT_Y_RISEREG (__risereg__(LIMIT_Y_PORT)) +#define LIMIT_Y_FALLREG (__fallreg__(LIMIT_Y_PORT)) +#define DIO101_ISR (LIMIT_Y_ISR) +#define DIO101_RISEREG LIMIT_Y_RISEREG +#define DIO101_FALLREG LIMIT_Y_FALLREG +#endif +#if (defined(LIMIT_Z_ISR) && defined(LIMIT_Z)) +#define LIMIT_Z_RISEREG (__risereg__(LIMIT_Z_PORT)) +#define LIMIT_Z_FALLREG (__fallreg__(LIMIT_Z_PORT)) +#define DIO102_ISR (LIMIT_Z_ISR) +#define DIO102_RISEREG LIMIT_Z_RISEREG +#define DIO102_FALLREG LIMIT_Z_FALLREG +#endif +#if (defined(LIMIT_X2_ISR) && defined(LIMIT_X2)) +#define LIMIT_X2_RISEREG (__risereg__(LIMIT_X2_PORT)) +#define LIMIT_X2_FALLREG (__fallreg__(LIMIT_X2_PORT)) +#define DIO103_ISR (LIMIT_X2_ISR) +#define DIO103_RISEREG LIMIT_X2_RISEREG +#define DIO103_FALLREG LIMIT_X2_FALLREG +#endif +#if (defined(LIMIT_Y2_ISR) && defined(LIMIT_Y2)) +#define LIMIT_Y2_RISEREG (__risereg__(LIMIT_Y2_PORT)) +#define LIMIT_Y2_FALLREG (__fallreg__(LIMIT_Y2_PORT)) +#define DIO104_ISR (LIMIT_Y2_ISR) +#define DIO104_RISEREG LIMIT_Y2_RISEREG +#define DIO104_FALLREG LIMIT_Y2_FALLREG +#endif +#if (defined(LIMIT_Z2_ISR) && defined(LIMIT_Z2)) +#define LIMIT_Z2_RISEREG (__risereg__(LIMIT_Z2_PORT)) +#define LIMIT_Z2_FALLREG (__fallreg__(LIMIT_Z2_PORT)) +#define DIO105_ISR (LIMIT_Z2_ISR) +#define DIO105_RISEREG LIMIT_Z2_RISEREG +#define DIO105_FALLREG LIMIT_Z2_FALLREG +#endif +#if (defined(LIMIT_A_ISR) && defined(LIMIT_A)) +#define LIMIT_A_RISEREG (__risereg__(LIMIT_A_PORT)) +#define LIMIT_A_FALLREG (__fallreg__(LIMIT_A_PORT)) +#define DIO106_ISR (LIMIT_A_ISR) +#define DIO106_RISEREG LIMIT_A_RISEREG +#define DIO106_FALLREG LIMIT_A_FALLREG +#endif +#if (defined(LIMIT_B_ISR) && defined(LIMIT_B)) +#define LIMIT_B_RISEREG (__risereg__(LIMIT_B_PORT)) +#define LIMIT_B_FALLREG (__fallreg__(LIMIT_B_PORT)) +#define DIO107_ISR (LIMIT_B_ISR) +#define DIO107_RISEREG LIMIT_B_RISEREG +#define DIO107_FALLREG LIMIT_B_FALLREG +#endif +#if (defined(LIMIT_C_ISR) && defined(LIMIT_C)) +#define LIMIT_C_RISEREG (__risereg__(LIMIT_C_PORT)) +#define LIMIT_C_FALLREG (__fallreg__(LIMIT_C_PORT)) +#define DIO108_ISR (LIMIT_C_ISR) +#define DIO108_RISEREG LIMIT_C_RISEREG +#define DIO108_FALLREG LIMIT_C_FALLREG +#endif +#if (defined(PROBE_ISR) && defined(PROBE)) +#define PROBE_RISEREG (__risereg__(PROBE_PORT)) +#define PROBE_FALLREG (__fallreg__(PROBE_PORT)) +#define DIO109_ISR (PROBE_ISR) +#define DIO109_RISEREG PROBE_RISEREG +#define DIO109_FALLREG PROBE_FALLREG +#endif +#if (defined(ESTOP_ISR) && defined(ESTOP)) +#define ESTOP_RISEREG (__risereg__(ESTOP_PORT)) +#define ESTOP_FALLREG (__fallreg__(ESTOP_PORT)) +#define DIO110_ISR (ESTOP_ISR) +#define DIO110_RISEREG ESTOP_RISEREG +#define DIO110_FALLREG ESTOP_FALLREG +#endif +#if (defined(SAFETY_DOOR_ISR) && defined(SAFETY_DOOR)) +#define SAFETY_DOOR_RISEREG (__risereg__(SAFETY_DOOR_PORT)) +#define SAFETY_DOOR_FALLREG (__fallreg__(SAFETY_DOOR_PORT)) +#define DIO111_ISR (SAFETY_DOOR_ISR) +#define DIO111_RISEREG SAFETY_DOOR_RISEREG +#define DIO111_FALLREG SAFETY_DOOR_FALLREG +#endif +#if (defined(FHOLD_ISR) && defined(FHOLD)) +#define FHOLD_RISEREG (__risereg__(FHOLD_PORT)) +#define FHOLD_FALLREG (__fallreg__(FHOLD_PORT)) +#define DIO112_ISR (FHOLD_ISR) +#define DIO112_RISEREG FHOLD_RISEREG +#define DIO112_FALLREG FHOLD_FALLREG +#endif +#if (defined(CS_RES_ISR) && defined(CS_RES)) +#define CS_RES_RISEREG (__risereg__(CS_RES_PORT)) +#define CS_RES_FALLREG (__fallreg__(CS_RES_PORT)) +#define DIO113_ISR (CS_RES_ISR) +#define DIO113_RISEREG CS_RES_RISEREG +#define DIO113_FALLREG CS_RES_FALLREG +#endif +#if (defined(DIN0_ISR) && defined(DIN0)) +#define DIN0_RISEREG (__risereg__(DIN0_PORT)) +#define DIN0_FALLREG (__fallreg__(DIN0_PORT)) +#define DIO130_ISR (DIN0_ISR) +#define DIO130_RISEREG DIN0_RISEREG +#define DIO130_FALLREG DIN0_FALLREG +#endif +#if (defined(DIN1_ISR) && defined(DIN1)) +#define DIN1_RISEREG (__risereg__(DIN1_PORT)) +#define DIN1_FALLREG (__fallreg__(DIN1_PORT)) +#define DIO131_ISR (DIN1_ISR) +#define DIO131_RISEREG DIN1_RISEREG +#define DIO131_FALLREG DIN1_FALLREG +#endif +#if (defined(DIN2_ISR) && defined(DIN2)) +#define DIN2_RISEREG (__risereg__(DIN2_PORT)) +#define DIN2_FALLREG (__fallreg__(DIN2_PORT)) +#define DIO132_ISR (DIN2_ISR) +#define DIO132_RISEREG DIN2_RISEREG +#define DIO132_FALLREG DIN2_FALLREG +#endif +#if (defined(DIN3_ISR) && defined(DIN3)) +#define DIN3_RISEREG (__risereg__(DIN3_PORT)) +#define DIN3_FALLREG (__fallreg__(DIN3_PORT)) +#define DIO133_ISR (DIN3_ISR) +#define DIO133_RISEREG DIN3_RISEREG +#define DIO133_FALLREG DIN3_FALLREG +#endif +#if (defined(DIN4_ISR) && defined(DIN4)) +#define DIN4_RISEREG (__risereg__(DIN4_PORT)) +#define DIN4_FALLREG (__fallreg__(DIN4_PORT)) +#define DIO134_ISR (DIN4_ISR) +#define DIO134_RISEREG DIN4_RISEREG +#define DIO134_FALLREG DIN4_FALLREG +#endif +#if (defined(DIN5_ISR) && defined(DIN5)) +#define DIN5_RISEREG (__risereg__(DIN5_PORT)) +#define DIN5_FALLREG (__fallreg__(DIN5_PORT)) +#define DIO135_ISR (DIN5_ISR) +#define DIO135_RISEREG DIN5_RISEREG +#define DIO135_FALLREG DIN5_FALLREG +#endif +#if (defined(DIN6_ISR) && defined(DIN6)) +#define DIN6_RISEREG (__risereg__(DIN6_PORT)) +#define DIN6_FALLREG (__fallreg__(DIN6_PORT)) +#define DIO136_ISR (DIN6_ISR) +#define DIO136_RISEREG DIN6_RISEREG +#define DIO136_FALLREG DIN6_FALLREG +#endif +#if (defined(DIN7_ISR) && defined(DIN7)) +#define DIN7_RISEREG (__risereg__(DIN7_PORT)) +#define DIN7_FALLREG (__fallreg__(DIN7_PORT)) +#define DIO137_ISR (DIN7_ISR) +#define DIO137_RISEREG DIN7_RISEREG +#define DIO137_FALLREG DIN7_FALLREG +#endif + + /** + * + * PWM + * + * */ +#define __mrreg__(X) __helper__(MR, X, ) +#ifdef PWM0 +#define PWM0_MR __mrreg__(PWM0_CHANNEL) +#if (PWM0_PORT == 1) +#define PWM0_PINSEL 2 +#define PWM0_FUNC 2 +#elif (PWM0_PORT == 2) +#define PWM0_PINSEL 1 +#define PWM0_FUNC 1 +#else +#define PWM0_PINSEL 0 +#define PWM0_FUNC 0 +#endif +#define DIO24_PINSEL PWM0_PINSEL +#define DIO24_FUNC PWM0_FUNC +#define DIO24_CHANNEL PWM0_CHANNEL +#define DIO24_MR PWM0_MR +#endif +#ifdef PWM1 +#define PWM1_MR __mrreg__(PWM1_CHANNEL) +#if (PWM1_PORT == 1) +#define PWM1_PINSEL 2 +#define PWM1_FUNC 2 +#elif (PWM1_PORT == 2) +#define PWM1_PINSEL 1 +#define PWM1_FUNC 1 +#else +#define PWM1_PINSEL 0 +#define PWM1_FUNC 0 +#endif +#define DIO25_PINSEL PWM1_PINSEL +#define DIO25_FUNC PWM1_FUNC +#define DIO25_CHANNEL PWM1_CHANNEL +#define DIO25_MR PWM1_MR +#endif +#ifdef PWM2 +#define PWM2_MR __mrreg__(PWM2_CHANNEL) +#if (PWM2_PORT == 1) +#define PWM2_PINSEL 2 +#define PWM2_FUNC 2 +#elif (PWM2_PORT == 2) +#define PWM2_PINSEL 1 +#define PWM2_FUNC 1 +#else +#define PWM2_PINSEL 0 +#define PWM2_FUNC 0 +#endif +#define DIO26_PINSEL PWM2_PINSEL +#define DIO26_FUNC PWM2_FUNC +#define DIO26_CHANNEL PWM2_CHANNEL +#define DIO26_MR PWM2_MR +#endif +#ifdef PWM3 +#define PWM3_MR __mrreg__(PWM3_CHANNEL) +#if (PWM3_PORT == 1) +#define PWM3_PINSEL 2 +#define PWM3_FUNC 2 +#elif (PWM3_PORT == 2) +#define PWM3_PINSEL 1 +#define PWM3_FUNC 1 +#else +#define PWM3_PINSEL 0 +#define PWM3_FUNC 0 +#endif +#define DIO27_PINSEL PWM3_PINSEL +#define DIO27_FUNC PWM3_FUNC +#define DIO27_CHANNEL PWM3_CHANNEL +#define DIO27_MR PWM3_MR +#endif +#ifdef PWM4 +#define PWM4_MR __mrreg__(PWM4_CHANNEL) +#if (PWM4_PORT == 1) +#define PWM4_PINSEL 2 +#define PWM4_FUNC 2 +#elif (PWM4_PORT == 2) +#define PWM4_PINSEL 1 +#define PWM4_FUNC 1 +#else +#define PWM4_PINSEL 0 +#define PWM4_FUNC 0 +#endif +#define DIO28_PINSEL PWM4_PINSEL +#define DIO28_FUNC PWM4_FUNC +#define DIO28_CHANNEL PWM4_CHANNEL +#define DIO28_MR PWM4_MR +#endif +#ifdef PWM5 +#define PWM5_MR __mrreg__(PWM5_CHANNEL) +#if (PWM5_PORT == 1) +#define PWM5_PINSEL 2 +#define PWM5_FUNC 2 +#elif (PWM5_PORT == 2) +#define PWM5_PINSEL 1 +#define PWM5_FUNC 1 +#else +#define PWM5_PINSEL 0 +#define PWM5_FUNC 0 +#endif +#define DIO29_PINSEL PWM5_PINSEL +#define DIO29_FUNC PWM5_FUNC +#define DIO29_CHANNEL PWM5_CHANNEL +#define DIO29_MR PWM5_MR +#endif +#ifdef PWM6 +#define PWM6_MR __mrreg__(PWM6_CHANNEL) +#if (PWM6_PORT == 1) +#define PWM6_PINSEL 2 +#define PWM6_FUNC 2 +#elif (PWM6_PORT == 2) +#define PWM6_PINSEL 1 +#define PWM6_FUNC 1 +#else +#define PWM6_PINSEL 0 +#define PWM6_FUNC 0 +#endif +#define DIO30_PINSEL PWM6_PINSEL +#define DIO30_FUNC PWM6_FUNC +#define DIO30_CHANNEL PWM6_CHANNEL +#define DIO30_MR PWM6_MR +#endif +#ifdef PWM7 +#define PWM7_MR __mrreg__(PWM7_CHANNEL) +#if (PWM7_PORT == 1) +#define PWM7_PINSEL 2 +#define PWM7_FUNC 2 +#elif (PWM7_PORT == 2) +#define PWM7_PINSEL 1 +#define PWM7_FUNC 1 +#else +#define PWM7_PINSEL 0 +#define PWM7_FUNC 0 +#endif +#define DIO31_PINSEL PWM7_PINSEL +#define DIO31_FUNC PWM7_FUNC +#define DIO31_CHANNEL PWM7_CHANNEL +#define DIO31_MR PWM7_MR +#endif +#ifdef PWM8 +#define PWM8_MR __mrreg__(PWM8_CHANNEL) +#if (PWM8_PORT == 1) +#define PWM8_PINSEL 2 +#define PWM8_FUNC 2 +#elif (PWM8_PORT == 2) +#define PWM8_PINSEL 1 +#define PWM8_FUNC 1 +#else +#define PWM8_PINSEL 0 +#define PWM8_FUNC 0 +#endif +#define DIO32_PINSEL PWM8_PINSEL +#define DIO32_FUNC PWM8_FUNC +#define DIO32_CHANNEL PWM8_CHANNEL +#define DIO32_MR PWM8_MR +#endif +#ifdef PWM9 +#define PWM9_MR __mrreg__(PWM9_CHANNEL) +#if (PWM9_PORT == 1) +#define PWM9_PINSEL 2 +#define PWM9_FUNC 2 +#elif (PWM9_PORT == 2) +#define PWM9_PINSEL 1 +#define PWM9_FUNC 1 +#else +#define PWM9_PINSEL 0 +#define PWM9_FUNC 0 +#endif +#define DIO33_PINSEL PWM9_PINSEL +#define DIO33_FUNC PWM9_FUNC +#define DIO33_CHANNEL PWM9_CHANNEL +#define DIO33_MR PWM9_MR +#endif +#ifdef PWM10 +#define PWM10_MR __mrreg__(PWM10_CHANNEL) +#if (PWM10_PORT == 1) +#define PWM10_PINSEL 2 +#define PWM10_FUNC 2 +#elif (PWM10_PORT == 2) +#define PWM10_PINSEL 1 +#define PWM10_FUNC 1 +#else +#define PWM10_PINSEL 0 +#define PWM10_FUNC 0 +#endif +#define DIO34_PINSEL PWM10_PINSEL +#define DIO34_FUNC PWM10_FUNC +#define DIO34_CHANNEL PWM10_CHANNEL +#define DIO34_MR PWM10_MR +#endif +#ifdef PWM11 +#define PWM11_MR __mrreg__(PWM11_CHANNEL) +#if (PWM11_PORT == 1) +#define PWM11_PINSEL 2 +#define PWM11_FUNC 2 +#elif (PWM11_PORT == 2) +#define PWM11_PINSEL 1 +#define PWM11_FUNC 1 +#else +#define PWM11_PINSEL 0 +#define PWM11_FUNC 0 +#endif +#define DIO35_PINSEL PWM11_PINSEL +#define DIO35_FUNC PWM11_FUNC +#define DIO35_CHANNEL PWM11_CHANNEL +#define DIO35_MR PWM11_MR +#endif +#ifdef PWM12 +#define PWM12_MR __mrreg__(PWM12_CHANNEL) +#if (PWM12_PORT == 1) +#define PWM12_PINSEL 2 +#define PWM12_FUNC 2 +#elif (PWM12_PORT == 2) +#define PWM12_PINSEL 1 +#define PWM12_FUNC 1 +#else +#define PWM12_PINSEL 0 +#define PWM12_FUNC 0 +#endif +#define DIO36_PINSEL PWM12_PINSEL +#define DIO36_FUNC PWM12_FUNC +#define DIO36_CHANNEL PWM12_CHANNEL +#define DIO36_MR PWM12_MR +#endif +#ifdef PWM13 +#define PWM13_MR __mrreg__(PWM13_CHANNEL) +#if (PWM13_PORT == 1) +#define PWM13_PINSEL 2 +#define PWM13_FUNC 2 +#elif (PWM13_PORT == 2) +#define PWM13_PINSEL 1 +#define PWM13_FUNC 1 +#else +#define PWM13_PINSEL 0 +#define PWM13_FUNC 0 +#endif +#define DIO37_PINSEL PWM13_PINSEL +#define DIO37_FUNC PWM13_FUNC +#define DIO37_CHANNEL PWM13_CHANNEL +#define DIO37_MR PWM13_MR +#endif +#ifdef PWM14 +#define PWM14_MR __mrreg__(PWM14_CHANNEL) +#if (PWM14_PORT == 1) +#define PWM14_PINSEL 2 +#define PWM14_FUNC 2 +#elif (PWM14_PORT == 2) +#define PWM14_PINSEL 1 +#define PWM14_FUNC 1 +#else +#define PWM14_PINSEL 0 +#define PWM14_FUNC 0 +#endif +#define DIO38_PINSEL PWM14_PINSEL +#define DIO38_FUNC PWM14_FUNC +#define DIO38_CHANNEL PWM14_CHANNEL +#define DIO38_MR PWM14_MR +#endif +#ifdef PWM15 +#define PWM15_MR __mrreg__(PWM15_CHANNEL) +#if (PWM15_PORT == 1) +#define PWM15_PINSEL 2 +#define PWM15_FUNC 2 +#elif (PWM15_PORT == 2) +#define PWM15_PINSEL 1 +#define PWM15_FUNC 1 +#else +#define PWM15_PINSEL 0 +#define PWM15_FUNC 0 +#endif +#define DIO39_PINSEL PWM15_PINSEL +#define DIO39_FUNC PWM15_FUNC +#define DIO39_CHANNEL PWM15_CHANNEL +#define DIO39_MR PWM15_MR +#endif + +#define PWM_LER ((1 << PWM0_CHANNEL) | (1 << PWM1_CHANNEL) | (1 << PWM2_CHANNEL) | (1 << PWM3_CHANNEL) | (1 << PWM4_CHANNEL) | (1 << PWM5_CHANNEL) | (1 << PWM6_CHANNEL) | (1 << PWM7_CHANNEL) | (1 << PWM8_CHANNEL) | (1 << PWM9_CHANNEL) | (1 << PWM10_CHANNEL) | (1 << PWM11_CHANNEL) | (1 << PWM12_CHANNEL) | (1 << PWM13_CHANNEL) | (1 << PWM14_CHANNEL) | (1 << PWM15_CHANNEL)) +#define PWM_ENA ((1 << (9 + PWM0_CHANNEL)) | (1 << (9 + PWM1_CHANNEL)) | (1 << (9 + PWM2_CHANNEL)) | (1 << (9 + PWM3_CHANNEL)) | (1 << (9 + PWM4_CHANNEL)) | (1 << (9 + PWM5_CHANNEL)) | (1 << (9 + PWM6_CHANNEL)) | (1 << (9 + PWM7_CHANNEL)) | (1 << (9 + PWM8_CHANNEL)) | (1 << (9 + PWM9_CHANNEL)) | (1 << (9 + PWM10_CHANNEL)) | (1 << (9 + PWM11_CHANNEL)) | (1 << (9 + PWM12_CHANNEL)) | (1 << (9 + PWM13_CHANNEL)) | (1 << (9 + PWM14_CHANNEL)) | (1 << (9 + PWM15_CHANNEL))) + +// COM registers +#if (INTERFACE == INTERFACE_UART) +#ifndef COM_NUMBER +#define COM_NUMBER 0 +#endif +#define COM_PCONP0 3 +#define COM_PCONP1 4 +#define COM_PCONP2 24 +#define COM_PCONP3 25 +#define __com_pconp__(X) COM_PCONP##X +#define __compconp__(X) __com_pconp__(X) + +// this MCU does not work well with both TX and RX interrupt +// this forces the sync TX method to fix communication +#define COM_USART __helper__(LPC_UART, COM_NUMBER, ) +#define COM_IRQ __helper__(UART, COM_NUMBER, _IRQn) +#define COM_PCLK __helper__(CLKPWR_PCLKSEL_UART, COM_NUMBER, ) +#if (!defined(ENABLE_SYNC_TX) || !defined(ENABLE_SYNC_RX)) +#define MCU_COM_ISR __helper__(UART, COM_NUMBER, _IRQHandler) +#endif + +#define COM_OUTREG (COM_USART)->THR +#define COM_INREG (COM_USART)->RBR + +#if (COM_NUMBER == 1 || COM_NUMBER == 2) +#if (TX_PORT == 2) +#define TX_ALT_FUNC 2 +#endif +#if (RX_PORT == 2) +#define RX_ALT_FUNC 2 +#endif +#endif +#if (COM_NUMBER == 3) +#if (TX_PORT == 0) +#define TX_ALT_FUNC 2 +#else +#define TX_ALT_FUNC 3 +#endif +#if (RX_PORT == 0) +#define RX_ALT_FUNC 2 +#else +#define RX_ALT_FUNC 3 +#endif +#endif + +#ifndef TX_ALT_FUNC +#define TX_ALT_FUNC 1 +#endif +#ifndef RX_ALT_FUNC +#define RX_ALT_FUNC 1 +#endif + +#endif + +#ifndef ITP_TIMER +#define ITP_TIMER 0 +#endif +#define ITP_TIMER_REG __helper__(LPC_TIM, ITP_TIMER, ) +#define MCU_ITP_ISR __helper__(TIMER, ITP_TIMER, _IRQHandler) +#define ITP_INT_FLAG __helper__(TIM_MR, ITP_TIMER, _INT) +#define ITP_TIMER_IRQ __helper__(TIMER, ITP_TIMER, _IRQn) + +#ifndef RTC_TIMER +#define RTC_TIMER 1 +#endif +#define RTC_TIMER_REG __helper__(LPC_TIM, RTC_TIMER, ) +#define MCU_RTC_ISR __helper__(TIMER, RTC_TIMER, _IRQHandler) +#define RTC_INT_FLAG __helper__(TIM_MR, RTC_TIMER, _INT) +#define RTC_TIMER_IRQ __helper__(TIMER, RTC_TIMER, _IRQn) + +// Indirect macro access +#define __indirect__ex__(X, Y) DIO##X##_##Y +#define __indirect__(X, Y) __indirect__ex__(X, Y) + +#define mcu_config_output(diopin) SETBIT(__indirect__(diopin, GPIOREG)->FIODIR, __indirect__(diopin, BIT)) +#define mcu_config_input(diopin) CLEARBIT(__indirect__(diopin, GPIOREG)->FIODIR, __indirect__(diopin, BIT)) +#define mcu_get_input(diopin) CHECKBIT(__indirect__(diopin, GPIOREG)->FIOPIN, __indirect__(diopin, BIT)) +#define mcu_get_output(diopin) CHECKBIT(__indirect__(diopin, GPIOREG)->FIOPIN, __indirect__(diopin, BIT)) +#define mcu_set_output(diopin) (__indirect__(diopin, GPIOREG)->FIOSET = (1 << __indirect__(diopin, BIT))) +#define mcu_clear_output(diopin) (__indirect__(diopin, GPIOREG)->FIOCLR = (1 << __indirect__(diopin, BIT))) +#define mcu_toggle_output(diopin) TOGGLEBIT(__indirect__(diopin, GPIOREG)->FIOPIN, __indirect__(diopin, BIT)) +#define mcu_set_pwm(diopin, pwmvalue) \ + { \ + LPC_PWM1->__indirect__(diopin, MR) = pwmvalue; \ + LPC_PWM1->LER |= ((uint32_t)(((__indirect__(diopin, CHANNEL)) < 7) ? (1 << (__indirect__(diopin, CHANNEL))) : 0)); \ + LPC_PWM1->TCR |= ((uint32_t)(1 << 1)); \ + LPC_PWM1->TCR &= (~((uint32_t)(1 << 1))) & ((uint32_t)(0x0000000B)); \ + } +#define mcu_get_pwm(diopin) LPC_PWM1->__indirect__(diopin, MR) + + extern volatile bool lpc_global_isr_enabled; +#define mcu_enable_global_isr() \ + { \ + __enable_irq(); \ + lpc_global_isr_enabled = true; \ + } +#define mcu_disable_global_isr() \ + { \ + lpc_global_isr_enabled = false; \ + __disable_irq(); \ + } +#define mcu_get_global_isr() lpc_global_isr_enabled + +#if (INTERFACE == INTERFACE_UART) +#define mcu_rx_ready() (CHECKBIT(COM_USART->LSR, 0)) +#define mcu_tx_ready() (CHECKBIT(COM_USART->LSR, 5)) +#elif (INTERFACE == INTERFACE_USB) +extern uint32_t tud_cdc_n_write_available(uint8_t itf); +extern uint32_t tud_cdc_n_available(uint8_t itf); +#define mcu_rx_ready() tud_cdc_n_available(0) +#define mcu_tx_ready() tud_cdc_n_write_available(0) +#endif + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/uCNC/src/hal/mcus/mcudefs.h b/uCNC/src/hal/mcus/mcudefs.h index 77f38bce5..c6b067468 100644 --- a/uCNC/src/hal/mcus/mcudefs.h +++ b/uCNC/src/hal/mcus/mcudefs.h @@ -57,6 +57,13 @@ extern "C" #endif #endif +#if (MCU == MCU_LPC176X) +#include "lpc176x/mcumap_lpc176x.h" +#ifndef CFG_TUSB_MCU +#define CFG_TUSB_MCU OPT_MCU_LPC175X_6X +#endif +#endif + #if (MCU == MCU_VIRTUAL_WIN) #include "virtual/mcumap_virtual.h" #endif diff --git a/uCNC/src/hal/mcus/mcus.h b/uCNC/src/hal/mcus/mcus.h index f140a6dd8..afa452c14 100644 --- a/uCNC/src/hal/mcus/mcus.h +++ b/uCNC/src/hal/mcus/mcus.h @@ -29,6 +29,7 @@ extern "C" #define MCU_STM32F1X 10 #define MCU_STM32F4X 11 #define MCU_SAMD21 20 +#define MCU_LPC176X 30 #define MCU_VIRTUAL_WIN 99 #ifdef __cplusplus diff --git a/uCNC/src/tinyusb/src/class/cdc/cdc.h b/uCNC/src/tinyusb/src/class/cdc/cdc.h index db6eb44a2..822d84139 100644 --- a/uCNC/src/tinyusb/src/class/cdc/cdc.h +++ b/uCNC/src/tinyusb/src/class/cdc/cdc.h @@ -39,374 +39,374 @@ extern "C" { #endif - /** \defgroup ClassDriver_CDC_Common Common Definitions - * @{ */ - - // TODO remove - /// CDC Pipe ID, used to indicate which pipe the API is addressing to (Notification, Out, In) - typedef enum - { - CDC_PIPE_NOTIFICATION, ///< Notification pipe - CDC_PIPE_DATA_IN, ///< Data in pipe - CDC_PIPE_DATA_OUT, ///< Data out pipe - CDC_PIPE_ERROR, ///< Invalid Pipe ID - } cdc_pipeid_t; - - //--------------------------------------------------------------------+ - // CDC Communication Interface Class - //--------------------------------------------------------------------+ - - /// Communication Interface Subclass Codes - typedef enum - { - CDC_COMM_SUBCLASS_DIRECT_LINE_CONTROL_MODEL = 0x01, ///< Direct Line Control Model [USBPSTN1.2] - CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL = 0x02, ///< Abstract Control Model [USBPSTN1.2] - CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL = 0x03, ///< Telephone Control Model [USBPSTN1.2] - CDC_COMM_SUBCLASS_MULTICHANNEL_CONTROL_MODEL = 0x04, ///< Multi-Channel Control Model [USBISDN1.2] - CDC_COMM_SUBCLASS_CAPI_CONTROL_MODEL = 0x05, ///< CAPI Control Model [USBISDN1.2] - CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL = 0x06, ///< Ethernet Networking Control Model [USBECM1.2] - CDC_COMM_SUBCLASS_ATM_NETWORKING_CONTROL_MODEL = 0x07, ///< ATM Networking Control Model [USBATM1.2] - CDC_COMM_SUBCLASS_WIRELESS_HANDSET_CONTROL_MODEL = 0x08, ///< Wireless Handset Control Model [USBWMC1.1] - CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT = 0x09, ///< Device Management [USBWMC1.1] - CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL = 0x0A, ///< Mobile Direct Line Model [USBWMC1.1] - CDC_COMM_SUBCLASS_OBEX = 0x0B, ///< OBEX [USBWMC1.1] - CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL = 0x0C, ///< Ethernet Emulation Model [USBEEM1.0] - CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL = 0x0D ///< Network Control Model [USBNCM1.0] - } cdc_comm_sublcass_type_t; - - /// Communication Interface Protocol Codes - typedef enum - { - CDC_COMM_PROTOCOL_NONE = 0x00, ///< No specific protocol - CDC_COMM_PROTOCOL_ATCOMMAND = 0x01, ///< AT Commands: V.250 etc - CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101 = 0x02, ///< AT Commands defined by PCCA-101 - CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101_AND_ANNEXO = 0x03, ///< AT Commands defined by PCCA-101 & Annex O - CDC_COMM_PROTOCOL_ATCOMMAND_GSM_707 = 0x04, ///< AT Commands defined by GSM 07.07 - CDC_COMM_PROTOCOL_ATCOMMAND_3GPP_27007 = 0x05, ///< AT Commands defined by 3GPP 27.007 - CDC_COMM_PROTOCOL_ATCOMMAND_CDMA = 0x06, ///< AT Commands defined by TIA for CDMA - CDC_COMM_PROTOCOL_ETHERNET_EMULATION_MODEL = 0x07 ///< Ethernet Emulation Model - } cdc_comm_protocol_type_t; - - //------------- SubType Descriptor in COMM Functional Descriptor -------------// - /// Communication Interface SubType Descriptor - typedef enum - { - CDC_FUNC_DESC_HEADER = 0x00, ///< Header Functional Descriptor, which marks the beginning of the concatenated set of functional descriptors for the interface. - CDC_FUNC_DESC_CALL_MANAGEMENT = 0x01, ///< Call Management Functional Descriptor. - CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT = 0x02, ///< Abstract Control Management Functional Descriptor. - CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT = 0x03, ///< Direct Line Management Functional Descriptor. - CDC_FUNC_DESC_TELEPHONE_RINGER = 0x04, ///< Telephone Ringer Functional Descriptor. - CDC_FUNC_DESC_TELEPHONE_CALL_AND_LINE_STATE_REPORTING_CAPACITY = 0x05, ///< Telephone Call and Line State Reporting Capabilities Functional Descriptor. - CDC_FUNC_DESC_UNION = 0x06, ///< Union Functional Descriptor - CDC_FUNC_DESC_COUNTRY_SELECTION = 0x07, ///< Country Selection Functional Descriptor - CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES = 0x08, ///< Telephone Operational ModesFunctional Descriptor - CDC_FUNC_DESC_USB_TERMINAL = 0x09, ///< USB Terminal Functional Descriptor - CDC_FUNC_DESC_NETWORK_CHANNEL_TERMINAL = 0x0A, ///< Network Channel Terminal Descriptor - CDC_FUNC_DESC_PROTOCOL_UNIT = 0x0B, ///< Protocol Unit Functional Descriptor - CDC_FUNC_DESC_EXTENSION_UNIT = 0x0C, ///< Extension Unit Functional Descriptor - CDC_FUNC_DESC_MULTICHANEL_MANAGEMENT = 0x0D, ///< Multi-Channel Management Functional Descriptor - CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT = 0x0E, ///< CAPI Control Management Functional Descriptor - CDC_FUNC_DESC_ETHERNET_NETWORKING = 0x0F, ///< Ethernet Networking Functional Descriptor - CDC_FUNC_DESC_ATM_NETWORKING = 0x10, ///< ATM Networking Functional Descriptor - CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL = 0x11, ///< Wireless Handset Control Model Functional Descriptor - CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL = 0x12, ///< Mobile Direct Line Model Functional Descriptor - CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL = 0x13, ///< MDLM Detail Functional Descriptor - CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL = 0x14, ///< Device Management Model Functional Descriptor - CDC_FUNC_DESC_OBEX = 0x15, ///< OBEX Functional Descriptor - CDC_FUNC_DESC_COMMAND_SET = 0x16, ///< Command Set Functional Descriptor - CDC_FUNC_DESC_COMMAND_SET_DETAIL = 0x17, ///< Command Set Detail Functional Descriptor - CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL = 0x18, ///< Telephone Control Model Functional Descriptor - CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER = 0x19, ///< OBEX Service Identifier Functional Descriptor - CDC_FUNC_DESC_NCM = 0x1A, ///< NCM Functional Descriptor - } cdc_func_desc_type_t; - - //--------------------------------------------------------------------+ - // CDC Data Interface Class - //--------------------------------------------------------------------+ - - // SUBCLASS code of Data Interface is not used and should/must be zero - - // Data Interface Protocol Codes - typedef enum - { - CDC_DATA_PROTOCOL_ISDN_BRI = 0x30, ///< Physical interface protocol for ISDN BRI - CDC_DATA_PROTOCOL_HDLC = 0x31, ///< HDLC - CDC_DATA_PROTOCOL_TRANSPARENT = 0x32, ///< Transparent - CDC_DATA_PROTOCOL_Q921_MANAGEMENT = 0x50, ///< Management protocol for Q.921 data link protocol - CDC_DATA_PROTOCOL_Q921_DATA_LINK = 0x51, ///< Data link protocol for Q.931 - CDC_DATA_PROTOCOL_Q921_TEI_MULTIPLEXOR = 0x52, ///< TEI-multiplexor for Q.921 data link protocol - CDC_DATA_PROTOCOL_V42BIS_DATA_COMPRESSION = 0x90, ///< Data compression procedures - CDC_DATA_PROTOCOL_EURO_ISDN = 0x91, ///< Euro-ISDN protocol control - CDC_DATA_PROTOCOL_V24_RATE_ADAPTION_TO_ISDN = 0x92, ///< V.24 rate adaptation to ISDN - CDC_DATA_PROTOCOL_CAPI_COMMAND = 0x93, ///< CAPI Commands - CDC_DATA_PROTOCOL_HOST_BASED_DRIVER = 0xFD, ///< Host based driver. Note: This protocol code should only be used in messages between host and device to identify the host driver portion of a protocol stack. - CDC_DATA_PROTOCOL_IN_PROTOCOL_UNIT_FUNCTIONAL_DESCRIPTOR = 0xFE ///< The protocol(s) are described using a ProtocolUnit Functional Descriptors on Communications Class Interface - } cdc_data_protocol_type_t; - - //--------------------------------------------------------------------+ - // Management Element Request (Control Endpoint) - //--------------------------------------------------------------------+ - - /// Communication Interface Management Element Request Codes - typedef enum - { - CDC_REQUEST_SEND_ENCAPSULATED_COMMAND = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface - CDC_REQUEST_GET_ENCAPSULATED_RESPONSE = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface. - CDC_REQUEST_SET_COMM_FEATURE = 0x02, - CDC_REQUEST_GET_COMM_FEATURE = 0x03, - CDC_REQUEST_CLEAR_COMM_FEATURE = 0x04, - - CDC_REQUEST_SET_AUX_LINE_STATE = 0x10, - CDC_REQUEST_SET_HOOK_STATE = 0x11, - CDC_REQUEST_PULSE_SETUP = 0x12, - CDC_REQUEST_SEND_PULSE = 0x13, - CDC_REQUEST_SET_PULSE_TIME = 0x14, - CDC_REQUEST_RING_AUX_JACK = 0x15, - - CDC_REQUEST_SET_LINE_CODING = 0x20, - CDC_REQUEST_GET_LINE_CODING = 0x21, - CDC_REQUEST_SET_CONTROL_LINE_STATE = 0x22, - CDC_REQUEST_SEND_BREAK = 0x23, - - CDC_REQUEST_SET_RINGER_PARMS = 0x30, - CDC_REQUEST_GET_RINGER_PARMS = 0x31, - CDC_REQUEST_SET_OPERATION_PARMS = 0x32, - CDC_REQUEST_GET_OPERATION_PARMS = 0x33, - CDC_REQUEST_SET_LINE_PARMS = 0x34, - CDC_REQUEST_GET_LINE_PARMS = 0x35, - CDC_REQUEST_DIAL_DIGITS = 0x36, - CDC_REQUEST_SET_UNIT_PARAMETER = 0x37, - CDC_REQUEST_GET_UNIT_PARAMETER = 0x38, - CDC_REQUEST_CLEAR_UNIT_PARAMETER = 0x39, - CDC_REQUEST_GET_PROFILE = 0x3A, - - CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS = 0x40, - CDC_REQUEST_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x41, - CDC_REQUEST_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x42, - CDC_REQUEST_SET_ETHERNET_PACKET_FILTER = 0x43, - CDC_REQUEST_GET_ETHERNET_STATISTIC = 0x44, - - CDC_REQUEST_SET_ATM_DATA_FORMAT = 0x50, - CDC_REQUEST_GET_ATM_DEVICE_STATISTICS = 0x51, - CDC_REQUEST_SET_ATM_DEFAULT_VC = 0x52, - CDC_REQUEST_GET_ATM_VC_STATISTICS = 0x53, - - CDC_REQUEST_MDLM_SEMANTIC_MODEL = 0x60, - } cdc_management_request_t; - - //--------------------------------------------------------------------+ - // Management Elemenent Notification (Notification Endpoint) - //--------------------------------------------------------------------+ - - /// 6.3 Notification Codes - typedef enum - { - CDC_NOTIF_NETWORK_CONNECTION = 0x00, ///< This notification allows the device to notify the host about network connection status. - CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request. - CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08, - CDC_NOTIF_RING_DETECT = 0x09, - CDC_NOTIF_SERIAL_STATE = 0x20, - CDC_NOTIF_CALL_STATE_CHANGE = 0x28, - CDC_NOTIF_LINE_STATE_CHANGE = 0x29, - CDC_NOTIF_CONNECTION_SPEED_CHANGE = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred - CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40, - } cdc_notification_request_t; - - //--------------------------------------------------------------------+ - // Class Specific Functional Descriptor (Communication Interface) - //--------------------------------------------------------------------+ - - // Start of all packed definitions for compiler without per-type packed - TU_ATTR_PACKED_BEGIN - TU_ATTR_BIT_FIELD_ORDER_BEGIN - - /// Header Functional Descriptor (Communication Interface) - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific - uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUNC_DESC_ - uint16_t bcdCDC; ///< CDC release number in Binary-Coded Decimal - } cdc_desc_func_header_t; - - /// Union Functional Descriptor (Communication Interface) - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific - uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ - uint8_t bControlInterface; ///< Interface number of Communication Interface - uint8_t bSubordinateInterface; ///< Array of Interface number of Data Interface - } cdc_desc_func_union_t; + /** \defgroup ClassDriver_CDC_Common Common Definitions + * @{ */ + + // TODO remove + /// CDC Pipe ID, used to indicate which pipe the API is addressing to (Notification, Out, In) + typedef enum + { + CDC_PIPE_NOTIFICATION, ///< Notification pipe + CDC_PIPE_DATA_IN, ///< Data in pipe + CDC_PIPE_DATA_OUT, ///< Data out pipe + CDC_PIPE_ERROR, ///< Invalid Pipe ID + } cdc_pipeid_t; + + //--------------------------------------------------------------------+ + // CDC Communication Interface Class + //--------------------------------------------------------------------+ + + /// Communication Interface Subclass Codes + typedef enum + { + CDC_COMM_SUBCLASS_DIRECT_LINE_CONTROL_MODEL = 0x01, ///< Direct Line Control Model [USBPSTN1.2] + CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL = 0x02, ///< Abstract Control Model [USBPSTN1.2] + CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL = 0x03, ///< Telephone Control Model [USBPSTN1.2] + CDC_COMM_SUBCLASS_MULTICHANNEL_CONTROL_MODEL = 0x04, ///< Multi-Channel Control Model [USBISDN1.2] + CDC_COMM_SUBCLASS_CAPI_CONTROL_MODEL = 0x05, ///< CAPI Control Model [USBISDN1.2] + CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL = 0x06, ///< Ethernet Networking Control Model [USBECM1.2] + CDC_COMM_SUBCLASS_ATM_NETWORKING_CONTROL_MODEL = 0x07, ///< ATM Networking Control Model [USBATM1.2] + CDC_COMM_SUBCLASS_WIRELESS_HANDSET_CONTROL_MODEL = 0x08, ///< Wireless Handset Control Model [USBWMC1.1] + CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT = 0x09, ///< Device Management [USBWMC1.1] + CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL = 0x0A, ///< Mobile Direct Line Model [USBWMC1.1] + CDC_COMM_SUBCLASS_OBEX = 0x0B, ///< OBEX [USBWMC1.1] + CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL = 0x0C, ///< Ethernet Emulation Model [USBEEM1.0] + CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL = 0x0D ///< Network Control Model [USBNCM1.0] + } cdc_comm_sublcass_type_t; + + /// Communication Interface Protocol Codes + typedef enum + { + CDC_COMM_PROTOCOL_NONE = 0x00, ///< No specific protocol + CDC_COMM_PROTOCOL_ATCOMMAND = 0x01, ///< AT Commands: V.250 etc + CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101 = 0x02, ///< AT Commands defined by PCCA-101 + CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101_AND_ANNEXO = 0x03, ///< AT Commands defined by PCCA-101 & Annex O + CDC_COMM_PROTOCOL_ATCOMMAND_GSM_707 = 0x04, ///< AT Commands defined by GSM 07.07 + CDC_COMM_PROTOCOL_ATCOMMAND_3GPP_27007 = 0x05, ///< AT Commands defined by 3GPP 27.007 + CDC_COMM_PROTOCOL_ATCOMMAND_CDMA = 0x06, ///< AT Commands defined by TIA for CDMA + CDC_COMM_PROTOCOL_ETHERNET_EMULATION_MODEL = 0x07 ///< Ethernet Emulation Model + } cdc_comm_protocol_type_t; + + //------------- SubType Descriptor in COMM Functional Descriptor -------------// + /// Communication Interface SubType Descriptor + typedef enum + { + CDC_FUNC_DESC_HEADER = 0x00, ///< Header Functional Descriptor, which marks the beginning of the concatenated set of functional descriptors for the interface. + CDC_FUNC_DESC_CALL_MANAGEMENT = 0x01, ///< Call Management Functional Descriptor. + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT = 0x02, ///< Abstract Control Management Functional Descriptor. + CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT = 0x03, ///< Direct Line Management Functional Descriptor. + CDC_FUNC_DESC_TELEPHONE_RINGER = 0x04, ///< Telephone Ringer Functional Descriptor. + CDC_FUNC_DESC_TELEPHONE_CALL_AND_LINE_STATE_REPORTING_CAPACITY = 0x05, ///< Telephone Call and Line State Reporting Capabilities Functional Descriptor. + CDC_FUNC_DESC_UNION = 0x06, ///< Union Functional Descriptor + CDC_FUNC_DESC_COUNTRY_SELECTION = 0x07, ///< Country Selection Functional Descriptor + CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES = 0x08, ///< Telephone Operational ModesFunctional Descriptor + CDC_FUNC_DESC_USB_TERMINAL = 0x09, ///< USB Terminal Functional Descriptor + CDC_FUNC_DESC_NETWORK_CHANNEL_TERMINAL = 0x0A, ///< Network Channel Terminal Descriptor + CDC_FUNC_DESC_PROTOCOL_UNIT = 0x0B, ///< Protocol Unit Functional Descriptor + CDC_FUNC_DESC_EXTENSION_UNIT = 0x0C, ///< Extension Unit Functional Descriptor + CDC_FUNC_DESC_MULTICHANEL_MANAGEMENT = 0x0D, ///< Multi-Channel Management Functional Descriptor + CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT = 0x0E, ///< CAPI Control Management Functional Descriptor + CDC_FUNC_DESC_ETHERNET_NETWORKING = 0x0F, ///< Ethernet Networking Functional Descriptor + CDC_FUNC_DESC_ATM_NETWORKING = 0x10, ///< ATM Networking Functional Descriptor + CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL = 0x11, ///< Wireless Handset Control Model Functional Descriptor + CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL = 0x12, ///< Mobile Direct Line Model Functional Descriptor + CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL = 0x13, ///< MDLM Detail Functional Descriptor + CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL = 0x14, ///< Device Management Model Functional Descriptor + CDC_FUNC_DESC_OBEX = 0x15, ///< OBEX Functional Descriptor + CDC_FUNC_DESC_COMMAND_SET = 0x16, ///< Command Set Functional Descriptor + CDC_FUNC_DESC_COMMAND_SET_DETAIL = 0x17, ///< Command Set Detail Functional Descriptor + CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL = 0x18, ///< Telephone Control Model Functional Descriptor + CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER = 0x19, ///< OBEX Service Identifier Functional Descriptor + CDC_FUNC_DESC_NCM = 0x1A, ///< NCM Functional Descriptor + } cdc_func_desc_type_t; + + //--------------------------------------------------------------------+ + // CDC Data Interface Class + //--------------------------------------------------------------------+ + + // SUBCLASS code of Data Interface is not used and should/must be zero + + // Data Interface Protocol Codes + typedef enum + { + CDC_DATA_PROTOCOL_ISDN_BRI = 0x30, ///< Physical interface protocol for ISDN BRI + CDC_DATA_PROTOCOL_HDLC = 0x31, ///< HDLC + CDC_DATA_PROTOCOL_TRANSPARENT = 0x32, ///< Transparent + CDC_DATA_PROTOCOL_Q921_MANAGEMENT = 0x50, ///< Management protocol for Q.921 data link protocol + CDC_DATA_PROTOCOL_Q921_DATA_LINK = 0x51, ///< Data link protocol for Q.931 + CDC_DATA_PROTOCOL_Q921_TEI_MULTIPLEXOR = 0x52, ///< TEI-multiplexor for Q.921 data link protocol + CDC_DATA_PROTOCOL_V42BIS_DATA_COMPRESSION = 0x90, ///< Data compression procedures + CDC_DATA_PROTOCOL_EURO_ISDN = 0x91, ///< Euro-ISDN protocol control + CDC_DATA_PROTOCOL_V24_RATE_ADAPTION_TO_ISDN = 0x92, ///< V.24 rate adaptation to ISDN + CDC_DATA_PROTOCOL_CAPI_COMMAND = 0x93, ///< CAPI Commands + CDC_DATA_PROTOCOL_HOST_BASED_DRIVER = 0xFD, ///< Host based driver. Note: This protocol code should only be used in messages between host and device to identify the host driver portion of a protocol stack. + CDC_DATA_PROTOCOL_IN_PROTOCOL_UNIT_FUNCTIONAL_DESCRIPTOR = 0xFE ///< The protocol(s) are described using a ProtocolUnit Functional Descriptors on Communications Class Interface + } cdc_data_protocol_type_t; + + //--------------------------------------------------------------------+ + // Management Element Request (Control Endpoint) + //--------------------------------------------------------------------+ + + /// Communication Interface Management Element Request Codes + typedef enum + { + CDC_REQUEST_SEND_ENCAPSULATED_COMMAND = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface + CDC_REQUEST_GET_ENCAPSULATED_RESPONSE = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface. + CDC_REQUEST_SET_COMM_FEATURE = 0x02, + CDC_REQUEST_GET_COMM_FEATURE = 0x03, + CDC_REQUEST_CLEAR_COMM_FEATURE = 0x04, + + CDC_REQUEST_SET_AUX_LINE_STATE = 0x10, + CDC_REQUEST_SET_HOOK_STATE = 0x11, + CDC_REQUEST_PULSE_SETUP = 0x12, + CDC_REQUEST_SEND_PULSE = 0x13, + CDC_REQUEST_SET_PULSE_TIME = 0x14, + CDC_REQUEST_RING_AUX_JACK = 0x15, + + CDC_REQUEST_SET_LINE_CODING = 0x20, + CDC_REQUEST_GET_LINE_CODING = 0x21, + CDC_REQUEST_SET_CONTROL_LINE_STATE = 0x22, + CDC_REQUEST_SEND_BREAK = 0x23, + + CDC_REQUEST_SET_RINGER_PARMS = 0x30, + CDC_REQUEST_GET_RINGER_PARMS = 0x31, + CDC_REQUEST_SET_OPERATION_PARMS = 0x32, + CDC_REQUEST_GET_OPERATION_PARMS = 0x33, + CDC_REQUEST_SET_LINE_PARMS = 0x34, + CDC_REQUEST_GET_LINE_PARMS = 0x35, + CDC_REQUEST_DIAL_DIGITS = 0x36, + CDC_REQUEST_SET_UNIT_PARAMETER = 0x37, + CDC_REQUEST_GET_UNIT_PARAMETER = 0x38, + CDC_REQUEST_CLEAR_UNIT_PARAMETER = 0x39, + CDC_REQUEST_GET_PROFILE = 0x3A, + + CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS = 0x40, + CDC_REQUEST_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x41, + CDC_REQUEST_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x42, + CDC_REQUEST_SET_ETHERNET_PACKET_FILTER = 0x43, + CDC_REQUEST_GET_ETHERNET_STATISTIC = 0x44, + + CDC_REQUEST_SET_ATM_DATA_FORMAT = 0x50, + CDC_REQUEST_GET_ATM_DEVICE_STATISTICS = 0x51, + CDC_REQUEST_SET_ATM_DEFAULT_VC = 0x52, + CDC_REQUEST_GET_ATM_VC_STATISTICS = 0x53, + + CDC_REQUEST_MDLM_SEMANTIC_MODEL = 0x60, + } cdc_management_request_t; + + //--------------------------------------------------------------------+ + // Management Elemenent Notification (Notification Endpoint) + //--------------------------------------------------------------------+ + + /// 6.3 Notification Codes + typedef enum + { + CDC_NOTIF_NETWORK_CONNECTION = 0x00, ///< This notification allows the device to notify the host about network connection status. + CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request. + CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08, + CDC_NOTIF_RING_DETECT = 0x09, + CDC_NOTIF_COM_STATE = 0x20, + CDC_NOTIF_CALL_STATE_CHANGE = 0x28, + CDC_NOTIF_LINE_STATE_CHANGE = 0x29, + CDC_NOTIF_CONNECTION_SPEED_CHANGE = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred + CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40, + } cdc_notification_request_t; + + //--------------------------------------------------------------------+ + // Class Specific Functional Descriptor (Communication Interface) + //--------------------------------------------------------------------+ + + // Start of all packed definitions for compiler without per-type packed + TU_ATTR_PACKED_BEGIN + TU_ATTR_BIT_FIELD_ORDER_BEGIN + + /// Header Functional Descriptor (Communication Interface) + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific + uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUNC_DESC_ + uint16_t bcdCDC; ///< CDC release number in Binary-Coded Decimal + } cdc_desc_func_header_t; + + /// Union Functional Descriptor (Communication Interface) + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific + uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ + uint8_t bControlInterface; ///< Interface number of Communication Interface + uint8_t bSubordinateInterface; ///< Array of Interface number of Data Interface + } cdc_desc_func_union_t; #define cdc_desc_func_union_n_t(no_slave) \ - struct TU_ATTR_PACKED \ - { \ - uint8_t bLength; \ - uint8_t bDescriptorType; \ - uint8_t bDescriptorSubType; \ - uint8_t bControlInterface; \ - uint8_t bSubordinateInterface[no_slave]; \ - } - - /// Country Selection Functional Descriptor (Communication Interface) - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific - uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ - uint8_t iCountryCodeRelDate; ///< Index of a string giving the release date for the implemented ISO 3166 Country Codes. - uint16_t wCountryCode; ///< Country code in the format as defined in [ISO3166], release date as specified inoffset 3 for the first supported country. - } cdc_desc_func_country_selection_t; + struct TU_ATTR_PACKED \ + { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bControlInterface; \ + uint8_t bSubordinateInterface[no_slave]; \ + } + + /// Country Selection Functional Descriptor (Communication Interface) + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific + uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ + uint8_t iCountryCodeRelDate; ///< Index of a string giving the release date for the implemented ISO 3166 Country Codes. + uint16_t wCountryCode; ///< Country code in the format as defined in [ISO3166], release date as specified inoffset 3 for the first supported country. + } cdc_desc_func_country_selection_t; #define cdc_desc_func_country_selection_n_t(no_country) \ - struct TU_ATTR_PACKED \ - { \ - uint8_t bLength; \ - uint8_t bDescriptorType; \ - uint8_t bDescriptorSubType; \ - uint8_t iCountryCodeRelDate; \ - uint16_t wCountryCode[no_country]; \ - } - - //--------------------------------------------------------------------+ - // PUBLIC SWITCHED TELEPHONE NETWORK (PSTN) SUBCLASS - //--------------------------------------------------------------------+ - - /// \brief Call Management Functional Descriptor - /// \details This functional descriptor describes the processing of calls for the Communications Class interface. - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific - uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ - - struct - { - uint8_t handle_call : 1; ///< 0 - Device sends/receives call management information only over the Communications Class interface. 1 - Device can send/receive call management information over a Data Class interface. - uint8_t send_recv_call : 1; ///< 0 - Device does not handle call management itself. 1 - Device handles call management itself. - uint8_t TU_RESERVED : 6; - } bmCapabilities; - - uint8_t bDataInterface; - } cdc_desc_func_call_management_t; - - typedef struct TU_ATTR_PACKED - { - uint8_t support_comm_request : 1; ///< Device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature. - uint8_t support_line_request : 1; ///< Device supports the request combination of Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State. - uint8_t support_send_break : 1; ///< Device supports the request Send_Break - uint8_t support_notification_network_connection : 1; ///< Device supports the notification Network_Connection. - uint8_t TU_RESERVED : 4; - } cdc_acm_capability_t; - - TU_VERIFY_STATIC(sizeof(cdc_acm_capability_t) == 1, "mostly problem with compiler"); - - /// Abstract Control Management Functional Descriptor - /// This functional descriptor describes the commands supported by by the Communications Class interface with SubClass code of \ref CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific - uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ - cdc_acm_capability_t bmCapabilities; - } cdc_desc_func_acm_t; - - /// \brief Direct Line Management Functional Descriptor - /// \details This functional descriptor describes the commands supported by the Communications Class interface with SubClass code of \ref CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific - uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ - struct - { - uint8_t require_pulse_setup : 1; ///< Device requires extra Pulse_Setup request during pulse dialing sequence to disengage holding circuit. - uint8_t support_aux_request : 1; ///< Device supports the request combination of Set_Aux_Line_State, Ring_Aux_Jack, and notification Aux_Jack_Hook_State. - uint8_t support_pulse_request : 1; ///< Device supports the request combination of Pulse_Setup, Send_Pulse, and Set_Pulse_Time. - uint8_t TU_RESERVED : 5; - } bmCapabilities; - } cdc_desc_func_direct_line_management_t; - - /// \brief Telephone Ringer Functional Descriptor - /// \details The Telephone Ringer functional descriptor describes the ringer capabilities supported by the Communications Class interface, - /// with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific - uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ - uint8_t bRingerVolSteps; - uint8_t bNumRingerPatterns; - } cdc_desc_func_telephone_ringer_t; - - /// \brief Telephone Operational Modes Functional Descriptor - /// \details The Telephone Operational Modes functional descriptor describes the operational modes supported by - /// the Communications Class interface, with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific - uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ - struct - { - uint8_t simple_mode : 1; - uint8_t standalone_mode : 1; - uint8_t computer_centric_mode : 1; - uint8_t TU_RESERVED : 5; - } bmCapabilities; - } cdc_desc_func_telephone_operational_modes_t; - - /// \brief Telephone Call and Line State Reporting Capabilities Descriptor - /// \details The Telephone Call and Line State Reporting Capabilities functional descriptor describes the abilities of a - /// telephone device to report optional call and line states. - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific - uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ - struct - { - uint32_t interrupted_dialtone : 1; ///< 0 : Reports only dialtone (does not differentiate between normal and interrupted dialtone). 1 : Reports interrupted dialtone in addition to normal dialtone - uint32_t ringback_busy_fastbusy : 1; ///< 0 : Reports only dialing state. 1 : Reports ringback, busy, and fast busy states. - uint32_t caller_id : 1; ///< 0 : Does not report caller ID. 1 : Reports caller ID information. - uint32_t incoming_distinctive : 1; ///< 0 : Reports only incoming ringing. 1 : Reports incoming distinctive ringing patterns. - uint32_t dual_tone_multi_freq : 1; ///< 0 : Cannot report dual tone multi-frequency (DTMF) digits input remotely over the telephone line. 1 : Can report DTMF digits input remotely over the telephone line. - uint32_t line_state_change : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification - uint32_t TU_RESERVED : 26; - } bmCapabilities; - } cdc_desc_func_telephone_call_state_reporting_capabilities_t; - - // TODO remove - static inline uint8_t cdc_functional_desc_typeof(uint8_t const *p_desc) - { - return p_desc[2]; - } - - //--------------------------------------------------------------------+ - // Requests - //--------------------------------------------------------------------+ - typedef struct TU_ATTR_PACKED - { - uint32_t bit_rate; - uint8_t stop_bits; ///< 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits - uint8_t parity; ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space - uint8_t data_bits; ///< can be 5, 6, 7, 8 or 16 - } cdc_line_coding_t; - - TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct"); - - typedef struct TU_ATTR_PACKED - { - uint16_t dte_is_present : 1; ///< Indicates to DCE if DTE is presentor not. This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR. - uint16_t half_duplex_carrier_control : 1; - uint16_t : 14; - } cdc_line_control_state_t; - - TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct"); - - TU_ATTR_PACKED_END // End of all packed definitions - TU_ATTR_BIT_FIELD_ORDER_END + struct TU_ATTR_PACKED \ + { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t iCountryCodeRelDate; \ + uint16_t wCountryCode[no_country]; \ + } + + //--------------------------------------------------------------------+ + // PUBLIC SWITCHED TELEPHONE NETWORK (PSTN) SUBCLASS + //--------------------------------------------------------------------+ + + /// \brief Call Management Functional Descriptor + /// \details This functional descriptor describes the processing of calls for the Communications Class interface. + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific + uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ + + struct + { + uint8_t handle_call : 1; ///< 0 - Device sends/receives call management information only over the Communications Class interface. 1 - Device can send/receive call management information over a Data Class interface. + uint8_t send_recv_call : 1; ///< 0 - Device does not handle call management itself. 1 - Device handles call management itself. + uint8_t TU_RESERVED : 6; + } bmCapabilities; + + uint8_t bDataInterface; + } cdc_desc_func_call_management_t; + + typedef struct TU_ATTR_PACKED + { + uint8_t support_comm_request : 1; ///< Device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature. + uint8_t support_line_request : 1; ///< Device supports the request combination of Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State. + uint8_t support_send_break : 1; ///< Device supports the request Send_Break + uint8_t support_notification_network_connection : 1; ///< Device supports the notification Network_Connection. + uint8_t TU_RESERVED : 4; + } cdc_acm_capability_t; + + TU_VERIFY_STATIC(sizeof(cdc_acm_capability_t) == 1, "mostly problem with compiler"); + + /// Abstract Control Management Functional Descriptor + /// This functional descriptor describes the commands supported by by the Communications Class interface with SubClass code of \ref CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific + uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ + cdc_acm_capability_t bmCapabilities; + } cdc_desc_func_acm_t; + + /// \brief Direct Line Management Functional Descriptor + /// \details This functional descriptor describes the commands supported by the Communications Class interface with SubClass code of \ref CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific + uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ + struct + { + uint8_t require_pulse_setup : 1; ///< Device requires extra Pulse_Setup request during pulse dialing sequence to disengage holding circuit. + uint8_t support_aux_request : 1; ///< Device supports the request combination of Set_Aux_Line_State, Ring_Aux_Jack, and notification Aux_Jack_Hook_State. + uint8_t support_pulse_request : 1; ///< Device supports the request combination of Pulse_Setup, Send_Pulse, and Set_Pulse_Time. + uint8_t TU_RESERVED : 5; + } bmCapabilities; + } cdc_desc_func_direct_line_management_t; + + /// \brief Telephone Ringer Functional Descriptor + /// \details The Telephone Ringer functional descriptor describes the ringer capabilities supported by the Communications Class interface, + /// with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific + uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ + uint8_t bRingerVolSteps; + uint8_t bNumRingerPatterns; + } cdc_desc_func_telephone_ringer_t; + + /// \brief Telephone Operational Modes Functional Descriptor + /// \details The Telephone Operational Modes functional descriptor describes the operational modes supported by + /// the Communications Class interface, with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific + uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ + struct + { + uint8_t simple_mode : 1; + uint8_t standalone_mode : 1; + uint8_t computer_centric_mode : 1; + uint8_t TU_RESERVED : 5; + } bmCapabilities; + } cdc_desc_func_telephone_operational_modes_t; + + /// \brief Telephone Call and Line State Reporting Capabilities Descriptor + /// \details The Telephone Call and Line State Reporting Capabilities functional descriptor describes the abilities of a + /// telephone device to report optional call and line states. + typedef struct TU_ATTR_PACKED + { + uint8_t bLength; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType; ///< Descriptor Type, must be Class-Specific + uint8_t bDescriptorSubType; ///< Descriptor SubType one of above CDC_FUCN_DESC_ + struct + { + uint32_t interrupted_dialtone : 1; ///< 0 : Reports only dialtone (does not differentiate between normal and interrupted dialtone). 1 : Reports interrupted dialtone in addition to normal dialtone + uint32_t ringback_busy_fastbusy : 1; ///< 0 : Reports only dialing state. 1 : Reports ringback, busy, and fast busy states. + uint32_t caller_id : 1; ///< 0 : Does not report caller ID. 1 : Reports caller ID information. + uint32_t incoming_distinctive : 1; ///< 0 : Reports only incoming ringing. 1 : Reports incoming distinctive ringing patterns. + uint32_t dual_tone_multi_freq : 1; ///< 0 : Cannot report dual tone multi-frequency (DTMF) digits input remotely over the telephone line. 1 : Can report DTMF digits input remotely over the telephone line. + uint32_t line_state_change : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification + uint32_t TU_RESERVED : 26; + } bmCapabilities; + } cdc_desc_func_telephone_call_state_reporting_capabilities_t; + + // TODO remove + static inline uint8_t cdc_functional_desc_typeof(uint8_t const *p_desc) + { + return p_desc[2]; + } + + //--------------------------------------------------------------------+ + // Requests + //--------------------------------------------------------------------+ + typedef struct TU_ATTR_PACKED + { + uint32_t bit_rate; + uint8_t stop_bits; ///< 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits + uint8_t parity; ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space + uint8_t data_bits; ///< can be 5, 6, 7, 8 or 16 + } cdc_line_coding_t; + + TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct"); + + typedef struct TU_ATTR_PACKED + { + uint16_t dte_is_present : 1; ///< Indicates to DCE if DTE is presentor not. This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR. + uint16_t half_duplex_carrier_control : 1; + uint16_t : 14; + } cdc_line_control_state_t; + + TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct"); + + TU_ATTR_PACKED_END // End of all packed definitions + TU_ATTR_BIT_FIELD_ORDER_END #ifdef __cplusplus } diff --git a/uCNC/src/tinyusb/src/class/cdc/cdc_device.c b/uCNC/src/tinyusb/src/class/cdc/cdc_device.c index 011c99e6d..acc201100 100644 --- a/uCNC/src/tinyusb/src/class/cdc/cdc_device.c +++ b/uCNC/src/tinyusb/src/class/cdc/cdc_device.c @@ -38,38 +38,38 @@ //--------------------------------------------------------------------+ enum { - BULK_PACKET_SIZE = (TUD_OPT_HIGH_SPEED ? 512 : 64) + BULK_PACKET_SIZE = (TUD_OPT_HIGH_SPEED ? 512 : 64) }; typedef struct { - uint8_t itf_num; - uint8_t ep_notif; - uint8_t ep_in; - uint8_t ep_out; + uint8_t itf_num; + uint8_t ep_notif; + uint8_t ep_in; + uint8_t ep_out; - // Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) - uint8_t line_state; + // Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) + uint8_t line_state; - /*------------- From this point, data is not cleared by bus reset -------------*/ - char wanted_char; - cdc_line_coding_t line_coding; + /*------------- From this point, data is not cleared by bus reset -------------*/ + char wanted_char; + cdc_line_coding_t line_coding; - // FIFO - tu_fifo_t rx_ff; - tu_fifo_t tx_ff; + // FIFO + tu_fifo_t rx_ff; + tu_fifo_t tx_ff; - uint8_t rx_ff_buf[CFG_TUD_CDC_RX_BUFSIZE]; - uint8_t tx_ff_buf[CFG_TUD_CDC_TX_BUFSIZE]; + uint8_t rx_ff_buf[CFG_TUD_CDC_RX_BUFSIZE]; + uint8_t tx_ff_buf[CFG_TUD_CDC_TX_BUFSIZE]; #if CFG_FIFO_MUTEX - osal_mutex_def_t rx_ff_mutex; - osal_mutex_def_t tx_ff_mutex; + osal_mutex_def_t rx_ff_mutex; + osal_mutex_def_t tx_ff_mutex; #endif - // Endpoint Transfer buffer - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + // Endpoint Transfer buffer + CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; + CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; } cdcd_interface_t; @@ -82,32 +82,32 @@ CFG_TUSB_MEM_SECTION static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; static bool _prep_out_transaction(cdcd_interface_t *p_cdc) { - uint8_t const rhport = TUD_OPT_RHPORT; - uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff); - - // Prepare for incoming data but only allow what we can store in the ring buffer. - // TODO Actually we can still carry out the transfer, keeping count of received bytes - // and slowly move it to the FIFO when read(). - // This pre-check reduces endpoint claiming - TU_VERIFY(available >= sizeof(p_cdc->epout_buf)); - - // claim endpoint - TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out)); - - // fifo can be changed before endpoint is claimed - available = tu_fifo_remaining(&p_cdc->rx_ff); - - if (available >= sizeof(p_cdc->epout_buf)) - { - return usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf)); - } - else - { - // Release endpoint since we don't make any transfer - usbd_edpt_release(rhport, p_cdc->ep_out); - - return false; - } + uint8_t const rhport = TUD_OPT_RHPORT; + uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff); + + // Prepare for incoming data but only allow what we can store in the ring buffer. + // TODO Actually we can still carry out the transfer, keeping count of received bytes + // and slowly move it to the FIFO when read(). + // This pre-check reduces endpoint claiming + TU_VERIFY(available >= sizeof(p_cdc->epout_buf)); + + // claim endpoint + TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out)); + + // fifo can be changed before endpoint is claimed + available = tu_fifo_remaining(&p_cdc->rx_ff); + + if (available >= sizeof(p_cdc->epout_buf)) + { + return usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf)); + } + else + { + // Release endpoint since we don't make any transfer + usbd_edpt_release(rhport, p_cdc->ep_out); + + return false; + } } //--------------------------------------------------------------------+ @@ -115,23 +115,23 @@ static bool _prep_out_transaction(cdcd_interface_t *p_cdc) //--------------------------------------------------------------------+ bool tud_cdc_n_connected(uint8_t itf) { - // DTR (bit 0) active is considered as connected - return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0); + // DTR (bit 0) active is considered as connected + return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0); } uint8_t tud_cdc_n_get_line_state(uint8_t itf) { - return _cdcd_itf[itf].line_state; + return _cdcd_itf[itf].line_state; } void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t *coding) { - (*coding) = _cdcd_itf[itf].line_coding; + (*coding) = _cdcd_itf[itf].line_coding; } void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted) { - _cdcd_itf[itf].wanted_char = wanted; + _cdcd_itf[itf].wanted_char = wanted; } //--------------------------------------------------------------------+ @@ -139,27 +139,27 @@ void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted) //--------------------------------------------------------------------+ uint32_t tud_cdc_n_available(uint8_t itf) { - return tu_fifo_count(&_cdcd_itf[itf].rx_ff); + return tu_fifo_count(&_cdcd_itf[itf].rx_ff); } uint32_t tud_cdc_n_read(uint8_t itf, void *buffer, uint32_t bufsize) { - cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; - uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, bufsize); - _prep_out_transaction(p_cdc); - return num_read; + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, bufsize); + _prep_out_transaction(p_cdc); + return num_read; } bool tud_cdc_n_peek(uint8_t itf, uint8_t *chr) { - return tu_fifo_peek(&_cdcd_itf[itf].rx_ff, chr); + return tu_fifo_peek(&_cdcd_itf[itf].rx_ff, chr); } void tud_cdc_n_read_flush(uint8_t itf) { - cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; - tu_fifo_clear(&p_cdc->rx_ff); - _prep_out_transaction(p_cdc); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + tu_fifo_clear(&p_cdc->rx_ff); + _prep_out_transaction(p_cdc); } //--------------------------------------------------------------------+ @@ -167,59 +167,59 @@ void tud_cdc_n_read_flush(uint8_t itf) //--------------------------------------------------------------------+ uint32_t tud_cdc_n_write(uint8_t itf, void const *buffer, uint32_t bufsize) { - cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; - uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, bufsize); + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, bufsize); - // flush if queue more than packet size - if (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE) - { - tud_cdc_n_write_flush(itf); - } + // flush if queue more than packet size + if (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE) + { + tud_cdc_n_write_flush(itf); + } - return ret; + return ret; } uint32_t tud_cdc_n_write_flush(uint8_t itf) { - cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; - - // Skip if usb is not ready yet - TU_VERIFY(tud_ready(), 0); - - // No data to send - if (!tu_fifo_count(&p_cdc->tx_ff)) - return 0; - - uint8_t const rhport = TUD_OPT_RHPORT; - - // Claim the endpoint - TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_in), 0); - - // Pull data from FIFO - uint16_t const count = tu_fifo_read_n(&p_cdc->tx_ff, p_cdc->epin_buf, sizeof(p_cdc->epin_buf)); - - if (count) - { - TU_ASSERT(usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0); - return count; - } - else - { - // Release endpoint since we don't make any transfer - // Note: data is dropped if terminal is not connected - usbd_edpt_release(rhport, p_cdc->ep_in); - return 0; - } + cdcd_interface_t *p_cdc = &_cdcd_itf[itf]; + + // Skip if usb is not ready yet + TU_VERIFY(tud_ready(), 0); + + // No data to send + if (!tu_fifo_count(&p_cdc->tx_ff)) + return 0; + + uint8_t const rhport = TUD_OPT_RHPORT; + + // Claim the endpoint + TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_in), 0); + + // Pull data from FIFO + uint16_t const count = tu_fifo_read_n(&p_cdc->tx_ff, p_cdc->epin_buf, sizeof(p_cdc->epin_buf)); + + if (count) + { + TU_ASSERT(usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0); + return count; + } + else + { + // Release endpoint since we don't make any transfer + // Note: data is dropped if terminal is not connected + usbd_edpt_release(rhport, p_cdc->ep_in); + return 0; + } } uint32_t tud_cdc_n_write_available(uint8_t itf) { - return tu_fifo_remaining(&_cdcd_itf[itf].tx_ff); + return tu_fifo_remaining(&_cdcd_itf[itf].tx_ff); } bool tud_cdc_n_write_clear(uint8_t itf) { - return tu_fifo_clear(&_cdcd_itf[itf].tx_ff); + return tu_fifo_clear(&_cdcd_itf[itf].tx_ff); } //--------------------------------------------------------------------+ @@ -227,112 +227,112 @@ bool tud_cdc_n_write_clear(uint8_t itf) //--------------------------------------------------------------------+ void cdcd_init(void) { - tu_memclr(_cdcd_itf, sizeof(_cdcd_itf)); + tu_memclr(_cdcd_itf, sizeof(_cdcd_itf)); - for (uint8_t i = 0; i < CFG_TUD_CDC; i++) - { - cdcd_interface_t *p_cdc = &_cdcd_itf[i]; + for (uint8_t i = 0; i < CFG_TUD_CDC; i++) + { + cdcd_interface_t *p_cdc = &_cdcd_itf[i]; - p_cdc->wanted_char = (char)-1; + p_cdc->wanted_char = (char)-1; - // default line coding is : stop bit = 1, parity = none, data bits = 8 - p_cdc->line_coding.bit_rate = 115200; - p_cdc->line_coding.stop_bits = 0; - p_cdc->line_coding.parity = 0; - p_cdc->line_coding.data_bits = 8; + // default line coding is : stop bit = 1, parity = none, data bits = 8 + p_cdc->line_coding.bit_rate = 115200; + p_cdc->line_coding.stop_bits = 0; + p_cdc->line_coding.parity = 0; + p_cdc->line_coding.data_bits = 8; - // Config RX fifo - tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false); + // Config RX fifo + tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false); - // Config TX fifo as overwritable at initialization and will be changed to non-overwritable - // if terminal supports DTR bit. Without DTR we do not know if data is actually polled by terminal. - // In this way, the most current data is prioritized. - tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true); + // Config TX fifo as overwritable at initialization and will be changed to non-overwritable + // if terminal supports DTR bit. Without DTR we do not know if data is actually polled by terminal. + // In this way, the most current data is prioritized. + tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true); #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, osal_mutex_create(&p_cdc->rx_ff_mutex)); - tu_fifo_config_mutex(&p_cdc->tx_ff, osal_mutex_create(&p_cdc->tx_ff_mutex), NULL); + tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, osal_mutex_create(&p_cdc->rx_ff_mutex)); + tu_fifo_config_mutex(&p_cdc->tx_ff, osal_mutex_create(&p_cdc->tx_ff_mutex), NULL); #endif - } + } } void cdcd_reset(uint8_t rhport) { - (void)rhport; + (void)rhport; - for (uint8_t i = 0; i < CFG_TUD_CDC; i++) - { - cdcd_interface_t *p_cdc = &_cdcd_itf[i]; + for (uint8_t i = 0; i < CFG_TUD_CDC; i++) + { + cdcd_interface_t *p_cdc = &_cdcd_itf[i]; - tu_memclr(p_cdc, ITF_MEM_RESET_SIZE); - tu_fifo_clear(&p_cdc->rx_ff); - tu_fifo_clear(&p_cdc->tx_ff); - tu_fifo_set_overwritable(&p_cdc->tx_ff, true); - } + tu_memclr(p_cdc, ITF_MEM_RESET_SIZE); + tu_fifo_clear(&p_cdc->rx_ff); + tu_fifo_clear(&p_cdc->tx_ff); + tu_fifo_set_overwritable(&p_cdc->tx_ff, true); + } } uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { - // Only support ACM subclass - TU_VERIFY(TUSB_CLASS_CDC == itf_desc->bInterfaceClass && - CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass, - 0); - - // Find available interface - cdcd_interface_t *p_cdc = NULL; - for (uint8_t cdc_id = 0; cdc_id < CFG_TUD_CDC; cdc_id++) - { - if (_cdcd_itf[cdc_id].ep_in == 0) - { - p_cdc = &_cdcd_itf[cdc_id]; - break; - } - } - TU_ASSERT(p_cdc, 0); - - //------------- Control Interface -------------// - p_cdc->itf_num = itf_desc->bInterfaceNumber; - - uint16_t drv_len = sizeof(tusb_desc_interface_t); - uint8_t const *p_desc = tu_desc_next(itf_desc); - - // Communication Functional Descriptors - while (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len) - { - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - } - - if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) - { - // notification endpoint - tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *)p_desc; - - TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0); - p_cdc->ep_notif = desc_ep->bEndpointAddress; - - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - } - - //------------- Data Interface (if any) -------------// - if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && - (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *)p_desc)->bInterfaceClass)) - { - // next to endpoint descriptor - drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - - // Open endpoint pair - TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &p_cdc->ep_out, &p_cdc->ep_in), 0); - - drv_len += 2 * sizeof(tusb_desc_endpoint_t); - } - - // Prepare for incoming data - _prep_out_transaction(p_cdc); - - return drv_len; + // Only support ACM subclass + TU_VERIFY(TUSB_CLASS_CDC == itf_desc->bInterfaceClass && + CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass, + 0); + + // Find available interface + cdcd_interface_t *p_cdc = NULL; + for (uint8_t cdc_id = 0; cdc_id < CFG_TUD_CDC; cdc_id++) + { + if (_cdcd_itf[cdc_id].ep_in == 0) + { + p_cdc = &_cdcd_itf[cdc_id]; + break; + } + } + TU_ASSERT(p_cdc, 0); + + //------------- Control Interface -------------// + p_cdc->itf_num = itf_desc->bInterfaceNumber; + + uint16_t drv_len = sizeof(tusb_desc_interface_t); + uint8_t const *p_desc = tu_desc_next(itf_desc); + + // Communication Functional Descriptors + while (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len) + { + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) + { + // notification endpoint + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *)p_desc; + + TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0); + p_cdc->ep_notif = desc_ep->bEndpointAddress; + + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + + //------------- Data Interface (if any) -------------// + if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && + (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *)p_desc)->bInterfaceClass)) + { + // next to endpoint descriptor + drv_len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + + // Open endpoint pair + TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &p_cdc->ep_out, &p_cdc->ep_in), 0); + + drv_len += 2 * sizeof(tusb_desc_endpoint_t); + } + + // Prepare for incoming data + _prep_out_transaction(p_cdc); + + return drv_len; } // Invoked when a control transfer occurred on an interface of this class @@ -340,159 +340,159 @@ uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16 // return false to stall control endpoint (e.g unsupported request) bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) { - // Handle class request only - TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS); - - uint8_t itf = 0; - cdcd_interface_t *p_cdc = _cdcd_itf; - - // Identify which interface to use - for (;; itf++, p_cdc++) - { - if (itf >= TU_ARRAY_SIZE(_cdcd_itf)) - return false; - - if (p_cdc->itf_num == request->wIndex) - break; - } - - switch (request->bRequest) - { - case CDC_REQUEST_SET_LINE_CODING: - if (stage == CONTROL_STAGE_SETUP) - { - TU_LOG2(" Set Line Coding\r\n"); - tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); - } - else if (stage == CONTROL_STAGE_ACK) - { - if (tud_cdc_line_coding_cb) - tud_cdc_line_coding_cb(itf, &p_cdc->line_coding); - } - break; - - case CDC_REQUEST_GET_LINE_CODING: - if (stage == CONTROL_STAGE_SETUP) - { - TU_LOG2(" Get Line Coding\r\n"); - tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); - } - break; - - case CDC_REQUEST_SET_CONTROL_LINE_STATE: - if (stage == CONTROL_STAGE_SETUP) - { - tud_control_status(rhport, request); - } - else if (stage == CONTROL_STAGE_ACK) - { - // CDC PSTN v1.2 section 6.3.12 - // Bit 0: Indicates if DTE is present or not. - // This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready) - // Bit 1: Carrier control for half-duplex modems. - // This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send) - bool const dtr = tu_bit_test(request->wValue, 0); - bool const rts = tu_bit_test(request->wValue, 1); - - p_cdc->line_state = (uint8_t)request->wValue; - - // Disable fifo overwriting if DTR bit is set - tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr); - - TU_LOG2(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts); - - // Invoke callback - if (tud_cdc_line_state_cb) - tud_cdc_line_state_cb(itf, dtr, rts); - } - break; - case CDC_REQUEST_SEND_BREAK: - if (stage == CONTROL_STAGE_SETUP) - { - tud_control_status(rhport, request); - } - else if (stage == CONTROL_STAGE_ACK) - { - TU_LOG2(" Send Break\r\n"); - if (tud_cdc_send_break_cb) - tud_cdc_send_break_cb(itf, request->wValue); - } - break; - - default: - return false; // stall unsupported request - } - - return true; + // Handle class request only + TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS); + + uint8_t itf = 0; + cdcd_interface_t *p_cdc = _cdcd_itf; + + // Identify which interface to use + for (;; itf++, p_cdc++) + { + if (itf >= TU_ARRAY_SIZE(_cdcd_itf)) + return false; + + if (p_cdc->itf_num == request->wIndex) + break; + } + + switch (request->bRequest) + { + case CDC_REQUEST_SET_LINE_CODING: + if (stage == CONTROL_STAGE_SETUP) + { + TU_LOG2(" Set Line Coding\r\n"); + tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); + } + else if (stage == CONTROL_STAGE_ACK) + { + if (tud_cdc_line_coding_cb) + tud_cdc_line_coding_cb(itf, &p_cdc->line_coding); + } + break; + + case CDC_REQUEST_GET_LINE_CODING: + if (stage == CONTROL_STAGE_SETUP) + { + TU_LOG2(" Get Line Coding\r\n"); + tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t)); + } + break; + + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + if (stage == CONTROL_STAGE_SETUP) + { + tud_control_status(rhport, request); + } + else if (stage == CONTROL_STAGE_ACK) + { + // CDC PSTN v1.2 section 6.3.12 + // Bit 0: Indicates if DTE is present or not. + // This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready) + // Bit 1: Carrier control for half-duplex modems. + // This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send) + bool const dtr = tu_bit_test(request->wValue, 0); + bool const rts = tu_bit_test(request->wValue, 1); + + p_cdc->line_state = (uint8_t)request->wValue; + + // Disable fifo overwriting if DTR bit is set + tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr); + + TU_LOG2(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts); + + // Invoke callback + if (tud_cdc_line_state_cb) + tud_cdc_line_state_cb(itf, dtr, rts); + } + break; + case CDC_REQUEST_SEND_BREAK: + if (stage == CONTROL_STAGE_SETUP) + { + tud_control_status(rhport, request); + } + else if (stage == CONTROL_STAGE_ACK) + { + TU_LOG2(" Send Break\r\n"); + if (tud_cdc_send_break_cb) + tud_cdc_send_break_cb(itf, request->wValue); + } + break; + + default: + return false; // stall unsupported request + } + + return true; } bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { - (void)result; - - uint8_t itf; - cdcd_interface_t *p_cdc; - - // Identify which interface to use - for (itf = 0; itf < CFG_TUD_CDC; itf++) - { - p_cdc = &_cdcd_itf[itf]; - if ((ep_addr == p_cdc->ep_out) || (ep_addr == p_cdc->ep_in)) - break; - } - TU_ASSERT(itf < CFG_TUD_CDC); - - // Received new data - if (ep_addr == p_cdc->ep_out) - { - tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, xferred_bytes); - - // Check for wanted char and invoke callback if needed - if (tud_cdc_rx_wanted_cb && (((signed char)p_cdc->wanted_char) != -1)) - { - for (uint32_t i = 0; i < xferred_bytes; i++) - { - if ((p_cdc->wanted_char == p_cdc->epout_buf[i]) && !tu_fifo_empty(&p_cdc->rx_ff)) - { - tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char); - } - } - } - - // invoke receive callback (if there is still data) - if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff)) - tud_cdc_rx_cb(itf); - - // prepare for OUT transaction - _prep_out_transaction(p_cdc); - } - - // Data sent to host, we continue to fetch from tx fifo to send. - // Note: This will cause incorrect baudrate set in line coding. - // Though maybe the baudrate is not really important !!! - if (ep_addr == p_cdc->ep_in) - { - // invoke transmit callback to possibly refill tx fifo - if (tud_cdc_tx_complete_cb) - tud_cdc_tx_complete_cb(itf); - - if (0 == tud_cdc_n_write_flush(itf)) - { - // If there is no data left, a ZLP should be sent if - // xferred_bytes is multiple of EP Packet size and not zero - if (!tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE - 1)))) - { - if (usbd_edpt_claim(rhport, p_cdc->ep_in)) - { - usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0); - } - } - } - } - - // nothing to do with notif endpoint for now - - return true; + (void)result; + + uint8_t itf; + cdcd_interface_t *p_cdc; + + // Identify which interface to use + for (itf = 0; itf < CFG_TUD_CDC; itf++) + { + p_cdc = &_cdcd_itf[itf]; + if ((ep_addr == p_cdc->ep_out) || (ep_addr == p_cdc->ep_in)) + break; + } + TU_ASSERT(itf < CFG_TUD_CDC); + + // Received new data + if (ep_addr == p_cdc->ep_out) + { + tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, xferred_bytes); + + // Check for wanted char and invoke callback if needed + if (tud_cdc_rx_wanted_cb && (((signed char)p_cdc->wanted_char) != -1)) + { + for (uint32_t i = 0; i < xferred_bytes; i++) + { + if ((p_cdc->wanted_char == p_cdc->epout_buf[i]) && !tu_fifo_empty(&p_cdc->rx_ff)) + { + tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char); + } + } + } + + // invoke receive callback (if there is still data) + if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff)) + tud_cdc_rx_cb(itf); + + // prepare for OUT transaction + _prep_out_transaction(p_cdc); + } + + // Data sent to host, we continue to fetch from tx fifo to send. + // Note: This will cause incorrect baudrate set in line coding. + // Though maybe the baudrate is not really important !!! + if (ep_addr == p_cdc->ep_in) + { + // invoke transmit callback to possibly refill tx fifo + if (tud_cdc_tx_complete_cb) + tud_cdc_tx_complete_cb(itf); + + if (0 == tud_cdc_n_write_flush(itf)) + { + // If there is no data left, a ZLP should be sent if + // xferred_bytes is multiple of EP Packet size and not zero + if (!tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE - 1)))) + { + if (usbd_edpt_claim(rhport, p_cdc->ep_in)) + { + usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0); + } + } + } + } + + // nothing to do with notif endpoint for now + + return true; } #endif diff --git a/uCNC/src/tinyusb/src/class/cdc/cdc_device.h b/uCNC/src/tinyusb/src/class/cdc/cdc_device.h index 05b99b967..2f9d393d5 100644 --- a/uCNC/src/tinyusb/src/class/cdc/cdc_device.h +++ b/uCNC/src/tinyusb/src/class/cdc/cdc_device.h @@ -47,209 +47,209 @@ extern "C" { #endif - /** \addtogroup CDC_Serial Serial - * @{ - * \defgroup CDC_Serial_Device Device - * @{ */ + /** \addtogroup CDC_Serial Serial + * @{ + * \defgroup CDC_Serial_Device Device + * @{ */ - //--------------------------------------------------------------------+ - // Application API (Multiple Ports) - // CFG_TUD_CDC > 1 - //--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // Application API (Multiple Ports) + // CFG_TUD_CDC > 1 + //--------------------------------------------------------------------+ - // Check if terminal is connected to this port - bool tud_cdc_n_connected(uint8_t itf); + // Check if terminal is connected to this port + bool tud_cdc_n_connected(uint8_t itf); - // Get current line state. Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) - uint8_t tud_cdc_n_get_line_state(uint8_t itf); + // Get current line state. Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) + uint8_t tud_cdc_n_get_line_state(uint8_t itf); - // Get current line encoding: bit rate, stop bits parity etc .. - void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t *coding); + // Get current line encoding: bit rate, stop bits parity etc .. + void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t *coding); - // Set special character that will trigger tud_cdc_rx_wanted_cb() callback on receiving - void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted); + // Set special character that will trigger tud_cdc_rx_wanted_cb() callback on receiving + void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted); - // Get the number of bytes available for reading - uint32_t tud_cdc_n_available(uint8_t itf); + // Get the number of bytes available for reading + uint32_t tud_cdc_n_available(uint8_t itf); - // Read received bytes - uint32_t tud_cdc_n_read(uint8_t itf, void *buffer, uint32_t bufsize); + // Read received bytes + uint32_t tud_cdc_n_read(uint8_t itf, void *buffer, uint32_t bufsize); - // Read a byte, return -1 if there is none - static inline int32_t tud_cdc_n_read_char(uint8_t itf); + // Read a byte, return -1 if there is none + static inline int32_t tud_cdc_n_read_char(uint8_t itf); - // Clear the received FIFO - void tud_cdc_n_read_flush(uint8_t itf); + // Clear the received FIFO + void tud_cdc_n_read_flush(uint8_t itf); - // Get a byte from FIFO at the specified position without removing it - bool tud_cdc_n_peek(uint8_t itf, uint8_t *ui8); + // Get a byte from FIFO at the specified position without removing it + bool tud_cdc_n_peek(uint8_t itf, uint8_t *ui8); - // Write bytes to TX FIFO, data may remain in the FIFO for a while - uint32_t tud_cdc_n_write(uint8_t itf, void const *buffer, uint32_t bufsize); - - // Write a byte - static inline uint32_t tud_cdc_n_write_char(uint8_t itf, char ch); + // Write bytes to TX FIFO, data may remain in the FIFO for a while + uint32_t tud_cdc_n_write(uint8_t itf, void const *buffer, uint32_t bufsize); + + // Write a byte + static inline uint32_t tud_cdc_n_write_char(uint8_t itf, char ch); - // Write a null-terminated string - static inline uint32_t tud_cdc_n_write_str(uint8_t itf, char const *str); - - // Force sending data if possible, return number of forced bytes - uint32_t tud_cdc_n_write_flush(uint8_t itf); - - // Return the number of bytes (characters) available for writing to TX FIFO buffer in a single n_write operation. - uint32_t tud_cdc_n_write_available(uint8_t itf); - - // Clear the transmit FIFO - bool tud_cdc_n_write_clear(uint8_t itf); - - //--------------------------------------------------------------------+ - // Application API (Single Port) - //--------------------------------------------------------------------+ - static inline bool tud_cdc_connected(void); - static inline uint8_t tud_cdc_get_line_state(void); - static inline void tud_cdc_get_line_coding(cdc_line_coding_t *coding); - static inline void tud_cdc_set_wanted_char(char wanted); - - static inline uint32_t tud_cdc_available(void); - static inline int32_t tud_cdc_read_char(void); - static inline uint32_t tud_cdc_read(void *buffer, uint32_t bufsize); - static inline void tud_cdc_read_flush(void); - static inline bool tud_cdc_peek(uint8_t *ui8); - - static inline uint32_t tud_cdc_write_char(char ch); - static inline uint32_t tud_cdc_write(void const *buffer, uint32_t bufsize); - static inline uint32_t tud_cdc_write_str(char const *str); - static inline uint32_t tud_cdc_write_flush(void); - static inline uint32_t tud_cdc_write_available(void); - static inline bool tud_cdc_write_clear(void); - - //--------------------------------------------------------------------+ - // Application Callback API (weak is optional) - //--------------------------------------------------------------------+ - - // Invoked when received new data - TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf); - - // Invoked when received `wanted_char` - TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char); - - // Invoked when space becomes available in TX buffer - TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf); - - // Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE - TU_ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts); - - // Invoked when line coding is change via SET_LINE_CODING - TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const *p_line_coding); - - // Invoked when received send break - TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms); - - //--------------------------------------------------------------------+ - // Inline Functions - //--------------------------------------------------------------------+ - static inline int32_t tud_cdc_n_read_char(uint8_t itf) - { - uint8_t ch; - return tud_cdc_n_read(itf, &ch, 1) ? (int32_t)ch : -1; - } - - static inline uint32_t tud_cdc_n_write_char(uint8_t itf, char ch) - { - return tud_cdc_n_write(itf, &ch, 1); - } - - static inline uint32_t tud_cdc_n_write_str(uint8_t itf, char const *str) - { - return tud_cdc_n_write(itf, str, strlen(str)); - } - - static inline bool tud_cdc_connected(void) - { - return tud_cdc_n_connected(0); - } - - static inline uint8_t tud_cdc_get_line_state(void) - { - return tud_cdc_n_get_line_state(0); - } - - static inline void tud_cdc_get_line_coding(cdc_line_coding_t *coding) - { - tud_cdc_n_get_line_coding(0, coding); - } - - static inline void tud_cdc_set_wanted_char(char wanted) - { - tud_cdc_n_set_wanted_char(0, wanted); - } - - static inline uint32_t tud_cdc_available(void) - { - return tud_cdc_n_available(0); - } - - static inline int32_t tud_cdc_read_char(void) - { - return tud_cdc_n_read_char(0); - } - - static inline uint32_t tud_cdc_read(void *buffer, uint32_t bufsize) - { - return tud_cdc_n_read(0, buffer, bufsize); - } - - static inline void tud_cdc_read_flush(void) - { - tud_cdc_n_read_flush(0); - } - - static inline bool tud_cdc_peek(uint8_t *ui8) - { - return tud_cdc_n_peek(0, ui8); - } - - static inline uint32_t tud_cdc_write_char(char ch) - { - return tud_cdc_n_write_char(0, ch); - } - - static inline uint32_t tud_cdc_write(void const *buffer, uint32_t bufsize) - { - return tud_cdc_n_write(0, buffer, bufsize); - } - - static inline uint32_t tud_cdc_write_str(char const *str) - { - return tud_cdc_n_write_str(0, str); - } - - static inline uint32_t tud_cdc_write_flush(void) - { - return tud_cdc_n_write_flush(0); - } - - static inline uint32_t tud_cdc_write_available(void) - { - return tud_cdc_n_write_available(0); - } - - static inline bool tud_cdc_write_clear(void) - { - return tud_cdc_n_write_clear(0); - } - - /** @} */ - /** @} */ - - //--------------------------------------------------------------------+ - // INTERNAL USBD-CLASS DRIVER API - //--------------------------------------------------------------------+ - void cdcd_init(void); - void cdcd_reset(uint8_t rhport); - uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len); - bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request); - bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); + // Write a null-terminated string + static inline uint32_t tud_cdc_n_write_str(uint8_t itf, char const *str); + + // Force sending data if possible, return number of forced bytes + uint32_t tud_cdc_n_write_flush(uint8_t itf); + + // Return the number of bytes (characters) available for writing to TX FIFO buffer in a single n_write operation. + uint32_t tud_cdc_n_write_available(uint8_t itf); + + // Clear the transmit FIFO + bool tud_cdc_n_write_clear(uint8_t itf); + + //--------------------------------------------------------------------+ + // Application API (Single Port) + //--------------------------------------------------------------------+ + static inline bool tud_cdc_connected(void); + static inline uint8_t tud_cdc_get_line_state(void); + static inline void tud_cdc_get_line_coding(cdc_line_coding_t *coding); + static inline void tud_cdc_set_wanted_char(char wanted); + + static inline uint32_t tud_cdc_available(void); + static inline int32_t tud_cdc_read_char(void); + static inline uint32_t tud_cdc_read(void *buffer, uint32_t bufsize); + static inline void tud_cdc_read_flush(void); + static inline bool tud_cdc_peek(uint8_t *ui8); + + static inline uint32_t tud_cdc_write_char(char ch); + static inline uint32_t tud_cdc_write(void const *buffer, uint32_t bufsize); + static inline uint32_t tud_cdc_write_str(char const *str); + static inline uint32_t tud_cdc_write_flush(void); + static inline uint32_t tud_cdc_write_available(void); + static inline bool tud_cdc_write_clear(void); + + //--------------------------------------------------------------------+ + // Application Callback API (weak is optional) + //--------------------------------------------------------------------+ + + // Invoked when received new data + TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf); + + // Invoked when received `wanted_char` + TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char); + + // Invoked when space becomes available in TX buffer + TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf); + + // Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE + TU_ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts); + + // Invoked when line coding is change via SET_LINE_CODING + TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const *p_line_coding); + + // Invoked when received send break + TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms); + + //--------------------------------------------------------------------+ + // Inline Functions + //--------------------------------------------------------------------+ + static inline int32_t tud_cdc_n_read_char(uint8_t itf) + { + uint8_t ch; + return tud_cdc_n_read(itf, &ch, 1) ? (int32_t)ch : -1; + } + + static inline uint32_t tud_cdc_n_write_char(uint8_t itf, char ch) + { + return tud_cdc_n_write(itf, &ch, 1); + } + + static inline uint32_t tud_cdc_n_write_str(uint8_t itf, char const *str) + { + return tud_cdc_n_write(itf, str, strlen(str)); + } + + static inline bool tud_cdc_connected(void) + { + return tud_cdc_n_connected(0); + } + + static inline uint8_t tud_cdc_get_line_state(void) + { + return tud_cdc_n_get_line_state(0); + } + + static inline void tud_cdc_get_line_coding(cdc_line_coding_t *coding) + { + tud_cdc_n_get_line_coding(0, coding); + } + + static inline void tud_cdc_set_wanted_char(char wanted) + { + tud_cdc_n_set_wanted_char(0, wanted); + } + + static inline uint32_t tud_cdc_available(void) + { + return tud_cdc_n_available(0); + } + + static inline int32_t tud_cdc_read_char(void) + { + return tud_cdc_n_read_char(0); + } + + static inline uint32_t tud_cdc_read(void *buffer, uint32_t bufsize) + { + return tud_cdc_n_read(0, buffer, bufsize); + } + + static inline void tud_cdc_read_flush(void) + { + tud_cdc_n_read_flush(0); + } + + static inline bool tud_cdc_peek(uint8_t *ui8) + { + return tud_cdc_n_peek(0, ui8); + } + + static inline uint32_t tud_cdc_write_char(char ch) + { + return tud_cdc_n_write_char(0, ch); + } + + static inline uint32_t tud_cdc_write(void const *buffer, uint32_t bufsize) + { + return tud_cdc_n_write(0, buffer, bufsize); + } + + static inline uint32_t tud_cdc_write_str(char const *str) + { + return tud_cdc_n_write_str(0, str); + } + + static inline uint32_t tud_cdc_write_flush(void) + { + return tud_cdc_n_write_flush(0); + } + + static inline uint32_t tud_cdc_write_available(void) + { + return tud_cdc_n_write_available(0); + } + + static inline bool tud_cdc_write_clear(void) + { + return tud_cdc_n_write_clear(0); + } + + /** @} */ + /** @} */ + + //--------------------------------------------------------------------+ + // INTERNAL USBD-CLASS DRIVER API + //--------------------------------------------------------------------+ + void cdcd_init(void); + void cdcd_reset(uint8_t rhport); + uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len); + bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request); + bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); #ifdef __cplusplus } diff --git a/uCNC/src/tinyusb/src/common/tusb_common.h b/uCNC/src/tinyusb/src/common/tusb_common.h index a1638cd61..b629e06fd 100644 --- a/uCNC/src/tinyusb/src/common/tusb_common.h +++ b/uCNC/src/tinyusb/src/common/tusb_common.h @@ -72,21 +72,21 @@ extern "C" #include "tusb_verify.h" #include "tusb_types.h" -#include "tusb_error.h" // TODO remove +#include "tusb_error.h" // TODO remove #include "tusb_timeout.h" // TODO remove - //--------------------------------------------------------------------+ - // Internal Helper used by Host and Device Stack - //--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // Internal Helper used by Host and Device Stack + //--------------------------------------------------------------------+ - // Check if endpoint descriptor is valid per USB specs - bool tu_edpt_validate(tusb_desc_endpoint_t const *desc_ep, tusb_speed_t speed); + // Check if endpoint descriptor is valid per USB specs + bool tu_edpt_validate(tusb_desc_endpoint_t const *desc_ep, tusb_speed_t speed); - // Bind all endpoint of a interface descriptor to class driver - void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const *p_desc, uint16_t desc_len, uint8_t driver_id); + // Bind all endpoint of a interface descriptor to class driver + void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const *p_desc, uint16_t desc_len, uint8_t driver_id); - // Calculate total length of n interfaces (depending on IAD) - uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const *desc_itf, uint8_t itf_count, uint16_t max_len); + // Calculate total length of n interfaces (depending on IAD) + uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const *desc_itf, uint8_t itf_count, uint16_t max_len); //--------------------------------------------------------------------+ // Internal Inline Functions @@ -96,111 +96,111 @@ extern "C" #define tu_memclr(buffer, size) memset((buffer), 0, (size)) #define tu_varclr(_var) tu_memclr(_var, sizeof(*(_var))) - //------------- Bytes -------------// - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) - { - return (((uint32_t)b3) << 24) | (((uint32_t)b2) << 16) | (((uint32_t)b1) << 8) | b0; - } - - TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) - { - return (uint16_t)((((uint16_t)high) << 8) | low); - } - - TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t ui32) { return TU_U32_BYTE3(ui32); } - TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t ui32) { return TU_U32_BYTE2(ui32); } - TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t ui32) { return TU_U32_BYTE1(ui32); } - TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t ui32) { return TU_U32_BYTE0(ui32); } - - TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_high16(uint32_t ui32) { return (uint16_t)(ui32 >> 16); } - TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_low16(uint32_t ui32) { return (uint16_t)(ui32 & 0x0000ffffu); } - - TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t ui16) { return TU_U16_HIGH(ui16); } - TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low(uint16_t ui16) { return TU_U16_LOW(ui16); } - - //------------- Bits -------------// - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set(uint32_t value, uint8_t pos) { return value | TU_BIT(pos); } - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_clear(uint32_t value, uint8_t pos) { return value & (~TU_BIT(pos)); } - TU_ATTR_ALWAYS_INLINE static inline bool tu_bit_test(uint32_t value, uint8_t pos) { return (value & TU_BIT(pos)) ? true : false; } - - //------------- Min -------------// - TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_min8(uint8_t x, uint8_t y) { return (x < y) ? x : y; } - TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_min16(uint16_t x, uint16_t y) { return (x < y) ? x : y; } - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_min32(uint32_t x, uint32_t y) { return (x < y) ? x : y; } - - //------------- Max -------------// - TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_max8(uint8_t x, uint8_t y) { return (x > y) ? x : y; } - TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_max16(uint16_t x, uint16_t y) { return (x > y) ? x : y; } - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_max32(uint32_t x, uint32_t y) { return (x > y) ? x : y; } - - //------------- Align -------------// - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment) - { - return value & ((uint32_t) ~(alignment - 1)); - } - - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16(uint32_t value) { return (value & 0xFFFFFFF0UL); } - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32(uint32_t value) { return (value & 0xFFFFFFE0UL); } - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k(uint32_t value) { return (value & 0xFFFFF000UL); } - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); } - - //------------- Mathematics -------------// - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d - 1) / d; } - - /// inclusive range checking TODO remove - TU_ATTR_ALWAYS_INLINE static inline bool tu_within(uint32_t lower, uint32_t value, uint32_t upper) - { - return (lower <= value) && (value <= upper); - } - - // log2 of a value is its MSB's position - // TODO use clz TODO remove - static inline uint8_t tu_log2(uint32_t value) - { - uint8_t result = 0; - while (value >>= 1) - { - result++; - } - return result; - } + //------------- Bytes -------------// + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) + { + return (((uint32_t)b3) << 24) | (((uint32_t)b2) << 16) | (((uint32_t)b1) << 8) | b0; + } + + TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) + { + return (uint16_t)((((uint16_t)high) << 8) | low); + } + + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t ui32) { return TU_U32_BYTE3(ui32); } + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t ui32) { return TU_U32_BYTE2(ui32); } + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t ui32) { return TU_U32_BYTE1(ui32); } + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t ui32) { return TU_U32_BYTE0(ui32); } + + TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_high16(uint32_t ui32) { return (uint16_t)(ui32 >> 16); } + TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u32_low16(uint32_t ui32) { return (uint16_t)(ui32 & 0x0000ffffu); } + + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t ui16) { return TU_U16_HIGH(ui16); } + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low(uint16_t ui16) { return TU_U16_LOW(ui16); } + + //------------- Bits -------------// + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set(uint32_t value, uint8_t pos) { return value | TU_BIT(pos); } + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_clear(uint32_t value, uint8_t pos) { return value & (~TU_BIT(pos)); } + TU_ATTR_ALWAYS_INLINE static inline bool tu_bit_test(uint32_t value, uint8_t pos) { return (value & TU_BIT(pos)) ? true : false; } + + //------------- Min -------------// + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_min8(uint8_t x, uint8_t y) { return (x < y) ? x : y; } + TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_min16(uint16_t x, uint16_t y) { return (x < y) ? x : y; } + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_min32(uint32_t x, uint32_t y) { return (x < y) ? x : y; } + + //------------- Max -------------// + TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_max8(uint8_t x, uint8_t y) { return (x > y) ? x : y; } + TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_max16(uint16_t x, uint16_t y) { return (x > y) ? x : y; } + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_max32(uint32_t x, uint32_t y) { return (x > y) ? x : y; } + + //------------- Align -------------// + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment) + { + return value & ((uint32_t) ~(alignment - 1)); + } + + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16(uint32_t value) { return (value & 0xFFFFFFF0UL); } + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32(uint32_t value) { return (value & 0xFFFFFFE0UL); } + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k(uint32_t value) { return (value & 0xFFFFF000UL); } + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); } + + //------------- Mathematics -------------// + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d - 1) / d; } + + /// inclusive range checking TODO remove + TU_ATTR_ALWAYS_INLINE static inline bool tu_within(uint32_t lower, uint32_t value, uint32_t upper) + { + return (lower <= value) && (value <= upper); + } + + // log2 of a value is its MSB's position + // TODO use clz TODO remove + static inline uint8_t tu_log2(uint32_t value) + { + uint8_t result = 0; + while (value >>= 1) + { + result++; + } + return result; + } //------------- Unaligned Access -------------// #if TUP_ARCH_STRICT_ALIGN - // Rely on compiler to generate correct code for unaligned access - typedef struct - { - uint16_t val; - } TU_ATTR_PACKED tu_unaligned_uint16_t; - typedef struct - { - uint32_t val; - } TU_ATTR_PACKED tu_unaligned_uint32_t; - - TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) - { - tu_unaligned_uint32_t const *ua32 = (tu_unaligned_uint32_t const *)mem; - return ua32->val; - } - - TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) - { - tu_unaligned_uint32_t *ua32 = (tu_unaligned_uint32_t *)mem; - ua32->val = value; - } - - TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) - { - tu_unaligned_uint16_t const *ua16 = (tu_unaligned_uint16_t const *)mem; - return ua16->val; - } - - TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) - { - tu_unaligned_uint16_t *ua16 = (tu_unaligned_uint16_t *)mem; - ua16->val = value; - } + // Rely on compiler to generate correct code for unaligned access + typedef struct + { + uint16_t val; + } TU_ATTR_PACKED tu_unaligned_uint16_t; + typedef struct + { + uint32_t val; + } TU_ATTR_PACKED tu_unaligned_uint32_t; + + TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) + { + tu_unaligned_uint32_t const *ua32 = (tu_unaligned_uint32_t const *)mem; + return ua32->val; + } + + TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) + { + tu_unaligned_uint32_t *ua32 = (tu_unaligned_uint32_t *)mem; + ua32->val = value; + } + + TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) + { + tu_unaligned_uint16_t const *ua16 = (tu_unaligned_uint16_t const *)mem; + return ua16->val; + } + + TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) + { + tu_unaligned_uint16_t *ua16 = (tu_unaligned_uint16_t *)mem; + ua16->val = value; + } #elif TUP_MCU_STRICT_ALIGN @@ -210,30 +210,30 @@ extern "C" // TODO Big Endian may need minor changes TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void *mem) { - volatile uint8_t const *buf8 = (uint8_t const *)mem; - return tu_u32(buf8[3], buf8[2], buf8[1], buf8[0]); + volatile uint8_t const *buf8 = (uint8_t const *)mem; + return tu_u32(buf8[3], buf8[2], buf8[1], buf8[0]); } TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void *mem, uint32_t value) { - volatile uint8_t *buf8 = (uint8_t *)mem; - buf8[0] = tu_u32_byte0(value); - buf8[1] = tu_u32_byte1(value); - buf8[2] = tu_u32_byte2(value); - buf8[3] = tu_u32_byte3(value); + volatile uint8_t *buf8 = (uint8_t *)mem; + buf8[0] = tu_u32_byte0(value); + buf8[1] = tu_u32_byte1(value); + buf8[2] = tu_u32_byte2(value); + buf8[3] = tu_u32_byte3(value); } TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void *mem) { - volatile uint8_t const *buf8 = (uint8_t const *)mem; - return tu_u16(buf8[1], buf8[0]); + volatile uint8_t const *buf8 = (uint8_t const *)mem; + return tu_u16(buf8[1], buf8[0]); } TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_t value) { - volatile uint8_t *buf8 = (uint8_t *)mem; - buf8[0] = tu_u16_low(value); - buf8[1] = tu_u16_high(value); + volatile uint8_t *buf8 = (uint8_t *)mem; + buf8[0] = tu_u16_low(value); + buf8[1] = tu_u16_high(value); } #else @@ -263,7 +263,7 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_ #define TU_BIN8(d) ((uint8_t)_B8__(0x##d##UL)) #define TU_BIN16(dmsb, dlsb) (((uint16_t)TU_BIN8(dmsb) << 8) + TU_BIN8(dlsb)) #define TU_BIN32(dmsb, db2, db3, dlsb) \ - (((uint32_t)TU_BIN8(dmsb) << 24) + ((uint32_t)TU_BIN8(db2) << 16) + ((uint32_t)TU_BIN8(db3) << 8) + TU_BIN8(dlsb)) + (((uint32_t)TU_BIN8(dmsb) << 24) + ((uint32_t)TU_BIN8(db2) << 16) + ((uint32_t)TU_BIN8(db3) << 8) + TU_BIN8(dlsb)) #endif //--------------------------------------------------------------------+ @@ -277,20 +277,20 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_ // 3 : print info #if CFG_TUSB_DEBUG - void tu_print_mem(void const *buf, uint32_t count, uint8_t indent); + void tu_print_mem(void const *buf, uint32_t count, uint8_t indent); #ifdef CFG_TUSB_DEBUG_PRINTF - extern int CFG_TUSB_DEBUG_PRINTF(const char *format, ...); + extern int CFG_TUSB_DEBUG_PRINTF(const char *format, ...); #define tu_printf CFG_TUSB_DEBUG_PRINTF #else #define tu_printf printf #endif - static inline void tu_print_var(uint8_t const *buf, uint32_t bufsize) - { - for (uint32_t i = 0; i < bufsize; i++) - tu_printf("%02X ", buf[i]); - } + static inline void tu_print_var(uint8_t const *buf, uint32_t bufsize) + { + for (uint32_t i = 0; i < bufsize; i++) + tu_printf("%02X ", buf[i]); + } // Log with Level #define TU_LOG(n, ...) TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__) @@ -326,33 +326,33 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_ #define TU_LOG3_HEX TU_LOG1_HEX #endif - typedef struct - { - uint32_t key; - const char *data; - } tu_lookup_entry_t; + typedef struct + { + uint32_t key; + const char *data; + } tu_lookup_entry_t; - typedef struct - { - uint16_t count; - tu_lookup_entry_t const *items; - } tu_lookup_table_t; + typedef struct + { + uint16_t count; + tu_lookup_entry_t const *items; + } tu_lookup_table_t; - static inline const char *tu_lookup_find(tu_lookup_table_t const *p_table, uint32_t key) - { - static char not_found[11]; + static inline const char *tu_lookup_find(tu_lookup_table_t const *p_table, uint32_t key) + { + static char not_found[11]; - for (uint16_t i = 0; i < p_table->count; i++) - { - if (p_table->items[i].key == key) - return p_table->items[i].data; - } + for (uint16_t i = 0; i < p_table->count; i++) + { + if (p_table->items[i].key == key) + return p_table->items[i].data; + } - // not found return the key value in hex - sprintf(not_found, "0x%08lX", (unsigned long)key); + // not found return the key value in hex + sprintf(not_found, "0x%08lX", (unsigned long)key); - return not_found; - } + return not_found; + } #endif // CFG_TUSB_DEBUG @@ -366,7 +366,7 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_ #define TU_LOG_FAILED() #endif - // TODO replace all TU_LOGn with TU_LOG(n) + // TODO replace all TU_LOGn with TU_LOG(n) #define TU_LOG0(...) #define TU_LOG0_MEM(...) diff --git a/uCNC/src/tinyusb/src/common/tusb_compiler.h b/uCNC/src/tinyusb/src/common/tusb_compiler.h index 40e5d35f8..38e6a16d0 100644 --- a/uCNC/src/tinyusb/src/common/tusb_compiler.h +++ b/uCNC/src/tinyusb/src/common/tusb_compiler.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -32,40 +32,37 @@ #ifndef _TUSB_COMPILER_H_ #define _TUSB_COMPILER_H_ -#define TU_TOKEN(x) x -#define TU_STRING(x) #x ///< stringify without expand -#define TU_XSTRING(x) TU_STRING(x) ///< expand then stringify +#define TU_TOKEN(x) x +#define TU_STRING(x) #x ///< stringify without expand +#define TU_XSTRING(x) TU_STRING(x) ///< expand then stringify -#define TU_STRCAT(a, b) a##b ///< concat without expand -#define TU_STRCAT3(a, b, c) a##b##c ///< concat without expand +#define TU_STRCAT(a, b) a##b ///< concat without expand +#define TU_STRCAT3(a, b, c) a##b##c ///< concat without expand -#define TU_XSTRCAT(a, b) TU_STRCAT(a, b) ///< expand then concat -#define TU_XSTRCAT3(a, b, c) TU_STRCAT3(a, b, c) ///< expand then concat 3 tokens +#define TU_XSTRCAT(a, b) TU_STRCAT(a, b) ///< expand then concat +#define TU_XSTRCAT3(a, b, c) TU_STRCAT3(a, b, c) ///< expand then concat 3 tokens -#define TU_INCLUDE_PATH(_dir, _file) TU_XSTRING(TU_TOKEN(_dir) TU_TOKEN(_file)) +#define TU_INCLUDE_PATH(_dir,_file) TU_XSTRING( TU_TOKEN(_dir)TU_TOKEN(_file) ) #if defined __COUNTER__ && __COUNTER__ != __COUNTER__ -#define _TU_COUNTER_ __COUNTER__ + #define _TU_COUNTER_ __COUNTER__ #else -#define _TU_COUNTER_ __LINE__ + #define _TU_COUNTER_ __LINE__ #endif // Compile-time Assert -#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L -#define TU_VERIFY_STATIC _Static_assert -#elif defined(__cplusplus) && __cplusplus >= 201103L -#define TU_VERIFY_STATIC static_assert +#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define TU_VERIFY_STATIC _Static_assert +#elif defined (__cplusplus) && __cplusplus >= 201103L + #define TU_VERIFY_STATIC static_assert #elif defined(__CCRX__) -#define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(Line, __LINE__)[(const_expr) ? 1 : 0]; + #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(Line, __LINE__)[(const_expr) ? 1 : 0]; #else -#define TU_VERIFY_STATIC(const_expr, _mess) enum \ -{ \ - TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1 / (!!(const_expr)) \ -} + #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) } #endif // for declaration of reserved field, make use of _TU_COUNTER_ -#define TU_RESERVED TU_XSTRCAT(reserved, _TU_COUNTER_) +#define TU_RESERVED TU_XSTRCAT(reserved, _TU_COUNTER_) #define TU_LITTLE_ENDIAN (0x12u) #define TU_BIG_ENDIAN (0x21u) @@ -78,36 +75,36 @@ * Nth position is the same as the number of arguments * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma) *------------------------------------------------------------------*/ -#define TU_ARGS_NUM(...) _TU_NARG(_0, ##__VA_ARGS__, _RSEQ_N()) - -#define _TU_NARG(...) _GET_NTH_ARG(__VA_ARGS__) -#define _GET_NTH_ARG( \ - _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ - _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ - _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ - _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ - _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ - _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ - _61, _62, _63, N, ...) N -#define _RSEQ_N() \ - 62, 61, 60, \ - 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, \ - 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, \ - 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, \ - 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, \ - 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \ - 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 +#define TU_ARGS_NUM(...) _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N()) + +#define _TU_NARG(...) _GET_NTH_ARG(__VA_ARGS__) +#define _GET_NTH_ARG( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \ + _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \ + _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \ + _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \ + _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \ + _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \ + _61,_62,_63,N,...) N +#define _RSEQ_N() \ + 62,61,60, \ + 59,58,57,56,55,54,53,52,51,50, \ + 49,48,47,46,45,44,43,42,41,40, \ + 39,38,37,36,35,34,33,32,31,30, \ + 29,28,27,26,25,24,23,22,21,20, \ + 19,18,17,16,15,14,13,12,11,10, \ + 9,8,7,6,5,4,3,2,1,0 // Apply an macro X to each of the arguments with an separated of choice -#define TU_ARGS_APPLY(_X, _s, ...) TU_XSTRCAT(_TU_ARGS_APPLY_, TU_ARGS_NUM(__VA_ARGS__))(_X, _s, __VA_ARGS__) - -#define _TU_ARGS_APPLY_1(_X, _s, _a1) _X(_a1) -#define _TU_ARGS_APPLY_2(_X, _s, _a1, _a2) _X(_a1) _s _X(_a2) -#define _TU_ARGS_APPLY_3(_X, _s, _a1, _a2, _a3) _X(_a1) _s _TU_ARGS_APPLY_2(_X, _s, _a2, _a3) -#define _TU_ARGS_APPLY_4(_X, _s, _a1, _a2, _a3, _a4) _X(_a1) _s _TU_ARGS_APPLY_3(_X, _s, _a2, _a3, _a4) -#define _TU_ARGS_APPLY_5(_X, _s, _a1, _a2, _a3, _a4, _a5) _X(_a1) _s _TU_ARGS_APPLY_4(_X, _s, _a2, _a3, _a4, _a5) -#define _TU_ARGS_APPLY_6(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6) _X(_a1) _s _TU_ARGS_APPLY_5(_X, _s, _a2, _a3, _a4, _a5, _a6) -#define _TU_ARGS_APPLY_7(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7) _X(_a1) _s _TU_ARGS_APPLY_6(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7) +#define TU_ARGS_APPLY(_X, _s, ...) TU_XSTRCAT(_TU_ARGS_APPLY_, TU_ARGS_NUM(__VA_ARGS__))(_X, _s, __VA_ARGS__) + +#define _TU_ARGS_APPLY_1(_X, _s, _a1) _X(_a1) +#define _TU_ARGS_APPLY_2(_X, _s, _a1, _a2) _X(_a1) _s _X(_a2) +#define _TU_ARGS_APPLY_3(_X, _s, _a1, _a2, _a3) _X(_a1) _s _TU_ARGS_APPLY_2(_X, _s, _a2, _a3) +#define _TU_ARGS_APPLY_4(_X, _s, _a1, _a2, _a3, _a4) _X(_a1) _s _TU_ARGS_APPLY_3(_X, _s, _a2, _a3, _a4) +#define _TU_ARGS_APPLY_5(_X, _s, _a1, _a2, _a3, _a4, _a5) _X(_a1) _s _TU_ARGS_APPLY_4(_X, _s, _a2, _a3, _a4, _a5) +#define _TU_ARGS_APPLY_6(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6) _X(_a1) _s _TU_ARGS_APPLY_5(_X, _s, _a2, _a3, _a4, _a5, _a6) +#define _TU_ARGS_APPLY_7(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7) _X(_a1) _s _TU_ARGS_APPLY_6(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7) #define _TU_ARGS_APPLY_8(_X, _s, _a1, _a2, _a3, _a4, _a5, _a6, _a7, _a8) _X(_a1) _s _TU_ARGS_APPLY_7(_X, _s, _a2, _a3, _a4, _a5, _a6, _a7, _a8) //--------------------------------------------------------------------+ @@ -116,144 +113,146 @@ // TODO refactor since __attribute__ is supported across many compiler #if defined(__GNUC__) -#define TU_ATTR_ALIGNED(Bytes) __attribute__((aligned(Bytes))) -#define TU_ATTR_SECTION(sec_name) __attribute__((section(#sec_name))) -#define TU_ATTR_PACKED __attribute__((packed)) -#define TU_ATTR_WEAK __attribute__((weak)) -#define TU_ATTR_ALWAYS_INLINE __attribute__((always_inline)) -#define TU_ATTR_DEPRECATED(mess) __attribute__((deprecated(mess))) // warn if function with this attribute is used -#define TU_ATTR_UNUSED __attribute__((unused)) // Function/Variable is meant to be possibly unused -#define TU_ATTR_USED __attribute__((used)) // Function/Variable is meant to be used - -#define TU_ATTR_PACKED_BEGIN -#define TU_ATTR_PACKED_END -#define TU_ATTR_BIT_FIELD_ORDER_BEGIN -#define TU_ATTR_BIT_FIELD_ORDER_END - -// Endian conversion use well-known host to network (big endian) naming -#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -#define TU_BYTE_ORDER TU_LITTLE_ENDIAN -#else -#define TU_BYTE_ORDER TU_BIG_ENDIAN -#endif - -#define TU_BSWAP16(u16) (__builtin_bswap16(u16)) -#define TU_BSWAP32(u32) (__builtin_bswap32(u32)) - -// List of obsolete callback function that is renamed and should not be defined. -// Put it here since only gcc support this pragma -#pragma GCC poison tud_vendor_control_request_cb + #define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes))) + #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) + #define TU_ATTR_PACKED __attribute__ ((packed)) + #define TU_ATTR_WEAK __attribute__ ((weak)) + #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) + #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used + #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused + #define TU_ATTR_USED __attribute__ ((used)) // Function/Variable is meant to be used + + #define TU_ATTR_PACKED_BEGIN + #define TU_ATTR_PACKED_END + #define TU_ATTR_BIT_FIELD_ORDER_BEGIN + #define TU_ATTR_BIT_FIELD_ORDER_END + + // Endian conversion use well-known host to network (big endian) naming + #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + #define TU_BYTE_ORDER TU_LITTLE_ENDIAN + #else + #define TU_BYTE_ORDER TU_BIG_ENDIAN + #endif + + #define TU_BSWAP16(u16) (__builtin_bswap16(u16)) + #define TU_BSWAP32(u32) (__builtin_bswap32(u32)) + + #ifndef __ARMCC_VERSION + // List of obsolete callback function that is renamed and should not be defined. + // Put it here since only gcc support this pragma + #pragma GCC poison tud_vendor_control_request_cb + #endif #elif defined(__TI_COMPILER_VERSION__) -#define TU_ATTR_ALIGNED(Bytes) __attribute__((aligned(Bytes))) -#define TU_ATTR_SECTION(sec_name) __attribute__((section(#sec_name))) -#define TU_ATTR_PACKED __attribute__((packed)) -#define TU_ATTR_WEAK __attribute__((weak)) -#define TU_ATTR_ALWAYS_INLINE __attribute__((always_inline)) -#define TU_ATTR_DEPRECATED(mess) __attribute__((deprecated(mess))) // warn if function with this attribute is used -#define TU_ATTR_UNUSED __attribute__((unused)) // Function/Variable is meant to be possibly unused -#define TU_ATTR_USED __attribute__((used)) - -#define TU_ATTR_PACKED_BEGIN -#define TU_ATTR_PACKED_END -#define TU_ATTR_BIT_FIELD_ORDER_BEGIN -#define TU_ATTR_BIT_FIELD_ORDER_END - -// __BYTE_ORDER is defined in the TI ARM compiler, but not MSP430 (which is little endian) -#if ((__BYTE_ORDER__) == (__ORDER_LITTLE_ENDIAN__)) || defined(__MSP430__) -#define TU_BYTE_ORDER TU_LITTLE_ENDIAN -#else -#define TU_BYTE_ORDER TU_BIG_ENDIAN -#endif - -#define TU_BSWAP16(u16) (__builtin_bswap16(u16)) -#define TU_BSWAP32(u32) (__builtin_bswap32(u32)) + #define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes))) + #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) + #define TU_ATTR_PACKED __attribute__ ((packed)) + #define TU_ATTR_WEAK __attribute__ ((weak)) + #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) + #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used + #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused + #define TU_ATTR_USED __attribute__ ((used)) + + #define TU_ATTR_PACKED_BEGIN + #define TU_ATTR_PACKED_END + #define TU_ATTR_BIT_FIELD_ORDER_BEGIN + #define TU_ATTR_BIT_FIELD_ORDER_END + + // __BYTE_ORDER is defined in the TI ARM compiler, but not MSP430 (which is little endian) + #if ((__BYTE_ORDER__) == (__ORDER_LITTLE_ENDIAN__)) || defined(__MSP430__) + #define TU_BYTE_ORDER TU_LITTLE_ENDIAN + #else + #define TU_BYTE_ORDER TU_BIG_ENDIAN + #endif + + #define TU_BSWAP16(u16) (__builtin_bswap16(u16)) + #define TU_BSWAP32(u32) (__builtin_bswap32(u32)) #elif defined(__ICCARM__) -#include -#define TU_ATTR_ALIGNED(Bytes) __attribute__((aligned(Bytes))) -#define TU_ATTR_SECTION(sec_name) __attribute__((section(#sec_name))) -#define TU_ATTR_PACKED __attribute__((packed)) -#define TU_ATTR_WEAK __attribute__((weak)) -#define TU_ATTR_ALWAYS_INLINE __attribute__((always_inline)) -#define TU_ATTR_DEPRECATED(mess) __attribute__((deprecated(mess))) // warn if function with this attribute is used -#define TU_ATTR_UNUSED __attribute__((unused)) // Function/Variable is meant to be possibly unused -#define TU_ATTR_USED __attribute__((used)) // Function/Variable is meant to be used - -#define TU_ATTR_PACKED_BEGIN -#define TU_ATTR_PACKED_END -#define TU_ATTR_BIT_FIELD_ORDER_BEGIN -#define TU_ATTR_BIT_FIELD_ORDER_END - -// Endian conversion use well-known host to network (big endian) naming -#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -#define TU_BYTE_ORDER TU_LITTLE_ENDIAN -#else -#define TU_BYTE_ORDER TU_BIG_ENDIAN -#endif - -#define TU_BSWAP16(u16) (__iar_builtin_REV16(u16)) -#define TU_BSWAP32(u32) (__iar_builtin_REV(u32)) + #include + #define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes))) + #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) + #define TU_ATTR_PACKED __attribute__ ((packed)) + #define TU_ATTR_WEAK __attribute__ ((weak)) + #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) + #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used + #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused + #define TU_ATTR_USED __attribute__ ((used)) // Function/Variable is meant to be used + + #define TU_ATTR_PACKED_BEGIN + #define TU_ATTR_PACKED_END + #define TU_ATTR_BIT_FIELD_ORDER_BEGIN + #define TU_ATTR_BIT_FIELD_ORDER_END + + // Endian conversion use well-known host to network (big endian) naming + #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + #define TU_BYTE_ORDER TU_LITTLE_ENDIAN + #else + #define TU_BYTE_ORDER TU_BIG_ENDIAN + #endif + + #define TU_BSWAP16(u16) (__iar_builtin_REV16(u16)) + #define TU_BSWAP32(u32) (__iar_builtin_REV(u32)) #elif defined(__CCRX__) -#define TU_ATTR_ALIGNED(Bytes) -#define TU_ATTR_SECTION(sec_name) -#define TU_ATTR_PACKED -#define TU_ATTR_WEAK -#define TU_ATTR_ALWAYS_INLINE -#define TU_ATTR_DEPRECATED(mess) -#define TU_ATTR_UNUSED -#define TU_ATTR_USED - -#define TU_ATTR_PACKED_BEGIN _Pragma("pack") -#define TU_ATTR_PACKED_END _Pragma("packoption") -#define TU_ATTR_BIT_FIELD_ORDER_BEGIN _Pragma("bit_order right") -#define TU_ATTR_BIT_FIELD_ORDER_END _Pragma("bit_order") - -// Endian conversion use well-known host to network (big endian) naming -#if defined(__LIT) -#define TU_BYTE_ORDER TU_LITTLE_ENDIAN -#else -#define TU_BYTE_ORDER TU_BIG_ENDIAN -#endif - -#define TU_BSWAP16(u16) ((unsigned short)_builtin_revw((unsigned long)u16)) -#define TU_BSWAP32(u32) (_builtin_revl(u32)) - -#else -#error "Compiler attribute porting is required" + #define TU_ATTR_ALIGNED(Bytes) + #define TU_ATTR_SECTION(sec_name) + #define TU_ATTR_PACKED + #define TU_ATTR_WEAK + #define TU_ATTR_ALWAYS_INLINE + #define TU_ATTR_DEPRECATED(mess) + #define TU_ATTR_UNUSED + #define TU_ATTR_USED + + #define TU_ATTR_PACKED_BEGIN _Pragma("pack") + #define TU_ATTR_PACKED_END _Pragma("packoption") + #define TU_ATTR_BIT_FIELD_ORDER_BEGIN _Pragma("bit_order right") + #define TU_ATTR_BIT_FIELD_ORDER_END _Pragma("bit_order") + + // Endian conversion use well-known host to network (big endian) naming + #if defined(__LIT) + #define TU_BYTE_ORDER TU_LITTLE_ENDIAN + #else + #define TU_BYTE_ORDER TU_BIG_ENDIAN + #endif + + #define TU_BSWAP16(u16) ((unsigned short)_builtin_revw((unsigned long)u16)) + #define TU_BSWAP32(u32) (_builtin_revl(u32)) + +#else + #error "Compiler attribute porting is required" #endif #if (TU_BYTE_ORDER == TU_LITTLE_ENDIAN) -#define tu_htons(u16) (TU_BSWAP16(u16)) -#define tu_ntohs(u16) (TU_BSWAP16(u16)) + #define tu_htons(u16) (TU_BSWAP16(u16)) + #define tu_ntohs(u16) (TU_BSWAP16(u16)) -#define tu_htonl(u32) (TU_BSWAP32(u32)) -#define tu_ntohl(u32) (TU_BSWAP32(u32)) + #define tu_htonl(u32) (TU_BSWAP32(u32)) + #define tu_ntohl(u32) (TU_BSWAP32(u32)) -#define tu_htole16(u16) (u16) -#define tu_le16toh(u16) (u16) + #define tu_htole16(u16) (u16) + #define tu_le16toh(u16) (u16) -#define tu_htole32(u32) (u32) -#define tu_le32toh(u32) (u32) + #define tu_htole32(u32) (u32) + #define tu_le32toh(u32) (u32) #elif (TU_BYTE_ORDER == TU_BIG_ENDIAN) -#define tu_htons(u16) (u16) -#define tu_ntohs(u16) (u16) + #define tu_htons(u16) (u16) + #define tu_ntohs(u16) (u16) -#define tu_htonl(u32) (u32) -#define tu_ntohl(u32) (u32) + #define tu_htonl(u32) (u32) + #define tu_ntohl(u32) (u32) -#define tu_htole16(u16) (TU_BSWAP16(u16)) -#define tu_le16toh(u16) (TU_BSWAP16(u16)) + #define tu_htole16(u16) (TU_BSWAP16(u16)) + #define tu_le16toh(u16) (TU_BSWAP16(u16)) -#define tu_htole32(u32) (TU_BSWAP32(u32)) -#define tu_le32toh(u32) (TU_BSWAP32(u32)) + #define tu_htole32(u32) (TU_BSWAP32(u32)) + #define tu_le32toh(u32) (TU_BSWAP32(u32)) #else -#error Byte order is undefined + #error Byte order is undefined #endif #endif /* _TUSB_COMPILER_H_ */ diff --git a/uCNC/src/tinyusb/src/common/tusb_error.h b/uCNC/src/tinyusb/src/common/tusb_error.h index ebcd3b19d..36901dcca 100644 --- a/uCNC/src/tinyusb/src/common/tusb_error.h +++ b/uCNC/src/tinyusb/src/common/tusb_error.h @@ -41,30 +41,30 @@ extern "C" #define ERROR_ENUM(x) x, #define ERROR_STRING(x) #x, -#define ERROR_TABLE(ENTRY) \ - ENTRY(TUSB_ERROR_NONE) \ - ENTRY(TUSB_ERROR_INVALID_PARA) \ - ENTRY(TUSB_ERROR_DEVICE_NOT_READY) \ - ENTRY(TUSB_ERROR_INTERFACE_IS_BUSY) \ - ENTRY(TUSB_ERROR_HCD_OPEN_PIPE_FAILED) \ - ENTRY(TUSB_ERROR_OSAL_TIMEOUT) \ - ENTRY(TUSB_ERROR_CDCH_DEVICE_NOT_MOUNTED) \ - ENTRY(TUSB_ERROR_MSCH_DEVICE_NOT_MOUNTED) \ - ENTRY(TUSB_ERROR_NOT_SUPPORTED) \ - ENTRY(TUSB_ERROR_NOT_ENOUGH_MEMORY) \ - ENTRY(TUSB_ERROR_FAILED) +#define ERROR_TABLE(ENTRY) \ + ENTRY(TUSB_ERROR_NONE) \ + ENTRY(TUSB_ERROR_INVALID_PARA) \ + ENTRY(TUSB_ERROR_DEVICE_NOT_READY) \ + ENTRY(TUSB_ERROR_INTERFACE_IS_BUSY) \ + ENTRY(TUSB_ERROR_HCD_OPEN_PIPE_FAILED) \ + ENTRY(TUSB_ERROR_OSAL_TIMEOUT) \ + ENTRY(TUSB_ERROR_CDCH_DEVICE_NOT_MOUNTED) \ + ENTRY(TUSB_ERROR_MSCH_DEVICE_NOT_MOUNTED) \ + ENTRY(TUSB_ERROR_NOT_SUPPORTED) \ + ENTRY(TUSB_ERROR_NOT_ENOUGH_MEMORY) \ + ENTRY(TUSB_ERROR_FAILED) - /// \brief Error Code returned - /// TODO obsolete and to be remove - typedef enum - { - ERROR_TABLE(ERROR_ENUM) - TUSB_ERROR_COUNT - } tusb_error_t; + /// \brief Error Code returned + /// TODO obsolete and to be remove + typedef enum + { + ERROR_TABLE(ERROR_ENUM) + TUSB_ERROR_COUNT + } tusb_error_t; #if CFG_TUSB_DEBUG - /// Enum to String for debugging purposes. Only available if \ref CFG_TUSB_DEBUG > 0 - extern char const *const tusb_strerr[TUSB_ERROR_COUNT]; + /// Enum to String for debugging purposes. Only available if \ref CFG_TUSB_DEBUG > 0 + extern char const *const tusb_strerr[TUSB_ERROR_COUNT]; #endif #ifdef __cplusplus diff --git a/uCNC/src/tinyusb/src/common/tusb_fifo.c b/uCNC/src/tinyusb/src/common/tusb_fifo.c index 96183ab99..2b74eb43f 100644 --- a/uCNC/src/tinyusb/src/common/tusb_fifo.c +++ b/uCNC/src/tinyusb/src/common/tusb_fifo.c @@ -39,14 +39,12 @@ static inline void _ff_lock(tu_fifo_mutex_t mutex) { - if (mutex) - osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); + if (mutex) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER); } static inline void _ff_unlock(tu_fifo_mutex_t mutex) { - if (mutex) - osal_mutex_unlock(mutex); + if (mutex) osal_mutex_unlock(mutex); } #else @@ -62,334 +60,324 @@ static inline void _ff_unlock(tu_fifo_mutex_t mutex) */ typedef enum { - TU_FIFO_COPY_INC, ///< Copy from/to an increasing source/destination address - default mode - TU_FIFO_COPY_CST_FULL_WORDS, ///< Copy from/to a constant source/destination address - required for e.g. STM32 to write into USB hardware FIFO + TU_FIFO_COPY_INC, ///< Copy from/to an increasing source/destination address - default mode + TU_FIFO_COPY_CST_FULL_WORDS, ///< Copy from/to a constant source/destination address - required for e.g. STM32 to write into USB hardware FIFO } tu_fifo_copy_mode_t; -bool tu_fifo_config(tu_fifo_t *f, void *buffer, uint16_t depth, uint16_t item_size, bool overwritable) +bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable) { - if (depth > 0x8000) - return false; // Maximum depth is 2^15 items + if (depth > 0x8000) return false; // Maximum depth is 2^15 items - _ff_lock(f->mutex_wr); - _ff_lock(f->mutex_rd); + _ff_lock(f->mutex_wr); + _ff_lock(f->mutex_rd); - f->buffer = (uint8_t *)buffer; - f->depth = depth; - f->item_size = item_size; - f->overwritable = overwritable; + f->buffer = (uint8_t*) buffer; + f->depth = depth; + f->item_size = item_size; + f->overwritable = overwritable; - // Limit index space to 2*depth - this allows for a fast "modulo" calculation - // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable - // only if overflow happens once (important for unsupervised DMA applications) - f->max_pointer_idx = 2 * depth - 1; - f->non_used_index_space = UINT16_MAX - f->max_pointer_idx; + // Limit index space to 2*depth - this allows for a fast "modulo" calculation + // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable + // only if overflow happens once (important for unsupervised DMA applications) + f->max_pointer_idx = 2*depth - 1; + f->non_used_index_space = UINT16_MAX - f->max_pointer_idx; - f->rd_idx = f->wr_idx = 0; + f->rd_idx = f->wr_idx = 0; - _ff_unlock(f->mutex_wr); - _ff_unlock(f->mutex_rd); + _ff_unlock(f->mutex_wr); + _ff_unlock(f->mutex_rd); - return true; + return true; } // Static functions are intended to work on local variables static inline uint16_t _ff_mod(uint16_t idx, uint16_t depth) { - while (idx >= depth) - idx -= depth; - return idx; + while ( idx >= depth) idx -= depth; + return idx; } // Intended to be used to read from hardware USB FIFO in e.g. STM32 where all data is read from a constant address // Code adapted from dcd_synopsis.c // TODO generalize with configurable 1 byte or 4 byte each read -static void _ff_push_const_addr(uint8_t *ff_buf, const void *app_buf, uint16_t len) +static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t len) { - volatile const uint32_t *rx_fifo = (volatile const uint32_t *)app_buf; + volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf; - // Reading full available 32 bit words from const app address - uint16_t full_words = len >> 2; - while (full_words--) - { - tu_unaligned_write32(ff_buf, *rx_fifo); - ff_buf += 4; - } + // Reading full available 32 bit words from const app address + uint16_t full_words = len >> 2; + while(full_words--) + { + tu_unaligned_write32(ff_buf, *rx_fifo); + ff_buf += 4; + } - // Read the remaining 1-3 bytes from const app address - uint8_t const bytes_rem = len & 0x03; - if (bytes_rem) - { - uint32_t tmp32 = *rx_fifo; - memcpy(ff_buf, &tmp32, bytes_rem); - } + // Read the remaining 1-3 bytes from const app address + uint8_t const bytes_rem = len & 0x03; + if ( bytes_rem ) + { + uint32_t tmp32 = *rx_fifo; + memcpy(ff_buf, &tmp32, bytes_rem); + } } // Intended to be used to write to hardware USB FIFO in e.g. STM32 // where all data is written to a constant address in full word copies -static void _ff_pull_const_addr(void *app_buf, const uint8_t *ff_buf, uint16_t len) +static void _ff_pull_const_addr(void * app_buf, const uint8_t * ff_buf, uint16_t len) { - volatile uint32_t *tx_fifo = (volatile uint32_t *)app_buf; + volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf; - // Pushing full available 32 bit words to const app address - uint16_t full_words = len >> 2; - while (full_words--) - { - *tx_fifo = tu_unaligned_read32(ff_buf); - ff_buf += 4; - } + // Pushing full available 32 bit words to const app address + uint16_t full_words = len >> 2; + while(full_words--) + { + *tx_fifo = tu_unaligned_read32(ff_buf); + ff_buf += 4; + } - // Write the remaining 1-3 bytes into const app address - uint8_t const bytes_rem = len & 0x03; - if (bytes_rem) - { - uint32_t tmp32 = 0; - memcpy(&tmp32, ff_buf, bytes_rem); + // Write the remaining 1-3 bytes into const app address + uint8_t const bytes_rem = len & 0x03; + if ( bytes_rem ) + { + uint32_t tmp32 = 0; + memcpy(&tmp32, ff_buf, bytes_rem); - *tx_fifo = tmp32; - } + *tx_fifo = tmp32; + } } // send one item to FIFO WITHOUT updating write pointer -static inline void _ff_push(tu_fifo_t *f, void const *app_buf, uint16_t rel) +static inline void _ff_push(tu_fifo_t* f, void const * app_buf, uint16_t rel) { - memcpy(f->buffer + (rel * f->item_size), app_buf, f->item_size); + memcpy(f->buffer + (rel * f->item_size), app_buf, f->item_size); } // send n items to FIFO WITHOUT updating write pointer -static void _ff_push_n(tu_fifo_t *f, void const *app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode) -{ - uint16_t const nLin = f->depth - rel; - uint16_t const nWrap = n - nLin; - - uint16_t nLin_bytes = nLin * f->item_size; - uint16_t nWrap_bytes = nWrap * f->item_size; - - // current buffer of fifo - uint8_t *ff_buf = f->buffer + (rel * f->item_size); - - switch (copy_mode) - { - case TU_FIFO_COPY_INC: - if (n <= nLin) - { - // Linear only - memcpy(ff_buf, app_buf, n * f->item_size); - } - else - { - // Wrap around - - // Write data to linear part of buffer - memcpy(ff_buf, app_buf, nLin_bytes); - - // Write data wrapped around - memcpy(f->buffer, ((uint8_t const *)app_buf) + nLin_bytes, nWrap_bytes); - } - break; - - case TU_FIFO_COPY_CST_FULL_WORDS: - // Intended for hardware buffers from which it can be read word by word only - if (n <= nLin) - { - // Linear only - _ff_push_const_addr(ff_buf, app_buf, n * f->item_size); - } - else - { - // Wrap around case - - // Write full words to linear part of buffer - uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC; - _ff_push_const_addr(ff_buf, app_buf, nLin_4n_bytes); - ff_buf += nLin_4n_bytes; - - // There could be odd 1-3 bytes before the wrap-around boundary - volatile const uint32_t *rx_fifo = (volatile const uint32_t *)app_buf; - uint8_t rem = nLin_bytes & 0x03; - if (rem > 0) - { - uint8_t remrem = tu_min16(nWrap_bytes, 4 - rem); - nWrap_bytes -= remrem; - - uint32_t tmp32 = *rx_fifo; - uint8_t *src_u8 = ((uint8_t *)&tmp32); - - // Write 1-3 bytes before wrapped boundary - while (rem--) - *ff_buf++ = *src_u8++; - - // Read more bytes to beginning to complete a word - ff_buf = f->buffer; - while (remrem--) - *ff_buf++ = *src_u8++; - } - else - { - ff_buf = f->buffer; // wrap around to beginning - } - - // Write data wrapped part - if (nWrap_bytes > 0) - _ff_push_const_addr(ff_buf, app_buf, nWrap_bytes); - } - break; - } +static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode) +{ + uint16_t const nLin = f->depth - rel; + uint16_t const nWrap = n - nLin; + + uint16_t nLin_bytes = nLin * f->item_size; + uint16_t nWrap_bytes = nWrap * f->item_size; + + // current buffer of fifo + uint8_t* ff_buf = f->buffer + (rel * f->item_size); + + switch (copy_mode) + { + case TU_FIFO_COPY_INC: + if(n <= nLin) + { + // Linear only + memcpy(ff_buf, app_buf, n*f->item_size); + } + else + { + // Wrap around + + // Write data to linear part of buffer + memcpy(ff_buf, app_buf, nLin_bytes); + + // Write data wrapped around + memcpy(f->buffer, ((uint8_t const*) app_buf) + nLin_bytes, nWrap_bytes); + } + break; + + case TU_FIFO_COPY_CST_FULL_WORDS: + // Intended for hardware buffers from which it can be read word by word only + if(n <= nLin) + { + // Linear only + _ff_push_const_addr(ff_buf, app_buf, n*f->item_size); + } + else + { + // Wrap around case + + // Write full words to linear part of buffer + uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC; + _ff_push_const_addr(ff_buf, app_buf, nLin_4n_bytes); + ff_buf += nLin_4n_bytes; + + // There could be odd 1-3 bytes before the wrap-around boundary + volatile const uint32_t * rx_fifo = (volatile const uint32_t *) app_buf; + uint8_t rem = nLin_bytes & 0x03; + if (rem > 0) + { + uint8_t remrem = tu_min16(nWrap_bytes, 4-rem); + nWrap_bytes -= remrem; + + uint32_t tmp32 = *rx_fifo; + uint8_t * src_u8 = ((uint8_t *) &tmp32); + + // Write 1-3 bytes before wrapped boundary + while(rem--) *ff_buf++ = *src_u8++; + + // Read more bytes to beginning to complete a word + ff_buf = f->buffer; + while(remrem--) *ff_buf++ = *src_u8++; + } + else + { + ff_buf = f->buffer; // wrap around to beginning + } + + // Write data wrapped part + if (nWrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, nWrap_bytes); + } + break; + } } // get one item from FIFO WITHOUT updating read pointer -static inline void _ff_pull(tu_fifo_t *f, void *app_buf, uint16_t rel) +static inline void _ff_pull(tu_fifo_t* f, void * app_buf, uint16_t rel) { - memcpy(app_buf, f->buffer + (rel * f->item_size), f->item_size); + memcpy(app_buf, f->buffer + (rel * f->item_size), f->item_size); } // get n items from FIFO WITHOUT updating read pointer -static void _ff_pull_n(tu_fifo_t *f, void *app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode) -{ - uint16_t const nLin = f->depth - rel; - uint16_t const nWrap = n - nLin; // only used if wrapped - - uint16_t nLin_bytes = nLin * f->item_size; - uint16_t nWrap_bytes = nWrap * f->item_size; - - // current buffer of fifo - uint8_t *ff_buf = f->buffer + (rel * f->item_size); - - switch (copy_mode) - { - case TU_FIFO_COPY_INC: - if (n <= nLin) - { - // Linear only - memcpy(app_buf, ff_buf, n * f->item_size); - } - else - { - // Wrap around - - // Read data from linear part of buffer - memcpy(app_buf, ff_buf, nLin_bytes); - - // Read data wrapped part - memcpy((uint8_t *)app_buf + nLin_bytes, f->buffer, nWrap_bytes); - } - break; - - case TU_FIFO_COPY_CST_FULL_WORDS: - if (n <= nLin) - { - // Linear only - _ff_pull_const_addr(app_buf, ff_buf, n * f->item_size); - } - else - { - // Wrap around case - - // Read full words from linear part of buffer - uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC; - _ff_pull_const_addr(app_buf, ff_buf, nLin_4n_bytes); - ff_buf += nLin_4n_bytes; - - // There could be odd 1-3 bytes before the wrap-around boundary - volatile uint32_t *tx_fifo = (volatile uint32_t *)app_buf; - uint8_t rem = nLin_bytes & 0x03; - if (rem > 0) - { - uint8_t remrem = tu_min16(nWrap_bytes, 4 - rem); - nWrap_bytes -= remrem; - - uint32_t tmp32 = 0; - uint8_t *dst_u8 = (uint8_t *)&tmp32; - - // Read 1-3 bytes before wrapped boundary - while (rem--) - *dst_u8++ = *ff_buf++; - - // Read more bytes from beginning to complete a word - ff_buf = f->buffer; - while (remrem--) - *dst_u8++ = *ff_buf++; - - *tx_fifo = tmp32; - } - else - { - ff_buf = f->buffer; // wrap around to beginning - } - - // Read data wrapped part - if (nWrap_bytes > 0) - _ff_pull_const_addr(app_buf, ff_buf, nWrap_bytes); - } - break; - - default: - break; - } +static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode) +{ + uint16_t const nLin = f->depth - rel; + uint16_t const nWrap = n - nLin; // only used if wrapped + + uint16_t nLin_bytes = nLin * f->item_size; + uint16_t nWrap_bytes = nWrap * f->item_size; + + // current buffer of fifo + uint8_t* ff_buf = f->buffer + (rel * f->item_size); + + switch (copy_mode) + { + case TU_FIFO_COPY_INC: + if ( n <= nLin ) + { + // Linear only + memcpy(app_buf, ff_buf, n*f->item_size); + } + else + { + // Wrap around + + // Read data from linear part of buffer + memcpy(app_buf, ff_buf, nLin_bytes); + + // Read data wrapped part + memcpy((uint8_t*) app_buf + nLin_bytes, f->buffer, nWrap_bytes); + } + break; + + case TU_FIFO_COPY_CST_FULL_WORDS: + if ( n <= nLin ) + { + // Linear only + _ff_pull_const_addr(app_buf, ff_buf, n*f->item_size); + } + else + { + // Wrap around case + + // Read full words from linear part of buffer + uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC; + _ff_pull_const_addr(app_buf, ff_buf, nLin_4n_bytes); + ff_buf += nLin_4n_bytes; + + // There could be odd 1-3 bytes before the wrap-around boundary + volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf; + uint8_t rem = nLin_bytes & 0x03; + if (rem > 0) + { + uint8_t remrem = tu_min16(nWrap_bytes, 4-rem); + nWrap_bytes -= remrem; + + uint32_t tmp32=0; + uint8_t * dst_u8 = (uint8_t *)&tmp32; + + // Read 1-3 bytes before wrapped boundary + while(rem--) *dst_u8++ = *ff_buf++; + + // Read more bytes from beginning to complete a word + ff_buf = f->buffer; + while(remrem--) *dst_u8++ = *ff_buf++; + + *tx_fifo = tmp32; + } + else + { + ff_buf = f->buffer; // wrap around to beginning + } + + // Read data wrapped part + if (nWrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, nWrap_bytes); + } + break; + + default: break; + } } // Advance an absolute pointer -static uint16_t advance_pointer(tu_fifo_t *f, uint16_t p, uint16_t offset) -{ - // We limit the index space of p such that a correct wrap around happens - // Check for a wrap around or if we are in unused index space - This has to be checked first!! - // We are exploiting the wrap around to the correct index - if ((p > (uint16_t)(p + offset)) || ((uint16_t)(p + offset) > f->max_pointer_idx)) - { - p = (p + offset) + f->non_used_index_space; - } - else - { - p += offset; - } - return p; +static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset) +{ + // We limit the index space of p such that a correct wrap around happens + // Check for a wrap around or if we are in unused index space - This has to be checked first!! + // We are exploiting the wrap around to the correct index + if ((p > (uint16_t)(p + offset)) || ((uint16_t)(p + offset) > f->max_pointer_idx)) + { + p = (p + offset) + f->non_used_index_space; + } + else + { + p += offset; + } + return p; } // Backward an absolute pointer -static uint16_t backward_pointer(tu_fifo_t *f, uint16_t p, uint16_t offset) -{ - // We limit the index space of p such that a correct wrap around happens - // Check for a wrap around or if we are in unused index space - This has to be checked first!! - // We are exploiting the wrap around to the correct index - if ((p < (uint16_t)(p - offset)) || ((uint16_t)(p - offset) > f->max_pointer_idx)) - { - p = (p - offset) - f->non_used_index_space; - } - else - { - p -= offset; - } - return p; +static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset) +{ + // We limit the index space of p such that a correct wrap around happens + // Check for a wrap around or if we are in unused index space - This has to be checked first!! + // We are exploiting the wrap around to the correct index + if ((p < (uint16_t)(p - offset)) || ((uint16_t)(p - offset) > f->max_pointer_idx)) + { + p = (p - offset) - f->non_used_index_space; + } + else + { + p -= offset; + } + return p; } // get relative from absolute pointer -static uint16_t get_relative_pointer(tu_fifo_t *f, uint16_t p) +static uint16_t get_relative_pointer(tu_fifo_t* f, uint16_t p) { - return _ff_mod(p, f->depth); + return _ff_mod(p, f->depth); } // Works on local copies of w and r - return only the difference and as such can be used to determine an overflow -static inline uint16_t _tu_fifo_count(tu_fifo_t *f, uint16_t wAbs, uint16_t rAbs) +static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) { - uint16_t cnt = wAbs - rAbs; + uint16_t cnt = wAbs-rAbs; - // In case we have non-power of two depth we need a further modification - if (rAbs > wAbs) - cnt -= f->non_used_index_space; + // In case we have non-power of two depth we need a further modification + if (rAbs > wAbs) cnt -= f->non_used_index_space; - return cnt; + return cnt; } // Works on local copies of w and r static inline bool _tu_fifo_empty(uint16_t wAbs, uint16_t rAbs) { - return wAbs == rAbs; + return wAbs == rAbs; } // Works on local copies of w and r -static inline bool _tu_fifo_full(tu_fifo_t *f, uint16_t wAbs, uint16_t rAbs) +static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) { - return (_tu_fifo_count(f, wAbs, rAbs) == f->depth); + return (_tu_fifo_count(f, wAbs, rAbs) == f->depth); } // Works on local copies of w and r @@ -398,507 +386,509 @@ static inline bool _tu_fifo_full(tu_fifo_t *f, uint16_t wAbs, uint16_t rAbs) // write more than 2*depth-1 items in one rush without updating write pointer. Otherwise // write pointer wraps and you pointer states are messed up. This can only happen if you // use DMAs, write functions do not allow such an error. -static inline bool _tu_fifo_overflowed(tu_fifo_t *f, uint16_t wAbs, uint16_t rAbs) +static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) { - return (_tu_fifo_count(f, wAbs, rAbs) > f->depth); + return (_tu_fifo_count(f, wAbs, rAbs) > f->depth); } // Works on local copies of w // For more details see _tu_fifo_overflow()! -static inline void _tu_fifo_correct_read_pointer(tu_fifo_t *f, uint16_t wAbs) +static inline void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs) { - f->rd_idx = backward_pointer(f, wAbs, f->depth); + f->rd_idx = backward_pointer(f, wAbs, f->depth); } // Works on local copies of w and r // Must be protected by mutexes since in case of an overflow read pointer gets modified -static bool _tu_fifo_peek(tu_fifo_t *f, void *p_buffer, uint16_t wAbs, uint16_t rAbs) +static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wAbs, uint16_t rAbs) { - uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs); + uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs); - // Check overflow and correct if required - if (cnt > f->depth) - { - _tu_fifo_correct_read_pointer(f, wAbs); - cnt = f->depth; - } + // Check overflow and correct if required + if (cnt > f->depth) + { + _tu_fifo_correct_read_pointer(f, wAbs); + cnt = f->depth; + } - // Skip beginning of buffer - if (cnt == 0) - return false; + // Skip beginning of buffer + if (cnt == 0) return false; - uint16_t rRel = get_relative_pointer(f, rAbs); + uint16_t rRel = get_relative_pointer(f, rAbs); - // Peek data - _ff_pull(f, p_buffer, rRel); + // Peek data + _ff_pull(f, p_buffer, rRel); - return true; + return true; } // Works on local copies of w and r // Must be protected by mutexes since in case of an overflow read pointer gets modified -static uint16_t _tu_fifo_peek_n(tu_fifo_t *f, void *p_buffer, uint16_t n, uint16_t wAbs, uint16_t rAbs, tu_fifo_copy_mode_t copy_mode) +static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wAbs, uint16_t rAbs, tu_fifo_copy_mode_t copy_mode) { - uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs); + uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs); - // Check overflow and correct if required - if (cnt > f->depth) - { - _tu_fifo_correct_read_pointer(f, wAbs); - rAbs = f->rd_idx; - cnt = f->depth; - } + // Check overflow and correct if required + if (cnt > f->depth) + { + _tu_fifo_correct_read_pointer(f, wAbs); + rAbs = f->rd_idx; + cnt = f->depth; + } - // Skip beginning of buffer - if (cnt == 0) - return 0; + // Skip beginning of buffer + if (cnt == 0) return 0; - // Check if we can read something at and after offset - if too less is available we read what remains - if (cnt < n) - n = cnt; + // Check if we can read something at and after offset - if too less is available we read what remains + if (cnt < n) n = cnt; - uint16_t rRel = get_relative_pointer(f, rAbs); + uint16_t rRel = get_relative_pointer(f, rAbs); - // Peek data - _ff_pull_n(f, p_buffer, n, rRel, copy_mode); + // Peek data + _ff_pull_n(f, p_buffer, n, rRel, copy_mode); - return n; + return n; } // Works on local copies of w and r -static inline uint16_t _tu_fifo_remaining(tu_fifo_t *f, uint16_t wAbs, uint16_t rAbs) +static inline uint16_t _tu_fifo_remaining(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs) { - return f->depth - _tu_fifo_count(f, wAbs, rAbs); + return f->depth - _tu_fifo_count(f, wAbs, rAbs); } -static uint16_t _tu_fifo_write_n(tu_fifo_t *f, const void *data, uint16_t n, tu_fifo_copy_mode_t copy_mode) +static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu_fifo_copy_mode_t copy_mode) { - if (n == 0) - return 0; + if ( n == 0 ) return 0; - _ff_lock(f->mutex_wr); + _ff_lock(f->mutex_wr); - uint16_t w = f->wr_idx, r = f->rd_idx; - uint8_t const *buf8 = (uint8_t const *)data; + uint16_t w = f->wr_idx, r = f->rd_idx; + uint8_t const* buf8 = (uint8_t const*) data; - if (!f->overwritable) - { - // Not overwritable limit up to full - n = tu_min16(n, _tu_fifo_remaining(f, w, r)); - } - else if (n >= f->depth) - { - // Only copy last part - buf8 = buf8 + (n - f->depth) * f->item_size; - n = f->depth; + if (!f->overwritable) + { + // Not overwritable limit up to full + n = tu_min16(n, _tu_fifo_remaining(f, w, r)); + } + else if (n >= f->depth) + { + // Only copy last part + buf8 = buf8 + (n - f->depth) * f->item_size; + n = f->depth; - // We start writing at the read pointer's position since we fill the complete - // buffer and we do not want to modify the read pointer within a write function! - // This would end up in a race condition with read functions! - w = r; - } + // We start writing at the read pointer's position since we fill the complete + // buffer and we do not want to modify the read pointer within a write function! + // This would end up in a race condition with read functions! + w = r; + } - uint16_t wRel = get_relative_pointer(f, w); + uint16_t wRel = get_relative_pointer(f, w); - // Write data - _ff_push_n(f, buf8, n, wRel, copy_mode); + // Write data + _ff_push_n(f, buf8, n, wRel, copy_mode); - // Advance pointer - f->wr_idx = advance_pointer(f, w, n); + // Advance pointer + f->wr_idx = advance_pointer(f, w, n); - _ff_unlock(f->mutex_wr); + _ff_unlock(f->mutex_wr); - return n; + return n; } -static uint16_t _tu_fifo_read_n(tu_fifo_t *f, void *buffer, uint16_t n, tu_fifo_copy_mode_t copy_mode) +static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo_copy_mode_t copy_mode) { - _ff_lock(f->mutex_rd); + _ff_lock(f->mutex_rd); - // Peek the data - // f->rd_idx might get modified in case of an overflow so we can not use a local variable - n = _tu_fifo_peek_n(f, buffer, n, f->wr_idx, f->rd_idx, copy_mode); + // Peek the data + // f->rd_idx might get modified in case of an overflow so we can not use a local variable + n = _tu_fifo_peek_n(f, buffer, n, f->wr_idx, f->rd_idx, copy_mode); - // Advance read pointer - f->rd_idx = advance_pointer(f, f->rd_idx, n); + // Advance read pointer + f->rd_idx = advance_pointer(f, f->rd_idx, n); - _ff_unlock(f->mutex_rd); - return n; + _ff_unlock(f->mutex_rd); + return n; } /******************************************************************************/ /*! - @brief Get number of items in FIFO. + @brief Get number of items in FIFO. - As this function only reads the read and write pointers once, this function is - reentrant and thus thread and ISR save without any mutexes. In case an - overflow occurred, this function return f.depth at maximum. Overflows are - checked and corrected for in the read functions! + As this function only reads the read and write pointers once, this function is + reentrant and thus thread and ISR save without any mutexes. In case an + overflow occurred, this function return f.depth at maximum. Overflows are + checked and corrected for in the read functions! - @param[in] f - Pointer to the FIFO buffer to manipulate + @param[in] f + Pointer to the FIFO buffer to manipulate - @returns Number of items in FIFO + @returns Number of items in FIFO */ /******************************************************************************/ -uint16_t tu_fifo_count(tu_fifo_t *f) +uint16_t tu_fifo_count(tu_fifo_t* f) { - return tu_min16(_tu_fifo_count(f, f->wr_idx, f->rd_idx), f->depth); + return tu_min16(_tu_fifo_count(f, f->wr_idx, f->rd_idx), f->depth); } /******************************************************************************/ /*! - @brief Check if FIFO is empty. + @brief Check if FIFO is empty. - As this function only reads the read and write pointers once, this function is - reentrant and thus thread and ISR save without any mutexes. + As this function only reads the read and write pointers once, this function is + reentrant and thus thread and ISR save without any mutexes. - @param[in] f - Pointer to the FIFO buffer to manipulate + @param[in] f + Pointer to the FIFO buffer to manipulate - @returns Number of items in FIFO + @returns Number of items in FIFO */ /******************************************************************************/ -bool tu_fifo_empty(tu_fifo_t *f) +bool tu_fifo_empty(tu_fifo_t* f) { - return _tu_fifo_empty(f->wr_idx, f->rd_idx); + return _tu_fifo_empty(f->wr_idx, f->rd_idx); } /******************************************************************************/ /*! - @brief Check if FIFO is full. + @brief Check if FIFO is full. - As this function only reads the read and write pointers once, this function is - reentrant and thus thread and ISR save without any mutexes. + As this function only reads the read and write pointers once, this function is + reentrant and thus thread and ISR save without any mutexes. - @param[in] f - Pointer to the FIFO buffer to manipulate + @param[in] f + Pointer to the FIFO buffer to manipulate - @returns Number of items in FIFO + @returns Number of items in FIFO */ /******************************************************************************/ -bool tu_fifo_full(tu_fifo_t *f) +bool tu_fifo_full(tu_fifo_t* f) { - return _tu_fifo_full(f, f->wr_idx, f->rd_idx); + return _tu_fifo_full(f, f->wr_idx, f->rd_idx); } /******************************************************************************/ /*! - @brief Get remaining space in FIFO. + @brief Get remaining space in FIFO. - As this function only reads the read and write pointers once, this function is - reentrant and thus thread and ISR save without any mutexes. + As this function only reads the read and write pointers once, this function is + reentrant and thus thread and ISR save without any mutexes. - @param[in] f - Pointer to the FIFO buffer to manipulate + @param[in] f + Pointer to the FIFO buffer to manipulate - @returns Number of items in FIFO + @returns Number of items in FIFO */ /******************************************************************************/ -uint16_t tu_fifo_remaining(tu_fifo_t *f) +uint16_t tu_fifo_remaining(tu_fifo_t* f) { - return _tu_fifo_remaining(f, f->wr_idx, f->rd_idx); + return _tu_fifo_remaining(f, f->wr_idx, f->rd_idx); } /******************************************************************************/ /*! - @brief Check if overflow happened. + @brief Check if overflow happened. - BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS" - Only one overflow is allowed for this function to work e.g. if depth = 100, you must not - write more than 2*depth-1 items in one rush without updating write pointer. Otherwise - write pointer wraps and your pointer states are messed up. This can only happen if you - use DMAs, write functions do not allow such an error. Avoid such nasty things! + BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS" + Only one overflow is allowed for this function to work e.g. if depth = 100, you must not + write more than 2*depth-1 items in one rush without updating write pointer. Otherwise + write pointer wraps and your pointer states are messed up. This can only happen if you + use DMAs, write functions do not allow such an error. Avoid such nasty things! - All reading functions (read, peek) check for overflows and correct read pointer on their own such - that latest items are read. - If required (e.g. for DMA use) you can also correct the read pointer by - tu_fifo_correct_read_pointer(). + All reading functions (read, peek) check for overflows and correct read pointer on their own such + that latest items are read. + If required (e.g. for DMA use) you can also correct the read pointer by + tu_fifo_correct_read_pointer(). - @param[in] f - Pointer to the FIFO buffer to manipulate + @param[in] f + Pointer to the FIFO buffer to manipulate - @returns True if overflow happened + @returns True if overflow happened */ /******************************************************************************/ -bool tu_fifo_overflowed(tu_fifo_t *f) +bool tu_fifo_overflowed(tu_fifo_t* f) { - return _tu_fifo_overflowed(f, f->wr_idx, f->rd_idx); + return _tu_fifo_overflowed(f, f->wr_idx, f->rd_idx); } // Only use in case tu_fifo_overflow() returned true! -void tu_fifo_correct_read_pointer(tu_fifo_t *f) +void tu_fifo_correct_read_pointer(tu_fifo_t* f) { - _ff_lock(f->mutex_rd); - _tu_fifo_correct_read_pointer(f, f->wr_idx); - _ff_unlock(f->mutex_rd); + _ff_lock(f->mutex_rd); + _tu_fifo_correct_read_pointer(f, f->wr_idx); + _ff_unlock(f->mutex_rd); } /******************************************************************************/ /*! - @brief Read one element out of the buffer. + @brief Read one element out of the buffer. - This function will return the element located at the array index of the - read pointer, and then increment the read pointer index. - This function checks for an overflow and corrects read pointer if required. + This function will return the element located at the array index of the + read pointer, and then increment the read pointer index. + This function checks for an overflow and corrects read pointer if required. - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] buffer - Pointer to the place holder for data read from the buffer + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] buffer + Pointer to the place holder for data read from the buffer - @returns TRUE if the queue is not empty + @returns TRUE if the queue is not empty */ /******************************************************************************/ -bool tu_fifo_read(tu_fifo_t *f, void *buffer) +bool tu_fifo_read(tu_fifo_t* f, void * buffer) { - _ff_lock(f->mutex_rd); + _ff_lock(f->mutex_rd); - // Peek the data - // f->rd_idx might get modified in case of an overflow so we can not use a local variable - bool ret = _tu_fifo_peek(f, buffer, f->wr_idx, f->rd_idx); + // Peek the data + // f->rd_idx might get modified in case of an overflow so we can not use a local variable + bool ret = _tu_fifo_peek(f, buffer, f->wr_idx, f->rd_idx); - // Advance pointer - f->rd_idx = advance_pointer(f, f->rd_idx, ret); + // Advance pointer + f->rd_idx = advance_pointer(f, f->rd_idx, ret); - _ff_unlock(f->mutex_rd); - return ret; + _ff_unlock(f->mutex_rd); + return ret; } /******************************************************************************/ /*! - @brief This function will read n elements from the array index specified by - the read pointer and increment the read index. - This function checks for an overflow and corrects read pointer if required. - - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] buffer - The pointer to data location - @param[in] n - Number of element that buffer can afford - - @returns number of items read from the FIFO + @brief This function will read n elements from the array index specified by + the read pointer and increment the read index. + This function checks for an overflow and corrects read pointer if required. + + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] buffer + The pointer to data location + @param[in] n + Number of element that buffer can afford + + @returns number of items read from the FIFO */ /******************************************************************************/ -uint16_t tu_fifo_read_n(tu_fifo_t *f, void *buffer, uint16_t n) +uint16_t tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n) { - return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_INC); + return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_INC); } -uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t *f, void *buffer, uint16_t n) +uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t* f, void * buffer, uint16_t n) { - return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_CST_FULL_WORDS); + return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_CST_FULL_WORDS); } /******************************************************************************/ /*! - @brief Read one item without removing it from the FIFO. - This function checks for an overflow and corrects read pointer if required. + @brief Read one item without removing it from the FIFO. + This function checks for an overflow and corrects read pointer if required. - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] offset - Position to read from in the FIFO buffer with respect to read pointer - @param[in] p_buffer - Pointer to the place holder for data read from the buffer + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] offset + Position to read from in the FIFO buffer with respect to read pointer + @param[in] p_buffer + Pointer to the place holder for data read from the buffer - @returns TRUE if the queue is not empty + @returns TRUE if the queue is not empty */ /******************************************************************************/ -bool tu_fifo_peek(tu_fifo_t *f, void *p_buffer) +bool tu_fifo_peek(tu_fifo_t* f, void * p_buffer) { - _ff_lock(f->mutex_rd); - bool ret = _tu_fifo_peek(f, p_buffer, f->wr_idx, f->rd_idx); - _ff_unlock(f->mutex_rd); - return ret; + _ff_lock(f->mutex_rd); + bool ret = _tu_fifo_peek(f, p_buffer, f->wr_idx, f->rd_idx); + _ff_unlock(f->mutex_rd); + return ret; } /******************************************************************************/ /*! - @brief Read n items without removing it from the FIFO - This function checks for an overflow and corrects read pointer if required. + @brief Read n items without removing it from the FIFO + This function checks for an overflow and corrects read pointer if required. - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] p_buffer - Pointer to the place holder for data read from the buffer - @param[in] n - Number of items to peek + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] p_buffer + Pointer to the place holder for data read from the buffer + @param[in] n + Number of items to peek - @returns Number of bytes written to p_buffer + @returns Number of bytes written to p_buffer */ /******************************************************************************/ -uint16_t tu_fifo_peek_n(tu_fifo_t *f, void *p_buffer, uint16_t n) +uint16_t tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n) { - _ff_lock(f->mutex_rd); - bool ret = _tu_fifo_peek_n(f, p_buffer, n, f->wr_idx, f->rd_idx, TU_FIFO_COPY_INC); - _ff_unlock(f->mutex_rd); - return ret; + _ff_lock(f->mutex_rd); + uint16_t ret = _tu_fifo_peek_n(f, p_buffer, n, f->wr_idx, f->rd_idx, TU_FIFO_COPY_INC); + _ff_unlock(f->mutex_rd); + return ret; } /******************************************************************************/ /*! - @brief Write one element into the buffer. + @brief Write one element into the buffer. - This function will write one element into the array index specified by - the write pointer and increment the write index. + This function will write one element into the array index specified by + the write pointer and increment the write index. - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] data - The byte to add to the FIFO + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] data + The byte to add to the FIFO - @returns TRUE if the data was written to the FIFO (overwrittable - FIFO will always return TRUE) + @returns TRUE if the data was written to the FIFO (overwrittable + FIFO will always return TRUE) */ /******************************************************************************/ -bool tu_fifo_write(tu_fifo_t *f, const void *data) +bool tu_fifo_write(tu_fifo_t* f, const void * data) { - _ff_lock(f->mutex_wr); + _ff_lock(f->mutex_wr); - uint16_t w = f->wr_idx; + bool ret; + uint16_t const w = f->wr_idx; - if (_tu_fifo_full(f, w, f->rd_idx) && !f->overwritable) - return false; + if ( _tu_fifo_full(f, w, f->rd_idx) && !f->overwritable ) + { + ret = false; + }else + { + uint16_t wRel = get_relative_pointer(f, w); - uint16_t wRel = get_relative_pointer(f, w); + // Write data + _ff_push(f, data, wRel); - // Write data - _ff_push(f, data, wRel); + // Advance pointer + f->wr_idx = advance_pointer(f, w, 1); - // Advance pointer - f->wr_idx = advance_pointer(f, w, 1); + ret = true; + } - _ff_unlock(f->mutex_wr); + _ff_unlock(f->mutex_wr); - return true; + return ret; } /******************************************************************************/ /*! - @brief This function will write n elements into the array index specified by - the write pointer and increment the write index. - - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] data - The pointer to data to add to the FIFO - @param[in] count - Number of element - @return Number of written elements + @brief This function will write n elements into the array index specified by + the write pointer and increment the write index. + + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] data + The pointer to data to add to the FIFO + @param[in] count + Number of element + @return Number of written elements */ /******************************************************************************/ -uint16_t tu_fifo_write_n(tu_fifo_t *f, const void *data, uint16_t n) +uint16_t tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n) { - return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_INC); + return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_INC); } /******************************************************************************/ /*! - @brief This function will write n elements into the array index specified by - the write pointer and increment the write index. The source address will - not be incremented which is useful for reading from registers. - - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] data - The pointer to data to add to the FIFO - @param[in] count - Number of element - @return Number of written elements + @brief This function will write n elements into the array index specified by + the write pointer and increment the write index. The source address will + not be incremented which is useful for reading from registers. + + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] data + The pointer to data to add to the FIFO + @param[in] count + Number of element + @return Number of written elements */ /******************************************************************************/ -uint16_t tu_fifo_write_n_const_addr_full_words(tu_fifo_t *f, const void *data, uint16_t n) +uint16_t tu_fifo_write_n_const_addr_full_words(tu_fifo_t* f, const void * data, uint16_t n) { - return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_CST_FULL_WORDS); + return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_CST_FULL_WORDS); } /******************************************************************************/ /*! - @brief Clear the fifo read and write pointers + @brief Clear the fifo read and write pointers - @param[in] f - Pointer to the FIFO buffer to manipulate + @param[in] f + Pointer to the FIFO buffer to manipulate */ /******************************************************************************/ bool tu_fifo_clear(tu_fifo_t *f) { - _ff_lock(f->mutex_wr); - _ff_lock(f->mutex_rd); + _ff_lock(f->mutex_wr); + _ff_lock(f->mutex_rd); - f->rd_idx = f->wr_idx = 0; - f->max_pointer_idx = 2 * f->depth - 1; - f->non_used_index_space = UINT16_MAX - f->max_pointer_idx; + f->rd_idx = f->wr_idx = 0; + f->max_pointer_idx = 2*f->depth-1; + f->non_used_index_space = UINT16_MAX - f->max_pointer_idx; - _ff_unlock(f->mutex_wr); - _ff_unlock(f->mutex_rd); - return true; + _ff_unlock(f->mutex_wr); + _ff_unlock(f->mutex_rd); + return true; } /******************************************************************************/ /*! - @brief Change the fifo mode to overwritable or not overwritable + @brief Change the fifo mode to overwritable or not overwritable - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] overwritable - Overwritable mode the fifo is set to + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] overwritable + Overwritable mode the fifo is set to */ /******************************************************************************/ bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) { - _ff_lock(f->mutex_wr); - _ff_lock(f->mutex_rd); + _ff_lock(f->mutex_wr); + _ff_lock(f->mutex_rd); - f->overwritable = overwritable; + f->overwritable = overwritable; - _ff_unlock(f->mutex_wr); - _ff_unlock(f->mutex_rd); + _ff_unlock(f->mutex_wr); + _ff_unlock(f->mutex_rd); - return true; + return true; } /******************************************************************************/ /*! - @brief Advance write pointer - intended to be used in combination with DMA. - It is possible to fill the FIFO by use of a DMA in circular mode. Within - DMA ISRs you may update the write pointer to be able to read from the FIFO. - As long as the DMA is the only process writing into the FIFO this is safe - to use. - - USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE! - - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] n - Number of items the write pointer moves forward + @brief Advance write pointer - intended to be used in combination with DMA. + It is possible to fill the FIFO by use of a DMA in circular mode. Within + DMA ISRs you may update the write pointer to be able to read from the FIFO. + As long as the DMA is the only process writing into the FIFO this is safe + to use. + + USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE! + + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] n + Number of items the write pointer moves forward */ /******************************************************************************/ void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n) { - f->wr_idx = advance_pointer(f, f->wr_idx, n); + f->wr_idx = advance_pointer(f, f->wr_idx, n); } /******************************************************************************/ /*! - @brief Advance read pointer - intended to be used in combination with DMA. - It is possible to read from the FIFO by use of a DMA in linear mode. Within - DMA ISRs you may update the read pointer to be able to again write into the - FIFO. As long as the DMA is the only process reading from the FIFO this is - safe to use. - - USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE! - - @param[in] f - Pointer to the FIFO buffer to manipulate - @param[in] n - Number of items the read pointer moves forward + @brief Advance read pointer - intended to be used in combination with DMA. + It is possible to read from the FIFO by use of a DMA in linear mode. Within + DMA ISRs you may update the read pointer to be able to again write into the + FIFO. As long as the DMA is the only process reading from the FIFO this is + safe to use. + + USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE! + + @param[in] f + Pointer to the FIFO buffer to manipulate + @param[in] n + Number of items the read pointer moves forward */ /******************************************************************************/ void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n) { - f->rd_idx = advance_pointer(f, f->rd_idx, n); + f->rd_idx = advance_pointer(f, f->rd_idx, n); } /******************************************************************************/ @@ -911,59 +901,58 @@ void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n) The read pointer does NOT get advanced, use tu_fifo_advance_read_pointer() to do so! @param[in] f - Pointer to FIFO + Pointer to FIFO @param[out] *info - Pointer to struct which holds the desired infos + Pointer to struct which holds the desired infos */ /******************************************************************************/ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) { - // Operate on temporary values in case they change in between - uint16_t w = f->wr_idx, r = f->rd_idx; - - uint16_t cnt = _tu_fifo_count(f, w, r); - - // Check overflow and correct if required - may happen in case a DMA wrote too fast - if (cnt > f->depth) - { - _ff_lock(f->mutex_rd); - _tu_fifo_correct_read_pointer(f, w); - _ff_unlock(f->mutex_rd); - r = f->rd_idx; - cnt = f->depth; - } - - // Check if fifo is empty - if (cnt == 0) - { - info->len_lin = 0; - info->len_wrap = 0; - info->ptr_lin = NULL; - info->ptr_wrap = NULL; - return; - } - - // Get relative pointers - w = get_relative_pointer(f, w); - r = get_relative_pointer(f, r); - - // Copy pointer to buffer to start reading from - info->ptr_lin = &f->buffer[r]; - - // Check if there is a wrap around necessary - if (w > r) - { - // Non wrapping case - info->len_lin = cnt; - info->len_wrap = 0; - info->ptr_wrap = NULL; - } - else - { - info->len_lin = f->depth - r; // Also the case if FIFO was full - info->len_wrap = cnt - info->len_lin; - info->ptr_wrap = f->buffer; - } + // Operate on temporary values in case they change in between + uint16_t w = f->wr_idx, r = f->rd_idx; + + uint16_t cnt = _tu_fifo_count(f, w, r); + + // Check overflow and correct if required - may happen in case a DMA wrote too fast + if (cnt > f->depth) + { + _ff_lock(f->mutex_rd); + _tu_fifo_correct_read_pointer(f, w); + _ff_unlock(f->mutex_rd); + r = f->rd_idx; + cnt = f->depth; + } + + // Check if fifo is empty + if (cnt == 0) + { + info->len_lin = 0; + info->len_wrap = 0; + info->ptr_lin = NULL; + info->ptr_wrap = NULL; + return; + } + + // Get relative pointers + w = get_relative_pointer(f, w); + r = get_relative_pointer(f, r); + + // Copy pointer to buffer to start reading from + info->ptr_lin = &f->buffer[r]; + + // Check if there is a wrap around necessary + if (w > r) { + // Non wrapping case + info->len_lin = cnt; + info->len_wrap = 0; + info->ptr_wrap = NULL; + } + else + { + info->len_lin = f->depth - r; // Also the case if FIFO was full + info->len_wrap = cnt - info->len_lin; + info->ptr_wrap = f->buffer; + } } /******************************************************************************/ @@ -976,43 +965,43 @@ void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) The write pointer does NOT get advanced, use tu_fifo_advance_write_pointer() to do so! TAKE CARE TO NOT OVERFLOW THE BUFFER MORE THAN TWO TIMES THE FIFO DEPTH - IT CAN NOT RECOVERE OTHERWISE! @param[in] f - Pointer to FIFO + Pointer to FIFO @param[out] *info - Pointer to struct which holds the desired infos + Pointer to struct which holds the desired infos */ /******************************************************************************/ void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info) { - uint16_t w = f->wr_idx, r = f->rd_idx; - uint16_t free = _tu_fifo_remaining(f, w, r); - - if (free == 0) - { - info->len_lin = 0; - info->len_wrap = 0; - info->ptr_lin = NULL; - info->ptr_wrap = NULL; - return; - } - - // Get relative pointers - w = get_relative_pointer(f, w); - r = get_relative_pointer(f, r); - - // Copy pointer to buffer to start writing to - info->ptr_lin = &f->buffer[w]; - - if (w < r) - { - // Non wrapping case - info->len_lin = r - w; - info->len_wrap = 0; - info->ptr_wrap = NULL; - } - else - { - info->len_lin = f->depth - w; - info->len_wrap = free - info->len_lin; // Remaining length - n already was limited to free or FIFO depth - info->ptr_wrap = f->buffer; // Always start of buffer - } + uint16_t w = f->wr_idx, r = f->rd_idx; + uint16_t free = _tu_fifo_remaining(f, w, r); + + if (free == 0) + { + info->len_lin = 0; + info->len_wrap = 0; + info->ptr_lin = NULL; + info->ptr_wrap = NULL; + return; + } + + // Get relative pointers + w = get_relative_pointer(f, w); + r = get_relative_pointer(f, r); + + // Copy pointer to buffer to start writing to + info->ptr_lin = &f->buffer[w]; + + if (w < r) + { + // Non wrapping case + info->len_lin = r-w; + info->len_wrap = 0; + info->ptr_wrap = NULL; + } + else + { + info->len_lin = f->depth - w; + info->len_wrap = free - info->len_lin; // Remaining length - n already was limited to free or FIFO depth + info->ptr_wrap = f->buffer; // Always start of buffer + } } diff --git a/uCNC/src/tinyusb/src/common/tusb_fifo.h b/uCNC/src/tinyusb/src/common/tusb_fifo.h index 3f10ba372..455a24821 100644 --- a/uCNC/src/tinyusb/src/common/tusb_fifo.h +++ b/uCNC/src/tinyusb/src/common/tusb_fifo.h @@ -33,113 +33,113 @@ extern "C" { #endif - // Due to the use of unmasked pointers, this FIFO does not suffer from loosing - // one item slice. Furthermore, write and read operations are completely - // decoupled as write and read functions do not modify a common state. Henceforth, - // writing or reading from the FIFO within an ISR is safe as long as no other - // process (thread or ISR) interferes. - // Also, this FIFO is ready to be used in combination with a DMA as the write and - // read pointers can be updated from within a DMA ISR. Overflows are detectable - // within a certain number (see tu_fifo_overflow()). + // Due to the use of unmasked pointers, this FIFO does not suffer from loosing + // one item slice. Furthermore, write and read operations are completely + // decoupled as write and read functions do not modify a common state. Henceforth, + // writing or reading from the FIFO within an ISR is safe as long as no other + // process (thread or ISR) interferes. + // Also, this FIFO is ready to be used in combination with a DMA as the write and + // read pointers can be updated from within a DMA ISR. Overflows are detectable + // within a certain number (see tu_fifo_overflow()). -#include "tusb_common.h" +#include "../common/tusb_common.h" // mutex is only needed for RTOS // for OS None, we don't get preempted #define CFG_FIFO_MUTEX (CFG_TUSB_OS != OPT_OS_NONE) #if CFG_FIFO_MUTEX -#include "osal/osal.h" +#include "../osal/osal.h" #define tu_fifo_mutex_t osal_mutex_t #endif - typedef struct - { - uint8_t *buffer; ///< buffer pointer - uint16_t depth; ///< max items - uint16_t item_size; ///< size of each item - bool overwritable; + typedef struct + { + uint8_t *buffer; ///< buffer pointer + uint16_t depth; ///< max items + uint16_t item_size; ///< size of each item + bool overwritable; - uint16_t non_used_index_space; ///< required for non-power-of-two buffer length - uint16_t max_pointer_idx; ///< maximum absolute pointer index + uint16_t non_used_index_space; ///< required for non-power-of-two buffer length + uint16_t max_pointer_idx; ///< maximum absolute pointer index - volatile uint16_t wr_idx; ///< write pointer - volatile uint16_t rd_idx; ///< read pointer + volatile uint16_t wr_idx; ///< write pointer + volatile uint16_t rd_idx; ///< read pointer #if CFG_FIFO_MUTEX - tu_fifo_mutex_t mutex_wr; - tu_fifo_mutex_t mutex_rd; + tu_fifo_mutex_t mutex_wr; + tu_fifo_mutex_t mutex_rd; #endif - } tu_fifo_t; - - typedef struct - { - uint16_t len_lin; ///< linear length in item size - uint16_t len_wrap; ///< wrapped length in item size - void *ptr_lin; ///< linear part start pointer - void *ptr_wrap; ///< wrapped part start pointer - } tu_fifo_buffer_info_t; - -#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \ - { \ - .buffer = _buffer, \ - .depth = _depth, \ - .item_size = sizeof(_type), \ - .overwritable = _overwritable, \ - .non_used_index_space = UINT16_MAX - (2 * (_depth)-1), \ - .max_pointer_idx = 2 * (_depth)-1, \ - } + } tu_fifo_t; + + typedef struct + { + uint16_t len_lin; ///< linear length in item size + uint16_t len_wrap; ///< wrapped length in item size + void *ptr_lin; ///< linear part start pointer + void *ptr_wrap; ///< wrapped part start pointer + } tu_fifo_buffer_info_t; + +#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \ + { \ + .buffer = _buffer, \ + .depth = _depth, \ + .item_size = sizeof(_type), \ + .overwritable = _overwritable, \ + .non_used_index_space = UINT16_MAX - (2 * (_depth)-1), \ + .max_pointer_idx = 2 * (_depth)-1, \ + } #define TU_FIFO_DEF(_name, _depth, _type, _overwritable) \ - uint8_t _name##_buf[_depth * sizeof(_type)]; \ - tu_fifo_t _name = TU_FIFO_INIT(_name##_buf, _depth, _type, _overwritable) + uint8_t _name##_buf[_depth * sizeof(_type)]; \ + tu_fifo_t _name = TU_FIFO_INIT(_name##_buf, _depth, _type, _overwritable) - bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable); - bool tu_fifo_clear(tu_fifo_t *f); - bool tu_fifo_config(tu_fifo_t *f, void *buffer, uint16_t depth, uint16_t item_size, bool overwritable); + bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable); + bool tu_fifo_clear(tu_fifo_t *f); + bool tu_fifo_config(tu_fifo_t *f, void *buffer, uint16_t depth, uint16_t item_size, bool overwritable); #if CFG_FIFO_MUTEX - TU_ATTR_ALWAYS_INLINE static inline void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t write_mutex_hdl, tu_fifo_mutex_t read_mutex_hdl) - { - f->mutex_wr = write_mutex_hdl; - f->mutex_rd = read_mutex_hdl; - } + TU_ATTR_ALWAYS_INLINE static inline void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t write_mutex_hdl, tu_fifo_mutex_t read_mutex_hdl) + { + f->mutex_wr = write_mutex_hdl; + f->mutex_rd = read_mutex_hdl; + } #endif - bool tu_fifo_write(tu_fifo_t *f, void const *p_data); - uint16_t tu_fifo_write_n(tu_fifo_t *f, void const *p_data, uint16_t n); - uint16_t tu_fifo_write_n_const_addr_full_words(tu_fifo_t *f, const void *data, uint16_t n); - - bool tu_fifo_read(tu_fifo_t *f, void *p_buffer); - uint16_t tu_fifo_read_n(tu_fifo_t *f, void *p_buffer, uint16_t n); - uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t *f, void *buffer, uint16_t n); - - bool tu_fifo_peek(tu_fifo_t *f, void *p_buffer); - uint16_t tu_fifo_peek_n(tu_fifo_t *f, void *p_buffer, uint16_t n); - - uint16_t tu_fifo_count(tu_fifo_t *f); - uint16_t tu_fifo_remaining(tu_fifo_t *f); - bool tu_fifo_empty(tu_fifo_t *f); - bool tu_fifo_full(tu_fifo_t *f); - bool tu_fifo_overflowed(tu_fifo_t *f); - void tu_fifo_correct_read_pointer(tu_fifo_t *f); - - TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_depth(tu_fifo_t *f) - { - return f->depth; - } - - // Pointer modifications intended to be used in combinations with DMAs. - // USE WITH CARE - NO SAFTY CHECKS CONDUCTED HERE! NOT MUTEX PROTECTED! - void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n); - void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n); - - // If you want to read/write from/to the FIFO by use of a DMA, you may need to conduct two copies - // to handle a possible wrapping part. These functions deliver a pointer to start - // reading/writing from/to and a valid linear length along which no wrap occurs. - void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info); - void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info); + bool tu_fifo_write(tu_fifo_t *f, void const *p_data); + uint16_t tu_fifo_write_n(tu_fifo_t *f, void const *p_data, uint16_t n); + uint16_t tu_fifo_write_n_const_addr_full_words(tu_fifo_t *f, const void *data, uint16_t n); + + bool tu_fifo_read(tu_fifo_t *f, void *p_buffer); + uint16_t tu_fifo_read_n(tu_fifo_t *f, void *p_buffer, uint16_t n); + uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t *f, void *buffer, uint16_t n); + + bool tu_fifo_peek(tu_fifo_t *f, void *p_buffer); + uint16_t tu_fifo_peek_n(tu_fifo_t *f, void *p_buffer, uint16_t n); + + uint16_t tu_fifo_count(tu_fifo_t *f); + uint16_t tu_fifo_remaining(tu_fifo_t *f); + bool tu_fifo_empty(tu_fifo_t *f); + bool tu_fifo_full(tu_fifo_t *f); + bool tu_fifo_overflowed(tu_fifo_t *f); + void tu_fifo_correct_read_pointer(tu_fifo_t *f); + + TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_fifo_depth(tu_fifo_t *f) + { + return f->depth; + } + + // Pointer modifications intended to be used in combinations with DMAs. + // USE WITH CARE - NO SAFTY CHECKS CONDUCTED HERE! NOT MUTEX PROTECTED! + void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n); + void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n); + + // If you want to read/write from/to the FIFO by use of a DMA, you may need to conduct two copies + // to handle a possible wrapping part. These functions deliver a pointer to start + // reading/writing from/to and a valid linear length along which no wrap occurs. + void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info); + void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info); #ifdef __cplusplus } diff --git a/uCNC/src/tinyusb/src/common/tusb_timeout.h b/uCNC/src/tinyusb/src/common/tusb_timeout.h index ec5c3d73a..ce53955f0 100644 --- a/uCNC/src/tinyusb/src/common/tusb_timeout.h +++ b/uCNC/src/tinyusb/src/common/tusb_timeout.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -35,15 +35,13 @@ #include #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - typedef struct - { - uint32_t start; - uint32_t interval; - } tu_timeout_t; +typedef struct { + uint32_t start; + uint32_t interval; +}tu_timeout_t; #if 0 @@ -74,7 +72,7 @@ static inline void tu_timeout_restart(tu_timeout_t* tt) #endif #ifdef __cplusplus -} + } #endif #endif /* _TUSB_TIMEOUT_H_ */ diff --git a/uCNC/src/tinyusb/src/common/tusb_types.h b/uCNC/src/tinyusb/src/common/tusb_types.h index 7d90c2ec1..5b26f5aec 100644 --- a/uCNC/src/tinyusb/src/common/tusb_types.h +++ b/uCNC/src/tinyusb/src/common/tusb_types.h @@ -36,516 +36,509 @@ #include "tusb_compiler.h" #ifdef __cplusplus -extern "C" -{ + extern "C" { #endif - /*------------------------------------------------------------------*/ - /* CONSTANTS - *------------------------------------------------------------------*/ - - /// defined base on EHCI specs value for Endpoint Speed - typedef enum - { - TUSB_SPEED_FULL = 0, - TUSB_SPEED_LOW = 1, - TUSB_SPEED_HIGH = 2, - TUSB_SPEED_INVALID = 0xff, - } tusb_speed_t; - - /// defined base on USB Specs Endpoint's bmAttributes - typedef enum - { - TUSB_XFER_CONTROL = 0, - TUSB_XFER_ISOCHRONOUS, - TUSB_XFER_BULK, - TUSB_XFER_INTERRUPT - } tusb_xfer_type_t; - - typedef enum - { - TUSB_DIR_OUT = 0, - TUSB_DIR_IN = 1, - - TUSB_DIR_IN_MASK = 0x80 - } tusb_dir_t; - - /// Isochronous End Point Attributes - typedef enum - { - TUSB_ISO_EP_ATT_NO_SYNC = 0x00, - TUSB_ISO_EP_ATT_ASYNCHRONOUS = 0x04, - TUSB_ISO_EP_ATT_ADAPTIVE = 0x08, - TUSB_ISO_EP_ATT_SYNCHRONOUS = 0x0C, - TUSB_ISO_EP_ATT_DATA = 0x00, ///< Data End Point - TUSB_ISO_EP_ATT_EXPLICIT_FB = 0x10, ///< Feedback End Point - TUSB_ISO_EP_ATT_IMPLICIT_FB = 0x20, ///< Data endpoint that also serves as an implicit feedback - } tusb_iso_ep_attribute_t; - - /// USB Descriptor Types - typedef enum - { - TUSB_DESC_DEVICE = 0x01, - TUSB_DESC_CONFIGURATION = 0x02, - TUSB_DESC_STRING = 0x03, - TUSB_DESC_INTERFACE = 0x04, - TUSB_DESC_ENDPOINT = 0x05, - TUSB_DESC_DEVICE_QUALIFIER = 0x06, - TUSB_DESC_OTHER_SPEED_CONFIG = 0x07, - TUSB_DESC_INTERFACE_POWER = 0x08, - TUSB_DESC_OTG = 0x09, - TUSB_DESC_DEBUG = 0x0A, - TUSB_DESC_INTERFACE_ASSOCIATION = 0x0B, - - TUSB_DESC_BOS = 0x0F, - TUSB_DESC_DEVICE_CAPABILITY = 0x10, - - TUSB_DESC_FUNCTIONAL = 0x21, - - // Class Specific Descriptor - TUSB_DESC_CS_DEVICE = 0x21, - TUSB_DESC_CS_CONFIGURATION = 0x22, - TUSB_DESC_CS_STRING = 0x23, - TUSB_DESC_CS_INTERFACE = 0x24, - TUSB_DESC_CS_ENDPOINT = 0x25, - - TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION = 0x30, - TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31 - } tusb_desc_type_t; - - typedef enum - { - TUSB_REQ_GET_STATUS = 0, - TUSB_REQ_CLEAR_FEATURE = 1, - TUSB_REQ_RESERVED = 2, - TUSB_REQ_SET_FEATURE = 3, - TUSB_REQ_RESERVED2 = 4, - TUSB_REQ_SET_ADDRESS = 5, - TUSB_REQ_GET_DESCRIPTOR = 6, - TUSB_REQ_SET_DESCRIPTOR = 7, - TUSB_REQ_GET_CONFIGURATION = 8, - TUSB_REQ_SET_CONFIGURATION = 9, - TUSB_REQ_GET_INTERFACE = 10, - TUSB_REQ_SET_INTERFACE = 11, - TUSB_REQ_SYNCH_FRAME = 12 - } tusb_request_code_t; - - typedef enum - { - TUSB_REQ_FEATURE_EDPT_HALT = 0, - TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1, - TUSB_REQ_FEATURE_TEST_MODE = 2 - } tusb_request_feature_selector_t; - - typedef enum - { - TUSB_REQ_TYPE_STANDARD = 0, - TUSB_REQ_TYPE_CLASS, - TUSB_REQ_TYPE_VENDOR, - TUSB_REQ_TYPE_INVALID - } tusb_request_type_t; - - typedef enum - { - TUSB_REQ_RCPT_DEVICE = 0, - TUSB_REQ_RCPT_INTERFACE, - TUSB_REQ_RCPT_ENDPOINT, - TUSB_REQ_RCPT_OTHER - } tusb_request_recipient_t; - - // https://www.usb.org/defined-class-codes - typedef enum - { - TUSB_CLASS_UNSPECIFIED = 0, - TUSB_CLASS_AUDIO = 1, - TUSB_CLASS_CDC = 2, - TUSB_CLASS_HID = 3, - TUSB_CLASS_RESERVED_4 = 4, - TUSB_CLASS_PHYSICAL = 5, - TUSB_CLASS_IMAGE = 6, - TUSB_CLASS_PRINTER = 7, - TUSB_CLASS_MSC = 8, - TUSB_CLASS_HUB = 9, - TUSB_CLASS_CDC_DATA = 10, - TUSB_CLASS_SMART_CARD = 11, - TUSB_CLASS_RESERVED_12 = 12, - TUSB_CLASS_CONTENT_SECURITY = 13, - TUSB_CLASS_VIDEO = 14, - TUSB_CLASS_PERSONAL_HEALTHCARE = 15, - TUSB_CLASS_AUDIO_VIDEO = 16, - - TUSB_CLASS_DIAGNOSTIC = 0xDC, - TUSB_CLASS_WIRELESS_CONTROLLER = 0xE0, - TUSB_CLASS_MISC = 0xEF, - TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE, - TUSB_CLASS_VENDOR_SPECIFIC = 0xFF - } tusb_class_code_t; - - typedef enum - { - MISC_SUBCLASS_COMMON = 2 - } misc_subclass_type_t; - - typedef enum - { - MISC_PROTOCOL_IAD = 1 - } misc_protocol_type_t; - - typedef enum - { - APP_SUBCLASS_USBTMC = 0x03, - APP_SUBCLASS_DFU_RUNTIME = 0x01 - } app_subclass_type_t; - - typedef enum - { - DEVICE_CAPABILITY_WIRELESS_USB = 0x01, - DEVICE_CAPABILITY_USB20_EXTENSION = 0x02, - DEVICE_CAPABILITY_SUPERSPEED_USB = 0x03, - DEVICE_CAPABILITY_CONTAINER_id = 0x04, - DEVICE_CAPABILITY_PLATFORM = 0x05, - DEVICE_CAPABILITY_POWER_DELIVERY = 0x06, - DEVICE_CAPABILITY_BATTERY_INFO = 0x07, - DEVICE_CAPABILITY_PD_CONSUMER_PORT = 0x08, - DEVICE_CAPABILITY_PD_PROVIDER_PORT = 0x09, - DEVICE_CAPABILITY_SUPERSPEED_PLUS = 0x0A, - DEVICE_CAPABILITY_PRECESION_TIME_MEASUREMENT = 0x0B, - DEVICE_CAPABILITY_WIRELESS_USB_EXT = 0x0C, - DEVICE_CAPABILITY_BILLBOARD = 0x0D, - DEVICE_CAPABILITY_AUTHENTICATION = 0x0E, - DEVICE_CAPABILITY_BILLBOARD_EX = 0x0F, - DEVICE_CAPABILITY_CONFIGURATION_SUMMARY = 0x10 - } device_capability_type_t; - - enum - { - TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5), - TUSB_DESC_CONFIG_ATT_SELF_POWERED = TU_BIT(6), - }; - -#define TUSB_DESC_CONFIG_POWER_MA(x) ((x) / 2) - - /// Device State TODO remove - typedef enum - { - TUSB_DEVICE_STATE_UNPLUG = 0, - TUSB_DEVICE_STATE_CONFIGURED, - TUSB_DEVICE_STATE_SUSPENDED, - } tusb_device_state_t; - - typedef enum - { - XFER_RESULT_SUCCESS, - XFER_RESULT_FAILED, - XFER_RESULT_STALLED, - } xfer_result_t; - - enum // TODO remove - { - DESC_OFFSET_LEN = 0, - DESC_OFFSET_TYPE = 1 - }; - - enum - { - INTERFACE_INVALID_NUMBER = 0xff - }; - - typedef enum - { - MS_OS_20_SET_HEADER_DESCRIPTOR = 0x00, - MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01, - MS_OS_20_SUBSET_HEADER_FUNCTION = 0x02, - MS_OS_20_FEATURE_COMPATBLE_ID = 0x03, - MS_OS_20_FEATURE_REG_PROPERTY = 0x04, - MS_OS_20_FEATURE_MIN_RESUME_TIME = 0x05, - MS_OS_20_FEATURE_MODEL_ID = 0x06, - MS_OS_20_FEATURE_CCGP_DEVICE = 0x07, - MS_OS_20_FEATURE_VENDOR_REVISION = 0x08 - } microsoft_os_20_type_t; - - enum - { - CONTROL_STAGE_SETUP, - CONTROL_STAGE_DATA, - CONTROL_STAGE_ACK - }; - - //--------------------------------------------------------------------+ - // USB Descriptors - //--------------------------------------------------------------------+ - - // Start of all packed definitions for compiler without per-type packed - TU_ATTR_PACKED_BEGIN - TU_ATTR_BIT_FIELD_ORDER_BEGIN - - /// USB Device Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes. - uint8_t bDescriptorType; ///< DEVICE Descriptor Type. - uint16_t bcdUSB; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant. - - uint8_t bDeviceClass; ///< Class code (assigned by the USB-IF). \li If this field is reset to zero, each interface within a configuration specifies its own class information and the various interfaces operate independently. \li If this field is set to a value between 1 and FEH, the device supports different class specifications on different interfaces and the interfaces may not operate independently. This value identifies the class definition used for the aggregate interfaces. \li If this field is set to FFH, the device class is vendor-specific. - uint8_t bDeviceSubClass; ///< Subclass code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass field. \li If the bDeviceClass field is reset to zero, this field must also be reset to zero. \li If the bDeviceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. - uint8_t bDeviceProtocol; ///< Protocol code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass and the bDeviceSubClass fields. If a device supports class-specific protocols on a device basis as opposed to an interface basis, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use class-specific protocols on a device basis. However, it may use classspecific protocols on an interface basis. \li If this field is set to FFH, the device uses a vendor-specific protocol on a device basis. - uint8_t bMaxPacketSize0; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64. - - uint16_t idVendor; ///< Vendor ID (assigned by the USB-IF). - uint16_t idProduct; ///< Product ID (assigned by the manufacturer). - uint16_t bcdDevice; ///< Device release number in binary-coded decimal. - uint8_t iManufacturer; ///< Index of string descriptor describing manufacturer. - uint8_t iProduct; ///< Index of string descriptor describing product. - uint8_t iSerialNumber; ///< Index of string descriptor describing the device's serial number. - - uint8_t bNumConfigurations; ///< Number of possible configurations. - } tusb_desc_device_t; - - TU_VERIFY_STATIC(sizeof(tusb_desc_device_t) == 18, "size is not correct"); - - // USB Binary Device Object Store (BOS) Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes - uint8_t bDescriptorType; ///< CONFIGURATION Descriptor Type - uint16_t wTotalLength; ///< Total length of data returned for this descriptor - uint8_t bNumDeviceCaps; ///< Number of device capability descriptors in the BOS - } tusb_desc_bos_t; - - TU_VERIFY_STATIC(sizeof(tusb_desc_bos_t) == 5, "size is not correct"); - - /// USB Configuration Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes - uint8_t bDescriptorType; ///< CONFIGURATION Descriptor Type - uint16_t wTotalLength; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. - - uint8_t bNumInterfaces; ///< Number of interfaces supported by this configuration - uint8_t bConfigurationValue; ///< Value to use as an argument to the SetConfiguration() request to select this configuration. - uint8_t iConfiguration; ///< Index of string descriptor describing this configuration - uint8_t bmAttributes; ///< Configuration characteristics \n D7: Reserved (set to one)\n D6: Self-powered \n D5: Remote Wakeup \n D4...0: Reserved (reset to zero) \n D7 is reserved and must be set to one for historical reasons. \n A device configuration that uses power from the bus and a local source reports a non-zero value in bMaxPower to indicate the amount of bus power required and sets D6. The actual power source at runtime may be determined using the GetStatus(DEVICE) request (see USB 2.0 spec Section 9.4.5). \n If a device configuration supports remote wakeup, D5 is set to one. - uint8_t bMaxPower; ///< Maximum power consumption of the USB device from the bus in this specific configuration when the device is fully operational. Expressed in 2 mA units (i.e., 50 = 100 mA). - } tusb_desc_configuration_t; - - TU_VERIFY_STATIC(sizeof(tusb_desc_configuration_t) == 9, "size is not correct"); - - /// USB Interface Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes - uint8_t bDescriptorType; ///< INTERFACE Descriptor Type - - uint8_t bInterfaceNumber; ///< Number of this interface. Zero-based value identifying the index in the array of concurrent interfaces supported by this configuration. - uint8_t bAlternateSetting; ///< Value used to select this alternate setting for the interface identified in the prior field - uint8_t bNumEndpoints; ///< Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the Default Control Pipe. - uint8_t bInterfaceClass; ///< Class code (assigned by the USB-IF). \li A value of zero is reserved for future standardization. \li If this field is set to FFH, the interface class is vendor-specific. \li All other values are reserved for assignment by the USB-IF. - uint8_t bInterfaceSubClass; ///< Subclass code (assigned by the USB-IF). \n These codes are qualified by the value of the bInterfaceClass field. \li If the bInterfaceClass field is reset to zero, this field must also be reset to zero. \li If the bInterfaceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. - uint8_t bInterfaceProtocol; ///< Protocol code (assigned by the USB). \n These codes are qualified by the value of the bInterfaceClass and the bInterfaceSubClass fields. If an interface supports class-specific requests, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use a class-specific protocol on this interface. \li If this field is set to FFH, the device uses a vendor-specific protocol for this interface. - uint8_t iInterface; ///< Index of string descriptor describing this interface - } tusb_desc_interface_t; - - TU_VERIFY_STATIC(sizeof(tusb_desc_interface_t) == 9, "size is not correct"); - - /// USB Endpoint Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; // Size of this descriptor in bytes - uint8_t bDescriptorType; // ENDPOINT Descriptor Type - - uint8_t bEndpointAddress; // The address of the endpoint - - struct TU_ATTR_PACKED - { - uint8_t xfer : 2; // Control, ISO, Bulk, Interrupt - uint8_t sync : 2; // None, Asynchronous, Adaptive, Synchronous - uint8_t usage : 2; // Data, Feedback, Implicit feedback - uint8_t : 2; - } bmAttributes; - - uint16_t wMaxPacketSize; // Bit 10..0 : max packet size, bit 12..11 additional transaction per highspeed micro-frame - uint8_t bInterval; // Polling interval, in frames or microframes depending on the operating speed - } tusb_desc_endpoint_t; - - TU_VERIFY_STATIC(sizeof(tusb_desc_endpoint_t) == 7, "size is not correct"); - - /// USB Other Speed Configuration Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of descriptor - uint8_t bDescriptorType; ///< Other_speed_Configuration Type - uint16_t wTotalLength; ///< Total length of data returned - - uint8_t bNumInterfaces; ///< Number of interfaces supported by this speed configuration - uint8_t bConfigurationValue; ///< Value to use to select configuration - uint8_t iConfiguration; ///< Index of string descriptor - uint8_t bmAttributes; ///< Same as Configuration descriptor - uint8_t bMaxPower; ///< Same as Configuration descriptor - } tusb_desc_other_speed_t; - - /// USB Device Qualifier Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of descriptor - uint8_t bDescriptorType; ///< Device Qualifier Type - uint16_t bcdUSB; ///< USB specification version number (e.g., 0200H for V2.00) - - uint8_t bDeviceClass; ///< Class Code - uint8_t bDeviceSubClass; ///< SubClass Code - uint8_t bDeviceProtocol; ///< Protocol Code - - uint8_t bMaxPacketSize0; ///< Maximum packet size for other speed - uint8_t bNumConfigurations; ///< Number of Other-speed Configurations - uint8_t bReserved; ///< Reserved for future use, must be zero - } tusb_desc_device_qualifier_t; - - TU_VERIFY_STATIC(sizeof(tusb_desc_device_qualifier_t) == 10, "size is not correct"); - - /// USB Interface Association Descriptor (IAD ECN) - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of descriptor - uint8_t bDescriptorType; ///< Other_speed_Configuration Type - - uint8_t bFirstInterface; ///< Index of the first associated interface. - uint8_t bInterfaceCount; ///< Total number of associated interfaces. - - uint8_t bFunctionClass; ///< Interface class ID. - uint8_t bFunctionSubClass; ///< Interface subclass ID. - uint8_t bFunctionProtocol; ///< Interface protocol ID. - - uint8_t iFunction; ///< Index of the string descriptor describing the interface association. - } tusb_desc_interface_assoc_t; - - // USB String Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; ///< Size of this descriptor in bytes - uint8_t bDescriptorType; ///< Descriptor Type - uint16_t unicode_string[]; - } tusb_desc_string_t; - - // USB Binary Device Object Store (BOS) - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint8_t bReserved; - uint8_t PlatformCapabilityUUID[16]; - uint8_t CapabilityData[]; - } tusb_desc_bos_platform_t; - - // USB WebuSB URL Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bScheme; - char url[]; - } tusb_desc_webusb_url_t; - - // DFU Functional Descriptor - typedef struct TU_ATTR_PACKED - { - uint8_t bLength; - uint8_t bDescriptorType; - - union - { - struct TU_ATTR_PACKED - { - uint8_t bitCanDnload : 1; - uint8_t bitCanUpload : 1; - uint8_t bitManifestationTolerant : 1; - uint8_t bitWillDetach : 1; - uint8_t reserved : 4; - } bmAttributes; - - uint8_t bAttributes; - }; - - uint16_t wDetachTimeOut; - uint16_t wTransferSize; - uint16_t bcdDFUVersion; - } tusb_desc_dfu_functional_t; - - /*------------------------------------------------------------------*/ - /* Types - *------------------------------------------------------------------*/ - typedef struct TU_ATTR_PACKED - { - union - { - struct TU_ATTR_PACKED - { - uint8_t recipient : 5; ///< Recipient type tusb_request_recipient_t. - uint8_t type : 2; ///< Request type tusb_request_type_t. - uint8_t direction : 1; ///< Direction type. tusb_dir_t - } bmRequestType_bit; - - uint8_t bmRequestType; - }; - - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; - } tusb_control_request_t; - - TU_VERIFY_STATIC(sizeof(tusb_control_request_t) == 8, "size is not correct"); - - TU_ATTR_PACKED_END // End of all packed definitions - TU_ATTR_BIT_FIELD_ORDER_END - - //--------------------------------------------------------------------+ - // Endpoint helper - //--------------------------------------------------------------------+ - - // Get direction from Endpoint address - static inline tusb_dir_t - tu_edpt_dir(uint8_t addr) - { - return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; - } - - // Get Endpoint number from address - static inline uint8_t tu_edpt_number(uint8_t addr) - { - return (uint8_t)(addr & (~TUSB_DIR_IN_MASK)); - } - - static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) - { - return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0)); - } - - static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const *desc_ep) - { - return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0); - } - - //--------------------------------------------------------------------+ - // Descriptor helper - //--------------------------------------------------------------------+ - static inline uint8_t const *tu_desc_next(void const *desc) - { - uint8_t const *desc8 = (uint8_t const *)desc; - return desc8 + desc8[DESC_OFFSET_LEN]; - } - - static inline uint8_t tu_desc_type(void const *desc) - { - return ((uint8_t const *)desc)[DESC_OFFSET_TYPE]; - } - - static inline uint8_t tu_desc_len(void const *desc) - { - return ((uint8_t const *)desc)[DESC_OFFSET_LEN]; - } +/*------------------------------------------------------------------*/ +/* CONSTANTS + *------------------------------------------------------------------*/ -#ifdef __cplusplus +/// defined base on EHCI specs value for Endpoint Speed +typedef enum +{ + TUSB_SPEED_FULL = 0, + TUSB_SPEED_LOW = 1, + TUSB_SPEED_HIGH = 2, + TUSB_SPEED_INVALID = 0xff, +}tusb_speed_t; + +/// defined base on USB Specs Endpoint's bmAttributes +typedef enum +{ + TUSB_XFER_CONTROL = 0 , + TUSB_XFER_ISOCHRONOUS , + TUSB_XFER_BULK , + TUSB_XFER_INTERRUPT +}tusb_xfer_type_t; + +typedef enum +{ + TUSB_DIR_OUT = 0, + TUSB_DIR_IN = 1, + + TUSB_DIR_IN_MASK = 0x80 +}tusb_dir_t; + +/// Isochronous End Point Attributes +typedef enum +{ + TUSB_ISO_EP_ATT_NO_SYNC = 0x00, + TUSB_ISO_EP_ATT_ASYNCHRONOUS = 0x04, + TUSB_ISO_EP_ATT_ADAPTIVE = 0x08, + TUSB_ISO_EP_ATT_SYNCHRONOUS = 0x0C, + TUSB_ISO_EP_ATT_DATA = 0x00, ///< Data End Point + TUSB_ISO_EP_ATT_EXPLICIT_FB = 0x10, ///< Feedback End Point + TUSB_ISO_EP_ATT_IMPLICIT_FB = 0x20, ///< Data endpoint that also serves as an implicit feedback +}tusb_iso_ep_attribute_t; + +/// USB Descriptor Types +typedef enum +{ + TUSB_DESC_DEVICE = 0x01, + TUSB_DESC_CONFIGURATION = 0x02, + TUSB_DESC_STRING = 0x03, + TUSB_DESC_INTERFACE = 0x04, + TUSB_DESC_ENDPOINT = 0x05, + TUSB_DESC_DEVICE_QUALIFIER = 0x06, + TUSB_DESC_OTHER_SPEED_CONFIG = 0x07, + TUSB_DESC_INTERFACE_POWER = 0x08, + TUSB_DESC_OTG = 0x09, + TUSB_DESC_DEBUG = 0x0A, + TUSB_DESC_INTERFACE_ASSOCIATION = 0x0B, + + TUSB_DESC_BOS = 0x0F, + TUSB_DESC_DEVICE_CAPABILITY = 0x10, + + TUSB_DESC_FUNCTIONAL = 0x21, + + // Class Specific Descriptor + TUSB_DESC_CS_DEVICE = 0x21, + TUSB_DESC_CS_CONFIGURATION = 0x22, + TUSB_DESC_CS_STRING = 0x23, + TUSB_DESC_CS_INTERFACE = 0x24, + TUSB_DESC_CS_ENDPOINT = 0x25, + + TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION = 0x30, + TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31 +}tusb_desc_type_t; + +typedef enum +{ + TUSB_REQ_GET_STATUS = 0 , + TUSB_REQ_CLEAR_FEATURE = 1 , + TUSB_REQ_RESERVED = 2 , + TUSB_REQ_SET_FEATURE = 3 , + TUSB_REQ_RESERVED2 = 4 , + TUSB_REQ_SET_ADDRESS = 5 , + TUSB_REQ_GET_DESCRIPTOR = 6 , + TUSB_REQ_SET_DESCRIPTOR = 7 , + TUSB_REQ_GET_CONFIGURATION = 8 , + TUSB_REQ_SET_CONFIGURATION = 9 , + TUSB_REQ_GET_INTERFACE = 10 , + TUSB_REQ_SET_INTERFACE = 11 , + TUSB_REQ_SYNCH_FRAME = 12 +}tusb_request_code_t; + +typedef enum +{ + TUSB_REQ_FEATURE_EDPT_HALT = 0, + TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1, + TUSB_REQ_FEATURE_TEST_MODE = 2 +}tusb_request_feature_selector_t; + +typedef enum +{ + TUSB_REQ_TYPE_STANDARD = 0, + TUSB_REQ_TYPE_CLASS, + TUSB_REQ_TYPE_VENDOR, + TUSB_REQ_TYPE_INVALID +} tusb_request_type_t; + +typedef enum +{ + TUSB_REQ_RCPT_DEVICE =0, + TUSB_REQ_RCPT_INTERFACE, + TUSB_REQ_RCPT_ENDPOINT, + TUSB_REQ_RCPT_OTHER +} tusb_request_recipient_t; + +// https://www.usb.org/defined-class-codes +typedef enum +{ + TUSB_CLASS_UNSPECIFIED = 0 , + TUSB_CLASS_AUDIO = 1 , + TUSB_CLASS_CDC = 2 , + TUSB_CLASS_HID = 3 , + TUSB_CLASS_RESERVED_4 = 4 , + TUSB_CLASS_PHYSICAL = 5 , + TUSB_CLASS_IMAGE = 6 , + TUSB_CLASS_PRINTER = 7 , + TUSB_CLASS_MSC = 8 , + TUSB_CLASS_HUB = 9 , + TUSB_CLASS_CDC_DATA = 10 , + TUSB_CLASS_SMART_CARD = 11 , + TUSB_CLASS_RESERVED_12 = 12 , + TUSB_CLASS_CONTENT_SECURITY = 13 , + TUSB_CLASS_VIDEO = 14 , + TUSB_CLASS_PERSONAL_HEALTHCARE = 15 , + TUSB_CLASS_AUDIO_VIDEO = 16 , + + TUSB_CLASS_DIAGNOSTIC = 0xDC , + TUSB_CLASS_WIRELESS_CONTROLLER = 0xE0 , + TUSB_CLASS_MISC = 0xEF , + TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE , + TUSB_CLASS_VENDOR_SPECIFIC = 0xFF +}tusb_class_code_t; + +typedef enum +{ + MISC_SUBCLASS_COMMON = 2 +}misc_subclass_type_t; + +typedef enum +{ + MISC_PROTOCOL_IAD = 1 +}misc_protocol_type_t; + +typedef enum +{ + APP_SUBCLASS_USBTMC = 0x03, + APP_SUBCLASS_DFU_RUNTIME = 0x01 +} app_subclass_type_t; + +typedef enum +{ + DEVICE_CAPABILITY_WIRELESS_USB = 0x01, + DEVICE_CAPABILITY_USB20_EXTENSION = 0x02, + DEVICE_CAPABILITY_SUPERSPEED_USB = 0x03, + DEVICE_CAPABILITY_CONTAINER_id = 0x04, + DEVICE_CAPABILITY_PLATFORM = 0x05, + DEVICE_CAPABILITY_POWER_DELIVERY = 0x06, + DEVICE_CAPABILITY_BATTERY_INFO = 0x07, + DEVICE_CAPABILITY_PD_CONSUMER_PORT = 0x08, + DEVICE_CAPABILITY_PD_PROVIDER_PORT = 0x09, + DEVICE_CAPABILITY_SUPERSPEED_PLUS = 0x0A, + DEVICE_CAPABILITY_PRECESION_TIME_MEASUREMENT = 0x0B, + DEVICE_CAPABILITY_WIRELESS_USB_EXT = 0x0C, + DEVICE_CAPABILITY_BILLBOARD = 0x0D, + DEVICE_CAPABILITY_AUTHENTICATION = 0x0E, + DEVICE_CAPABILITY_BILLBOARD_EX = 0x0F, + DEVICE_CAPABILITY_CONFIGURATION_SUMMARY = 0x10 +}device_capability_type_t; + +enum { + TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5), + TUSB_DESC_CONFIG_ATT_SELF_POWERED = TU_BIT(6), +}; + +#define TUSB_DESC_CONFIG_POWER_MA(x) ((x)/2) + +/// Device State TODO remove +typedef enum +{ + TUSB_DEVICE_STATE_UNPLUG = 0 , + TUSB_DEVICE_STATE_CONFIGURED , + TUSB_DEVICE_STATE_SUSPENDED , +}tusb_device_state_t; + +typedef enum +{ + XFER_RESULT_SUCCESS, + XFER_RESULT_FAILED, + XFER_RESULT_STALLED, +}xfer_result_t; + +enum // TODO remove +{ + DESC_OFFSET_LEN = 0, + DESC_OFFSET_TYPE = 1 +}; + +enum +{ + INTERFACE_INVALID_NUMBER = 0xff +}; + + +typedef enum +{ + MS_OS_20_SET_HEADER_DESCRIPTOR = 0x00, + MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01, + MS_OS_20_SUBSET_HEADER_FUNCTION = 0x02, + MS_OS_20_FEATURE_COMPATBLE_ID = 0x03, + MS_OS_20_FEATURE_REG_PROPERTY = 0x04, + MS_OS_20_FEATURE_MIN_RESUME_TIME = 0x05, + MS_OS_20_FEATURE_MODEL_ID = 0x06, + MS_OS_20_FEATURE_CCGP_DEVICE = 0x07, + MS_OS_20_FEATURE_VENDOR_REVISION = 0x08 +} microsoft_os_20_type_t; + +enum +{ + CONTROL_STAGE_SETUP, + CONTROL_STAGE_DATA, + CONTROL_STAGE_ACK +}; + +//--------------------------------------------------------------------+ +// USB Descriptors +//--------------------------------------------------------------------+ + +// Start of all packed definitions for compiler without per-type packed +TU_ATTR_PACKED_BEGIN +TU_ATTR_BIT_FIELD_ORDER_BEGIN + +/// USB Device Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes. + uint8_t bDescriptorType ; ///< DEVICE Descriptor Type. + uint16_t bcdUSB ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant. + + uint8_t bDeviceClass ; ///< Class code (assigned by the USB-IF). \li If this field is reset to zero, each interface within a configuration specifies its own class information and the various interfaces operate independently. \li If this field is set to a value between 1 and FEH, the device supports different class specifications on different interfaces and the interfaces may not operate independently. This value identifies the class definition used for the aggregate interfaces. \li If this field is set to FFH, the device class is vendor-specific. + uint8_t bDeviceSubClass ; ///< Subclass code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass field. \li If the bDeviceClass field is reset to zero, this field must also be reset to zero. \li If the bDeviceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. + uint8_t bDeviceProtocol ; ///< Protocol code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass and the bDeviceSubClass fields. If a device supports class-specific protocols on a device basis as opposed to an interface basis, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use class-specific protocols on a device basis. However, it may use classspecific protocols on an interface basis. \li If this field is set to FFH, the device uses a vendor-specific protocol on a device basis. + uint8_t bMaxPacketSize0 ; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64. + + uint16_t idVendor ; ///< Vendor ID (assigned by the USB-IF). + uint16_t idProduct ; ///< Product ID (assigned by the manufacturer). + uint16_t bcdDevice ; ///< Device release number in binary-coded decimal. + uint8_t iManufacturer ; ///< Index of string descriptor describing manufacturer. + uint8_t iProduct ; ///< Index of string descriptor describing product. + uint8_t iSerialNumber ; ///< Index of string descriptor describing the device's serial number. + + uint8_t bNumConfigurations ; ///< Number of possible configurations. +} tusb_desc_device_t; + +TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct"); + +// USB Binary Device Object Store (BOS) Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes + uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type + uint16_t wTotalLength ; ///< Total length of data returned for this descriptor + uint8_t bNumDeviceCaps ; ///< Number of device capability descriptors in the BOS +} tusb_desc_bos_t; + +TU_VERIFY_STATIC( sizeof(tusb_desc_bos_t) == 5, "size is not correct"); + +/// USB Configuration Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes + uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type + uint16_t wTotalLength ; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration. + + uint8_t bNumInterfaces ; ///< Number of interfaces supported by this configuration + uint8_t bConfigurationValue ; ///< Value to use as an argument to the SetConfiguration() request to select this configuration. + uint8_t iConfiguration ; ///< Index of string descriptor describing this configuration + uint8_t bmAttributes ; ///< Configuration characteristics \n D7: Reserved (set to one)\n D6: Self-powered \n D5: Remote Wakeup \n D4...0: Reserved (reset to zero) \n D7 is reserved and must be set to one for historical reasons. \n A device configuration that uses power from the bus and a local source reports a non-zero value in bMaxPower to indicate the amount of bus power required and sets D6. The actual power source at runtime may be determined using the GetStatus(DEVICE) request (see USB 2.0 spec Section 9.4.5). \n If a device configuration supports remote wakeup, D5 is set to one. + uint8_t bMaxPower ; ///< Maximum power consumption of the USB device from the bus in this specific configuration when the device is fully operational. Expressed in 2 mA units (i.e., 50 = 100 mA). +} tusb_desc_configuration_t; + +TU_VERIFY_STATIC( sizeof(tusb_desc_configuration_t) == 9, "size is not correct"); + +/// USB Interface Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes + uint8_t bDescriptorType ; ///< INTERFACE Descriptor Type + + uint8_t bInterfaceNumber ; ///< Number of this interface. Zero-based value identifying the index in the array of concurrent interfaces supported by this configuration. + uint8_t bAlternateSetting ; ///< Value used to select this alternate setting for the interface identified in the prior field + uint8_t bNumEndpoints ; ///< Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the Default Control Pipe. + uint8_t bInterfaceClass ; ///< Class code (assigned by the USB-IF). \li A value of zero is reserved for future standardization. \li If this field is set to FFH, the interface class is vendor-specific. \li All other values are reserved for assignment by the USB-IF. + uint8_t bInterfaceSubClass ; ///< Subclass code (assigned by the USB-IF). \n These codes are qualified by the value of the bInterfaceClass field. \li If the bInterfaceClass field is reset to zero, this field must also be reset to zero. \li If the bInterfaceClass field is not set to FFH, all values are reserved for assignment by the USB-IF. + uint8_t bInterfaceProtocol ; ///< Protocol code (assigned by the USB). \n These codes are qualified by the value of the bInterfaceClass and the bInterfaceSubClass fields. If an interface supports class-specific requests, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use a class-specific protocol on this interface. \li If this field is set to FFH, the device uses a vendor-specific protocol for this interface. + uint8_t iInterface ; ///< Index of string descriptor describing this interface +} tusb_desc_interface_t; + +TU_VERIFY_STATIC( sizeof(tusb_desc_interface_t) == 9, "size is not correct"); + +/// USB Endpoint Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; // Size of this descriptor in bytes + uint8_t bDescriptorType ; // ENDPOINT Descriptor Type + + uint8_t bEndpointAddress ; // The address of the endpoint + + struct TU_ATTR_PACKED { + uint8_t xfer : 2; // Control, ISO, Bulk, Interrupt + uint8_t sync : 2; // None, Asynchronous, Adaptive, Synchronous + uint8_t usage : 2; // Data, Feedback, Implicit feedback + uint8_t : 2; + } bmAttributes; + + uint16_t wMaxPacketSize ; // Bit 10..0 : max packet size, bit 12..11 additional transaction per highspeed micro-frame + uint8_t bInterval ; // Polling interval, in frames or microframes depending on the operating speed +} tusb_desc_endpoint_t; + +TU_VERIFY_STATIC( sizeof(tusb_desc_endpoint_t) == 7, "size is not correct"); + +/// USB Other Speed Configuration Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of descriptor + uint8_t bDescriptorType ; ///< Other_speed_Configuration Type + uint16_t wTotalLength ; ///< Total length of data returned + + uint8_t bNumInterfaces ; ///< Number of interfaces supported by this speed configuration + uint8_t bConfigurationValue ; ///< Value to use to select configuration + uint8_t iConfiguration ; ///< Index of string descriptor + uint8_t bmAttributes ; ///< Same as Configuration descriptor + uint8_t bMaxPower ; ///< Same as Configuration descriptor +} tusb_desc_other_speed_t; + +/// USB Device Qualifier Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of descriptor + uint8_t bDescriptorType ; ///< Device Qualifier Type + uint16_t bcdUSB ; ///< USB specification version number (e.g., 0200H for V2.00) + + uint8_t bDeviceClass ; ///< Class Code + uint8_t bDeviceSubClass ; ///< SubClass Code + uint8_t bDeviceProtocol ; ///< Protocol Code + + uint8_t bMaxPacketSize0 ; ///< Maximum packet size for other speed + uint8_t bNumConfigurations ; ///< Number of Other-speed Configurations + uint8_t bReserved ; ///< Reserved for future use, must be zero +} tusb_desc_device_qualifier_t; + +TU_VERIFY_STATIC( sizeof(tusb_desc_device_qualifier_t) == 10, "size is not correct"); + +/// USB Interface Association Descriptor (IAD ECN) +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of descriptor + uint8_t bDescriptorType ; ///< Other_speed_Configuration Type + + uint8_t bFirstInterface ; ///< Index of the first associated interface. + uint8_t bInterfaceCount ; ///< Total number of associated interfaces. + + uint8_t bFunctionClass ; ///< Interface class ID. + uint8_t bFunctionSubClass ; ///< Interface subclass ID. + uint8_t bFunctionProtocol ; ///< Interface protocol ID. + + uint8_t iFunction ; ///< Index of the string descriptor describing the interface association. +} tusb_desc_interface_assoc_t; + +// USB String Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength ; ///< Size of this descriptor in bytes + uint8_t bDescriptorType ; ///< Descriptor Type + uint16_t unicode_string[]; +} tusb_desc_string_t; + +// USB Binary Device Object Store (BOS) +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength; + uint8_t bDescriptorType ; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t PlatformCapabilityUUID[16]; + uint8_t CapabilityData[]; +} tusb_desc_bos_platform_t; + +// USB WebuSB URL Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bScheme; + char url[]; +} tusb_desc_webusb_url_t; + +// DFU Functional Descriptor +typedef struct TU_ATTR_PACKED +{ + uint8_t bLength; + uint8_t bDescriptorType; + + union { + struct TU_ATTR_PACKED { + uint8_t bitCanDnload : 1; + uint8_t bitCanUpload : 1; + uint8_t bitManifestationTolerant : 1; + uint8_t bitWillDetach : 1; + uint8_t reserved : 4; + } bmAttributes; + + uint8_t bAttributes; + }; + + uint16_t wDetachTimeOut; + uint16_t wTransferSize; + uint16_t bcdDFUVersion; +} tusb_desc_dfu_functional_t; + +/*------------------------------------------------------------------*/ +/* Types + *------------------------------------------------------------------*/ +typedef struct TU_ATTR_PACKED{ + union { + struct TU_ATTR_PACKED { + uint8_t recipient : 5; ///< Recipient type tusb_request_recipient_t. + uint8_t type : 2; ///< Request type tusb_request_type_t. + uint8_t direction : 1; ///< Direction type. tusb_dir_t + } bmRequestType_bit; + + uint8_t bmRequestType; + }; + + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} tusb_control_request_t; + +TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct"); + + +TU_ATTR_PACKED_END // End of all packed definitions +TU_ATTR_BIT_FIELD_ORDER_END + +//--------------------------------------------------------------------+ +// Endpoint helper +//--------------------------------------------------------------------+ + +// Get direction from Endpoint address +static inline tusb_dir_t tu_edpt_dir(uint8_t addr) +{ + return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT; +} + +// Get Endpoint number from address +static inline uint8_t tu_edpt_number(uint8_t addr) +{ + return (uint8_t)(addr & (~TUSB_DIR_IN_MASK)); +} + +static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir) +{ + return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0)); +} + +static inline uint16_t tu_edpt_packet_size(tusb_desc_endpoint_t const* desc_ep) +{ + return tu_le16toh(desc_ep->wMaxPacketSize) & TU_GENMASK(10, 0); } + +//--------------------------------------------------------------------+ +// Descriptor helper +//--------------------------------------------------------------------+ +static inline uint8_t const * tu_desc_next(void const* desc) +{ + uint8_t const* desc8 = (uint8_t const*) desc; + return desc8 + desc8[DESC_OFFSET_LEN]; +} + +static inline uint8_t tu_desc_type(void const* desc) +{ + return ((uint8_t const*) desc)[DESC_OFFSET_TYPE]; +} + +static inline uint8_t tu_desc_len(void const* desc) +{ + return ((uint8_t const*) desc)[DESC_OFFSET_LEN]; +} + +#ifdef __cplusplus + } #endif #endif /* _TUSB_TYPES_H_ */ diff --git a/uCNC/src/tinyusb/src/common/tusb_verify.h b/uCNC/src/tinyusb/src/common/tusb_verify.h index 2847f15d2..c3f6b5b09 100644 --- a/uCNC/src/tinyusb/src/common/tusb_verify.h +++ b/uCNC/src/tinyusb/src/common/tusb_verify.h @@ -69,9 +69,9 @@ extern "C" { #endif - //--------------------------------------------------------------------+ - // TU_VERIFY Helper - //--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // TU_VERIFY Helper + //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG #include @@ -79,37 +79,37 @@ extern "C" #define _MESS_FAILED() tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__) #else #define _MESS_ERR(_err) \ - do \ - { \ - } while (0) + do \ + { \ + } while (0) #define _MESS_FAILED() \ - do \ - { \ - } while (0) + do \ + { \ + } while (0) #endif -// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 -#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -#define TU_BREAKPOINT() \ - do \ - { \ - volatile uint32_t *ARM_CM_DHCSR = ((volatile uint32_t *)0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ - if ((*ARM_CM_DHCSR) & 1UL) \ - __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \ - } while (0) +// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33 +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) +#define TU_BREAKPOINT() \ + do \ + { \ + volatile uint32_t *ARM_CM_DHCSR = ((volatile uint32_t *)0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ + if ((*ARM_CM_DHCSR) & 1UL) \ + __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \ + } while (0) #elif defined(__riscv) -#define TU_BREAKPOINT() \ - do \ - { \ - __asm("ebreak\n"); \ - } while (0) +#define TU_BREAKPOINT() \ + do \ + { \ + __asm("ebreak\n"); \ + } while (0) #else #define TU_BREAKPOINT() \ - do \ - { \ - } while (0) + do \ + { \ + } while (0) #endif /*------------------------------------------------------------------*/ @@ -122,14 +122,14 @@ extern "C" /*------------- Generator for TU_VERIFY and TU_VERIFY_HDLR -------------*/ #define TU_VERIFY_DEFINE(_cond, _handler, _ret) \ - do \ - { \ - if (!(_cond)) \ - { \ - _handler; \ - return _ret; \ - } \ - } while (0) + do \ + { \ + if (!(_cond)) \ + { \ + _handler; \ + return _ret; \ + } \ + } while (0) /*------------------------------------------------------------------*/ /* TU_VERIFY @@ -168,28 +168,28 @@ extern "C" /*------------- Generator for TU_VERIFY_ERR and TU_VERIFY_ERR_HDLR -------------*/ #define TU_VERIFY_ERR_DEF2(_error, _handler) \ - do \ - { \ - uint32_t _err = (uint32_t)(_error); \ - if (0 != _err) \ - { \ - _MESS_ERR(_err); \ - _handler; \ - return _err; \ - } \ - } while (0) + do \ + { \ + uint32_t _err = (uint32_t)(_error); \ + if (0 != _err) \ + { \ + _MESS_ERR(_err); \ + _handler; \ + return _err; \ + } \ + } while (0) #define TU_VERIFY_ERR_DEF3(_error, _handler, _ret) \ - do \ - { \ - uint32_t _err = (uint32_t)(_error); \ - if (0 != _err) \ - { \ - _MESS_ERR(_err); \ - _handler; \ - return _ret; \ - } \ - } while (0) + do \ + { \ + uint32_t _err = (uint32_t)(_error); \ + if (0 != _err) \ + { \ + _MESS_ERR(_err); \ + _handler; \ + return _ret; \ + } \ + } while (0) /*------------------------------------------------------------------*/ /* ASSERT Error @@ -202,9 +202,9 @@ extern "C" #define TU_ASSERT_ERR(...) GET_3RD_ARG(__VA_ARGS__, ASSERT_ERR_2ARGS, ASSERT_ERR_1ARGS, UNUSED)(__VA_ARGS__) #endif - /*------------------------------------------------------------------*/ - /* ASSERT HDLR - *------------------------------------------------------------------*/ + /*------------------------------------------------------------------*/ + /* ASSERT HDLR + *------------------------------------------------------------------*/ #ifdef __cplusplus } diff --git a/uCNC/src/tinyusb/src/device/dcd.h b/uCNC/src/tinyusb/src/device/dcd.h index ed074454e..a5be831e5 100644 --- a/uCNC/src/tinyusb/src/device/dcd.h +++ b/uCNC/src/tinyusb/src/device/dcd.h @@ -37,158 +37,158 @@ extern "C" { #endif - //--------------------------------------------------------------------+ - // Configuration - //--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // Configuration + //--------------------------------------------------------------------+ #ifndef CFG_TUD_ENDPPOINT_MAX #define CFG_TUD_ENDPPOINT_MAX DCD_ATTR_ENDPOINT_MAX #endif - //--------------------------------------------------------------------+ - // MACRO CONSTANT TYPEDEF PROTYPES - //--------------------------------------------------------------------+ - - typedef enum - { - DCD_EVENT_INVALID = 0, - DCD_EVENT_BUS_RESET, - DCD_EVENT_UNPLUGGED, - DCD_EVENT_SOF, - DCD_EVENT_SUSPEND, // TODO LPM Sleep L1 support - DCD_EVENT_RESUME, - - DCD_EVENT_SETUP_RECEIVED, - DCD_EVENT_XFER_COMPLETE, - - // Not an DCD event, just a convenient way to defer ISR function - USBD_EVENT_FUNC_CALL, - - DCD_EVENT_COUNT - } dcd_eventid_t; - - typedef struct TU_ATTR_ALIGNED(4) - { - uint8_t rhport; - uint8_t event_id; - - union - { - // BUS RESET - struct - { - tusb_speed_t speed; - } bus_reset; - - // SETUP_RECEIVED - tusb_control_request_t setup_received; - - // XFER_COMPLETE - struct - { - uint8_t ep_addr; - uint8_t result; - uint32_t len; - } xfer_complete; - - // FUNC_CALL - struct - { - void (*func)(void *); - void *param; - } func_call; - }; - } dcd_event_t; - - // TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct"); - - //--------------------------------------------------------------------+ - // Controller API - //--------------------------------------------------------------------+ - - // Initialize controller to device mode - void dcd_init(uint8_t rhport); + //--------------------------------------------------------------------+ + // MACRO CONSTANT TYPEDEF PROTYPES + //--------------------------------------------------------------------+ + + typedef enum + { + DCD_EVENT_INVALID = 0, + DCD_EVENT_BUS_RESET, + DCD_EVENT_UNPLUGGED, + DCD_EVENT_SOF, + DCD_EVENT_SUSPEND, // TODO LPM Sleep L1 support + DCD_EVENT_RESUME, + + DCD_EVENT_SETUP_RECEIVED, + DCD_EVENT_XFER_COMPLETE, + + // Not an DCD event, just a convenient way to defer ISR function + USBD_EVENT_FUNC_CALL, + + DCD_EVENT_COUNT + } dcd_eventid_t; + + typedef struct TU_ATTR_ALIGNED(4) + { + uint8_t rhport; + uint8_t event_id; + + union + { + // BUS RESET + struct + { + tusb_speed_t speed; + } bus_reset; + + // SETUP_RECEIVED + tusb_control_request_t setup_received; + + // XFER_COMPLETE + struct + { + uint8_t ep_addr; + uint8_t result; + uint32_t len; + } xfer_complete; + + // FUNC_CALL + struct + { + void (*func)(void *); + void *param; + } func_call; + }; + } dcd_event_t; + + // TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct"); + + //--------------------------------------------------------------------+ + // Controller API + //--------------------------------------------------------------------+ + + // Initialize controller to device mode + void dcd_init(uint8_t rhport); // Interrupt Handler -#if __GNUC__ +#if __GNUC__ && !defined(__ARMCC_VERSION) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wredundant-decls" #endif - void dcd_int_handler(uint8_t rhport); -#if __GNUC__ + void dcd_int_handler(uint8_t rhport); +#if __GNUC__ && !defined(__ARMCC_VERSION) #pragma GCC diagnostic pop #endif - // Enable device interrupt - void dcd_int_enable(uint8_t rhport); + // Enable device interrupt + void dcd_int_enable(uint8_t rhport); - // Disable device interrupt - void dcd_int_disable(uint8_t rhport); + // Disable device interrupt + void dcd_int_disable(uint8_t rhport); - // Receive Set Address request, mcu port must also include status IN response - void dcd_set_address(uint8_t rhport, uint8_t dev_addr); + // Receive Set Address request, mcu port must also include status IN response + void dcd_set_address(uint8_t rhport, uint8_t dev_addr); - // Wake up host - void dcd_remote_wakeup(uint8_t rhport); + // Wake up host + void dcd_remote_wakeup(uint8_t rhport); - // Connect by enabling internal pull-up resistor on D+/D- - void dcd_connect(uint8_t rhport) TU_ATTR_WEAK; + // Connect by enabling internal pull-up resistor on D+/D- + void dcd_connect(uint8_t rhport) TU_ATTR_WEAK; - // Disconnect by disabling internal pull-up resistor on D+/D- - void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK; + // Disconnect by disabling internal pull-up resistor on D+/D- + void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK; - //--------------------------------------------------------------------+ - // Endpoint API - //--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // Endpoint API + //--------------------------------------------------------------------+ - // Invoked when a control transfer's status stage is complete. - // May help DCD to prepare for next control transfer, this API is optional. - void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) TU_ATTR_WEAK; + // Invoked when a control transfer's status stage is complete. + // May help DCD to prepare for next control transfer, this API is optional. + void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) TU_ATTR_WEAK; - // Configure endpoint's registers according to descriptor - bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep); + // Configure endpoint's registers according to descriptor + bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep); - // Close all non-control endpoints, cancel all pending transfers if any. - // Invoked when switching from a non-zero Configuration by SET_CONFIGURE therefore - // required for multiple configuration support. - void dcd_edpt_close_all(uint8_t rhport); + // Close all non-control endpoints, cancel all pending transfers if any. + // Invoked when switching from a non-zero Configuration by SET_CONFIGURE therefore + // required for multiple configuration support. + void dcd_edpt_close_all(uint8_t rhport); - // Close an endpoint. - // Since it is weak, caller must TU_ASSERT this function's existence before calling it. - void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK; + // Close an endpoint. + // Since it is weak, caller must TU_ASSERT this function's existence before calling it. + void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK; - // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack - bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes); + // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack + bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes); - // Submit an transfer using fifo, When complete dcd_event_xfer_complete() is invoked to notify the stack - // This API is optional, may be useful for register-based for transferring data. - bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) TU_ATTR_WEAK; + // Submit an transfer using fifo, When complete dcd_event_xfer_complete() is invoked to notify the stack + // This API is optional, may be useful for register-based for transferring data. + bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) TU_ATTR_WEAK; - // Stall endpoint, any queuing transfer should be removed from endpoint - void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr); + // Stall endpoint, any queuing transfer should be removed from endpoint + void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr); - // clear stall, data toggle is also reset to DATA0 - // This API never calls with control endpoints, since it is auto cleared when receiving setup packet - void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr); + // clear stall, data toggle is also reset to DATA0 + // This API never calls with control endpoints, since it is auto cleared when receiving setup packet + void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr); - //--------------------------------------------------------------------+ - // Event API (implemented by stack) - //--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // Event API (implemented by stack) + //--------------------------------------------------------------------+ - // Called by DCD to notify device stack - extern void dcd_event_handler(dcd_event_t const *event, bool in_isr); + // Called by DCD to notify device stack + extern void dcd_event_handler(dcd_event_t const *event, bool in_isr); - // helper to send bus signal event - extern void dcd_event_bus_signal(uint8_t rhport, dcd_eventid_t eid, bool in_isr); + // helper to send bus signal event + extern void dcd_event_bus_signal(uint8_t rhport, dcd_eventid_t eid, bool in_isr); - // helper to send bus reset event - extern void dcd_event_bus_reset(uint8_t rhport, tusb_speed_t speed, bool in_isr); + // helper to send bus reset event + extern void dcd_event_bus_reset(uint8_t rhport, tusb_speed_t speed, bool in_isr); - // helper to send setup received - extern void dcd_event_setup_received(uint8_t rhport, uint8_t const *setup, bool in_isr); + // helper to send setup received + extern void dcd_event_setup_received(uint8_t rhport, uint8_t const *setup, bool in_isr); - // helper to send transfer complete event - extern void dcd_event_xfer_complete(uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr); + // helper to send transfer complete event + extern void dcd_event_xfer_complete(uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr); #ifdef __cplusplus } diff --git a/uCNC/src/tinyusb/src/device/dcd_attr.h b/uCNC/src/tinyusb/src/device/dcd_attr.h index 3345886c8..43d25bc91 100644 --- a/uCNC/src/tinyusb/src/device/dcd_attr.h +++ b/uCNC/src/tinyusb/src/device/dcd_attr.h @@ -75,7 +75,7 @@ //------------- Microchip -------------// #elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAMD51, OPT_MCU_SAME5X) || \ - TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22) + TU_CHECK_MCU(OPT_MCU_SAMD11, OPT_MCU_SAML21, OPT_MCU_SAML22) #define DCD_ATTR_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_SAMG) @@ -86,13 +86,17 @@ #define DCD_ATTR_ENDPOINT_MAX 10 #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER +#elif TU_CHECK_MCU(OPT_MCU_PIC32MZ) +#define DCD_ATTR_ENDPOINT_MAX 8 +#define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER + //------------- ST -------------// #elif TU_CHECK_MCU(OPT_MCU_STM32F0) #define DCD_ATTR_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_STM32F1) #if defined(STM32F105x8) || defined(STM32F105xB) || defined(STM32F105xC) || \ - defined(STM32F107xB) || defined(STM32F107xC) + defined(STM32F107xB) || defined(STM32F107xC) #define DCD_ATTR_ENDPOINT_MAX 4 #define DCD_ATTR_DWC2_STM32 #else @@ -129,10 +133,10 @@ #elif TU_CHECK_MCU(OPT_MCU_STM32L4) #if defined(STM32L475xx) || defined(STM32L476xx) || \ - defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || \ - defined(STM32L4A6xx) || defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || \ - defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || \ + defined(STM32L4A6xx) || defined(STM32L4P5xx) || defined(STM32L4Q5xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || \ + defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DCD_ATTR_ENDPOINT_MAX 6 #define DCD_ATTR_DWC2_STM32 #else @@ -190,13 +194,24 @@ #define DCD_ATTR_ENDPOINT_MAX 4 //------------- Broadcom -------------// -#elif TU_CHECK_MCU(OPT_MCU_BCM2711) +#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) #define DCD_ATTR_ENDPOINT_MAX 8 //------------- Broadcom -------------// #elif TU_CHECK_MCU(OPT_MCU_XMC4000) #define DCD_ATTR_ENDPOINT_MAX 8 +//------------- BridgeTek -------------// +#elif TU_CHECK_MCU(OPT_MCU_FT90X) +#define DCD_ATTR_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_FT93X) +#define DCD_ATTR_ENDPOINT_MAX 16 + +//------------ Allwinner -------------// +#elif TU_CHECK_MCU(OPT_MCU_F1C100S) +#define DCD_ATTR_ENDPOINT_MAX 4 + #else #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8" #define DCD_ATTR_ENDPOINT_MAX 8 diff --git a/uCNC/src/tinyusb/src/device/usbd.c b/uCNC/src/tinyusb/src/device/usbd.c index c405f6533..d039fe585 100644 --- a/uCNC/src/tinyusb/src/device/usbd.c +++ b/uCNC/src/tinyusb/src/device/usbd.c @@ -51,36 +51,36 @@ // Invalid driver ID in itf2drv[] ep2drv[][] mapping enum { - DRVID_INVALID = 0xFFu + DRVID_INVALID = 0xFFu }; typedef struct { - struct TU_ATTR_PACKED - { - volatile uint8_t connected : 1; - volatile uint8_t addressed : 1; - volatile uint8_t suspended : 1; + struct TU_ATTR_PACKED + { + volatile uint8_t connected : 1; + volatile uint8_t addressed : 1; + volatile uint8_t suspended : 1; - uint8_t remote_wakeup_en : 1; // enable/disable by host - uint8_t remote_wakeup_support : 1; // configuration descriptor's attribute - uint8_t self_powered : 1; // configuration descriptor's attribute - }; + uint8_t remote_wakeup_en : 1; // enable/disable by host + uint8_t remote_wakeup_support : 1; // configuration descriptor's attribute + uint8_t self_powered : 1; // configuration descriptor's attribute + }; - volatile uint8_t cfg_num; // current active configuration (0x00 is not configured) - uint8_t speed; + volatile uint8_t cfg_num; // current active configuration (0x00 is not configured) + uint8_t speed; - uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid) - uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ) + uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid) + uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid ) - struct TU_ATTR_PACKED - { - volatile bool busy : 1; - volatile bool stalled : 1; - volatile bool claimed : 1; + struct TU_ATTR_PACKED + { + volatile bool busy : 1; + volatile bool stalled : 1; + volatile bool claimed : 1; - // TODO merge ep2drv here, 4-bit should be sufficient - } ep_status[CFG_TUD_ENDPPOINT_MAX][2]; + // TODO merge ep2drv here, 4-bit should be sufficient + } ep_status[CFG_TUD_ENDPPOINT_MAX][2]; } usbd_device_t; @@ -97,133 +97,133 @@ static usbd_device_t _usbd_dev; // Built-in class drivers static usbd_class_driver_t const _usbd_driver[] = - { + { #if CFG_TUD_CDC - {DRIVER_NAME("CDC") - .init = cdcd_init, - .reset = cdcd_reset, - .open = cdcd_open, - .control_xfer_cb = cdcd_control_xfer_cb, - .xfer_cb = cdcd_xfer_cb, - .sof = NULL}, + {DRIVER_NAME("CDC") + .init = cdcd_init, + .reset = cdcd_reset, + .open = cdcd_open, + .control_xfer_cb = cdcd_control_xfer_cb, + .xfer_cb = cdcd_xfer_cb, + .sof = NULL}, #endif #if CFG_TUD_MSC - {DRIVER_NAME("MSC") - .init = mscd_init, - .reset = mscd_reset, - .open = mscd_open, - .control_xfer_cb = mscd_control_xfer_cb, - .xfer_cb = mscd_xfer_cb, - .sof = NULL}, + {DRIVER_NAME("MSC") + .init = mscd_init, + .reset = mscd_reset, + .open = mscd_open, + .control_xfer_cb = mscd_control_xfer_cb, + .xfer_cb = mscd_xfer_cb, + .sof = NULL}, #endif #if CFG_TUD_HID - {DRIVER_NAME("HID") - .init = hidd_init, - .reset = hidd_reset, - .open = hidd_open, - .control_xfer_cb = hidd_control_xfer_cb, - .xfer_cb = hidd_xfer_cb, - .sof = NULL}, + {DRIVER_NAME("HID") + .init = hidd_init, + .reset = hidd_reset, + .open = hidd_open, + .control_xfer_cb = hidd_control_xfer_cb, + .xfer_cb = hidd_xfer_cb, + .sof = NULL}, #endif #if CFG_TUD_AUDIO - {DRIVER_NAME("AUDIO") - .init = audiod_init, - .reset = audiod_reset, - .open = audiod_open, - .control_xfer_cb = audiod_control_xfer_cb, - .xfer_cb = audiod_xfer_cb, - .sof = NULL}, + {DRIVER_NAME("AUDIO") + .init = audiod_init, + .reset = audiod_reset, + .open = audiod_open, + .control_xfer_cb = audiod_control_xfer_cb, + .xfer_cb = audiod_xfer_cb, + .sof = NULL}, #endif #if CFG_TUD_VIDEO - {DRIVER_NAME("VIDEO") - .init = videod_init, - .reset = videod_reset, - .open = videod_open, - .control_xfer_cb = videod_control_xfer_cb, - .xfer_cb = videod_xfer_cb, - .sof = NULL}, + {DRIVER_NAME("VIDEO") + .init = videod_init, + .reset = videod_reset, + .open = videod_open, + .control_xfer_cb = videod_control_xfer_cb, + .xfer_cb = videod_xfer_cb, + .sof = NULL}, #endif #if CFG_TUD_MIDI - {DRIVER_NAME("MIDI") - .init = midid_init, - .open = midid_open, - .reset = midid_reset, - .control_xfer_cb = midid_control_xfer_cb, - .xfer_cb = midid_xfer_cb, - .sof = NULL}, + {DRIVER_NAME("MIDI") + .init = midid_init, + .open = midid_open, + .reset = midid_reset, + .control_xfer_cb = midid_control_xfer_cb, + .xfer_cb = midid_xfer_cb, + .sof = NULL}, #endif #if CFG_TUD_VENDOR - {DRIVER_NAME("VENDOR") - .init = vendord_init, - .reset = vendord_reset, - .open = vendord_open, - .control_xfer_cb = tud_vendor_control_xfer_cb, - .xfer_cb = vendord_xfer_cb, - .sof = NULL}, + {DRIVER_NAME("VENDOR") + .init = vendord_init, + .reset = vendord_reset, + .open = vendord_open, + .control_xfer_cb = tud_vendor_control_xfer_cb, + .xfer_cb = vendord_xfer_cb, + .sof = NULL}, #endif #if CFG_TUD_USBTMC - {DRIVER_NAME("TMC") - .init = usbtmcd_init_cb, - .reset = usbtmcd_reset_cb, - .open = usbtmcd_open_cb, - .control_xfer_cb = usbtmcd_control_xfer_cb, - .xfer_cb = usbtmcd_xfer_cb, - .sof = NULL}, + {DRIVER_NAME("TMC") + .init = usbtmcd_init_cb, + .reset = usbtmcd_reset_cb, + .open = usbtmcd_open_cb, + .control_xfer_cb = usbtmcd_control_xfer_cb, + .xfer_cb = usbtmcd_xfer_cb, + .sof = NULL}, #endif #if CFG_TUD_DFU_RUNTIME - {DRIVER_NAME("DFU-RUNTIME") - .init = dfu_rtd_init, - .reset = dfu_rtd_reset, - .open = dfu_rtd_open, - .control_xfer_cb = dfu_rtd_control_xfer_cb, - .xfer_cb = NULL, - .sof = NULL}, + {DRIVER_NAME("DFU-RUNTIME") + .init = dfu_rtd_init, + .reset = dfu_rtd_reset, + .open = dfu_rtd_open, + .control_xfer_cb = dfu_rtd_control_xfer_cb, + .xfer_cb = NULL, + .sof = NULL}, #endif #if CFG_TUD_DFU - {DRIVER_NAME("DFU") - .init = dfu_moded_init, - .reset = dfu_moded_reset, - .open = dfu_moded_open, - .control_xfer_cb = dfu_moded_control_xfer_cb, - .xfer_cb = NULL, - .sof = NULL}, + {DRIVER_NAME("DFU") + .init = dfu_moded_init, + .reset = dfu_moded_reset, + .open = dfu_moded_open, + .control_xfer_cb = dfu_moded_control_xfer_cb, + .xfer_cb = NULL, + .sof = NULL}, #endif #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM - { - DRIVER_NAME("NET") - .init = netd_init, - .reset = netd_reset, - .open = netd_open, - .control_xfer_cb = netd_control_xfer_cb, - .xfer_cb = netd_xfer_cb, - .sof = NULL, - }, + { + DRIVER_NAME("NET") + .init = netd_init, + .reset = netd_reset, + .open = netd_open, + .control_xfer_cb = netd_control_xfer_cb, + .xfer_cb = netd_xfer_cb, + .sof = NULL, + }, #endif #if CFG_TUD_BTH - {DRIVER_NAME("BTH") - .init = btd_init, - .reset = btd_reset, - .open = btd_open, - .control_xfer_cb = btd_control_xfer_cb, - .xfer_cb = btd_xfer_cb, - .sof = NULL}, + {DRIVER_NAME("BTH") + .init = btd_init, + .reset = btd_reset, + .open = btd_open, + .control_xfer_cb = btd_control_xfer_cb, + .xfer_cb = btd_xfer_cb, + .sof = NULL}, #endif }; enum { - BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) + BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) }; // Additional class drivers implemented by application @@ -234,19 +234,19 @@ static uint8_t _app_driver_count = 0; // Application is positioned first to allow overwriting built-in ones. static inline usbd_class_driver_t const *get_driver(uint8_t drvid) { - // Application drivers - if (usbd_app_driver_get_cb) - { - if (drvid < _app_driver_count) - return &_app_driver[drvid]; - drvid -= _app_driver_count; - } - - // Built-in drivers - if (drvid < BUILTIN_DRIVER_COUNT) - return &_usbd_driver[drvid]; - - return NULL; + // Application drivers + if (usbd_app_driver_get_cb) + { + if (drvid < _app_driver_count) + return &_app_driver[drvid]; + drvid -= _app_driver_count; + } + + // Built-in drivers + if (drvid < BUILTIN_DRIVER_COUNT) + return &_usbd_driver[drvid]; + + return NULL; } #define TOTAL_DRIVER_COUNT (_app_driver_count + BUILTIN_DRIVER_COUNT) @@ -286,47 +286,47 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= 2 static char const *const _usbd_event_str[DCD_EVENT_COUNT] = - { - "Invalid", - "Bus Reset", - "Unplugged", - "SOF", - "Suspend", - "Resume", - "Setup Received", - "Xfer Complete", - "Func Call"}; + { + "Invalid", + "Bus Reset", + "Unplugged", + "SOF", + "Suspend", + "Resume", + "Setup Received", + "Xfer Complete", + "Func Call"}; static char const *const _tusb_std_request_str[] = - { - "Get Status", - "Clear Feature", - "Reserved", - "Set Feature", - "Reserved", - "Set Address", - "Get Descriptor", - "Set Descriptor", - "Get Configuration", - "Set Configuration", - "Get Interface", - "Set Interface", - "Synch Frame"}; + { + "Get Status", + "Clear Feature", + "Reserved", + "Set Feature", + "Reserved", + "Set Address", + "Get Descriptor", + "Set Descriptor", + "Get Configuration", + "Set Configuration", + "Get Interface", + "Set Interface", + "Synch Frame"}; static char const *const _tusb_speed_str[] = {"Full", "Low", "High"}; // for usbd_control to print the name of control complete driver void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) { - for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) - { - usbd_class_driver_t const *driver = get_driver(i); - if (driver->control_xfer_cb == callback) - { - TU_LOG2(" %s control complete\r\n", driver->name); - return; - } - } + for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) + { + usbd_class_driver_t const *driver = get_driver(i); + if (driver->control_xfer_cb == callback) + { + TU_LOG2(" %s control complete\r\n", driver->name); + return; + } + } } #endif @@ -336,44 +336,44 @@ void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback) //--------------------------------------------------------------------+ tusb_speed_t tud_speed_get(void) { - return (tusb_speed_t)_usbd_dev.speed; + return (tusb_speed_t)_usbd_dev.speed; } bool tud_connected(void) { - return _usbd_dev.connected; + return _usbd_dev.connected; } bool tud_mounted(void) { - return _usbd_dev.cfg_num ? true : false; + return _usbd_dev.cfg_num ? true : false; } bool tud_suspended(void) { - return _usbd_dev.suspended; + return _usbd_dev.suspended; } bool tud_remote_wakeup(void) { - // only wake up host if this feature is supported and enabled and we are suspended - TU_VERIFY(_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en); - dcd_remote_wakeup(TUD_OPT_RHPORT); - return true; + // only wake up host if this feature is supported and enabled and we are suspended + TU_VERIFY(_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en); + dcd_remote_wakeup(TUD_OPT_RHPORT); + return true; } bool tud_disconnect(void) { - TU_VERIFY(dcd_disconnect); - dcd_disconnect(TUD_OPT_RHPORT); - return true; + TU_VERIFY(dcd_disconnect); + dcd_disconnect(TUD_OPT_RHPORT); + return true; } bool tud_connect(void) { - TU_VERIFY(dcd_connect); - dcd_connect(TUD_OPT_RHPORT); - return true; + TU_VERIFY(dcd_connect); + dcd_connect(TUD_OPT_RHPORT); + return true; } //--------------------------------------------------------------------+ @@ -381,77 +381,77 @@ bool tud_connect(void) //--------------------------------------------------------------------+ bool tud_inited(void) { - return _usbd_initialized; + return _usbd_initialized; } bool tud_init(uint8_t rhport) { - // skip if already initialized - if (_usbd_initialized) - return _usbd_initialized; + // skip if already initialized + if (_usbd_initialized) + return _usbd_initialized; - TU_LOG2("USBD init\r\n"); + TU_LOG2("USBD init\r\n"); - tu_varclr(&_usbd_dev); + tu_varclr(&_usbd_dev); #if CFG_TUSB_OS != OPT_OS_NONE - // Init device mutex - _usbd_mutex = osal_mutex_create(&_ubsd_mutexdef); - TU_ASSERT(_usbd_mutex); + // Init device mutex + _usbd_mutex = osal_mutex_create(&_ubsd_mutexdef); + TU_ASSERT(_usbd_mutex); #endif - // Init device queue & task - _usbd_q = osal_queue_create(&_usbd_qdef); - TU_ASSERT(_usbd_q); + // Init device queue & task + _usbd_q = osal_queue_create(&_usbd_qdef); + TU_ASSERT(_usbd_q); - // Get application driver if available - if (usbd_app_driver_get_cb) - { - _app_driver = usbd_app_driver_get_cb(&_app_driver_count); - } + // Get application driver if available + if (usbd_app_driver_get_cb) + { + _app_driver = usbd_app_driver_get_cb(&_app_driver_count); + } - // Init class drivers - for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) - { - usbd_class_driver_t const *driver = get_driver(i); - TU_LOG2("%s init\r\n", driver->name); - driver->init(); - } + // Init class drivers + for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) + { + usbd_class_driver_t const *driver = get_driver(i); + TU_LOG2("%s init\r\n", driver->name); + driver->init(); + } - // Init device controller driver - dcd_init(rhport); - dcd_int_enable(rhport); + // Init device controller driver + dcd_init(rhport); + dcd_int_enable(rhport); - _usbd_initialized = true; + _usbd_initialized = true; - return true; + return true; } static void configuration_reset(uint8_t rhport) { - for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) - { - get_driver(i)->reset(rhport); - } - - tu_varclr(&_usbd_dev); - memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping - memset(_usbd_dev.ep2drv, DRVID_INVALID, sizeof(_usbd_dev.ep2drv)); // invalid mapping + for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) + { + get_driver(i)->reset(rhport); + } + + tu_varclr(&_usbd_dev); + memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping + memset(_usbd_dev.ep2drv, DRVID_INVALID, sizeof(_usbd_dev.ep2drv)); // invalid mapping } static void usbd_reset(uint8_t rhport) { - configuration_reset(rhport); - usbd_control_reset(); + configuration_reset(rhport); + usbd_control_reset(); } bool tud_task_event_ready(void) { - // Skip if stack is not initialized - if (!tusb_inited()) - return false; + // Skip if stack is not initialized + if (!tusb_inited()) + return false; - return !osal_queue_empty(_usbd_q); + return !osal_queue_empty(_usbd_q); } /* USB Device Driver task @@ -459,157 +459,157 @@ bool tud_task_event_ready(void) * This should be called periodically within the mainloop or rtos thread. * @code - int main(void) - { - application_init(); - tusb_init(); - - while(1) // the mainloop - { - application_code(); - tud_task(); // tinyusb device task - } - } - @endcode + int main(void) + { + application_init(); + tusb_init(); + + while(1) // the mainloop + { + application_code(); + tud_task(); // tinyusb device task + } + } + @endcode */ void tud_task(void) { - // Skip if stack is not initialized - if (!tusb_inited()) - return; + // Skip if stack is not initialized + if (!tusb_inited()) + return; - // Loop until there is no more events in the queue - while (1) - { - dcd_event_t event; + // Loop until there is no more events in the queue + while (1) + { + dcd_event_t event; - if (!osal_queue_receive(_usbd_q, &event)) - return; + if (!osal_queue_receive(_usbd_q, &event)) + return; #if CFG_TUSB_DEBUG >= 2 - if (event.event_id == DCD_EVENT_SETUP_RECEIVED) - TU_LOG2("\r\n"); // extra line for setup - TU_LOG2("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED"); + if (event.event_id == DCD_EVENT_SETUP_RECEIVED) + TU_LOG2("\r\n"); // extra line for setup + TU_LOG2("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED"); #endif - switch (event.event_id) - { - case DCD_EVENT_BUS_RESET: - TU_LOG2(": %s Speed\r\n", _tusb_speed_str[event.bus_reset.speed]); - usbd_reset(event.rhport); - _usbd_dev.speed = event.bus_reset.speed; - break; - - case DCD_EVENT_UNPLUGGED: - TU_LOG2("\r\n"); - usbd_reset(event.rhport); - - // invoke callback - if (tud_umount_cb) - tud_umount_cb(); - break; - - case DCD_EVENT_SETUP_RECEIVED: - TU_LOG2_VAR(&event.setup_received); - TU_LOG2("\r\n"); - - // Mark as connected after receiving 1st setup packet. - // But it is easier to set it every time instead of wasting time to check then set - _usbd_dev.connected = 1; - - // mark both in & out control as free - _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = false; - _usbd_dev.ep_status[0][TUSB_DIR_OUT].claimed = 0; - _usbd_dev.ep_status[0][TUSB_DIR_IN].busy = false; - _usbd_dev.ep_status[0][TUSB_DIR_IN].claimed = 0; - - // Process control request - if (!process_control_request(event.rhport, &event.setup_received)) - { - TU_LOG2(" Stall EP0\r\n"); - // Failed -> stall both control endpoint IN and OUT - dcd_edpt_stall(event.rhport, 0); - dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK); - } - break; - - case DCD_EVENT_XFER_COMPLETE: - { - // Invoke the class callback associated with the endpoint address - uint8_t const ep_addr = event.xfer_complete.ep_addr; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const ep_dir = tu_edpt_dir(ep_addr); - - TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int)event.xfer_complete.len); - - _usbd_dev.ep_status[epnum][ep_dir].busy = false; - _usbd_dev.ep_status[epnum][ep_dir].claimed = 0; - - if (0 == epnum) - { - usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len); - } - else - { - usbd_class_driver_t const *driver = get_driver(_usbd_dev.ep2drv[epnum][ep_dir]); - TU_ASSERT(driver, ); - - TU_LOG2(" %s xfer callback\r\n", driver->name); - driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len); - } - } - break; - - case DCD_EVENT_SUSPEND: - // NOTE: When plugging/unplugging device, the D+/D- state are unstable and - // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ), which result in a series of event - // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected - if (_usbd_dev.connected) - { - TU_LOG2(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en); - if (tud_suspend_cb) - tud_suspend_cb(_usbd_dev.remote_wakeup_en); - } - else - { - TU_LOG2(" Skipped\r\n"); - } - break; - - case DCD_EVENT_RESUME: - if (_usbd_dev.connected) - { - TU_LOG2("\r\n"); - if (tud_resume_cb) - tud_resume_cb(); - } - else - { - TU_LOG2(" Skipped\r\n"); - } - break; - - case DCD_EVENT_SOF: - TU_LOG2("\r\n"); - for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) - { - usbd_class_driver_t const *driver = get_driver(i); - if (driver->sof) - driver->sof(event.rhport); - } - break; - - case USBD_EVENT_FUNC_CALL: - TU_LOG2("\r\n"); - if (event.func_call.func) - event.func_call.func(event.func_call.param); - break; - - default: - TU_BREAKPOINT(); - break; - } - } + switch (event.event_id) + { + case DCD_EVENT_BUS_RESET: + TU_LOG2(": %s Speed\r\n", _tusb_speed_str[event.bus_reset.speed]); + usbd_reset(event.rhport); + _usbd_dev.speed = event.bus_reset.speed; + break; + + case DCD_EVENT_UNPLUGGED: + TU_LOG2("\r\n"); + usbd_reset(event.rhport); + + // invoke callback + if (tud_umount_cb) + tud_umount_cb(); + break; + + case DCD_EVENT_SETUP_RECEIVED: + TU_LOG2_VAR(&event.setup_received); + TU_LOG2("\r\n"); + + // Mark as connected after receiving 1st setup packet. + // But it is easier to set it every time instead of wasting time to check then set + _usbd_dev.connected = 1; + + // mark both in & out control as free + _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = false; + _usbd_dev.ep_status[0][TUSB_DIR_OUT].claimed = 0; + _usbd_dev.ep_status[0][TUSB_DIR_IN].busy = false; + _usbd_dev.ep_status[0][TUSB_DIR_IN].claimed = 0; + + // Process control request + if (!process_control_request(event.rhport, &event.setup_received)) + { + TU_LOG2(" Stall EP0\r\n"); + // Failed -> stall both control endpoint IN and OUT + dcd_edpt_stall(event.rhport, 0); + dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK); + } + break; + + case DCD_EVENT_XFER_COMPLETE: + { + // Invoke the class callback associated with the endpoint address + uint8_t const ep_addr = event.xfer_complete.ep_addr; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const ep_dir = tu_edpt_dir(ep_addr); + + TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int)event.xfer_complete.len); + + _usbd_dev.ep_status[epnum][ep_dir].busy = false; + _usbd_dev.ep_status[epnum][ep_dir].claimed = 0; + + if (0 == epnum) + { + usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len); + } + else + { + usbd_class_driver_t const *driver = get_driver(_usbd_dev.ep2drv[epnum][ep_dir]); + TU_ASSERT(driver, ); + + TU_LOG2(" %s xfer callback\r\n", driver->name); + driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len); + } + } + break; + + case DCD_EVENT_SUSPEND: + // NOTE: When plugging/unplugging device, the D+/D- state are unstable and + // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ), which result in a series of event + // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected + if (_usbd_dev.connected) + { + TU_LOG2(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en); + if (tud_suspend_cb) + tud_suspend_cb(_usbd_dev.remote_wakeup_en); + } + else + { + TU_LOG2(" Skipped\r\n"); + } + break; + + case DCD_EVENT_RESUME: + if (_usbd_dev.connected) + { + TU_LOG2("\r\n"); + if (tud_resume_cb) + tud_resume_cb(); + } + else + { + TU_LOG2(" Skipped\r\n"); + } + break; + + case DCD_EVENT_SOF: + TU_LOG2("\r\n"); + for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++) + { + usbd_class_driver_t const *driver = get_driver(i); + if (driver->sof) + driver->sof(event.rhport); + } + break; + + case USBD_EVENT_FUNC_CALL: + TU_LOG2("\r\n"); + if (event.func_call.func) + event.func_call.func(event.func_call.param); + break; + + default: + TU_BREAKPOINT(); + break; + } + } } //--------------------------------------------------------------------+ @@ -619,483 +619,483 @@ void tud_task(void) // Helper to invoke class driver control request handler static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const *driver, tusb_control_request_t const *request) { - usbd_control_set_complete_callback(driver->control_xfer_cb); - TU_LOG2(" %s control request\r\n", driver->name); - return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request); + usbd_control_set_complete_callback(driver->control_xfer_cb); + TU_LOG2(" %s control request\r\n", driver->name); + return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request); } // This handles the actual request and its response. // return false will cause its caller to stall control endpoint static bool process_control_request(uint8_t rhport, tusb_control_request_t const *p_request) { - usbd_control_set_complete_callback(NULL); + usbd_control_set_complete_callback(NULL); - TU_ASSERT(p_request->bmRequestType_bit.type < TUSB_REQ_TYPE_INVALID); + TU_ASSERT(p_request->bmRequestType_bit.type < TUSB_REQ_TYPE_INVALID); - // Vendor request - if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR) - { - TU_VERIFY(tud_vendor_control_xfer_cb); + // Vendor request + if (p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR) + { + TU_VERIFY(tud_vendor_control_xfer_cb); - usbd_control_set_complete_callback(tud_vendor_control_xfer_cb); - return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request); - } + usbd_control_set_complete_callback(tud_vendor_control_xfer_cb); + return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request); + } #if CFG_TUSB_DEBUG >= 2 - if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME) - { - TU_LOG2(" %s", _tusb_std_request_str[p_request->bRequest]); - if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) - TU_LOG2("\r\n"); - } + if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME) + { + TU_LOG2(" %s", _tusb_std_request_str[p_request->bRequest]); + if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) + TU_LOG2("\r\n"); + } #endif - switch (p_request->bmRequestType_bit.recipient) - { - //------------- Device Requests e.g in enumeration -------------// - case TUSB_REQ_RCPT_DEVICE: - if (TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type) - { - uint8_t const itf = tu_u16_low(p_request->wIndex); - TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv)); - - usbd_class_driver_t const *driver = get_driver(_usbd_dev.itf2drv[itf]); - TU_VERIFY(driver); - - // forward to class driver: "non-STD request to Interface" - return invoke_class_control(rhport, driver, p_request); - } - - if (TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type) - { - // Non standard request is not supported - TU_BREAKPOINT(); - return false; - } - - switch (p_request->bRequest) - { - case TUSB_REQ_SET_ADDRESS: - // Depending on mcu, status phase could be sent either before or after changing device address, - // or even require stack to not response with status at all - // Therefore DCD must take full responsibility to response and include zlp status packet if needed. - usbd_control_set_request(p_request); // set request since DCD has no access to tud_control_status() API - dcd_set_address(rhport, (uint8_t)p_request->wValue); - // skip tud_control_status() - _usbd_dev.addressed = 1; - break; - - case TUSB_REQ_GET_CONFIGURATION: - { - uint8_t cfg_num = _usbd_dev.cfg_num; - tud_control_xfer(rhport, p_request, &cfg_num, 1); - } - break; - - case TUSB_REQ_SET_CONFIGURATION: - { - uint8_t const cfg_num = (uint8_t)p_request->wValue; - - // Only process if new configure is different - if (_usbd_dev.cfg_num != cfg_num) - { - if (_usbd_dev.cfg_num) - { - // already configured: need to clear all endpoints and driver first - TU_LOG(USBD_DBG, " Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num); - - // close all non-control endpoints, cancel all pending transfers if any - dcd_edpt_close_all(rhport); - - // close all drivers and current configured state except bus speed - uint8_t const speed = _usbd_dev.speed; - configuration_reset(rhport); - - _usbd_dev.speed = speed; // restore speed - } - - // switch to new configuration if not zero - if (cfg_num) - TU_ASSERT(process_set_config(rhport, cfg_num)); - } - - _usbd_dev.cfg_num = cfg_num; - tud_control_status(rhport, p_request); - } - break; - - case TUSB_REQ_GET_DESCRIPTOR: - TU_VERIFY(process_get_descriptor(rhport, p_request)); - break; - - case TUSB_REQ_SET_FEATURE: - // Only support remote wakeup for device feature - TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue); - - TU_LOG(USBD_DBG, " Enable Remote Wakeup\r\n"); - - // Host may enable remote wake up before suspending especially HID device - _usbd_dev.remote_wakeup_en = true; - tud_control_status(rhport, p_request); - break; - - case TUSB_REQ_CLEAR_FEATURE: - // Only support remote wakeup for device feature - TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue); - - TU_LOG(USBD_DBG, " Disable Remote Wakeup\r\n"); - - // Host may disable remote wake up after resuming - _usbd_dev.remote_wakeup_en = false; - tud_control_status(rhport, p_request); - break; - - case TUSB_REQ_GET_STATUS: - { - // Device status bit mask - // - Bit 0: Self Powered - // - Bit 1: Remote Wakeup enabled - uint16_t status = (_usbd_dev.self_powered ? 1 : 0) | (_usbd_dev.remote_wakeup_en ? 2 : 0); - tud_control_xfer(rhport, p_request, &status, 2); - } - break; - - // Unknown/Unsupported request - default: - TU_BREAKPOINT(); - return false; - } - break; - - //------------- Class/Interface Specific Request -------------// - case TUSB_REQ_RCPT_INTERFACE: - { - uint8_t const itf = tu_u16_low(p_request->wIndex); - TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv)); - - usbd_class_driver_t const *driver = get_driver(_usbd_dev.itf2drv[itf]); - TU_VERIFY(driver); - - // all requests to Interface (STD or Class) is forwarded to class driver. - // notable requests are: GET HID REPORT DESCRIPTOR, SET_INTERFACE, GET_INTERFACE - if (!invoke_class_control(rhport, driver, p_request)) - { - // For GET_INTERFACE and SET_INTERFACE, it is mandatory to respond even if the class - // driver doesn't use alternate settings or implement this - TU_VERIFY(TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type); - - switch (p_request->bRequest) - { - case TUSB_REQ_GET_INTERFACE: - case TUSB_REQ_SET_INTERFACE: - // Clear complete callback if driver set since it can also stall the request. - usbd_control_set_complete_callback(NULL); - - if (TUSB_REQ_GET_INTERFACE == p_request->bRequest) - { - uint8_t alternate = 0; - tud_control_xfer(rhport, p_request, &alternate, 1); - } - else - { - tud_control_status(rhport, p_request); - } - break; - - default: - return false; - } - } - } - break; - - //------------- Endpoint Request -------------// - case TUSB_REQ_RCPT_ENDPOINT: - { - uint8_t const ep_addr = tu_u16_low(p_request->wIndex); - uint8_t const ep_num = tu_edpt_number(ep_addr); - uint8_t const ep_dir = tu_edpt_dir(ep_addr); - - TU_ASSERT(ep_num < TU_ARRAY_SIZE(_usbd_dev.ep2drv)); - - usbd_class_driver_t const *driver = get_driver(_usbd_dev.ep2drv[ep_num][ep_dir]); - - if (TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type) - { - // Forward class request to its driver - TU_VERIFY(driver); - return invoke_class_control(rhport, driver, p_request); - } - else - { - // Handle STD request to endpoint - switch (p_request->bRequest) - { - case TUSB_REQ_GET_STATUS: - { - uint16_t status = usbd_edpt_stalled(rhport, ep_addr) ? 0x0001 : 0x0000; - tud_control_xfer(rhport, p_request, &status, 2); - } - break; - - case TUSB_REQ_CLEAR_FEATURE: - case TUSB_REQ_SET_FEATURE: - { - if (TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue) - { - if (TUSB_REQ_CLEAR_FEATURE == p_request->bRequest) - { - usbd_edpt_clear_stall(rhport, ep_addr); - } - else - { - usbd_edpt_stall(rhport, ep_addr); - } - } - - if (driver) - { - // Some classes such as USBTMC needs to clear/re-init its buffer when receiving CLEAR_FEATURE request - // We will also forward std request targeted endpoint to class drivers as well - - // STD request must always be ACKed regardless of driver returned value - // Also clear complete callback if driver set since it can also stall the request. - (void)invoke_class_control(rhport, driver, p_request); - usbd_control_set_complete_callback(NULL); - - // skip ZLP status if driver already did that - if (!_usbd_dev.ep_status[0][TUSB_DIR_IN].busy) - tud_control_status(rhport, p_request); - } - } - break; - - // Unknown/Unsupported request - default: - TU_BREAKPOINT(); - return false; - } - } - } - break; - - // Unknown recipient - default: - TU_BREAKPOINT(); - return false; - } - - return true; + switch (p_request->bmRequestType_bit.recipient) + { + //------------- Device Requests e.g in enumeration -------------// + case TUSB_REQ_RCPT_DEVICE: + if (TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type) + { + uint8_t const itf = tu_u16_low(p_request->wIndex); + TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv)); + + usbd_class_driver_t const *driver = get_driver(_usbd_dev.itf2drv[itf]); + TU_VERIFY(driver); + + // forward to class driver: "non-STD request to Interface" + return invoke_class_control(rhport, driver, p_request); + } + + if (TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type) + { + // Non standard request is not supported + TU_BREAKPOINT(); + return false; + } + + switch (p_request->bRequest) + { + case TUSB_REQ_SET_ADDRESS: + // Depending on mcu, status phase could be sent either before or after changing device address, + // or even require stack to not response with status at all + // Therefore DCD must take full responsibility to response and include zlp status packet if needed. + usbd_control_set_request(p_request); // set request since DCD has no access to tud_control_status() API + dcd_set_address(rhport, (uint8_t)p_request->wValue); + // skip tud_control_status() + _usbd_dev.addressed = 1; + break; + + case TUSB_REQ_GET_CONFIGURATION: + { + uint8_t cfg_num = _usbd_dev.cfg_num; + tud_control_xfer(rhport, p_request, &cfg_num, 1); + } + break; + + case TUSB_REQ_SET_CONFIGURATION: + { + uint8_t const cfg_num = (uint8_t)p_request->wValue; + + // Only process if new configure is different + if (_usbd_dev.cfg_num != cfg_num) + { + if (_usbd_dev.cfg_num) + { + // already configured: need to clear all endpoints and driver first + TU_LOG(USBD_DBG, " Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num); + + // close all non-control endpoints, cancel all pending transfers if any + dcd_edpt_close_all(rhport); + + // close all drivers and current configured state except bus speed + uint8_t const speed = _usbd_dev.speed; + configuration_reset(rhport); + + _usbd_dev.speed = speed; // restore speed + } + + // switch to new configuration if not zero + if (cfg_num) + TU_ASSERT(process_set_config(rhport, cfg_num)); + } + + _usbd_dev.cfg_num = cfg_num; + tud_control_status(rhport, p_request); + } + break; + + case TUSB_REQ_GET_DESCRIPTOR: + TU_VERIFY(process_get_descriptor(rhport, p_request)); + break; + + case TUSB_REQ_SET_FEATURE: + // Only support remote wakeup for device feature + TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue); + + TU_LOG(USBD_DBG, " Enable Remote Wakeup\r\n"); + + // Host may enable remote wake up before suspending especially HID device + _usbd_dev.remote_wakeup_en = true; + tud_control_status(rhport, p_request); + break; + + case TUSB_REQ_CLEAR_FEATURE: + // Only support remote wakeup for device feature + TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue); + + TU_LOG(USBD_DBG, " Disable Remote Wakeup\r\n"); + + // Host may disable remote wake up after resuming + _usbd_dev.remote_wakeup_en = false; + tud_control_status(rhport, p_request); + break; + + case TUSB_REQ_GET_STATUS: + { + // Device status bit mask + // - Bit 0: Self Powered + // - Bit 1: Remote Wakeup enabled + uint16_t status = (_usbd_dev.self_powered ? 1 : 0) | (_usbd_dev.remote_wakeup_en ? 2 : 0); + tud_control_xfer(rhport, p_request, &status, 2); + } + break; + + // Unknown/Unsupported request + default: + TU_BREAKPOINT(); + return false; + } + break; + + //------------- Class/Interface Specific Request -------------// + case TUSB_REQ_RCPT_INTERFACE: + { + uint8_t const itf = tu_u16_low(p_request->wIndex); + TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv)); + + usbd_class_driver_t const *driver = get_driver(_usbd_dev.itf2drv[itf]); + TU_VERIFY(driver); + + // all requests to Interface (STD or Class) is forwarded to class driver. + // notable requests are: GET HID REPORT DESCRIPTOR, SET_INTERFACE, GET_INTERFACE + if (!invoke_class_control(rhport, driver, p_request)) + { + // For GET_INTERFACE and SET_INTERFACE, it is mandatory to respond even if the class + // driver doesn't use alternate settings or implement this + TU_VERIFY(TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type); + + switch (p_request->bRequest) + { + case TUSB_REQ_GET_INTERFACE: + case TUSB_REQ_SET_INTERFACE: + // Clear complete callback if driver set since it can also stall the request. + usbd_control_set_complete_callback(NULL); + + if (TUSB_REQ_GET_INTERFACE == p_request->bRequest) + { + uint8_t alternate = 0; + tud_control_xfer(rhport, p_request, &alternate, 1); + } + else + { + tud_control_status(rhport, p_request); + } + break; + + default: + return false; + } + } + } + break; + + //------------- Endpoint Request -------------// + case TUSB_REQ_RCPT_ENDPOINT: + { + uint8_t const ep_addr = tu_u16_low(p_request->wIndex); + uint8_t const ep_num = tu_edpt_number(ep_addr); + uint8_t const ep_dir = tu_edpt_dir(ep_addr); + + TU_ASSERT(ep_num < TU_ARRAY_SIZE(_usbd_dev.ep2drv)); + + usbd_class_driver_t const *driver = get_driver(_usbd_dev.ep2drv[ep_num][ep_dir]); + + if (TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type) + { + // Forward class request to its driver + TU_VERIFY(driver); + return invoke_class_control(rhport, driver, p_request); + } + else + { + // Handle STD request to endpoint + switch (p_request->bRequest) + { + case TUSB_REQ_GET_STATUS: + { + uint16_t status = usbd_edpt_stalled(rhport, ep_addr) ? 0x0001 : 0x0000; + tud_control_xfer(rhport, p_request, &status, 2); + } + break; + + case TUSB_REQ_CLEAR_FEATURE: + case TUSB_REQ_SET_FEATURE: + { + if (TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue) + { + if (TUSB_REQ_CLEAR_FEATURE == p_request->bRequest) + { + usbd_edpt_clear_stall(rhport, ep_addr); + } + else + { + usbd_edpt_stall(rhport, ep_addr); + } + } + + if (driver) + { + // Some classes such as USBTMC needs to clear/re-init its buffer when receiving CLEAR_FEATURE request + // We will also forward std request targeted endpoint to class drivers as well + + // STD request must always be ACKed regardless of driver returned value + // Also clear complete callback if driver set since it can also stall the request. + (void)invoke_class_control(rhport, driver, p_request); + usbd_control_set_complete_callback(NULL); + + // skip ZLP status if driver already did that + if (!_usbd_dev.ep_status[0][TUSB_DIR_IN].busy) + tud_control_status(rhport, p_request); + } + } + break; + + // Unknown/Unsupported request + default: + TU_BREAKPOINT(); + return false; + } + } + } + break; + + // Unknown recipient + default: + TU_BREAKPOINT(); + return false; + } + + return true; } // Process Set Configure Request // This function parse configuration descriptor & open drivers accordingly static bool process_set_config(uint8_t rhport, uint8_t cfg_num) { - // index is cfg_num-1 - tusb_desc_configuration_t const *desc_cfg = (tusb_desc_configuration_t const *)tud_descriptor_configuration_cb(cfg_num - 1); - TU_ASSERT(desc_cfg != NULL && desc_cfg->bDescriptorType == TUSB_DESC_CONFIGURATION); - - // Parse configuration descriptor - _usbd_dev.remote_wakeup_support = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP) ? 1 : 0; - _usbd_dev.self_powered = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_SELF_POWERED) ? 1 : 0; - - // Parse interface descriptor - uint8_t const *p_desc = ((uint8_t const *)desc_cfg) + sizeof(tusb_desc_configuration_t); - uint8_t const *desc_end = ((uint8_t const *)desc_cfg) + tu_le16toh(desc_cfg->wTotalLength); - - while (p_desc < desc_end) - { - uint8_t assoc_itf_count = 1; - - // Class will always starts with Interface Association (if any) and then Interface descriptor - if (TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc)) - { - tusb_desc_interface_assoc_t const *desc_iad = (tusb_desc_interface_assoc_t const *)p_desc; - assoc_itf_count = desc_iad->bInterfaceCount; - - p_desc = tu_desc_next(p_desc); // next to Interface - - // IAD's first interface number and class should match with opened interface - // TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber && - // desc_iad->bFunctionClass == desc_itf->bInterfaceClass); - } - - TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc)); - tusb_desc_interface_t const *desc_itf = (tusb_desc_interface_t const *)p_desc; - - // Find driver for this interface - uint16_t const remaining_len = desc_end - p_desc; - uint8_t drv_id; - for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) - { - usbd_class_driver_t const *driver = get_driver(drv_id); - uint16_t const drv_len = driver->open(rhport, desc_itf, remaining_len); - - if ((sizeof(tusb_desc_interface_t) <= drv_len) && (drv_len <= remaining_len)) - { - // Open successfully - TU_LOG2(" %s opened\r\n", driver->name); - - // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or - // BTH (even CDC) with class in device descriptor (single interface) - if (assoc_itf_count == 1) - { + // index is cfg_num-1 + tusb_desc_configuration_t const *desc_cfg = (tusb_desc_configuration_t const *)tud_descriptor_configuration_cb(cfg_num - 1); + TU_ASSERT(desc_cfg != NULL && desc_cfg->bDescriptorType == TUSB_DESC_CONFIGURATION); + + // Parse configuration descriptor + _usbd_dev.remote_wakeup_support = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP) ? 1 : 0; + _usbd_dev.self_powered = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_SELF_POWERED) ? 1 : 0; + + // Parse interface descriptor + uint8_t const *p_desc = ((uint8_t const *)desc_cfg) + sizeof(tusb_desc_configuration_t); + uint8_t const *desc_end = ((uint8_t const *)desc_cfg) + tu_le16toh(desc_cfg->wTotalLength); + + while (p_desc < desc_end) + { + uint8_t assoc_itf_count = 1; + + // Class will always starts with Interface Association (if any) and then Interface descriptor + if (TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc)) + { + tusb_desc_interface_assoc_t const *desc_iad = (tusb_desc_interface_assoc_t const *)p_desc; + assoc_itf_count = desc_iad->bInterfaceCount; + + p_desc = tu_desc_next(p_desc); // next to Interface + + // IAD's first interface number and class should match with opened interface + // TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber && + // desc_iad->bFunctionClass == desc_itf->bInterfaceClass); + } + + TU_ASSERT(TUSB_DESC_INTERFACE == tu_desc_type(p_desc)); + tusb_desc_interface_t const *desc_itf = (tusb_desc_interface_t const *)p_desc; + + // Find driver for this interface + uint16_t const remaining_len = desc_end - p_desc; + uint8_t drv_id; + for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) + { + usbd_class_driver_t const *driver = get_driver(drv_id); + uint16_t const drv_len = driver->open(rhport, desc_itf, remaining_len); + + if ((sizeof(tusb_desc_interface_t) <= drv_len) && (drv_len <= remaining_len)) + { + // Open successfully + TU_LOG2(" %s opened\r\n", driver->name); + + // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or + // BTH (even CDC) with class in device descriptor (single interface) + if (assoc_itf_count == 1) + { #if CFG_TUD_CDC - if (driver->open == cdcd_open) - assoc_itf_count = 2; + if (driver->open == cdcd_open) + assoc_itf_count = 2; #endif #if CFG_TUD_MIDI - if (driver->open == midid_open) - assoc_itf_count = 2; + if (driver->open == midid_open) + assoc_itf_count = 2; #endif #if CFG_TUD_BTH && CFG_TUD_BTH_ISO_ALT_COUNT - if (driver->open == btd_open) - assoc_itf_count = 2; + if (driver->open == btd_open) + assoc_itf_count = 2; #endif - } + } - // bind (associated) interfaces to found driver - for (uint8_t i = 0; i < assoc_itf_count; i++) - { - uint8_t const itf_num = desc_itf->bInterfaceNumber + i; + // bind (associated) interfaces to found driver + for (uint8_t i = 0; i < assoc_itf_count; i++) + { + uint8_t const itf_num = desc_itf->bInterfaceNumber + i; - // Interface number must not be used already - TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[itf_num]); - _usbd_dev.itf2drv[itf_num] = drv_id; - } + // Interface number must not be used already + TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[itf_num]); + _usbd_dev.itf2drv[itf_num] = drv_id; + } - // bind all endpoints to found driver - tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id); + // bind all endpoints to found driver + tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id); - // next Interface - p_desc += drv_len; + // next Interface + p_desc += drv_len; - break; // exit driver find loop - } - } + break; // exit driver find loop + } + } - // Failed if there is no supported drivers - TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT); - } + // Failed if there is no supported drivers + TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT); + } - // invoke callback - if (tud_mount_cb) - tud_mount_cb(); + // invoke callback + if (tud_mount_cb) + tud_mount_cb(); - return true; + return true; } // return descriptor's buffer and update desc_len static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const *p_request) { - tusb_desc_type_t const desc_type = (tusb_desc_type_t)tu_u16_high(p_request->wValue); - uint8_t const desc_index = tu_u16_low(p_request->wValue); - - switch (desc_type) - { - case TUSB_DESC_DEVICE: - { - TU_LOG2(" Device\r\n"); - - void *desc_device = (void *)(uintptr_t)tud_descriptor_device_cb(); - - // Only response with exactly 1 Packet if: not addressed and host requested more data than device descriptor has. - // This only happens with the very first get device descriptor and EP0 size = 8 or 16. - if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed && - ((tusb_control_request_t const *)p_request)->wLength > sizeof(tusb_desc_device_t)) - { - // Hack here: we modify the request length to prevent usbd_control response with zlp - // since we are responding with 1 packet & less data than wLength. - tusb_control_request_t mod_request = *p_request; - mod_request.wLength = CFG_TUD_ENDPOINT0_SIZE; - - return tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE); - } - else - { - return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t)); - } - } - break; - - case TUSB_DESC_BOS: - { - TU_LOG2(" BOS\r\n"); - - // requested by host if USB > 2.0 ( i.e 2.1 or 3.x ) - if (!tud_descriptor_bos_cb) - return false; - - uintptr_t desc_bos = (uintptr_t)tud_descriptor_bos_cb(); - TU_ASSERT(desc_bos); - - // Use offsetof to avoid pointer to the odd/misaligned address - uint16_t const total_len = tu_le16toh(tu_unaligned_read16((const void *)(desc_bos + offsetof(tusb_desc_bos_t, wTotalLength)))); - - return tud_control_xfer(rhport, p_request, (void *)desc_bos, total_len); - } - break; - - case TUSB_DESC_CONFIGURATION: - case TUSB_DESC_OTHER_SPEED_CONFIG: - { - uintptr_t desc_config; - - if (desc_type == TUSB_DESC_CONFIGURATION) - { - TU_LOG2(" Configuration[%u]\r\n", desc_index); - desc_config = (uintptr_t)tud_descriptor_configuration_cb(desc_index); - } - else - { - // Host only request this after getting Device Qualifier descriptor - TU_LOG2(" Other Speed Configuration\r\n"); - TU_VERIFY(tud_descriptor_other_speed_configuration_cb); - desc_config = (uintptr_t)tud_descriptor_other_speed_configuration_cb(desc_index); - } - - TU_ASSERT(desc_config); - - // Use offsetof to avoid pointer to the odd/misaligned address - uint16_t const total_len = tu_le16toh(tu_unaligned_read16((const void *)(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)))); - - return tud_control_xfer(rhport, p_request, (void *)desc_config, total_len); - } - break; - - case TUSB_DESC_STRING: - { - TU_LOG2(" String[%u]\r\n", desc_index); - - // String Descriptor always uses the desc set from user - uint8_t const *desc_str = (uint8_t const *)tud_descriptor_string_cb(desc_index, tu_le16toh(p_request->wIndex)); - TU_VERIFY(desc_str); - - // first byte of descriptor is its size - return tud_control_xfer(rhport, p_request, (void *)(uintptr_t)desc_str, tu_desc_len(desc_str)); - } - break; - - case TUSB_DESC_DEVICE_QUALIFIER: - { - TU_LOG2(" Device Qualifier\r\n"); - - TU_VERIFY(tud_descriptor_device_qualifier_cb); - - uint8_t const *desc_qualifier = tud_descriptor_device_qualifier_cb(); - TU_VERIFY(desc_qualifier); - - // first byte of descriptor is its size - return tud_control_xfer(rhport, p_request, (void *)(uintptr_t)desc_qualifier, tu_desc_len(desc_qualifier)); - } - break; - - default: - return false; - } + tusb_desc_type_t const desc_type = (tusb_desc_type_t)tu_u16_high(p_request->wValue); + uint8_t const desc_index = tu_u16_low(p_request->wValue); + + switch (desc_type) + { + case TUSB_DESC_DEVICE: + { + TU_LOG2(" Device\r\n"); + + void *desc_device = (void *)(uintptr_t)tud_descriptor_device_cb(); + + // Only response with exactly 1 Packet if: not addressed and host requested more data than device descriptor has. + // This only happens with the very first get device descriptor and EP0 size = 8 or 16. + if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed && + ((tusb_control_request_t const *)p_request)->wLength > sizeof(tusb_desc_device_t)) + { + // Hack here: we modify the request length to prevent usbd_control response with zlp + // since we are responding with 1 packet & less data than wLength. + tusb_control_request_t mod_request = *p_request; + mod_request.wLength = CFG_TUD_ENDPOINT0_SIZE; + + return tud_control_xfer(rhport, &mod_request, desc_device, CFG_TUD_ENDPOINT0_SIZE); + } + else + { + return tud_control_xfer(rhport, p_request, desc_device, sizeof(tusb_desc_device_t)); + } + } + // break; // unreachable + + case TUSB_DESC_BOS: + { + TU_LOG2(" BOS\r\n"); + + // requested by host if USB > 2.0 ( i.e 2.1 or 3.x ) + if (!tud_descriptor_bos_cb) + return false; + + uintptr_t desc_bos = (uintptr_t)tud_descriptor_bos_cb(); + TU_ASSERT(desc_bos); + + // Use offsetof to avoid pointer to the odd/misaligned address + uint16_t const total_len = tu_le16toh(tu_unaligned_read16((const void *)(desc_bos + offsetof(tusb_desc_bos_t, wTotalLength)))); + + return tud_control_xfer(rhport, p_request, (void *)desc_bos, total_len); + } + // break; // unreachable + + case TUSB_DESC_CONFIGURATION: + case TUSB_DESC_OTHER_SPEED_CONFIG: + { + uintptr_t desc_config; + + if (desc_type == TUSB_DESC_CONFIGURATION) + { + TU_LOG2(" Configuration[%u]\r\n", desc_index); + desc_config = (uintptr_t)tud_descriptor_configuration_cb(desc_index); + } + else + { + // Host only request this after getting Device Qualifier descriptor + TU_LOG2(" Other Speed Configuration\r\n"); + TU_VERIFY(tud_descriptor_other_speed_configuration_cb); + desc_config = (uintptr_t)tud_descriptor_other_speed_configuration_cb(desc_index); + } + + TU_ASSERT(desc_config); + + // Use offsetof to avoid pointer to the odd/misaligned address + uint16_t const total_len = tu_le16toh(tu_unaligned_read16((const void *)(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)))); + + return tud_control_xfer(rhport, p_request, (void *)desc_config, total_len); + } + // break; // unreachable + + case TUSB_DESC_STRING: + { + TU_LOG2(" String[%u]\r\n", desc_index); + + // String Descriptor always uses the desc set from user + uint8_t const *desc_str = (uint8_t const *)tud_descriptor_string_cb(desc_index, tu_le16toh(p_request->wIndex)); + TU_VERIFY(desc_str); + + // first byte of descriptor is its size + return tud_control_xfer(rhport, p_request, (void *)(uintptr_t)desc_str, tu_desc_len(desc_str)); + } + // break; // unreachable + + case TUSB_DESC_DEVICE_QUALIFIER: + { + TU_LOG2(" Device Qualifier\r\n"); + + TU_VERIFY(tud_descriptor_device_qualifier_cb); + + uint8_t const *desc_qualifier = tud_descriptor_device_qualifier_cb(); + TU_VERIFY(desc_qualifier); + + // first byte of descriptor is its size + return tud_control_xfer(rhport, p_request, (void *)(uintptr_t)desc_qualifier, tu_desc_len(desc_qualifier)); + } + // break; // unreachable + + default: + return false; + } } //--------------------------------------------------------------------+ @@ -1103,84 +1103,84 @@ static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const //--------------------------------------------------------------------+ void dcd_event_handler(dcd_event_t const *event, bool in_isr) { - switch (event->event_id) - { - case DCD_EVENT_UNPLUGGED: - _usbd_dev.connected = 0; - _usbd_dev.addressed = 0; - _usbd_dev.cfg_num = 0; - _usbd_dev.suspended = 0; - osal_queue_send(_usbd_q, event, in_isr); - break; - - case DCD_EVENT_SUSPEND: - // NOTE: When plugging/unplugging device, the D+/D- state are unstable and - // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ). - // In addition, some MCUs such as SAMD or boards that haven no VBUS detection cannot distinguish - // suspended vs disconnected. We will skip handling SUSPEND/RESUME event if not currently connected - if (_usbd_dev.connected) - { - _usbd_dev.suspended = 1; - osal_queue_send(_usbd_q, event, in_isr); - } - break; - - case DCD_EVENT_RESUME: - // skip event if not connected (especially required for SAMD) - if (_usbd_dev.connected) - { - _usbd_dev.suspended = 0; - osal_queue_send(_usbd_q, event, in_isr); - } - break; - - case DCD_EVENT_SOF: - // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup - // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational - if (_usbd_dev.suspended) - { - _usbd_dev.suspended = 0; - dcd_event_t const event_resume = {.rhport = event->rhport, .event_id = DCD_EVENT_RESUME}; - osal_queue_send(_usbd_q, &event_resume, in_isr); - } - break; - - default: - osal_queue_send(_usbd_q, event, in_isr); - break; - } + switch (event->event_id) + { + case DCD_EVENT_UNPLUGGED: + _usbd_dev.connected = 0; + _usbd_dev.addressed = 0; + _usbd_dev.cfg_num = 0; + _usbd_dev.suspended = 0; + osal_queue_send(_usbd_q, event, in_isr); + break; + + case DCD_EVENT_SUSPEND: + // NOTE: When plugging/unplugging device, the D+/D- state are unstable and + // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ). + // In addition, some MCUs such as SAMD or boards that haven no VBUS detection cannot distinguish + // suspended vs disconnected. We will skip handling SUSPEND/RESUME event if not currently connected + if (_usbd_dev.connected) + { + _usbd_dev.suspended = 1; + osal_queue_send(_usbd_q, event, in_isr); + } + break; + + case DCD_EVENT_RESUME: + // skip event if not connected (especially required for SAMD) + if (_usbd_dev.connected) + { + _usbd_dev.suspended = 0; + osal_queue_send(_usbd_q, event, in_isr); + } + break; + + case DCD_EVENT_SOF: + // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup + // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational + if (_usbd_dev.suspended) + { + _usbd_dev.suspended = 0; + dcd_event_t const event_resume = {.rhport = event->rhport, .event_id = DCD_EVENT_RESUME}; + osal_queue_send(_usbd_q, &event_resume, in_isr); + } + break; + + default: + osal_queue_send(_usbd_q, event, in_isr); + break; + } } void dcd_event_bus_signal(uint8_t rhport, dcd_eventid_t eid, bool in_isr) { - dcd_event_t event = {.rhport = rhport, .event_id = eid}; - dcd_event_handler(&event, in_isr); + dcd_event_t event = {.rhport = rhport, .event_id = eid}; + dcd_event_handler(&event, in_isr); } void dcd_event_bus_reset(uint8_t rhport, tusb_speed_t speed, bool in_isr) { - dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_BUS_RESET}; - event.bus_reset.speed = speed; - dcd_event_handler(&event, in_isr); + dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_BUS_RESET}; + event.bus_reset.speed = speed; + dcd_event_handler(&event, in_isr); } void dcd_event_setup_received(uint8_t rhport, uint8_t const *setup, bool in_isr) { - dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED}; - memcpy(&event.setup_received, setup, 8); + dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED}; + memcpy(&event.setup_received, setup, 8); - dcd_event_handler(&event, in_isr); + dcd_event_handler(&event, in_isr); } void dcd_event_xfer_complete(uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr) { - dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE}; + dcd_event_t event = {.rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE}; - event.xfer_complete.ep_addr = ep_addr; - event.xfer_complete.len = xferred_bytes; - event.xfer_complete.result = result; + event.xfer_complete.ep_addr = ep_addr; + event.xfer_complete.len = xferred_bytes; + event.xfer_complete.result = result; - dcd_event_handler(&event, in_isr); + dcd_event_handler(&event, in_isr); } //--------------------------------------------------------------------+ @@ -1190,41 +1190,41 @@ void dcd_event_xfer_complete(uint8_t rhport, uint8_t ep_addr, uint32_t xferred_b // Parse consecutive endpoint descriptors (IN & OUT) bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const *p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t *ep_out, uint8_t *ep_in) { - for (int i = 0; i < ep_count; i++) - { - tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *)p_desc; - - TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && xfer_type == desc_ep->bmAttributes.xfer); - TU_ASSERT(usbd_edpt_open(rhport, desc_ep)); - - if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) - { - (*ep_in) = desc_ep->bEndpointAddress; - } - else - { - (*ep_out) = desc_ep->bEndpointAddress; - } - - p_desc = tu_desc_next(p_desc); - } - - return true; + for (int i = 0; i < ep_count; i++) + { + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *)p_desc; + + TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && xfer_type == desc_ep->bmAttributes.xfer); + TU_ASSERT(usbd_edpt_open(rhport, desc_ep)); + + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) + { + (*ep_in) = desc_ep->bEndpointAddress; + } + else + { + (*ep_out) = desc_ep->bEndpointAddress; + } + + p_desc = tu_desc_next(p_desc); + } + + return true; } // Helper to defer an isr function void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr) { - dcd_event_t event = - { - .rhport = 0, - .event_id = USBD_EVENT_FUNC_CALL, - }; + dcd_event_t event = + { + .rhport = 0, + .event_id = USBD_EVENT_FUNC_CALL, + }; - event.func_call.func = func; - event.func_call.param = param; + event.func_call.func = func; + event.func_call.param = param; - dcd_event_handler(&event, in_isr); + dcd_event_handler(&event, in_isr); } //--------------------------------------------------------------------+ @@ -1233,97 +1233,97 @@ void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr) bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) { - TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX); - TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t)_usbd_dev.speed)); + TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX); + TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t)_usbd_dev.speed)); - return dcd_edpt_open(rhport, desc_ep); + return dcd_edpt_open(rhport, desc_ep); } bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; + (void)rhport; - // TODO add this check later, also make sure we don't starve an out endpoint while suspending - // TU_VERIFY(tud_ready()); + // TODO add this check later, also make sure we don't starve an out endpoint while suspending + // TU_VERIFY(tud_ready()); - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); #if CFG_TUSB_OS != OPT_OS_NONE - // pre-check to help reducing mutex lock - TU_VERIFY((_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0)); - osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + // pre-check to help reducing mutex lock + TU_VERIFY((_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0)); + osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER); #endif - // can only claim the endpoint if it is not busy and not claimed yet. - bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0); - if (ret) - { - _usbd_dev.ep_status[epnum][dir].claimed = 1; - } + // can only claim the endpoint if it is not busy and not claimed yet. + bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0); + if (ret) + { + _usbd_dev.ep_status[epnum][dir].claimed = 1; + } #if CFG_TUSB_OS != OPT_OS_NONE - osal_mutex_unlock(_usbd_mutex); + osal_mutex_unlock(_usbd_mutex); #endif - return ret; + return ret; } bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; + (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); #if CFG_TUSB_OS != OPT_OS_NONE - osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER); #endif - // can only release the endpoint if it is claimed and not busy - bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 1); - if (ret) - { - _usbd_dev.ep_status[epnum][dir].claimed = 0; - } + // can only release the endpoint if it is claimed and not busy + bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 1); + if (ret) + { + _usbd_dev.ep_status[epnum][dir].claimed = 0; + } #if CFG_TUSB_OS != OPT_OS_NONE - osal_mutex_unlock(_usbd_mutex); + osal_mutex_unlock(_usbd_mutex); #endif - return ret; + return ret; } bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - // TODO skip ready() check for now since enumeration also use this API - // TU_VERIFY(tud_ready()); - - TU_LOG2(" Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes); - - // Attempt to transfer on a busy endpoint, sound like an race condition ! - TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0); - - // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() - // could return and USBD task can preempt and clear the busy - _usbd_dev.ep_status[epnum][dir].busy = true; - - if (dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes)) - { - return true; - } - else - { - // DCD error, mark endpoint as ready to allow next transfer - _usbd_dev.ep_status[epnum][dir].busy = false; - _usbd_dev.ep_status[epnum][dir].claimed = 0; - TU_LOG2("FAILED\r\n"); - TU_BREAKPOINT(); - return false; - } + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + // TODO skip ready() check for now since enumeration also use this API + // TU_VERIFY(tud_ready()); + + TU_LOG2(" Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes); + + // Attempt to transfer on a busy endpoint, sound like an race condition ! + TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0); + + // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() + // could return and USBD task can preempt and clear the busy + _usbd_dev.ep_status[epnum][dir].busy = true; + + if (dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes)) + { + return true; + } + else + { + // DCD error, mark endpoint as ready to allow next transfer + _usbd_dev.ep_status[epnum][dir].busy = false; + _usbd_dev.ep_status[epnum][dir].claimed = 0; + TU_LOG2("FAILED\r\n"); + TU_BREAKPOINT(); + return false; + } } // The number of bytes has to be given explicitly to allow more flexible control of how many @@ -1332,83 +1332,83 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t t // into the USB buffer! bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) { - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - TU_LOG2(" Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes); - - // Attempt to transfer on a busy endpoint, sound like an race condition ! - TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0); - - // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() could return - // and usbd task can preempt and clear the busy - _usbd_dev.ep_status[epnum][dir].busy = true; - - if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes)) - { - TU_LOG2("OK\r\n"); - return true; - } - else - { - // DCD error, mark endpoint as ready to allow next transfer - _usbd_dev.ep_status[epnum][dir].busy = false; - _usbd_dev.ep_status[epnum][dir].claimed = 0; - TU_LOG2("failed\r\n"); - TU_BREAKPOINT(); - return false; - } + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + TU_LOG2(" Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes); + + // Attempt to transfer on a busy endpoint, sound like an race condition ! + TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0); + + // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() could return + // and usbd task can preempt and clear the busy + _usbd_dev.ep_status[epnum][dir].busy = true; + + if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes)) + { + TU_LOG2("OK\r\n"); + return true; + } + else + { + // DCD error, mark endpoint as ready to allow next transfer + _usbd_dev.ep_status[epnum][dir].busy = false; + _usbd_dev.ep_status[epnum][dir].claimed = 0; + TU_LOG2("failed\r\n"); + TU_BREAKPOINT(); + return false; + } } bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; + (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - return _usbd_dev.ep_status[epnum][dir].busy; + return _usbd_dev.ep_status[epnum][dir].busy; } void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - // only stalled if currently cleared - if (!_usbd_dev.ep_status[epnum][dir].stalled) - { - TU_LOG(USBD_DBG, " Stall EP %02X\r\n", ep_addr); - dcd_edpt_stall(rhport, ep_addr); - _usbd_dev.ep_status[epnum][dir].stalled = true; - _usbd_dev.ep_status[epnum][dir].busy = true; - } + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + // only stalled if currently cleared + if (!_usbd_dev.ep_status[epnum][dir].stalled) + { + TU_LOG(USBD_DBG, " Stall EP %02X\r\n", ep_addr); + dcd_edpt_stall(rhport, ep_addr); + _usbd_dev.ep_status[epnum][dir].stalled = true; + _usbd_dev.ep_status[epnum][dir].busy = true; + } } void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - // only clear if currently stalled - if (_usbd_dev.ep_status[epnum][dir].stalled) - { - TU_LOG(USBD_DBG, " Clear Stall EP %02X\r\n", ep_addr); - dcd_edpt_clear_stall(rhport, ep_addr); - _usbd_dev.ep_status[epnum][dir].stalled = false; - _usbd_dev.ep_status[epnum][dir].busy = false; - } + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + // only clear if currently stalled + if (_usbd_dev.ep_status[epnum][dir].stalled) + { + TU_LOG(USBD_DBG, " Clear Stall EP %02X\r\n", ep_addr); + dcd_edpt_clear_stall(rhport, ep_addr); + _usbd_dev.ep_status[epnum][dir].stalled = false; + _usbd_dev.ep_status[epnum][dir].busy = false; + } } bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; + (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - return _usbd_dev.ep_status[epnum][dir].stalled; + return _usbd_dev.ep_status[epnum][dir].stalled; } /** @@ -1419,18 +1419,18 @@ bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) */ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - TU_ASSERT(dcd_edpt_close, /**/); - TU_LOG2(" CLOSING Endpoint: 0x%02X\r\n", ep_addr); + TU_ASSERT(dcd_edpt_close, /**/); + TU_LOG2(" CLOSING Endpoint: 0x%02X\r\n", ep_addr); - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - dcd_edpt_close(rhport, ep_addr); - _usbd_dev.ep_status[epnum][dir].stalled = false; - _usbd_dev.ep_status[epnum][dir].busy = false; - _usbd_dev.ep_status[epnum][dir].claimed = false; + dcd_edpt_close(rhport, ep_addr); + _usbd_dev.ep_status[epnum][dir].stalled = false; + _usbd_dev.ep_status[epnum][dir].busy = false; + _usbd_dev.ep_status[epnum][dir].claimed = false; - return; + return; } #endif diff --git a/uCNC/src/tinyusb/src/device/usbd.h b/uCNC/src/tinyusb/src/device/usbd.h index b5345790d..2690e3e69 100644 --- a/uCNC/src/tinyusb/src/device/usbd.h +++ b/uCNC/src/tinyusb/src/device/usbd.h @@ -30,264 +30,288 @@ #include "../common/tusb_common.h" #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - //--------------------------------------------------------------------+ - // Application API - //--------------------------------------------------------------------+ +//--------------------------------------------------------------------+ +// Application API +//--------------------------------------------------------------------+ - // Init device stack - bool tud_init(uint8_t rhport); +// Init device stack +bool tud_init (uint8_t rhport); - // Check if device stack is already initialized - bool tud_inited(void); +// Check if device stack is already initialized +bool tud_inited(void); - // Task function should be called in main/rtos loop - void tud_task(void); +// Task function should be called in main/rtos loop +void tud_task (void); - // Check if there is pending events need proccessing by tud_task() - bool tud_task_event_ready(void); +// Check if there is pending events need proccessing by tud_task() +bool tud_task_event_ready(void); - // Interrupt handler, name alias to DCD - extern void dcd_int_handler(uint8_t rhport); -#define tud_int_handler dcd_int_handler +// Interrupt handler, name alias to DCD +extern void dcd_int_handler(uint8_t rhport); +#define tud_int_handler dcd_int_handler - // Get current bus speed - tusb_speed_t tud_speed_get(void); +// Get current bus speed +tusb_speed_t tud_speed_get(void); - // Check if device is connected (may not mounted/configured yet) - // True if just got out of Bus Reset and received the very first data from host - bool tud_connected(void); +// Check if device is connected (may not mounted/configured yet) +// True if just got out of Bus Reset and received the very first data from host +bool tud_connected(void); - // Check if device is connected and configured - bool tud_mounted(void); +// Check if device is connected and configured +bool tud_mounted(void); - // Check if device is suspended - bool tud_suspended(void); +// Check if device is suspended +bool tud_suspended(void); - // Check if device is ready to transfer - TU_ATTR_ALWAYS_INLINE static inline bool tud_ready(void) - { - return tud_mounted() && !tud_suspended(); - } +// Check if device is ready to transfer +TU_ATTR_ALWAYS_INLINE static inline +bool tud_ready(void) +{ + return tud_mounted() && !tud_suspended(); +} - // Remote wake up host, only if suspended and enabled by host - bool tud_remote_wakeup(void); +// Remote wake up host, only if suspended and enabled by host +bool tud_remote_wakeup(void); - // Enable pull-up resistor on D+ D- - // Return false on unsupported MCUs - bool tud_disconnect(void); +// Enable pull-up resistor on D+ D- +// Return false on unsupported MCUs +bool tud_disconnect(void); - // Disable pull-up resistor on D+ D- - // Return false on unsupported MCUs - bool tud_connect(void); +// Disable pull-up resistor on D+ D- +// Return false on unsupported MCUs +bool tud_connect(void); - // Carry out Data and Status stage of control transfer - // - If len = 0, it is equivalent to sending status only - // - If len > wLength : it will be truncated - bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const *request, void *buffer, uint16_t len); +// Carry out Data and Status stage of control transfer +// - If len = 0, it is equivalent to sending status only +// - If len > wLength : it will be truncated +bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, void* buffer, uint16_t len); - // Send STATUS (zero length) packet - bool tud_control_status(uint8_t rhport, tusb_control_request_t const *request); +// Send STATUS (zero length) packet +bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request); - //--------------------------------------------------------------------+ - // Application Callbacks (WEAK is optional) - //--------------------------------------------------------------------+ +//--------------------------------------------------------------------+ +// Application Callbacks (WEAK is optional) +//--------------------------------------------------------------------+ - // Invoked when received GET DEVICE DESCRIPTOR request - // Application return pointer to descriptor - uint8_t const *tud_descriptor_device_cb(void); +// Invoked when received GET DEVICE DESCRIPTOR request +// Application return pointer to descriptor +uint8_t const * tud_descriptor_device_cb(void); - // Invoked when received GET CONFIGURATION DESCRIPTOR request - // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete - uint8_t const *tud_descriptor_configuration_cb(uint8_t index); +// Invoked when received GET CONFIGURATION DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint8_t const * tud_descriptor_configuration_cb(uint8_t index); - // Invoked when received GET STRING DESCRIPTOR request - // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete - uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid); +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid); - // Invoked when received GET BOS DESCRIPTOR request - // Application return pointer to descriptor - TU_ATTR_WEAK uint8_t const *tud_descriptor_bos_cb(void); +// Invoked when received GET BOS DESCRIPTOR request +// Application return pointer to descriptor +TU_ATTR_WEAK uint8_t const * tud_descriptor_bos_cb(void); - // Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request - // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete. - // device_qualifier descriptor describes information about a high-speed capable device that would - // change if the device were operating at the other speed. If not highspeed capable stall this request. - TU_ATTR_WEAK uint8_t const *tud_descriptor_device_qualifier_cb(void); +// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete. +// device_qualifier descriptor describes information about a high-speed capable device that would +// change if the device were operating at the other speed. If not highspeed capable stall this request. +TU_ATTR_WEAK uint8_t const* tud_descriptor_device_qualifier_cb(void); - // Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request - // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete - // Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa - TU_ATTR_WEAK uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index); +// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa +TU_ATTR_WEAK uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index); - // Invoked when device is mounted (configured) - TU_ATTR_WEAK void tud_mount_cb(void); +// Invoked when device is mounted (configured) +TU_ATTR_WEAK void tud_mount_cb(void); - // Invoked when device is unmounted - TU_ATTR_WEAK void tud_umount_cb(void); +// Invoked when device is unmounted +TU_ATTR_WEAK void tud_umount_cb(void); - // Invoked when usb bus is suspended - // Within 7ms, device must draw an average of current less than 2.5 mA from bus - TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en); +// Invoked when usb bus is suspended +// Within 7ms, device must draw an average of current less than 2.5 mA from bus +TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en); - // Invoked when usb bus is resumed - TU_ATTR_WEAK void tud_resume_cb(void); +// Invoked when usb bus is resumed +TU_ATTR_WEAK void tud_resume_cb(void); - // Invoked when received control request with VENDOR TYPE - TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request); +// Invoked when received control request with VENDOR TYPE +TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request); - //--------------------------------------------------------------------+ - // Binary Device Object Store (BOS) Descriptor Templates - //--------------------------------------------------------------------+ +//--------------------------------------------------------------------+ +// Binary Device Object Store (BOS) Descriptor Templates +//--------------------------------------------------------------------+ -#define TUD_BOS_DESC_LEN 5 +#define TUD_BOS_DESC_LEN 5 // total length, number of device caps #define TUD_BOS_DESCRIPTOR(_total_len, _caps_num) \ - 5, TUSB_DESC_BOS, U16_TO_U8S_LE(_total_len), _caps_num + 5, TUSB_DESC_BOS, U16_TO_U8S_LE(_total_len), _caps_num // Device Capability Platform 128-bit UUID + Data #define TUD_BOS_PLATFORM_DESCRIPTOR(...) \ - 4 + TU_ARGS_NUM(__VA_ARGS__), TUSB_DESC_DEVICE_CAPABILITY, DEVICE_CAPABILITY_PLATFORM, 0x00, __VA_ARGS__ + 4+TU_ARGS_NUM(__VA_ARGS__), TUSB_DESC_DEVICE_CAPABILITY, DEVICE_CAPABILITY_PLATFORM, 0x00, __VA_ARGS__ //------------- WebUSB BOS Platform -------------// // Descriptor Length -#define TUD_BOS_WEBUSB_DESC_LEN 24 +#define TUD_BOS_WEBUSB_DESC_LEN 24 // Vendor Code, iLandingPage #define TUD_BOS_WEBUSB_DESCRIPTOR(_vendor_code, _ipage) \ - TUD_BOS_PLATFORM_DESCRIPTOR(TUD_BOS_WEBUSB_UUID, U16_TO_U8S_LE(0x0100), _vendor_code, _ipage) + TUD_BOS_PLATFORM_DESCRIPTOR(TUD_BOS_WEBUSB_UUID, U16_TO_U8S_LE(0x0100), _vendor_code, _ipage) -#define TUD_BOS_WEBUSB_UUID \ - 0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, \ - 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65 +#define TUD_BOS_WEBUSB_UUID \ + 0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, \ + 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65 //------------- Microsoft OS 2.0 Platform -------------// -#define TUD_BOS_MICROSOFT_OS_DESC_LEN 28 +#define TUD_BOS_MICROSOFT_OS_DESC_LEN 28 // Total Length of descriptor set, vendor code #define TUD_BOS_MS_OS_20_DESCRIPTOR(_desc_set_len, _vendor_code) \ - TUD_BOS_PLATFORM_DESCRIPTOR(TUD_BOS_MS_OS_20_UUID, U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(_desc_set_len), _vendor_code, 0) + TUD_BOS_PLATFORM_DESCRIPTOR(TUD_BOS_MS_OS_20_UUID, U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(_desc_set_len), _vendor_code, 0) -#define TUD_BOS_MS_OS_20_UUID \ - 0xDF, 0x60, 0xDD, 0xD8, 0x89, 0x45, 0xC7, 0x4C, \ - 0x9C, 0xD2, 0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F +#define TUD_BOS_MS_OS_20_UUID \ + 0xDF, 0x60, 0xDD, 0xD8, 0x89, 0x45, 0xC7, 0x4C, \ + 0x9C, 0xD2, 0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F - //--------------------------------------------------------------------+ - // Configuration Descriptor Templates - //--------------------------------------------------------------------+ +//--------------------------------------------------------------------+ +// Configuration Descriptor Templates +//--------------------------------------------------------------------+ -#define TUD_CONFIG_DESC_LEN (9) +#define TUD_CONFIG_DESC_LEN (9) // Config number, interface count, string index, total length, attribute, power in mA #define TUD_CONFIG_DESCRIPTOR(config_num, _itfcount, _stridx, _total_len, _attribute, _power_ma) \ - 9, TUSB_DESC_CONFIGURATION, U16_TO_U8S_LE(_total_len), _itfcount, config_num, _stridx, TU_BIT(7) | _attribute, (_power_ma) / 2 + 9, TUSB_DESC_CONFIGURATION, U16_TO_U8S_LE(_total_len), _itfcount, config_num, _stridx, TU_BIT(7) | _attribute, (_power_ma)/2 //--------------------------------------------------------------------+ // CDC Descriptor Templates //--------------------------------------------------------------------+ // Length of template descriptor: 66 bytes -#define TUD_CDC_DESC_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +#define TUD_CDC_DESC_LEN (8+9+5+5+4+5+7+9+7+7) // CDC Descriptor Template // Interface number, string index, EP notification address and size, EP data address (out, in) and size. -#define TUD_CDC_DESCRIPTOR(_itfnum, _stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize) \ - /* Interface Associate */ \ - 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL, CDC_COMM_PROTOCOL_NONE, 0, /* CDC Control Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL, CDC_COMM_PROTOCOL_NONE, _stridx, /* CDC Header */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0120), /* CDC Call */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_CALL_MANAGEMENT, 0, (uint8_t)((_itfnum) + 1), /* CDC ACM: support line request */ \ - 4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 2, /* CDC Union */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1), /* Endpoint Notification */ \ - 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 16, /* CDC Data Interface */ \ - 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0, /* Endpoint Out */ \ - 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0, /* Endpoint In */ \ - 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 +#define TUD_CDC_DESCRIPTOR(_itfnum, _stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize) \ + /* Interface Associate */\ + 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL, CDC_COMM_PROTOCOL_NONE, 0,\ + /* CDC Control Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL, CDC_COMM_PROTOCOL_NONE, _stridx,\ + /* CDC Header */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0120),\ + /* CDC Call */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_CALL_MANAGEMENT, 0, (uint8_t)((_itfnum) + 1),\ + /* CDC ACM: support line request */\ + 4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 2,\ + /* CDC Union */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\ + /* Endpoint Notification */\ + 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 16,\ + /* CDC Data Interface */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0,\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 //--------------------------------------------------------------------+ // MSC Descriptor Templates //--------------------------------------------------------------------+ // Length of template descriptor: 23 bytes -#define TUD_MSC_DESC_LEN (9 + 7 + 7) +#define TUD_MSC_DESC_LEN (9 + 7 + 7) // Interface number, string index, EP Out & EP In address, EP size -#define TUD_MSC_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \ - /* Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_MSC, MSC_SUBCLASS_SCSI, MSC_PROTOCOL_BOT, _stridx, /* Endpoint Out */ \ - 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0, /* Endpoint In */ \ - 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 +#define TUD_MSC_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \ + /* Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_MSC, MSC_SUBCLASS_SCSI, MSC_PROTOCOL_BOT, _stridx,\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 + //--------------------------------------------------------------------+ // HID Descriptor Templates //--------------------------------------------------------------------+ // Length of template descriptor: 25 bytes -#define TUD_HID_DESC_LEN (9 + 9 + 7) +#define TUD_HID_DESC_LEN (9 + 9 + 7) // HID Input only descriptor // Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval -#define TUD_HID_DESCRIPTOR(_itfnum, _stridx, _boot_protocol, _report_desc_len, _epin, _epsize, _ep_interval) \ - /* Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? (uint8_t)HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx, /* HID descriptor */ \ - 9, HID_DESC_TYPE_HID, U16_TO_U8S_LE(0x0111), 0, 1, HID_DESC_TYPE_REPORT, U16_TO_U8S_LE(_report_desc_len), /* Endpoint In */ \ - 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval +#define TUD_HID_DESCRIPTOR(_itfnum, _stridx, _boot_protocol, _report_desc_len, _epin, _epsize, _ep_interval) \ + /* Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? (uint8_t)HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx,\ + /* HID descriptor */\ + 9, HID_DESC_TYPE_HID, U16_TO_U8S_LE(0x0111), 0, 1, HID_DESC_TYPE_REPORT, U16_TO_U8S_LE(_report_desc_len),\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval // Length of template descriptor: 32 bytes -#define TUD_HID_INOUT_DESC_LEN (9 + 9 + 7 + 7) +#define TUD_HID_INOUT_DESC_LEN (9 + 9 + 7 + 7) // HID Input & Output descriptor // Interface number, string index, protocol, report descriptor len, EP OUT & IN address, size & polling interval -#define TUD_HID_INOUT_DESCRIPTOR(_itfnum, _stridx, _boot_protocol, _report_desc_len, _epout, _epin, _epsize, _ep_interval) \ - /* Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? (uint8_t)HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx, /* HID descriptor */ \ - 9, HID_DESC_TYPE_HID, U16_TO_U8S_LE(0x0111), 0, 1, HID_DESC_TYPE_REPORT, U16_TO_U8S_LE(_report_desc_len), /* Endpoint Out */ \ - 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval, /* Endpoint In */ \ - 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval - - //--------------------------------------------------------------------+ - // MIDI Descriptor Templates - // Note: MIDI v1.0 is based on Audio v1.0 - //--------------------------------------------------------------------+ +#define TUD_HID_INOUT_DESCRIPTOR(_itfnum, _stridx, _boot_protocol, _report_desc_len, _epout, _epin, _epsize, _ep_interval) \ + /* Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? (uint8_t)HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx,\ + /* HID descriptor */\ + 9, HID_DESC_TYPE_HID, U16_TO_U8S_LE(0x0111), 0, 1, HID_DESC_TYPE_REPORT, U16_TO_U8S_LE(_report_desc_len),\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval, \ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval + +//--------------------------------------------------------------------+ +// MIDI Descriptor Templates +// Note: MIDI v1.0 is based on Audio v1.0 +//--------------------------------------------------------------------+ #define TUD_MIDI_DESC_HEAD_LEN (9 + 9 + 9 + 7) -#define TUD_MIDI_DESC_HEAD(_itfnum, _stridx, _numcables) \ - /* Audio Control (AC) Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_CONTROL, AUDIO_FUNC_PROTOCOL_CODE_UNDEF, _stridx, /* AC Header */ \ - 9, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(0x0009), 1, (uint8_t)((_itfnum) + 1), /* MIDI Streaming (MS) Interface */ \ - 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 2, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_MIDI_STREAMING, AUDIO_FUNC_PROTOCOL_CODE_UNDEF, 0, /* MS Header */ \ - 7, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(7 + (_numcables)*TUD_MIDI_DESC_JACK_LEN) +#define TUD_MIDI_DESC_HEAD(_itfnum, _stridx, _numcables) \ + /* Audio Control (AC) Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_CONTROL, AUDIO_FUNC_PROTOCOL_CODE_UNDEF, _stridx,\ + /* AC Header */\ + 9, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(0x0009), 1, (uint8_t)((_itfnum) + 1),\ + /* MIDI Streaming (MS) Interface */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 2, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_MIDI_STREAMING, AUDIO_FUNC_PROTOCOL_CODE_UNDEF, 0,\ + /* MS Header */\ + 7, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(7 + (_numcables) * TUD_MIDI_DESC_JACK_LEN) #define TUD_MIDI_JACKID_IN_EMB(_cablenum) \ - (uint8_t)(((_cablenum)-1) * 4 + 1) + (uint8_t)(((_cablenum) - 1) * 4 + 1) #define TUD_MIDI_JACKID_IN_EXT(_cablenum) \ - (uint8_t)(((_cablenum)-1) * 4 + 2) + (uint8_t)(((_cablenum) - 1) * 4 + 2) #define TUD_MIDI_JACKID_OUT_EMB(_cablenum) \ - (uint8_t)(((_cablenum)-1) * 4 + 3) + (uint8_t)(((_cablenum) - 1) * 4 + 3) #define TUD_MIDI_JACKID_OUT_EXT(_cablenum) \ - (uint8_t)(((_cablenum)-1) * 4 + 4) + (uint8_t)(((_cablenum) - 1) * 4 + 4) #define TUD_MIDI_DESC_JACK_LEN (6 + 6 + 9 + 9) -#define TUD_MIDI_DESC_JACK(_cablenum) \ - /* MS In Jack (Embedded) */ \ - 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_IN_EMB(_cablenum), 0, /* MS In Jack (External) */ \ - 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_IN_EXT(_cablenum), 0, /* MS Out Jack (Embedded), connected to In Jack External */ \ - 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, 0, /* MS Out Jack (External), connected to In Jack Embedded */ \ - 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, 0 +#define TUD_MIDI_DESC_JACK(_cablenum) \ + /* MS In Jack (Embedded) */\ + 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_IN_EMB(_cablenum), 0,\ + /* MS In Jack (External) */\ + 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_IN_EXT(_cablenum), 0,\ + /* MS Out Jack (Embedded), connected to In Jack External */\ + 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, 0,\ + /* MS Out Jack (External), connected to In Jack Embedded */\ + 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, 0 #define TUD_MIDI_DESC_EP_LEN(_numcables) (9 + 4 + (_numcables)) -#define TUD_MIDI_DESC_EP(_epout, _epsize, _numcables) \ - /* Endpoint: Note Audio v1.0's endpoint has 9 bytes instead of 7 */ \ - 9, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0, 0, 0, /* MS Endpoint (connected to embedded jack) */ \ - (uint8_t)(4 + (_numcables)), TUSB_DESC_CS_ENDPOINT, MIDI_CS_ENDPOINT_GENERAL, _numcables +#define TUD_MIDI_DESC_EP(_epout, _epsize, _numcables) \ + /* Endpoint: Note Audio v1.0's endpoint has 9 bytes instead of 7 */\ + 9, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0, 0, 0, \ + /* MS Endpoint (connected to embedded jack) */\ + (uint8_t)(4 + (_numcables)), TUSB_DESC_CS_ENDPOINT, MIDI_CS_ENDPOINT_GENERAL, _numcables // Length of template descriptor (88 bytes) #define TUD_MIDI_DESC_LEN (TUD_MIDI_DESC_HEAD_LEN + TUD_MIDI_DESC_JACK_LEN + TUD_MIDI_DESC_EP_LEN(1) * 2) @@ -296,12 +320,12 @@ extern "C" // - 1 Embedded Jack In connected to 1 External Jack Out // - 1 Embedded Jack out connected to 1 External Jack In #define TUD_MIDI_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \ - TUD_MIDI_DESC_HEAD(_itfnum, _stridx, 1), \ - TUD_MIDI_DESC_JACK(1), \ - TUD_MIDI_DESC_EP(_epout, _epsize, 1), \ - TUD_MIDI_JACKID_IN_EMB(1), \ - TUD_MIDI_DESC_EP(_epin, _epsize, 1), \ - TUD_MIDI_JACKID_OUT_EMB(1) + TUD_MIDI_DESC_HEAD(_itfnum, _stridx, 1),\ + TUD_MIDI_DESC_JACK(1),\ + TUD_MIDI_DESC_EP(_epout, _epsize, 1),\ + TUD_MIDI_JACKID_IN_EMB(1),\ + TUD_MIDI_DESC_EP(_epin, _epsize, 1),\ + TUD_MIDI_JACKID_OUT_EMB(1) //--------------------------------------------------------------------+ // Audio v2.0 Descriptor Templates @@ -310,201 +334,286 @@ extern "C" /* Standard Interface Association Descriptor (IAD) */ #define TUD_AUDIO_DESC_IAD_LEN 8 #define TUD_AUDIO_DESC_IAD(_firstitfs, _nitfs, _stridx) \ - TUD_AUDIO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, _firstitfs, _nitfs, TUSB_CLASS_AUDIO, AUDIO_FUNCTION_SUBCLASS_UNDEFINED, AUDIO_FUNC_PROTOCOL_CODE_V2, _stridx + TUD_AUDIO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, _firstitfs, _nitfs, TUSB_CLASS_AUDIO, AUDIO_FUNCTION_SUBCLASS_UNDEFINED, AUDIO_FUNC_PROTOCOL_CODE_V2, _stridx /* Standard AC Interface Descriptor(4.7.1) */ #define TUD_AUDIO_DESC_STD_AC_LEN 9 -#define TUD_AUDIO_DESC_STD_AC(_itfnum, _nEPs, _stridx) /* _nEPs is 0 or 1 */ \ - TUD_AUDIO_DESC_STD_AC_LEN, TUSB_DESC_INTERFACE, _itfnum, /* fixed to zero */ 0x00, _nEPs, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_CONTROL, AUDIO_INT_PROTOCOL_CODE_V2, _stridx +#define TUD_AUDIO_DESC_STD_AC(_itfnum, _nEPs, _stridx) /* _nEPs is 0 or 1 */\ + TUD_AUDIO_DESC_STD_AC_LEN, TUSB_DESC_INTERFACE, _itfnum, /* fixed to zero */ 0x00, _nEPs, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_CONTROL, AUDIO_INT_PROTOCOL_CODE_V2, _stridx /* Class-Specific AC Interface Header Descriptor(4.7.2) */ #define TUD_AUDIO_DESC_CS_AC_LEN 9 #define TUD_AUDIO_DESC_CS_AC(_bcdADC, _category, _totallen, _ctrl) /* _bcdADC : Audio Device Class Specification Release Number in Binary-Coded Decimal, _category : see audio_function_t, _totallen : Total number of bytes returned for the class-specific AudioControl interface i.e. Clock Source, Unit and Terminal descriptors - Do not include TUD_AUDIO_DESC_CS_AC_LEN, we already do this here*/ \ - TUD_AUDIO_DESC_CS_AC_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_HEADER, U16_TO_U8S_LE(_bcdADC), _category, U16_TO_U8S_LE(_totallen + TUD_AUDIO_DESC_CS_AC_LEN), _ctrl + TUD_AUDIO_DESC_CS_AC_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_HEADER, U16_TO_U8S_LE(_bcdADC), _category, U16_TO_U8S_LE(_totallen + TUD_AUDIO_DESC_CS_AC_LEN), _ctrl /* Clock Source Descriptor(4.7.2.1) */ #define TUD_AUDIO_DESC_CLK_SRC_LEN 8 #define TUD_AUDIO_DESC_CLK_SRC(_clkid, _attr, _ctrl, _assocTerm, _stridx) \ - TUD_AUDIO_DESC_CLK_SRC_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_CLOCK_SOURCE, _clkid, _attr, _ctrl, _assocTerm, _stridx + TUD_AUDIO_DESC_CLK_SRC_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_CLOCK_SOURCE, _clkid, _attr, _ctrl, _assocTerm, _stridx /* Input Terminal Descriptor(4.7.2.4) */ #define TUD_AUDIO_DESC_INPUT_TERM_LEN 17 #define TUD_AUDIO_DESC_INPUT_TERM(_termid, _termtype, _assocTerm, _clkid, _nchannelslogical, _channelcfg, _idxchannelnames, _ctrl, _stridx) \ - TUD_AUDIO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_INPUT_TERMINAL, _termid, U16_TO_U8S_LE(_termtype), _assocTerm, _clkid, _nchannelslogical, U32_TO_U8S_LE(_channelcfg), _idxchannelnames, U16_TO_U8S_LE(_ctrl), _stridx + TUD_AUDIO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_INPUT_TERMINAL, _termid, U16_TO_U8S_LE(_termtype), _assocTerm, _clkid, _nchannelslogical, U32_TO_U8S_LE(_channelcfg), _idxchannelnames, U16_TO_U8S_LE(_ctrl), _stridx /* Output Terminal Descriptor(4.7.2.5) */ #define TUD_AUDIO_DESC_OUTPUT_TERM_LEN 12 #define TUD_AUDIO_DESC_OUTPUT_TERM(_termid, _termtype, _assocTerm, _srcid, _clkid, _ctrl, _stridx) \ - TUD_AUDIO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_OUTPUT_TERMINAL, _termid, U16_TO_U8S_LE(_termtype), _assocTerm, _srcid, _clkid, U16_TO_U8S_LE(_ctrl), _stridx + TUD_AUDIO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_OUTPUT_TERMINAL, _termid, U16_TO_U8S_LE(_termtype), _assocTerm, _srcid, _clkid, U16_TO_U8S_LE(_ctrl), _stridx /* Feature Unit Descriptor(4.7.2.8) */ // 1 - Channel -#define TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN 6 + (1 + 1) * 4 +#define TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN 6+(1+1)*4 #define TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(_unitid, _srcid, _ctrlch0master, _ctrlch1, _stridx) \ - TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_FEATURE_UNIT, _unitid, _srcid, U32_TO_U8S_LE(_ctrlch0master), U32_TO_U8S_LE(_ctrlch1), _stridx + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_FEATURE_UNIT, _unitid, _srcid, U32_TO_U8S_LE(_ctrlch0master), U32_TO_U8S_LE(_ctrlch1), _stridx // 2 - Channels -#define TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN (6 + (2 + 1) * 4) +#define TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN (6+(2+1)*4) #define TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL(_unitid, _srcid, _ctrlch0master, _ctrlch1, _ctrlch2, _stridx) \ - TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_FEATURE_UNIT, _unitid, _srcid, U32_TO_U8S_LE(_ctrlch0master), U32_TO_U8S_LE(_ctrlch1), U32_TO_U8S_LE(_ctrlch2), _stridx + TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_FEATURE_UNIT, _unitid, _srcid, U32_TO_U8S_LE(_ctrlch0master), U32_TO_U8S_LE(_ctrlch1), U32_TO_U8S_LE(_ctrlch2), _stridx // 4 - Channels -#define TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN (6 + (4 + 1) * 4) +#define TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN (6+(4+1)*4) #define TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL(_unitid, _srcid, _ctrlch0master, _ctrlch1, _ctrlch2, _ctrlch3, _ctrlch4, _stridx) \ - TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_FEATURE_UNIT, _unitid, _srcid, U32_TO_U8S_LE(_ctrlch0master), U32_TO_U8S_LE(_ctrlch1), U32_TO_U8S_LE(_ctrlch2), U32_TO_U8S_LE(_ctrlch3), U32_TO_U8S_LE(_ctrlch4), _stridx + TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_FEATURE_UNIT, _unitid, _srcid, U32_TO_U8S_LE(_ctrlch0master), U32_TO_U8S_LE(_ctrlch1), U32_TO_U8S_LE(_ctrlch2), U32_TO_U8S_LE(_ctrlch3), U32_TO_U8S_LE(_ctrlch4), _stridx // For more channels, add definitions here /* Standard AS Interface Descriptor(4.9.1) */ #define TUD_AUDIO_DESC_STD_AS_INT_LEN 9 #define TUD_AUDIO_DESC_STD_AS_INT(_itfnum, _altset, _nEPs, _stridx) \ - TUD_AUDIO_DESC_STD_AS_INT_LEN, TUSB_DESC_INTERFACE, _itfnum, _altset, _nEPs, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_STREAMING, AUDIO_INT_PROTOCOL_CODE_V2, _stridx + TUD_AUDIO_DESC_STD_AS_INT_LEN, TUSB_DESC_INTERFACE, _itfnum, _altset, _nEPs, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_STREAMING, AUDIO_INT_PROTOCOL_CODE_V2, _stridx /* Class-Specific AS Interface Descriptor(4.9.2) */ #define TUD_AUDIO_DESC_CS_AS_INT_LEN 16 #define TUD_AUDIO_DESC_CS_AS_INT(_termid, _ctrl, _formattype, _formats, _nchannelsphysical, _channelcfg, _stridx) \ - TUD_AUDIO_DESC_CS_AS_INT_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AS_INTERFACE_AS_GENERAL, _termid, _ctrl, _formattype, U32_TO_U8S_LE(_formats), _nchannelsphysical, U32_TO_U8S_LE(_channelcfg), _stridx + TUD_AUDIO_DESC_CS_AS_INT_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AS_INTERFACE_AS_GENERAL, _termid, _ctrl, _formattype, U32_TO_U8S_LE(_formats), _nchannelsphysical, U32_TO_U8S_LE(_channelcfg), _stridx /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */ #define TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN 6 -#define TUD_AUDIO_DESC_TYPE_I_FORMAT(_subslotsize, _bitresolution) /* _subslotsize is number of bytes per sample (i.e. subslot) and can be 1,2,3, or 4 */ \ - TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AS_INTERFACE_FORMAT_TYPE, AUDIO_FORMAT_TYPE_I, _subslotsize, _bitresolution +#define TUD_AUDIO_DESC_TYPE_I_FORMAT(_subslotsize, _bitresolution) /* _subslotsize is number of bytes per sample (i.e. subslot) and can be 1,2,3, or 4 */\ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AS_INTERFACE_FORMAT_TYPE, AUDIO_FORMAT_TYPE_I, _subslotsize, _bitresolution /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */ #define TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN 7 #define TUD_AUDIO_DESC_STD_AS_ISO_EP(_ep, _attr, _maxEPsize, _interval) \ - TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN, TUSB_DESC_ENDPOINT, _ep, _attr, U16_TO_U8S_LE(_maxEPsize), _interval + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN, TUSB_DESC_ENDPOINT, _ep, _attr, U16_TO_U8S_LE(_maxEPsize), _interval /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */ #define TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN 8 #define TUD_AUDIO_DESC_CS_AS_ISO_EP(_attr, _ctrl, _lockdelayunit, _lockdelay) \ - TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN, TUSB_DESC_CS_ENDPOINT, AUDIO_CS_EP_SUBTYPE_GENERAL, _attr, _ctrl, _lockdelayunit, U16_TO_U8S_LE(_lockdelay) + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN, TUSB_DESC_CS_ENDPOINT, AUDIO_CS_EP_SUBTYPE_GENERAL, _attr, _ctrl, _lockdelayunit, U16_TO_U8S_LE(_lockdelay) /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */ #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7 #define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \ - TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval - - // AUDIO simple descriptor (UAC2) for 1 microphone input - // - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source - -#define TUD_AUDIO_MIC_ONE_CH_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN + TUD_AUDIO_DESC_STD_AC_LEN + TUD_AUDIO_DESC_CS_AC_LEN + TUD_AUDIO_DESC_CLK_SRC_LEN + TUD_AUDIO_DESC_INPUT_TERM_LEN + TUD_AUDIO_DESC_OUTPUT_TERM_LEN + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN + TUD_AUDIO_DESC_STD_AS_INT_LEN + TUD_AUDIO_DESC_STD_AS_INT_LEN + TUD_AUDIO_DESC_CS_AS_INT_LEN + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN) - -#define TUD_AUDIO_MIC_ONE_CH_DESC_N_AS_INT 1 // Number of AS interfaces - -#define TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \ - /* Standard Interface Association Descriptor (IAD) */ \ - TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00), /* Standard AC Interface Descriptor(4.7.1) */ \ - TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx), /* Class-Specific AC Interface Header Descriptor(4.7.2) */ \ - TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_MICROPHONE, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN + TUD_AUDIO_DESC_INPUT_TERM_LEN + TUD_AUDIO_DESC_OUTPUT_TERM_LEN + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS), /* Clock Source Descriptor(4.7.2.1) */ \ - TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_FIX_CLK, /*_ctrl*/ (AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00), /* Input Terminal Descriptor(4.7.2.4) */ \ - TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x03, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS, /*_stridx*/ 0x00), /* Output Terminal Descriptor(4.7.2.5) */ \ - TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00), /* Feature Unit Descriptor(4.7.2.8) */ \ - TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00), /* Standard AS Interface Descriptor(4.9.1) */ /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */ \ - TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00), /* Standard AS Interface Descriptor(4.9.1) */ /* Interface 1, Alternate 1 - alternate interface for data streaming */ \ - TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x00), /* Class-Specific AS Interface Descriptor(4.9.2) */ \ - TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x03, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00), /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */ \ - TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample), /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */ \ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01), /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */ \ - TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) - - // AUDIO simple descriptor (UAC2) for 4 microphone input - // - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source - -#define TUD_AUDIO_MIC_FOUR_CH_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN + TUD_AUDIO_DESC_STD_AC_LEN + TUD_AUDIO_DESC_CS_AC_LEN + TUD_AUDIO_DESC_CLK_SRC_LEN + TUD_AUDIO_DESC_INPUT_TERM_LEN + TUD_AUDIO_DESC_OUTPUT_TERM_LEN + TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN + TUD_AUDIO_DESC_STD_AS_INT_LEN + TUD_AUDIO_DESC_STD_AS_INT_LEN + TUD_AUDIO_DESC_CS_AS_INT_LEN + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN) - -#define TUD_AUDIO_MIC_FOUR_CH_DESC_N_AS_INT 1 // Number of AS interfaces - -#define TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \ - /* Standard Interface Association Descriptor (IAD) */ \ - TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00), /* Standard AC Interface Descriptor(4.7.1) */ \ - TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx), /* Class-Specific AC Interface Header Descriptor(4.7.2) */ \ - TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_MICROPHONE, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN + TUD_AUDIO_DESC_INPUT_TERM_LEN + TUD_AUDIO_DESC_OUTPUT_TERM_LEN + TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS), /* Clock Source Descriptor(4.7.2.1) */ \ - TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_FIX_CLK, /*_ctrl*/ (AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00), /* Input Terminal Descriptor(4.7.2.4) */ \ - TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x03, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x04, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS, /*_stridx*/ 0x00), /* Output Terminal Descriptor(4.7.2.5) */ \ - TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00), /* Feature Unit Descriptor(4.7.2.8) */ \ - TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch2*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch3*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch4*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00), /* Standard AS Interface Descriptor(4.9.1) */ /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */ \ - TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00), /* Standard AS Interface Descriptor(4.9.1) */ /* Interface 1, Alternate 1 - alternate interface for data streaming */ \ - TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x00), /* Class-Specific AS Interface Descriptor(4.9.2) */ \ - TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x03, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x04, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00), /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */ \ - TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample), /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */ \ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01), /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */ \ - TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) - - // AUDIO simple descriptor (UAC2) for mono speaker - // - 1 Input Terminal, 2 Feature Unit (Mute and Volume Control), 3 Output Terminal, 4 Clock Source - -#define TUD_AUDIO_SPEAKER_MONO_FB_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN + TUD_AUDIO_DESC_STD_AC_LEN + TUD_AUDIO_DESC_CS_AC_LEN + TUD_AUDIO_DESC_CLK_SRC_LEN + TUD_AUDIO_DESC_INPUT_TERM_LEN + TUD_AUDIO_DESC_OUTPUT_TERM_LEN + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN + TUD_AUDIO_DESC_STD_AS_INT_LEN + TUD_AUDIO_DESC_STD_AS_INT_LEN + TUD_AUDIO_DESC_CS_AS_INT_LEN + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN) - -#define TUD_AUDIO_SPEAKER_MONO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epsize, _epfb) \ - /* Standard Interface Association Descriptor (IAD) */ \ - TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00), /* Standard AC Interface Descriptor(4.7.1) */ \ - TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx), /* Class-Specific AC Interface Header Descriptor(4.7.2) */ \ - TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_DESKTOP_SPEAKER, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN + TUD_AUDIO_DESC_INPUT_TERM_LEN + TUD_AUDIO_DESC_OUTPUT_TERM_LEN + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS), /* Clock Source Descriptor(4.7.2.1) */ \ - TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_FIX_CLK, /*_ctrl*/ (AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00), /* Input Terminal Descriptor(4.7.2.4) */ \ - TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00), /* Output Terminal Descriptor(4.7.2.5) */ \ - TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_OUT_DESKTOP_SPEAKER, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00), /* Feature Unit Descriptor(4.7.2.8) */ \ - TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00), /* Standard AS Interface Descriptor(4.9.1) */ /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */ \ - TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00), /* Standard AS Interface Descriptor(4.9.1) */ /* Interface 1, Alternate 1 - alternate interface for data streaming */ \ - TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x01, /*_nEPs*/ 0x02, /*_stridx*/ 0x00), /* Class-Specific AS Interface Descriptor(4.9.2) */ \ - TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x01, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00), /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */ \ - TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample), /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */ \ - TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01), /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */ \ - TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000), /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */ \ - TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_interval*/ 1) + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval + +// AUDIO simple descriptor (UAC2) for 1 microphone input +// - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source + +#define TUD_AUDIO_MIC_ONE_CH_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\ + + TUD_AUDIO_DESC_STD_AC_LEN\ + + TUD_AUDIO_DESC_CS_AC_LEN\ + + TUD_AUDIO_DESC_CLK_SRC_LEN\ + + TUD_AUDIO_DESC_INPUT_TERM_LEN\ + + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\ + + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN\ + + TUD_AUDIO_DESC_STD_AS_INT_LEN\ + + TUD_AUDIO_DESC_STD_AS_INT_LEN\ + + TUD_AUDIO_DESC_CS_AS_INT_LEN\ + + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\ + + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\ + + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN) + +#define TUD_AUDIO_MIC_ONE_CH_DESC_N_AS_INT 1 // Number of AS interfaces + +#define TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \ + /* Standard Interface Association Descriptor (IAD) */\ + TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ + /* Standard AC Interface Descriptor(4.7.1) */\ + TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\ + /* Class-Specific AC Interface Header Descriptor(4.7.2) */\ + TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_MICROPHONE, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\ + /* Clock Source Descriptor(4.7.2.1) */\ + TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_FIX_CLK, /*_ctrl*/ (AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00),\ + /* Input Terminal Descriptor(4.7.2.4) */\ + TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x03, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS, /*_stridx*/ 0x00),\ + /* Output Terminal Descriptor(4.7.2.5) */\ + TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\ + /* Feature Unit Descriptor(4.7.2.8) */\ + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00),\ + /* Standard AS Interface Descriptor(4.9.1) */\ + /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\ + TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\ + /* Standard AS Interface Descriptor(4.9.1) */\ + /* Interface 1, Alternate 1 - alternate interface for data streaming */\ + TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\ + /* Class-Specific AS Interface Descriptor(4.9.2) */\ + TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x03, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\ + /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ + TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ + /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\ + /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ + TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) + +// AUDIO simple descriptor (UAC2) for 4 microphone input +// - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source + +#define TUD_AUDIO_MIC_FOUR_CH_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\ + + TUD_AUDIO_DESC_STD_AC_LEN\ + + TUD_AUDIO_DESC_CS_AC_LEN\ + + TUD_AUDIO_DESC_CLK_SRC_LEN\ + + TUD_AUDIO_DESC_INPUT_TERM_LEN\ + + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\ + + TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN\ + + TUD_AUDIO_DESC_STD_AS_INT_LEN\ + + TUD_AUDIO_DESC_STD_AS_INT_LEN\ + + TUD_AUDIO_DESC_CS_AS_INT_LEN\ + + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\ + + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\ + + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN) + +#define TUD_AUDIO_MIC_FOUR_CH_DESC_N_AS_INT 1 // Number of AS interfaces + +#define TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \ + /* Standard Interface Association Descriptor (IAD) */\ + TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ + /* Standard AC Interface Descriptor(4.7.1) */\ + TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\ + /* Class-Specific AC Interface Header Descriptor(4.7.2) */\ + TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_MICROPHONE, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\ + /* Clock Source Descriptor(4.7.2.1) */\ + TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_FIX_CLK, /*_ctrl*/ (AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00),\ + /* Input Terminal Descriptor(4.7.2.4) */\ + TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x03, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x04, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS, /*_stridx*/ 0x00),\ + /* Output Terminal Descriptor(4.7.2.5) */\ + TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\ + /* Feature Unit Descriptor(4.7.2.8) */\ + TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch2*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch3*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch4*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00),\ + /* Standard AS Interface Descriptor(4.9.1) */\ + /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\ + TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\ + /* Standard AS Interface Descriptor(4.9.1) */\ + /* Interface 1, Alternate 1 - alternate interface for data streaming */\ + TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\ + /* Class-Specific AS Interface Descriptor(4.9.2) */\ + TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x03, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x04, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\ + /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ + TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ + /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\ + /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ + TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000) + +// AUDIO simple descriptor (UAC2) for mono speaker +// - 1 Input Terminal, 2 Feature Unit (Mute and Volume Control), 3 Output Terminal, 4 Clock Source + +#define TUD_AUDIO_SPEAKER_MONO_FB_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\ + + TUD_AUDIO_DESC_STD_AC_LEN\ + + TUD_AUDIO_DESC_CS_AC_LEN\ + + TUD_AUDIO_DESC_CLK_SRC_LEN\ + + TUD_AUDIO_DESC_INPUT_TERM_LEN\ + + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\ + + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN\ + + TUD_AUDIO_DESC_STD_AS_INT_LEN\ + + TUD_AUDIO_DESC_STD_AS_INT_LEN\ + + TUD_AUDIO_DESC_CS_AS_INT_LEN\ + + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\ + + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\ + + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\ + + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN) + +#define TUD_AUDIO_SPEAKER_MONO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epsize, _epfb) \ + /* Standard Interface Association Descriptor (IAD) */\ + TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\ + /* Standard AC Interface Descriptor(4.7.1) */\ + TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\ + /* Class-Specific AC Interface Header Descriptor(4.7.2) */\ + TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_DESKTOP_SPEAKER, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\ + /* Clock Source Descriptor(4.7.2.1) */\ + TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_FIX_CLK, /*_ctrl*/ (AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00),\ + /* Input Terminal Descriptor(4.7.2.4) */\ + TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\ + /* Output Terminal Descriptor(4.7.2.5) */\ + TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_OUT_DESKTOP_SPEAKER, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\ + /* Feature Unit Descriptor(4.7.2.8) */\ + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00),\ + /* Standard AS Interface Descriptor(4.9.1) */\ + /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\ + TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\ + /* Standard AS Interface Descriptor(4.9.1) */\ + /* Interface 1, Alternate 1 - alternate interface for data streaming */\ + TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x01, /*_nEPs*/ 0x02, /*_stridx*/ 0x00),\ + /* Class-Specific AS Interface Descriptor(4.9.2) */\ + TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x01, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\ + /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\ + TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\ + /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\ + TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\ + /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\ + TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\ + /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\ + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_interval*/ 1)\ // Calculate wMaxPacketSize of Endpoints #define TUD_AUDIO_EP_SIZE(_maxFrequency, _nBytesPerSample, _nChannels) \ - ((((_maxFrequency + ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 7999 : 999)) / ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels) + ((((_maxFrequency + ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 7999 : 999)) / ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels) - //--------------------------------------------------------------------+ - // USBTMC/USB488 Descriptor Templates - //--------------------------------------------------------------------+ -#define TUD_USBTMC_APP_CLASS (TUSB_CLASS_APPLICATION_SPECIFIC) +//--------------------------------------------------------------------+ +// USBTMC/USB488 Descriptor Templates +//--------------------------------------------------------------------+ + +#define TUD_USBTMC_APP_CLASS (TUSB_CLASS_APPLICATION_SPECIFIC) #define TUD_USBTMC_APP_SUBCLASS 0x03u -#define TUD_USBTMC_PROTOCOL_STD 0x00u +#define TUD_USBTMC_PROTOCOL_STD 0x00u #define TUD_USBTMC_PROTOCOL_USB488 0x01u // Interface number, number of endpoints, EP string index, USB_TMC_PROTOCOL*, bulk-out endpoint ID, // bulk-in endpoint ID #define TUD_USBTMC_IF_DESCRIPTOR(_itfnum, _bNumEndpoints, _stridx, _itfProtocol) \ - /* Interface */ \ - 0x09, TUSB_DESC_INTERFACE, _itfnum, 0x00, _bNumEndpoints, TUD_USBTMC_APP_CLASS, TUD_USBTMC_APP_SUBCLASS, _itfProtocol, _stridx + /* Interface */ \ + 0x09, TUSB_DESC_INTERFACE, _itfnum, 0x00, _bNumEndpoints, TUD_USBTMC_APP_CLASS, TUD_USBTMC_APP_SUBCLASS, _itfProtocol, _stridx #define TUD_USBTMC_IF_DESCRIPTOR_LEN 9u -#define TUD_USBTMC_BULK_DESCRIPTORS(_epout, _epin, _bulk_epsize) \ - /* Endpoint Out */ \ - 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_bulk_epsize), 0u, /* Endpoint In */ \ - 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_bulk_epsize), 0u +#define TUD_USBTMC_BULK_DESCRIPTORS(_epout, _epin, _bulk_epsize) \ + /* Endpoint Out */ \ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_bulk_epsize), 0u, \ + /* Endpoint In */ \ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_bulk_epsize), 0u -#define TUD_USBTMC_BULK_DESCRIPTORS_LEN (7u + 7u) +#define TUD_USBTMC_BULK_DESCRIPTORS_LEN (7u+7u) -/* optional interrupt endpoint */ // _int_pollingInterval : for LS/FS, expressed in frames (1ms each). 16 may be a good number? -#define TUD_USBTMC_INT_DESCRIPTOR(_ep_interrupt, _ep_interrupt_size, _int_pollingInterval) \ - 7, TUSB_DESC_ENDPOINT, _ep_interrupt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_interrupt_size), 0x16 +/* optional interrupt endpoint */ \ +// _int_pollingInterval : for LS/FS, expressed in frames (1ms each). 16 may be a good number? +#define TUD_USBTMC_INT_DESCRIPTOR(_ep_interrupt, _ep_interrupt_size, _int_pollingInterval ) \ + 7, TUSB_DESC_ENDPOINT, _ep_interrupt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_interrupt_size), 0x16 #define TUD_USBTMC_INT_DESCRIPTOR_LEN (7u) - //--------------------------------------------------------------------+ - // Vendor Descriptor Templates - //--------------------------------------------------------------------+ +//--------------------------------------------------------------------+ +// Vendor Descriptor Templates +//--------------------------------------------------------------------+ -#define TUD_VENDOR_DESC_LEN (9 + 7 + 7) +#define TUD_VENDOR_DESC_LEN (9+7+7) // Interface number, string index, EP Out & IN address, EP size -#define TUD_VENDOR_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \ - /* Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_VENDOR_SPECIFIC, 0x00, 0x00, _stridx, /* Endpoint Out */ \ - 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0, /* Endpoint In */ \ - 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 +#define TUD_VENDOR_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \ + /* Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_VENDOR_SPECIFIC, 0x00, 0x00, _stridx,\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 - //--------------------------------------------------------------------+ - // DFU Runtime Descriptor Templates - //--------------------------------------------------------------------+ +//--------------------------------------------------------------------+ +// DFU Runtime Descriptor Templates +//--------------------------------------------------------------------+ -#define TUD_DFU_APP_CLASS (TUSB_CLASS_APPLICATION_SPECIFIC) +#define TUD_DFU_APP_CLASS (TUSB_CLASS_APPLICATION_SPECIFIC) #define TUD_DFU_APP_SUBCLASS (APP_SUBCLASS_DFU_RUNTIME) // Length of template descriptr: 18 bytes @@ -512,124 +621,143 @@ extern "C" // DFU runtime descriptor // Interface number, string index, attributes, detach timeout, transfer size -#define TUD_DFU_RT_DESCRIPTOR(_itfnum, _stridx, _attr, _timeout, _xfer_size) \ - /* Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_RT, _stridx, /* Function */ \ - 9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101) +#define TUD_DFU_RT_DESCRIPTOR(_itfnum, _stridx, _attr, _timeout, _xfer_size) \ + /* Interface */ \ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_RT, _stridx, \ + /* Function */ \ + 9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101) //--------------------------------------------------------------------+ // DFU Descriptor Templates //--------------------------------------------------------------------+ // Length of template descriptor: 9 bytes + number of alternatives * 9 -#define TUD_DFU_DESC_LEN(_alt_count) (9 + (_alt_count)*9) +#define TUD_DFU_DESC_LEN(_alt_count) (9 + (_alt_count) * 9) // Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size // Note: Alternate count must be numberic or macro, string index is increased by one for each Alt interface #define TUD_DFU_DESCRIPTOR(_itfnum, _alt_count, _stridx, _attr, _timeout, _xfer_size) \ - TU_XSTRCAT(_TUD_DFU_ALT_, _alt_count) \ - (_itfnum, 0, _stridx), /* Function */ \ - 9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101) + TU_XSTRCAT(_TUD_DFU_ALT_,_alt_count)(_itfnum, 0, _stridx), \ + /* Function */ \ + 9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101) #define _TUD_DFU_ALT(_itfnum, _alt, _stridx) \ - /* Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx + /* Interface */ \ + 9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx #define _TUD_DFU_ALT_1(_itfnum, _alt_count, _stridx) \ - _TUD_DFU_ALT(_itfnum, _alt_count, _stridx) + _TUD_DFU_ALT(_itfnum, _alt_count, _stridx) #define _TUD_DFU_ALT_2(_itfnum, _alt_count, _stridx) \ - _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ - _TUD_DFU_ALT_1(_itfnum, _alt_count + 1, _stridx + 1) + _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ + _TUD_DFU_ALT_1(_itfnum, _alt_count+1, _stridx+1) #define _TUD_DFU_ALT_3(_itfnum, _alt_count, _stridx) \ - _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ - _TUD_DFU_ALT_2(_itfnum, _alt_count + 1, _stridx + 1) + _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ + _TUD_DFU_ALT_2(_itfnum, _alt_count+1, _stridx+1) #define _TUD_DFU_ALT_4(_itfnum, _alt_count, _stridx) \ - _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ - _TUD_DFU_ALT_3(_itfnum, _alt_count + 1, _stridx + 1) + _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ + _TUD_DFU_ALT_3(_itfnum, _alt_count+1, _stridx+1) #define _TUD_DFU_ALT_5(_itfnum, _alt_count, _stridx) \ - _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ - _TUD_DFU_ALT_4(_itfnum, _alt_count + 1, _stridx + 1) + _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ + _TUD_DFU_ALT_4(_itfnum, _alt_count+1, _stridx+1) #define _TUD_DFU_ALT_6(_itfnum, _alt_count, _stridx) \ - _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ - _TUD_DFU_ALT_5(_itfnum, _alt_count + 1, _stridx + 1) + _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ + _TUD_DFU_ALT_5(_itfnum, _alt_count+1, _stridx+1) #define _TUD_DFU_ALT_7(_itfnum, _alt_count, _stridx) \ - _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ - _TUD_DFU_ALT_6(_itfnum, _alt_count + 1, _stridx + 1) + _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ + _TUD_DFU_ALT_6(_itfnum, _alt_count+1, _stridx+1) #define _TUD_DFU_ALT_8(_itfnum, _alt_count, _stridx) \ - _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ - _TUD_DFU_ALT_7(_itfnum, _alt_count + 1, _stridx + 1) + _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \ + _TUD_DFU_ALT_7(_itfnum, _alt_count+1, _stridx+1) //--------------------------------------------------------------------+ // CDC-ECM Descriptor Templates //--------------------------------------------------------------------+ // Length of template descriptor: 71 bytes -#define TUD_CDC_ECM_DESC_LEN (8 + 9 + 5 + 5 + 13 + 7 + 9 + 9 + 7 + 7) +#define TUD_CDC_ECM_DESC_LEN (8+9+5+5+13+7+9+9+7+7) // CDC-ECM Descriptor Template // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size. -#define TUD_CDC_ECM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \ - /* Interface Association */ \ - 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL, 0, 0, /* CDC Control Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL, 0, _desc_stridx, /* CDC-ECM Header */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0120), /* CDC-ECM Union */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1), /* CDC-ECM Functional Descriptor */ \ - 13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, /* Endpoint Notification */ \ - 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1, /* CDC Data Interface (default inactive) */ \ - 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 0, 0, /* CDC Data Interface (alternative active) */ \ - 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 1, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0, /* Endpoint In */ \ - 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0, /* Endpoint Out */ \ - 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 - - //--------------------------------------------------------------------+ - // RNDIS Descriptor Templates - //--------------------------------------------------------------------+ +#define TUD_CDC_ECM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \ + /* Interface Association */\ + 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL, 0, 0,\ + /* CDC Control Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL, 0, _desc_stridx,\ + /* CDC-ECM Header */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0120),\ + /* CDC-ECM Union */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\ + /* CDC-ECM Functional Descriptor */\ + 13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0,\ + /* Endpoint Notification */\ + 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1,\ + /* CDC Data Interface (default inactive) */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 0, 0,\ + /* CDC Data Interface (alternative active) */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0,\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 + +//--------------------------------------------------------------------+ +// RNDIS Descriptor Templates +//--------------------------------------------------------------------+ #if 0 /* Windows XP */ -#define TUD_RNDIS_ITF_CLASS TUSB_CLASS_CDC +#define TUD_RNDIS_ITF_CLASS TUSB_CLASS_CDC #define TUD_RNDIS_ITF_SUBCLASS CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL #define TUD_RNDIS_ITF_PROTOCOL 0xFF /* CDC_COMM_PROTOCOL_MICROSOFT_RNDIS */ #else /* Windows 7+ */ -#define TUD_RNDIS_ITF_CLASS TUSB_CLASS_WIRELESS_CONTROLLER +#define TUD_RNDIS_ITF_CLASS TUSB_CLASS_WIRELESS_CONTROLLER #define TUD_RNDIS_ITF_SUBCLASS 0x01 #define TUD_RNDIS_ITF_PROTOCOL 0x03 #endif // Length of template descriptor: 66 bytes -#define TUD_RNDIS_DESC_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +#define TUD_RNDIS_DESC_LEN (8+9+5+5+4+5+7+9+7+7) // RNDIS Descriptor Template // Interface number, string index, EP notification address and size, EP data address (out, in) and size. -#define TUD_RNDIS_DESCRIPTOR(_itfnum, _stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize) \ - /* Interface Association */ \ - 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUD_RNDIS_ITF_CLASS, TUD_RNDIS_ITF_SUBCLASS, TUD_RNDIS_ITF_PROTOCOL, 0, /* CDC Control Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUD_RNDIS_ITF_CLASS, TUD_RNDIS_ITF_SUBCLASS, TUD_RNDIS_ITF_PROTOCOL, _stridx, /* CDC-ACM Header */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110), /* CDC Call Management */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_CALL_MANAGEMENT, 0, (uint8_t)((_itfnum) + 1), /* ACM */ \ - 4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 0, /* CDC Union */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1), /* Endpoint Notification */ \ - 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1, /* CDC Data Interface */ \ - 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0, /* Endpoint In */ \ - 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0, /* Endpoint Out */ \ - 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 - - //--------------------------------------------------------------------+ - // Bluetooth Radio Descriptor Templates - //--------------------------------------------------------------------+ - -#define TUD_BT_APP_CLASS (TUSB_CLASS_WIRELESS_CONTROLLER) -#define TUD_BT_APP_SUBCLASS 0x01 -#define TUD_BT_PROTOCOL_PRIMARY_CONTROLLER 0x01 -#define TUD_BT_PROTOCOL_AMP_CONTROLLER 0x02 +#define TUD_RNDIS_DESCRIPTOR(_itfnum, _stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize) \ + /* Interface Association */\ + 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUD_RNDIS_ITF_CLASS, TUD_RNDIS_ITF_SUBCLASS, TUD_RNDIS_ITF_PROTOCOL, 0,\ + /* CDC Control Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUD_RNDIS_ITF_CLASS, TUD_RNDIS_ITF_SUBCLASS, TUD_RNDIS_ITF_PROTOCOL, _stridx,\ + /* CDC-ACM Header */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\ + /* CDC Call Management */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_CALL_MANAGEMENT, 0, (uint8_t)((_itfnum) + 1),\ + /* ACM */\ + 4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 0,\ + /* CDC Union */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\ + /* Endpoint Notification */\ + 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1,\ + /* CDC Data Interface */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0,\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 + +//--------------------------------------------------------------------+ +// Bluetooth Radio Descriptor Templates +//--------------------------------------------------------------------+ + +#define TUD_BT_APP_CLASS (TUSB_CLASS_WIRELESS_CONTROLLER) +#define TUD_BT_APP_SUBCLASS 0x01 +#define TUD_BT_PROTOCOL_PRIMARY_CONTROLLER 0x01 +#define TUD_BT_PROTOCOL_AMP_CONTROLLER 0x02 #ifndef CFG_TUD_BTH_ISO_ALT_COUNT #define CFG_TUD_BTH_ISO_ALT_COUNT 0 @@ -639,73 +767,82 @@ extern "C" #define TUD_BTH_DESC_LEN (8 + 9 + 7 + 7 + 7 + (CFG_TUD_BTH_ISO_ALT_COUNT) * (9 + 7 + 7)) /* Primary Interface */ -#define TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 3, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, _stridx, /* Endpoint In for events */ \ - 7, TUSB_DESC_ENDPOINT, _ep_evt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_evt_size), _ep_evt_interval, /* Endpoint In for ACL data */ \ - 7, TUSB_DESC_ENDPOINT, _ep_in, TUSB_XFER_BULK, U16_TO_U8S_LE(_ep_size), 1, /* Endpoint Out for ACL data */ \ - 7, TUSB_DESC_ENDPOINT, _ep_out, TUSB_XFER_BULK, U16_TO_U8S_LE(_ep_size), 1 - -#define TUD_BTH_ISO_ITF(_itfnum, _alt, _ep_in, _ep_out, _n) , /* Interface with 2 endpoints */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, _alt, 2, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, 0, /* Isochronous endpoints */ \ - 7, TUSB_DESC_ENDPOINT, _ep_in, TUSB_XFER_ISOCHRONOUS, U16_TO_U8S_LE(_n), 1, \ - 7, TUSB_DESC_ENDPOINT, _ep_out, TUSB_XFER_ISOCHRONOUS, U16_TO_U8S_LE(_n), 1 +#define TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 3, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, _stridx, \ + /* Endpoint In for events */ \ + 7, TUSB_DESC_ENDPOINT, _ep_evt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_evt_size), _ep_evt_interval, \ + /* Endpoint In for ACL data */ \ + 7, TUSB_DESC_ENDPOINT, _ep_in, TUSB_XFER_BULK, U16_TO_U8S_LE(_ep_size), 1, \ + /* Endpoint Out for ACL data */ \ + 7, TUSB_DESC_ENDPOINT, _ep_out, TUSB_XFER_BULK, U16_TO_U8S_LE(_ep_size), 1 + +#define TUD_BTH_ISO_ITF(_itfnum, _alt, _ep_in, _ep_out, _n) ,\ + /* Interface with 2 endpoints */ \ + 9, TUSB_DESC_INTERFACE, _itfnum, _alt, 2, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, 0, \ + /* Isochronous endpoints */ \ + 7, TUSB_DESC_ENDPOINT, _ep_in, TUSB_XFER_ISOCHRONOUS, U16_TO_U8S_LE(_n), 1, \ + 7, TUSB_DESC_ENDPOINT, _ep_out, TUSB_XFER_ISOCHRONOUS, U16_TO_U8S_LE(_n), 1 #define _FIRST(a, ...) a #define _REST(a, ...) __VA_ARGS__ #define TUD_BTH_ISO_ITF_0(_itfnum, ...) -#define TUD_BTH_ISO_ITF_1(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT)-1, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) -#define TUD_BTH_ISO_ITF_2(_itfnum, _ep_in, _ep_out, ...) \ - TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT)-2, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ - TUD_BTH_ISO_ITF_1(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) -#define TUD_BTH_ISO_ITF_3(_itfnum, _ep_in, _ep_out, ...) \ - TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT)-3, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ - TUD_BTH_ISO_ITF_2(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) -#define TUD_BTH_ISO_ITF_4(_itfnum, _ep_in, _ep_out, ...) \ - TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT)-4, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ - TUD_BTH_ISO_ITF_3(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) -#define TUD_BTH_ISO_ITF_5(_itfnum, _ep_in, _ep_out, ...) \ - TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT)-5, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ - TUD_BTH_ISO_ITF_4(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) -#define TUD_BTH_ISO_ITF_6(_itfnum, _ep_in, _ep_out, ...) \ - TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT)-6, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ - TUD_BTH_ISO_ITF_5(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) - -#define TUD_BTH_ISO_ITFS(_itfnum, _ep_in, _ep_out, ...) \ - TU_XSTRCAT(TUD_BTH_ISO_ITF_, CFG_TUD_BTH_ISO_ALT_COUNT) \ - (_itfnum, _ep_in, _ep_out, __VA_ARGS__) +#define TUD_BTH_ISO_ITF_1(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 1, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) +#define TUD_BTH_ISO_ITF_2(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 2, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ + TUD_BTH_ISO_ITF_1(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) +#define TUD_BTH_ISO_ITF_3(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 3, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ + TUD_BTH_ISO_ITF_2(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) +#define TUD_BTH_ISO_ITF_4(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 4, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ + TUD_BTH_ISO_ITF_3(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) +#define TUD_BTH_ISO_ITF_5(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 5, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ + TUD_BTH_ISO_ITF_4(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) +#define TUD_BTH_ISO_ITF_6(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 6, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \ + TUD_BTH_ISO_ITF_5(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__)) + +#define TUD_BTH_ISO_ITFS(_itfnum, _ep_in, _ep_out, ...) \ + TU_XSTRCAT(TUD_BTH_ISO_ITF_, CFG_TUD_BTH_ISO_ALT_COUNT)(_itfnum, _ep_in, _ep_out, __VA_ARGS__) // BT Primary controller descriptor // Interface number, string index, attributes, event endpoint, event endpoint size, interval, data in, data out, data endpoint size, iso endpoint sizes // TODO BTH should also use IAD like CDC for composite device -#define TUD_BTH_DESCRIPTOR(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size, ...) \ - /* Interface Associate */ \ - 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, 0, \ - TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \ - TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__) +#define TUD_BTH_DESCRIPTOR(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size,...) \ + /* Interface Associate */\ + 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, 0,\ + TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \ + TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__) //--------------------------------------------------------------------+ // CDC-NCM Descriptor Templates //--------------------------------------------------------------------+ // Length of template descriptor -#define TUD_CDC_NCM_DESC_LEN (8 + 9 + 5 + 5 + 13 + 6 + 7 + 9 + 9 + 7 + 7) +#define TUD_CDC_NCM_DESC_LEN (8+9+5+5+13+6+7+9+9+7+7) // CDC-ECM Descriptor Template // Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size. -#define TUD_CDC_NCM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \ - /* Interface Association */ \ - 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, 0, /* CDC Control Interface */ \ - 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, _desc_stridx, /* CDC-NCM Header */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110), /* CDC-NCM Union */ \ - 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1), /* CDC-NCM Functional Descriptor */ \ - 13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, /* CDC-NCM Functional Descriptor */ \ - 6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, /* Endpoint Notification */ \ - 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 50, /* CDC Data Interface (default inactive) */ \ - 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 0, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0, /* CDC Data Interface (alternative active) */ \ - 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 1, 2, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0, /* Endpoint In */ \ - 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0, /* Endpoint Out */ \ - 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 +#define TUD_CDC_NCM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \ + /* Interface Association */\ + 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, 0,\ + /* CDC Control Interface */\ + 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, _desc_stridx,\ + /* CDC-NCM Header */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\ + /* CDC-NCM Union */\ + 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\ + /* CDC-NCM Functional Descriptor */\ + 13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, \ + /* CDC-NCM Functional Descriptor */\ + 6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \ + /* Endpoint Notification */\ + 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 50,\ + /* CDC Data Interface (default inactive) */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0,\ + /* CDC Data Interface (alternative active) */\ + 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0,\ + /* Endpoint In */\ + 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\ + /* Endpoint Out */\ + 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0 #ifdef __cplusplus } diff --git a/uCNC/src/tinyusb/src/device/usbd_control.c b/uCNC/src/tinyusb/src/device/usbd_control.c index c7635a2a2..a3e5a087b 100644 --- a/uCNC/src/tinyusb/src/device/usbd_control.c +++ b/uCNC/src/tinyusb/src/device/usbd_control.c @@ -38,19 +38,19 @@ extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callb enum { - EDPT_CTRL_OUT = 0x00, - EDPT_CTRL_IN = 0x80 + EDPT_CTRL_OUT = 0x00, + EDPT_CTRL_IN = 0x80 }; typedef struct { - tusb_control_request_t request; + tusb_control_request_t request; - uint8_t *buffer; - uint16_t data_len; - uint16_t total_xferred; + uint8_t *buffer; + uint16_t data_len; + uint16_t total_xferred; - usbd_control_xfer_cb_t complete_cb; + usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; static usbd_control_xfer_t _ctrl_xfer; @@ -64,20 +64,20 @@ CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbd_ctrl_buf[CFG_TUD_EN // Queue ZLP status transaction static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const *request) { - // Opposite to endpoint in Data Phase - uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; - return usbd_edpt_xfer(rhport, ep_addr, NULL, 0); + // Opposite to endpoint in Data Phase + uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; + return usbd_edpt_xfer(rhport, ep_addr, NULL, 0); } // Status phase bool tud_control_status(uint8_t rhport, tusb_control_request_t const *request) { - _ctrl_xfer.request = (*request); - _ctrl_xfer.buffer = NULL; - _ctrl_xfer.total_xferred = 0; - _ctrl_xfer.data_len = 0; + _ctrl_xfer.request = (*request); + _ctrl_xfer.buffer = NULL; + _ctrl_xfer.total_xferred = 0; + _ctrl_xfer.data_len = 0; - return _status_stage_xact(rhport, request); + return _status_stage_xact(rhport, request); } // Queue a transaction in Data Stage @@ -85,48 +85,48 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const *request) // This function can also transfer an zero-length packet static bool _data_stage_xact(uint8_t rhport) { - uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE); + uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE); - uint8_t ep_addr = EDPT_CTRL_OUT; + uint8_t ep_addr = EDPT_CTRL_OUT; - if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) - { - ep_addr = EDPT_CTRL_IN; - if (xact_len) - memcpy(_usbd_ctrl_buf, _ctrl_xfer.buffer, xact_len); - } + if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) + { + ep_addr = EDPT_CTRL_IN; + if (xact_len) + memcpy(_usbd_ctrl_buf, _ctrl_xfer.buffer, xact_len); + } - return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len); + return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len); } // Transmit data to/from the control endpoint. // If the request's wLength is zero, a status packet is sent instead. bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const *request, void *buffer, uint16_t len) { - _ctrl_xfer.request = (*request); - _ctrl_xfer.buffer = (uint8_t *)buffer; - _ctrl_xfer.total_xferred = 0U; - _ctrl_xfer.data_len = tu_min16(len, request->wLength); - - if (request->wLength > 0U) - { - if (_ctrl_xfer.data_len > 0U) - { - TU_ASSERT(buffer); - } - - // TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len); - - // Data stage - TU_ASSERT(_data_stage_xact(rhport)); - } - else - { - // Status stage - TU_ASSERT(_status_stage_xact(rhport, request)); - } - - return true; + _ctrl_xfer.request = (*request); + _ctrl_xfer.buffer = (uint8_t *)buffer; + _ctrl_xfer.total_xferred = 0U; + _ctrl_xfer.data_len = tu_min16(len, request->wLength); + + if (request->wLength > 0U) + { + if (_ctrl_xfer.data_len > 0U) + { + TU_ASSERT(buffer); + } + + // TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len); + + // Data stage + TU_ASSERT(_data_stage_xact(rhport)); + } + else + { + // Status stage + TU_ASSERT(_status_stage_xact(rhport, request)); + } + + return true; } //--------------------------------------------------------------------+ @@ -140,22 +140,22 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, void usbd_control_reset(void) { - tu_varclr(&_ctrl_xfer); + tu_varclr(&_ctrl_xfer); } // Set complete callback void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp) { - _ctrl_xfer.complete_cb = fp; + _ctrl_xfer.complete_cb = fp; } // for dcd_set_address where DCD is responsible for status response void usbd_control_set_request(tusb_control_request_t const *request) { - _ctrl_xfer.request = (*request); - _ctrl_xfer.buffer = NULL; - _ctrl_xfer.total_xferred = 0; - _ctrl_xfer.data_len = 0; + _ctrl_xfer.request = (*request); + _ctrl_xfer.buffer = NULL; + _ctrl_xfer.total_xferred = 0; + _ctrl_xfer.data_len = 0; } // callback when a transaction complete on @@ -163,73 +163,73 @@ void usbd_control_set_request(tusb_control_request_t const *request) // - Status stage bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { - (void)result; - - // Endpoint Address is opposite to direction bit, this is Status Stage complete event - if (tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction) - { - TU_ASSERT(0 == xferred_bytes); - - // invoke optional dcd hook if available - if (dcd_edpt0_status_complete) - dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request); - - if (_ctrl_xfer.complete_cb) - { - // TODO refactor with usbd_driver_print_control_complete_name - _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_ACK, &_ctrl_xfer.request); - } - - return true; - } - - if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) - { - TU_VERIFY(_ctrl_xfer.buffer); - memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes); - TU_LOG_MEM(2, _usbd_ctrl_buf, xferred_bytes, 2); - } - - _ctrl_xfer.total_xferred += xferred_bytes; - _ctrl_xfer.buffer += xferred_bytes; - - // Data Stage is complete when all request's length are transferred or - // a short packet is sent including zero-length packet. - if ((_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) || (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE)) - { - // DATA stage is complete - bool is_ok = true; - - // invoke complete callback if set - // callback can still stall control in status phase e.g out data does not make sense - if (_ctrl_xfer.complete_cb) - { + (void)result; + + // Endpoint Address is opposite to direction bit, this is Status Stage complete event + if (tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction) + { + TU_ASSERT(0 == xferred_bytes); + + // invoke optional dcd hook if available + if (dcd_edpt0_status_complete) + dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request); + + if (_ctrl_xfer.complete_cb) + { + // TODO refactor with usbd_driver_print_control_complete_name + _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_ACK, &_ctrl_xfer.request); + } + + return true; + } + + if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) + { + TU_VERIFY(_ctrl_xfer.buffer); + memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes); + TU_LOG_MEM(2, _usbd_ctrl_buf, xferred_bytes, 2); + } + + _ctrl_xfer.total_xferred += xferred_bytes; + _ctrl_xfer.buffer += xferred_bytes; + + // Data Stage is complete when all request's length are transferred or + // a short packet is sent including zero-length packet. + if ((_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) || (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE)) + { + // DATA stage is complete + bool is_ok = true; + + // invoke complete callback if set + // callback can still stall control in status phase e.g out data does not make sense + if (_ctrl_xfer.complete_cb) + { #if CFG_TUSB_DEBUG >= 2 - usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb); + usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb); #endif - is_ok = _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_DATA, &_ctrl_xfer.request); - } - - if (is_ok) - { - // Send status - TU_ASSERT(_status_stage_xact(rhport, &_ctrl_xfer.request)); - } - else - { - // Stall both IN and OUT control endpoint - dcd_edpt_stall(rhport, EDPT_CTRL_OUT); - dcd_edpt_stall(rhport, EDPT_CTRL_IN); - } - } - else - { - // More data to transfer - TU_ASSERT(_data_stage_xact(rhport)); - } - - return true; + is_ok = _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_DATA, &_ctrl_xfer.request); + } + + if (is_ok) + { + // Send status + TU_ASSERT(_status_stage_xact(rhport, &_ctrl_xfer.request)); + } + else + { + // Stall both IN and OUT control endpoint + dcd_edpt_stall(rhport, EDPT_CTRL_OUT); + dcd_edpt_stall(rhport, EDPT_CTRL_IN); + } + } + else + { + // More data to transfer + TU_ASSERT(_data_stage_xact(rhport)); + } + + return true; } #endif diff --git a/uCNC/src/tinyusb/src/device/usbd_pvt.h b/uCNC/src/tinyusb/src/device/usbd_pvt.h index c2df2a547..eda68155c 100644 --- a/uCNC/src/tinyusb/src/device/usbd_pvt.h +++ b/uCNC/src/tinyusb/src/device/usbd_pvt.h @@ -34,78 +34,78 @@ extern "C" { #endif - //--------------------------------------------------------------------+ - // Class Driver API - //--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // Class Driver API + //--------------------------------------------------------------------+ - typedef struct - { + typedef struct + { #if CFG_TUSB_DEBUG >= 2 - char const *name; + char const *name; #endif - void (*init)(void); - void (*reset)(uint8_t rhport); - uint16_t (*open)(uint8_t rhport, tusb_desc_interface_t const *desc_intf, uint16_t max_len); - bool (*control_xfer_cb)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request); - bool (*xfer_cb)(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); - void (*sof)(uint8_t rhport); /* optional */ - } usbd_class_driver_t; + void (*init)(void); + void (*reset)(uint8_t rhport); + uint16_t (*open)(uint8_t rhport, tusb_desc_interface_t const *desc_intf, uint16_t max_len); + bool (*control_xfer_cb)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request); + bool (*xfer_cb)(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); + void (*sof)(uint8_t rhport); /* optional */ + } usbd_class_driver_t; - // Invoked when initializing device stack to get additional class drivers. - // Can optionally implemented by application to extend/overwrite class driver support. - // Note: The drivers array must be accessible at all time when stack is active - usbd_class_driver_t const *usbd_app_driver_get_cb(uint8_t *driver_count) TU_ATTR_WEAK; + // Invoked when initializing device stack to get additional class drivers. + // Can optionally implemented by application to extend/overwrite class driver support. + // Note: The drivers array must be accessible at all time when stack is active + usbd_class_driver_t const *usbd_app_driver_get_cb(uint8_t *driver_count) TU_ATTR_WEAK; - typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request); + typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request); - //--------------------------------------------------------------------+ - // USBD Endpoint API - //--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // USBD Endpoint API + //--------------------------------------------------------------------+ - // Open an endpoint - bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep); + // Open an endpoint + bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep); - // Close an endpoint - void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr); + // Close an endpoint + void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr); - // Submit a usb transfer - bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes); + // Submit a usb transfer + bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes); - // Submit a usb ISO transfer by use of a FIFO (ring buffer) - all bytes in FIFO get transmitted - bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes); + // Submit a usb ISO transfer by use of a FIFO (ring buffer) - all bytes in FIFO get transmitted + bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes); - // Claim an endpoint before submitting a transfer. - // If caller does not make any transfer, it must release endpoint for others. - bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr); + // Claim an endpoint before submitting a transfer. + // If caller does not make any transfer, it must release endpoint for others. + bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr); - // Release an endpoint without submitting a transfer - bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr); + // Release an endpoint without submitting a transfer + bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr); - // Check if endpoint is busy transferring - bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr); + // Check if endpoint is busy transferring + bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr); - // Stall endpoint - void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr); + // Stall endpoint + void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr); - // Clear stalled endpoint - void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr); + // Clear stalled endpoint + void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr); - // Check if endpoint is stalled - bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr); + // Check if endpoint is stalled + bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr); - // Check if endpoint is ready (not busy and not stalled) - TU_ATTR_ALWAYS_INLINE static inline bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) - { - return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr); - } + // Check if endpoint is ready (not busy and not stalled) + TU_ATTR_ALWAYS_INLINE static inline bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) + { + return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr); + } - /*------------------------------------------------------------------*/ - /* Helper - *------------------------------------------------------------------*/ + /*------------------------------------------------------------------*/ + /* Helper + *------------------------------------------------------------------*/ - bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const *p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t *ep_out, uint8_t *ep_in); - void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr); + bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const *p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t *ep_out, uint8_t *ep_in); + void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr); #ifdef __cplusplus } diff --git a/uCNC/src/tinyusb/src/osal/osal.h b/uCNC/src/tinyusb/src/osal/osal.h index 3396b36bd..1ca0f6a27 100644 --- a/uCNC/src/tinyusb/src/osal/osal.h +++ b/uCNC/src/tinyusb/src/osal/osal.h @@ -32,8 +32,8 @@ extern "C" { #endif - /** \addtogroup group_osal - * @{ */ + /** \addtogroup group_osal + * @{ */ #include "../common/tusb_common.h" @@ -46,7 +46,7 @@ extern "C" #define OSAL_TIMEOUT_CONTROL_XFER OSAL_TIMEOUT_WAIT_FOREVER - typedef void (*osal_task_func_t)(void *); + typedef void (*osal_task_func_t)(void *); #if CFG_TUSB_OS == OPT_OS_NONE #include "osal_none.h" @@ -58,38 +58,40 @@ extern "C" #include "osal_pico.h" #elif CFG_TUSB_OS == OPT_OS_RTTHREAD #include "osal_rtthread.h" +#elif CFG_TUSB_OS == OPT_OS_RTX4 +#include "osal_rtx4.h" #elif CFG_TUSB_OS == OPT_OS_CUSTOM #include "tusb_os_custom.h" // implemented by application #else #error OS is not supported yet #endif - //--------------------------------------------------------------------+ - // OSAL Porting API - //--------------------------------------------------------------------+ + //--------------------------------------------------------------------+ + // OSAL Porting API + //--------------------------------------------------------------------+ -#if __GNUC__ +#if __GNUC__ && !defined(__ARMCC_VERSION) #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wredundant-decls" #endif - //------------- Semaphore -------------// - static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef); - static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr); - static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec); - - static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed - - //------------- Mutex -------------// - static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef); - static inline bool osal_mutex_lock(osal_mutex_t sem_hdl, uint32_t msec); - static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl); - - //------------- Queue -------------// - static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef); - static inline bool osal_queue_receive(osal_queue_t qhdl, void *data); - static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr); - static inline bool osal_queue_empty(osal_queue_t qhdl); -#if __GNUC__ + //------------- Semaphore -------------// + static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef); + static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr); + static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec); + + static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed + + //------------- Mutex -------------// + static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef); + static inline bool osal_mutex_lock(osal_mutex_t sem_hdl, uint32_t msec); + static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl); + + //------------- Queue -------------// + static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef); + static inline bool osal_queue_receive(osal_queue_t qhdl, void *data); + static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr); + static inline bool osal_queue_empty(osal_queue_t qhdl); +#if __GNUC__ && !defined(__ARMCC_VERSION) #pragma GCC diagnostic pop #endif diff --git a/uCNC/src/tinyusb/src/osal/osal_freertos.h b/uCNC/src/tinyusb/src/osal/osal_freertos.h index 6f72d91c3..aa102b15c 100644 --- a/uCNC/src/tinyusb/src/osal/osal_freertos.h +++ b/uCNC/src/tinyusb/src/osal/osal_freertos.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -28,88 +28,87 @@ #define _TUSB_OSAL_FREERTOS_H_ // FreeRTOS Headers -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH, FreeRTOS.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH, semphr.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH, queue.h) -#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH, task.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h) +#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h) #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - //--------------------------------------------------------------------+ - // TASK API - //--------------------------------------------------------------------+ - static inline void osal_task_delay(uint32_t msec) - { - vTaskDelay(pdMS_TO_TICKS(msec)); - } - - //--------------------------------------------------------------------+ - // Semaphore API - //--------------------------------------------------------------------+ - typedef StaticSemaphore_t osal_semaphore_def_t; - typedef SemaphoreHandle_t osal_semaphore_t; - - static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) - { - return xSemaphoreCreateBinaryStatic(semdef); - } - - static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) - { - if (!in_isr) - { - return xSemaphoreGive(sem_hdl) != 0; - } - else - { - BaseType_t xHigherPriorityTaskWoken; - BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken); +//--------------------------------------------------------------------+ +// TASK API +//--------------------------------------------------------------------+ +static inline void osal_task_delay(uint32_t msec) +{ + vTaskDelay( pdMS_TO_TICKS(msec) ); +} + +//--------------------------------------------------------------------+ +// Semaphore API +//--------------------------------------------------------------------+ +typedef StaticSemaphore_t osal_semaphore_def_t; +typedef SemaphoreHandle_t osal_semaphore_t; + +static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) +{ + return xSemaphoreCreateBinaryStatic(semdef); +} + +static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) +{ + if ( !in_isr ) + { + return xSemaphoreGive(sem_hdl) != 0; + } + else + { + BaseType_t xHigherPriorityTaskWoken; + BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken); #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 - if (xHigherPriorityTaskWoken) - portYIELD_FROM_ISR(); + // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 + if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR(); #else - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); #endif - return res != 0; - } - } - - static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) - { - uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? portMAX_DELAY : pdMS_TO_TICKS(msec); - return xSemaphoreTake(sem_hdl, ticks); - } - - static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) - { - xQueueReset(sem_hdl); - } - - //--------------------------------------------------------------------+ - // MUTEX API (priority inheritance) - //--------------------------------------------------------------------+ - typedef StaticSemaphore_t osal_mutex_def_t; - typedef SemaphoreHandle_t osal_mutex_t; - - static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) - { - return xSemaphoreCreateMutexStatic(mdef); - } - - static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) - { - return osal_semaphore_wait(mutex_hdl, msec); - } - - static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) - { - return xSemaphoreGive(mutex_hdl); - } + return res != 0; + } +} + +static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) +{ + uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? portMAX_DELAY : pdMS_TO_TICKS(msec); + return xSemaphoreTake(sem_hdl, ticks); +} + +static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) +{ + xQueueReset(sem_hdl); +} + +//--------------------------------------------------------------------+ +// MUTEX API (priority inheritance) +//--------------------------------------------------------------------+ +typedef StaticSemaphore_t osal_mutex_def_t; +typedef SemaphoreHandle_t osal_mutex_t; + +static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) +{ + return xSemaphoreCreateMutexStatic(mdef); +} + +static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) +{ + return osal_semaphore_wait(mutex_hdl, msec); +} + +static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) +{ + return xSemaphoreGive(mutex_hdl); +} //--------------------------------------------------------------------+ // QUEUE API @@ -117,59 +116,59 @@ extern "C" // role device/host is used by OS NONE for mutex (disable usb isr) only #define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \ - static _type _name##_##buf[_depth]; \ - osal_queue_def_t _name = {.depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf}; - - typedef struct - { - uint16_t depth; - uint16_t item_sz; - void *buf; - - StaticQueue_t sq; - } osal_queue_def_t; - - typedef QueueHandle_t osal_queue_t; - - static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) - { - return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t *)qdef->buf, &qdef->sq); - } - - static inline bool osal_queue_receive(osal_queue_t qhdl, void *data) - { - return xQueueReceive(qhdl, data, portMAX_DELAY); - } - - static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) - { - if (!in_isr) - { - return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0; - } - else - { - BaseType_t xHigherPriorityTaskWoken; - BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken); + static _type _name##_##buf[_depth];\ + osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf }; + +typedef struct +{ + uint16_t depth; + uint16_t item_sz; + void* buf; + + StaticQueue_t sq; +}osal_queue_def_t; + +typedef QueueHandle_t osal_queue_t; + +static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) +{ + return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq); +} + +static inline bool osal_queue_receive(osal_queue_t qhdl, void* data) +{ + return xQueueReceive(qhdl, data, portMAX_DELAY); +} + +static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) +{ + if ( !in_isr ) + { + return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0; + } + else + { + BaseType_t xHigherPriorityTaskWoken; + BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken); #if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 - if (xHigherPriorityTaskWoken) - portYIELD_FROM_ISR(); + // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 + if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR(); #else - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); #endif - return res != 0; - } - } + return res != 0; + } +} - static inline bool osal_queue_empty(osal_queue_t qhdl) - { - return uxQueueMessagesWaiting(qhdl) == 0; - } +static inline bool osal_queue_empty(osal_queue_t qhdl) +{ + return uxQueueMessagesWaiting(qhdl) == 0; +} #ifdef __cplusplus -} + } #endif -#endif /* _TUSB_OSAL_FREERTOS_H_ */ +#endif diff --git a/uCNC/src/tinyusb/src/osal/osal_mynewt.h b/uCNC/src/tinyusb/src/osal/osal_mynewt.h index 7834e6cfb..6882329c1 100644 --- a/uCNC/src/tinyusb/src/osal/osal_mynewt.h +++ b/uCNC/src/tinyusb/src/osal/osal_mynewt.h @@ -30,67 +30,66 @@ #include "os/os.h" #ifdef __cplusplus -extern "C" -{ + extern "C" { #endif - //--------------------------------------------------------------------+ - // TASK API - //--------------------------------------------------------------------+ - static inline void osal_task_delay(uint32_t msec) - { - os_time_delay(os_time_ms_to_ticks32(msec)); - } - - //--------------------------------------------------------------------+ - // Semaphore API - //--------------------------------------------------------------------+ - typedef struct os_sem osal_semaphore_def_t; - typedef struct os_sem *osal_semaphore_t; - - static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) - { - return (os_sem_init(semdef, 0) == OS_OK) ? (osal_semaphore_t)semdef : NULL; - } - - static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) - { - (void)in_isr; - return os_sem_release(sem_hdl) == OS_OK; - } - - static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) - { - uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec); - return os_sem_pend(sem_hdl, ticks) == OS_OK; - } - - static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) - { - // TODO implement later - } - - //--------------------------------------------------------------------+ - // MUTEX API (priority inheritance) - //--------------------------------------------------------------------+ - typedef struct os_mutex osal_mutex_def_t; - typedef struct os_mutex *osal_mutex_t; - - static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) - { - return (os_mutex_init(mdef) == OS_OK) ? (osal_mutex_t)mdef : NULL; - } - - static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) - { - uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec); - return os_mutex_pend(mutex_hdl, ticks) == OS_OK; - } - - static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) - { - return os_mutex_release(mutex_hdl) == OS_OK; - } +//--------------------------------------------------------------------+ +// TASK API +//--------------------------------------------------------------------+ +static inline void osal_task_delay(uint32_t msec) +{ + os_time_delay( os_time_ms_to_ticks32(msec) ); +} + +//--------------------------------------------------------------------+ +// Semaphore API +//--------------------------------------------------------------------+ +typedef struct os_sem osal_semaphore_def_t; +typedef struct os_sem* osal_semaphore_t; + +static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) +{ + return (os_sem_init(semdef, 0) == OS_OK) ? (osal_semaphore_t) semdef : NULL; +} + +static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) +{ + (void) in_isr; + return os_sem_release(sem_hdl) == OS_OK; +} + +static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) +{ + uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec); + return os_sem_pend(sem_hdl, ticks) == OS_OK; +} + +static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) +{ + // TODO implement later +} + +//--------------------------------------------------------------------+ +// MUTEX API (priority inheritance) +//--------------------------------------------------------------------+ +typedef struct os_mutex osal_mutex_def_t; +typedef struct os_mutex* osal_mutex_t; + +static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) +{ + return (os_mutex_init(mdef) == OS_OK) ? (osal_mutex_t) mdef : NULL; +} + +static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) +{ + uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec); + return os_mutex_pend(mutex_hdl, ticks) == OS_OK; +} + +static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) +{ + return os_mutex_release(mutex_hdl) == OS_OK; +} //--------------------------------------------------------------------+ // QUEUE API @@ -98,80 +97,78 @@ extern "C" // role device/host is used by OS NONE for mutex (disable usb isr) only #define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \ - static _type _name##_##buf[_depth]; \ - static struct os_event _name##_##evbuf[_depth]; \ - osal_queue_def_t _name = {.depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .evbuf = _name##_##evbuf}; - - typedef struct - { - uint16_t depth; - uint16_t item_sz; - void *buf; - void *evbuf; - - struct os_mempool mpool; - struct os_mempool epool; - - struct os_eventq evq; - } osal_queue_def_t; - - typedef osal_queue_def_t *osal_queue_t; - - static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) - { - if (OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usbd queue")) - return NULL; - if (OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usbd evqueue")) - return NULL; - - os_eventq_init(&qdef->evq); - return (osal_queue_t)qdef; - } - - static inline bool osal_queue_receive(osal_queue_t qhdl, void *data) - { - struct os_event *ev; - ev = os_eventq_get(&qhdl->evq); - - memcpy(data, ev->ev_arg, qhdl->item_sz); // copy message - os_memblock_put(&qhdl->mpool, ev->ev_arg); // put back mem block - os_memblock_put(&qhdl->epool, ev); // put back ev block - - return true; - } - - static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) - { - (void)in_isr; - - // get a block from mem pool for data - void *ptr = os_memblock_get(&qhdl->mpool); - if (!ptr) - return false; - memcpy(ptr, data, qhdl->item_sz); - - // get a block from event pool to put into queue - struct os_event *ev = (struct os_event *)os_memblock_get(&qhdl->epool); - if (!ev) - { - os_memblock_put(&qhdl->mpool, ptr); - return false; - } - tu_memclr(ev, sizeof(struct os_event)); - ev->ev_arg = ptr; - - os_eventq_put(&qhdl->evq, ev); - - return true; - } - - static inline bool osal_queue_empty(osal_queue_t qhdl) - { - return STAILQ_EMPTY(&qhdl->evq.evq_list); - } + static _type _name##_##buf[_depth];\ + static struct os_event _name##_##evbuf[_depth];\ + osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .evbuf = _name##_##evbuf};\ -#ifdef __cplusplus +typedef struct +{ + uint16_t depth; + uint16_t item_sz; + void* buf; + void* evbuf; + + struct os_mempool mpool; + struct os_mempool epool; + + struct os_eventq evq; +}osal_queue_def_t; + +typedef osal_queue_def_t* osal_queue_t; + +static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) +{ + if ( OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usbd queue") ) return NULL; + if ( OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usbd evqueue") ) return NULL; + + os_eventq_init(&qdef->evq); + return (osal_queue_t) qdef; } + +static inline bool osal_queue_receive(osal_queue_t qhdl, void* data) +{ + struct os_event* ev; + ev = os_eventq_get(&qhdl->evq); + + memcpy(data, ev->ev_arg, qhdl->item_sz); // copy message + os_memblock_put(&qhdl->mpool, ev->ev_arg); // put back mem block + os_memblock_put(&qhdl->epool, ev); // put back ev block + + return true; +} + +static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) +{ + (void) in_isr; + + // get a block from mem pool for data + void* ptr = os_memblock_get(&qhdl->mpool); + if (!ptr) return false; + memcpy(ptr, data, qhdl->item_sz); + + // get a block from event pool to put into queue + struct os_event* ev = (struct os_event*) os_memblock_get(&qhdl->epool); + if (!ev) + { + os_memblock_put(&qhdl->mpool, ptr); + return false; + } + tu_memclr(ev, sizeof(struct os_event)); + ev->ev_arg = ptr; + + os_eventq_put(&qhdl->evq, ev); + + return true; +} + +static inline bool osal_queue_empty(osal_queue_t qhdl) +{ + return STAILQ_EMPTY(&qhdl->evq.evq_list); +} + + +#ifdef __cplusplus + } #endif #endif /* OSAL_MYNEWT_H_ */ diff --git a/uCNC/src/tinyusb/src/osal/osal_none.h b/uCNC/src/tinyusb/src/osal/osal_none.h index 3fc4f6d4c..5df7912a8 100644 --- a/uCNC/src/tinyusb/src/osal/osal_none.h +++ b/uCNC/src/tinyusb/src/osal/osal_none.h @@ -32,73 +32,73 @@ extern "C" { #endif - //--------------------------------------------------------------------+ - // TASK API - //--------------------------------------------------------------------+ - - //--------------------------------------------------------------------+ - // Binary Semaphore API - //--------------------------------------------------------------------+ - typedef struct - { - volatile uint16_t count; - } osal_semaphore_def_t; - - typedef osal_semaphore_def_t *osal_semaphore_t; - - static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) - { - semdef->count = 0; - return semdef; - } - - static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) - { - (void)in_isr; - sem_hdl->count++; - return true; - } - - // TODO blocking for now - static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) - { - (void)msec; - - while (sem_hdl->count == 0) - { - } - sem_hdl->count--; - - return true; - } - - static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) - { - sem_hdl->count = 0; - } - - //--------------------------------------------------------------------+ - // MUTEX API - // Within tinyusb, mutex is never used in ISR context - //--------------------------------------------------------------------+ - typedef osal_semaphore_def_t osal_mutex_def_t; - typedef osal_semaphore_t osal_mutex_t; - - static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) - { - mdef->count = 1; - return mdef; - } - - static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) - { - return osal_semaphore_wait(mutex_hdl, msec); - } - - static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) - { - return osal_semaphore_post(mutex_hdl, false); - } + //--------------------------------------------------------------------+ + // TASK API + //--------------------------------------------------------------------+ + + //--------------------------------------------------------------------+ + // Binary Semaphore API + //--------------------------------------------------------------------+ + typedef struct + { + volatile uint16_t count; + } osal_semaphore_def_t; + + typedef osal_semaphore_def_t *osal_semaphore_t; + + static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) + { + semdef->count = 0; + return semdef; + } + + static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) + { + (void)in_isr; + sem_hdl->count++; + return true; + } + + // TODO blocking for now + static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) + { + (void)msec; + + while (sem_hdl->count == 0) + { + } + sem_hdl->count--; + + return true; + } + + static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) + { + sem_hdl->count = 0; + } + + //--------------------------------------------------------------------+ + // MUTEX API + // Within tinyusb, mutex is never used in ISR context + //--------------------------------------------------------------------+ + typedef osal_semaphore_def_t osal_mutex_def_t; + typedef osal_semaphore_t osal_mutex_t; + + static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) + { + mdef->count = 1; + return mdef; + } + + static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) + { + return osal_semaphore_wait(mutex_hdl, msec); + } + + static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) + { + return osal_semaphore_post(mutex_hdl, false); + } //--------------------------------------------------------------------+ // QUEUE API @@ -107,102 +107,102 @@ extern "C" // extern to avoid including dcd.h and hcd.h #if TUSB_OPT_DEVICE_ENABLED - extern void dcd_int_disable(uint8_t rhport); - extern void dcd_int_enable(uint8_t rhport); + extern void dcd_int_disable(uint8_t rhport); + extern void dcd_int_enable(uint8_t rhport); #endif #if TUSB_OPT_HOST_ENABLED - extern void hcd_int_disable(uint8_t rhport); - extern void hcd_int_enable(uint8_t rhport); + extern void hcd_int_disable(uint8_t rhport); + extern void hcd_int_enable(uint8_t rhport); #endif - typedef struct - { - uint8_t role; // device or host - tu_fifo_t ff; - } osal_queue_def_t; + typedef struct + { + uint8_t role; // device or host + tu_fifo_t ff; + } osal_queue_def_t; - typedef osal_queue_def_t *osal_queue_t; + typedef osal_queue_def_t *osal_queue_t; // role device/host is used by OS NONE for mutex (disable usb isr) only #define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \ - uint8_t _name##_buf[_depth * sizeof(_type)]; \ - osal_queue_def_t _name = { \ - .role = _role, \ - .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false)} + uint8_t _name##_buf[_depth * sizeof(_type)]; \ + osal_queue_def_t _name = { \ + .role = _role, \ + .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false)} - // lock queue by disable USB interrupt - static inline void _osal_q_lock(osal_queue_t qhdl) - { - (void)qhdl; + // lock queue by disable USB interrupt + static inline void _osal_q_lock(osal_queue_t qhdl) + { + (void)qhdl; #if TUSB_OPT_DEVICE_ENABLED - if (qhdl->role == OPT_MODE_DEVICE) - dcd_int_disable(TUD_OPT_RHPORT); + if (qhdl->role == OPT_MODE_DEVICE) + dcd_int_disable(TUD_OPT_RHPORT); #endif #if TUSB_OPT_HOST_ENABLED - if (qhdl->role == OPT_MODE_HOST) - hcd_int_disable(TUH_OPT_RHPORT); + if (qhdl->role == OPT_MODE_HOST) + hcd_int_disable(TUH_OPT_RHPORT); #endif - } + } - // unlock queue - static inline void _osal_q_unlock(osal_queue_t qhdl) - { - (void)qhdl; + // unlock queue + static inline void _osal_q_unlock(osal_queue_t qhdl) + { + (void)qhdl; #if TUSB_OPT_DEVICE_ENABLED - if (qhdl->role == OPT_MODE_DEVICE) - dcd_int_enable(TUD_OPT_RHPORT); + if (qhdl->role == OPT_MODE_DEVICE) + dcd_int_enable(TUD_OPT_RHPORT); #endif #if TUSB_OPT_HOST_ENABLED - if (qhdl->role == OPT_MODE_HOST) - hcd_int_enable(TUH_OPT_RHPORT); + if (qhdl->role == OPT_MODE_HOST) + hcd_int_enable(TUH_OPT_RHPORT); #endif - } - - static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) - { - tu_fifo_clear(&qdef->ff); - return (osal_queue_t)qdef; - } - - static inline bool osal_queue_receive(osal_queue_t qhdl, void *data) - { - _osal_q_lock(qhdl); - bool success = tu_fifo_read(&qhdl->ff, data); - _osal_q_unlock(qhdl); - - return success; - } - - static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) - { - if (!in_isr) - { - _osal_q_lock(qhdl); - } - - bool success = tu_fifo_write(&qhdl->ff, data); - - if (!in_isr) - { - _osal_q_unlock(qhdl); - } - - TU_ASSERT(success); - - return success; - } - - static inline bool osal_queue_empty(osal_queue_t qhdl) - { - // Skip queue lock/unlock since this function is primarily called - // with interrupt disabled before going into low power mode - return tu_fifo_empty(&qhdl->ff); - } + } + + static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) + { + tu_fifo_clear(&qdef->ff); + return (osal_queue_t)qdef; + } + + static inline bool osal_queue_receive(osal_queue_t qhdl, void *data) + { + _osal_q_lock(qhdl); + bool success = tu_fifo_read(&qhdl->ff, data); + _osal_q_unlock(qhdl); + + return success; + } + + static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) + { + if (!in_isr) + { + _osal_q_lock(qhdl); + } + + bool success = tu_fifo_write(&qhdl->ff, data); + + if (!in_isr) + { + _osal_q_unlock(qhdl); + } + + TU_ASSERT(success); + + return success; + } + + static inline bool osal_queue_empty(osal_queue_t qhdl) + { + // Skip queue lock/unlock since this function is primarily called + // with interrupt disabled before going into low power mode + return tu_fifo_empty(&qhdl->ff); + } #ifdef __cplusplus } diff --git a/uCNC/src/tinyusb/src/osal/osal_pico.h b/uCNC/src/tinyusb/src/osal/osal_pico.h index 40be4bf20..1c3366e01 100644 --- a/uCNC/src/tinyusb/src/osal/osal_pico.h +++ b/uCNC/src/tinyusb/src/osal/osal_pico.h @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. @@ -33,68 +33,67 @@ #include "pico/critical_section.h" #ifdef __cplusplus -extern "C" -{ + extern "C" { #endif - //--------------------------------------------------------------------+ - // TASK API - //--------------------------------------------------------------------+ - static inline void osal_task_delay(uint32_t msec) - { - sleep_ms(msec); - } - - //--------------------------------------------------------------------+ - // Binary Semaphore API - //--------------------------------------------------------------------+ - typedef struct semaphore osal_semaphore_def_t, *osal_semaphore_t; - - static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) - { - sem_init(semdef, 0, 255); - return semdef; - } - - static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) - { - (void)in_isr; - sem_release(sem_hdl); - return true; - } - - static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) - { - return sem_acquire_timeout_ms(sem_hdl, msec); - } - - static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) - { - sem_reset(sem_hdl, 0); - } - - //--------------------------------------------------------------------+ - // MUTEX API - // Within tinyusb, mutex is never used in ISR context - //--------------------------------------------------------------------+ - typedef struct mutex osal_mutex_def_t, *osal_mutex_t; - - static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) - { - mutex_init(mdef); - return mdef; - } - - static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) - { - return mutex_enter_timeout_ms(mutex_hdl, msec); - } - - static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) - { - mutex_exit(mutex_hdl); - return true; - } +//--------------------------------------------------------------------+ +// TASK API +//--------------------------------------------------------------------+ +static inline void osal_task_delay(uint32_t msec) +{ + sleep_ms(msec); +} + +//--------------------------------------------------------------------+ +// Binary Semaphore API +//--------------------------------------------------------------------+ +typedef struct semaphore osal_semaphore_def_t, *osal_semaphore_t; + +static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) +{ + sem_init(semdef, 0, 255); + return semdef; +} + +static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) +{ + (void) in_isr; + sem_release(sem_hdl); + return true; +} + +static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) +{ + return sem_acquire_timeout_ms(sem_hdl, msec); +} + +static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) +{ + sem_reset(sem_hdl, 0); +} + +//--------------------------------------------------------------------+ +// MUTEX API +// Within tinyusb, mutex is never used in ISR context +//--------------------------------------------------------------------+ +typedef struct mutex osal_mutex_def_t, *osal_mutex_t; + +static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) +{ + mutex_init(mdef); + return mdef; +} + +static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) +{ + return mutex_enter_timeout_ms(mutex_hdl, msec); +} + +static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) +{ + mutex_exit(mutex_hdl); + return true; +} //--------------------------------------------------------------------+ // QUEUE API @@ -102,86 +101,87 @@ extern "C" #include "common/tusb_fifo.h" #if TUSB_OPT_HOST_ENABLED - extern void hcd_int_disable(uint8_t rhport); - extern void hcd_int_enable(uint8_t rhport); +extern void hcd_int_disable(uint8_t rhport); +extern void hcd_int_enable(uint8_t rhport); #endif - typedef struct - { - tu_fifo_t ff; - struct critical_section critsec; // osal_queue may be used in IRQs, so need critical section - } osal_queue_def_t; +typedef struct +{ + tu_fifo_t ff; + struct critical_section critsec; // osal_queue may be used in IRQs, so need critical section +} osal_queue_def_t; - typedef osal_queue_def_t *osal_queue_t; +typedef osal_queue_def_t* osal_queue_t; // role device/host is used by OS NONE for mutex (disable usb isr) only -#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \ - uint8_t _name##_buf[_depth * sizeof(_type)]; \ - osal_queue_def_t _name = { \ - .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false)} - - // lock queue by disable USB interrupt - static inline void _osal_q_lock(osal_queue_t qhdl) - { - critical_section_enter_blocking(&qhdl->critsec); - } - - // unlock queue - static inline void _osal_q_unlock(osal_queue_t qhdl) - { - critical_section_exit(&qhdl->critsec); - } - - static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) - { - critical_section_init(&qdef->critsec); - tu_fifo_clear(&qdef->ff); - return (osal_queue_t)qdef; - } - - static inline bool osal_queue_receive(osal_queue_t qhdl, void *data) - { - // TODO: revisit... docs say that mutexes are never used from IRQ context, - // however osal_queue_recieve may be. therefore my assumption is that - // the fifo mutex is not populated for queues used from an IRQ context - // assert(!qhdl->ff.mutex); - - _osal_q_lock(qhdl); - bool success = tu_fifo_read(&qhdl->ff, data); - _osal_q_unlock(qhdl); - - return success; - } - - static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) - { - // TODO: revisit... docs say that mutexes are never used from IRQ context, - // however osal_queue_recieve may be. therefore my assumption is that - // the fifo mutex is not populated for queues used from an IRQ context - // assert(!qhdl->ff.mutex); - (void)in_isr; - - _osal_q_lock(qhdl); - bool success = tu_fifo_write(&qhdl->ff, data); - _osal_q_unlock(qhdl); - - TU_ASSERT(success); - - return success; - } - - static inline bool osal_queue_empty(osal_queue_t qhdl) - { - // TODO: revisit; whether this is true or not currently, tu_fifo_empty is a single - // volatile read. - - // Skip queue lock/unlock since this function is primarily called - // with interrupt disabled before going into low power mode - return tu_fifo_empty(&qhdl->ff); - } +#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \ + uint8_t _name##_buf[_depth*sizeof(_type)]; \ + osal_queue_def_t _name = { \ + .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \ + } + +// lock queue by disable USB interrupt +static inline void _osal_q_lock(osal_queue_t qhdl) +{ + critical_section_enter_blocking(&qhdl->critsec); +} -#ifdef __cplusplus +// unlock queue +static inline void _osal_q_unlock(osal_queue_t qhdl) +{ + critical_section_exit(&qhdl->critsec); +} + +static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) +{ + critical_section_init(&qdef->critsec); + tu_fifo_clear(&qdef->ff); + return (osal_queue_t) qdef; +} + +static inline bool osal_queue_receive(osal_queue_t qhdl, void* data) +{ + // TODO: revisit... docs say that mutexes are never used from IRQ context, + // however osal_queue_recieve may be. therefore my assumption is that + // the fifo mutex is not populated for queues used from an IRQ context + //assert(!qhdl->ff.mutex); + + _osal_q_lock(qhdl); + bool success = tu_fifo_read(&qhdl->ff, data); + _osal_q_unlock(qhdl); + + return success; +} + +static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) +{ + // TODO: revisit... docs say that mutexes are never used from IRQ context, + // however osal_queue_recieve may be. therefore my assumption is that + // the fifo mutex is not populated for queues used from an IRQ context + //assert(!qhdl->ff.mutex); + (void) in_isr; + + _osal_q_lock(qhdl); + bool success = tu_fifo_write(&qhdl->ff, data); + _osal_q_unlock(qhdl); + + TU_ASSERT(success); + + return success; } + +static inline bool osal_queue_empty(osal_queue_t qhdl) +{ + // TODO: revisit; whether this is true or not currently, tu_fifo_empty is a single + // volatile read. + + // Skip queue lock/unlock since this function is primarily called + // with interrupt disabled before going into low power mode + return tu_fifo_empty(&qhdl->ff); +} + +#ifdef __cplusplus + } #endif #endif /* _TUSB_OSAL_PICO_H_ */ diff --git a/uCNC/src/tinyusb/src/osal/osal_rtthread.h b/uCNC/src/tinyusb/src/osal/osal_rtthread.h index 15ed0c7d1..d5c062ac1 100644 --- a/uCNC/src/tinyusb/src/osal/osal_rtthread.h +++ b/uCNC/src/tinyusb/src/osal/osal_rtthread.h @@ -31,68 +31,59 @@ #include "rtthread.h" #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif - //--------------------------------------------------------------------+ - // TASK API - //--------------------------------------------------------------------+ - static inline void osal_task_delay(uint32_t msec) - { - rt_thread_mdelay(msec); - } - - //--------------------------------------------------------------------+ - // Semaphore API - //--------------------------------------------------------------------+ - typedef struct rt_semaphore osal_semaphore_def_t; - typedef rt_sem_t osal_semaphore_t; - - static inline osal_semaphore_t - osal_semaphore_create(osal_semaphore_def_t *semdef) - { - rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_FIFO); - return semdef; - } - - static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) - { - (void)in_isr; - return rt_sem_release(sem_hdl) == RT_EOK; - } - - static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) - { - return rt_sem_take(sem_hdl, rt_tick_from_millisecond(msec)) == RT_EOK; - } - - static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) - { - // TODO: implement - } - - //--------------------------------------------------------------------+ - // MUTEX API (priority inheritance) - //--------------------------------------------------------------------+ - typedef struct rt_mutex osal_mutex_def_t; - typedef rt_mutex_t osal_mutex_t; - - static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) - { - rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_FIFO); - return mdef; - } - - static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) - { - return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond(msec)) == RT_EOK; - } - - static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) - { - return rt_mutex_release(mutex_hdl) == RT_EOK; - } +//--------------------------------------------------------------------+ +// TASK API +//--------------------------------------------------------------------+ +static inline void osal_task_delay(uint32_t msec) { + rt_thread_mdelay(msec); +} + +//--------------------------------------------------------------------+ +// Semaphore API +//--------------------------------------------------------------------+ +typedef struct rt_semaphore osal_semaphore_def_t; +typedef rt_sem_t osal_semaphore_t; + +static inline osal_semaphore_t +osal_semaphore_create(osal_semaphore_def_t *semdef) { + rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_FIFO); + return semdef; +} + +static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { + (void) in_isr; + return rt_sem_release(sem_hdl) == RT_EOK; +} + +static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { + return rt_sem_take(sem_hdl, rt_tick_from_millisecond(msec)) == RT_EOK; +} + +static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) { + // TODO: implement +} + +//--------------------------------------------------------------------+ +// MUTEX API (priority inheritance) +//--------------------------------------------------------------------+ +typedef struct rt_mutex osal_mutex_def_t; +typedef rt_mutex_t osal_mutex_t; + +static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) { + rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_FIFO); + return mdef; +} + +static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) { + return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond(msec)) == RT_EOK; +} + +static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { + return rt_mutex_release(mutex_hdl) == RT_EOK; +} //--------------------------------------------------------------------+ // QUEUE API @@ -100,42 +91,37 @@ extern "C" // role device/host is used by OS NONE for mutex (disable usb isr) only #define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \ - static _type _name##_##buf[_depth]; \ - osal_queue_def_t _name = {.depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf}; - - typedef struct - { - uint16_t depth; - uint16_t item_sz; - void *buf; - - struct rt_messagequeue sq; - } osal_queue_def_t; - - typedef rt_mq_t osal_queue_t; - - static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) - { - rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz, - qdef->item_sz * qdef->depth, RT_IPC_FLAG_FIFO); - return &(qdef->sq); - } - - static inline bool osal_queue_receive(osal_queue_t qhdl, void *data) - { - return rt_mq_recv(qhdl, data, qhdl->msg_size, RT_WAITING_FOREVER) == RT_EOK; - } - - static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) - { - (void)in_isr; - return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK; - } - - static inline bool osal_queue_empty(osal_queue_t qhdl) - { - return (qhdl->entry) == 0; - } + static _type _name##_##buf[_depth]; \ + osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf }; + +typedef struct { + uint16_t depth; + uint16_t item_sz; + void *buf; + + struct rt_messagequeue sq; +} osal_queue_def_t; + +typedef rt_mq_t osal_queue_t; + +static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) { + rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz, + qdef->item_sz * qdef->depth, RT_IPC_FLAG_FIFO); + return &(qdef->sq); +} + +static inline bool osal_queue_receive(osal_queue_t qhdl, void *data) { + return rt_mq_recv(qhdl, data, qhdl->msg_size, RT_WAITING_FOREVER) == RT_EOK; +} + +static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) { + (void) in_isr; + return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK; +} + +static inline bool osal_queue_empty(osal_queue_t qhdl) { + return (qhdl->entry) == 0; +} #ifdef __cplusplus } diff --git a/uCNC/src/tinyusb/src/osal/osal_rtx4.h b/uCNC/src/tinyusb/src/osal/osal_rtx4.h new file mode 100644 index 000000000..f7e88e322 --- /dev/null +++ b/uCNC/src/tinyusb/src/osal/osal_rtx4.h @@ -0,0 +1,170 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Tian Yunhao (t123yh) + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_OSAL_RTX4_H_ +#define _TUSB_OSAL_RTX4_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------+ +// TASK API +//--------------------------------------------------------------------+ +static inline void osal_task_delay(uint32_t msec) +{ + uint16_t hi = msec >> 16; + uint16_t lo = msec; + while (hi--) { + os_dly_wait(0xFFFE); + } + os_dly_wait(lo); +} + +static inline uint16_t msec2wait(uint32_t msec) { + if (msec == OSAL_TIMEOUT_WAIT_FOREVER) + return 0xFFFF; + else if (msec >= 0xFFFE) + return 0xFFFE; + else + return msec; +} + +//--------------------------------------------------------------------+ +// Semaphore API +//--------------------------------------------------------------------+ +typedef OS_SEM osal_semaphore_def_t; +typedef OS_ID osal_semaphore_t; + +static inline OS_ID osal_semaphore_create(osal_semaphore_def_t* semdef) { + os_sem_init(semdef, 0); + return semdef; +} + +static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { + if ( !in_isr ) { + os_sem_send(sem_hdl); + } else { + isr_sem_send(sem_hdl); + } + return true; +} + +static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) { + return os_sem_wait(sem_hdl, msec2wait(msec)) != OS_R_TMO; +} + +static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) { + // TODO: implement +} + +//--------------------------------------------------------------------+ +// MUTEX API (priority inheritance) +//--------------------------------------------------------------------+ +typedef OS_MUT osal_mutex_def_t; +typedef OS_ID osal_mutex_t; + +static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) +{ + os_mut_init(mdef); + return mdef; +} + +static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) +{ + return os_mut_wait(mutex_hdl, msec2wait(msec)) != OS_R_TMO; +} + +static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) +{ + return os_mut_release(mutex_hdl) == OS_R_OK; +} + +//--------------------------------------------------------------------+ +// QUEUE API +//--------------------------------------------------------------------+ + +// role device/host is used by OS NONE for mutex (disable usb isr) only +#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \ + os_mbx_declare(_name##__mbox, _depth); \ + _declare_box(_name##__pool, sizeof(_type), _depth); \ + osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .pool = _name##__pool, .mbox = _name##__mbox }; + + +typedef struct +{ + uint16_t depth; + uint16_t item_sz; + U32* pool; + U32* mbox; +}osal_queue_def_t; + +typedef osal_queue_def_t* osal_queue_t; + +static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) +{ + os_mbx_init(qdef->mbox, (qdef->depth + 4) * 4); + _init_box(qdef->pool, ((qdef->item_sz+3)/4)*(qdef->depth) + 3, qdef->item_sz); + return qdef; +} + +static inline bool osal_queue_receive(osal_queue_t qhdl, void* data) +{ + void* buf; + os_mbx_wait(qhdl->mbox, &buf, 0xFFFF); + memcpy(data, buf, qhdl->item_sz); + _free_box(qhdl->pool, buf); + return true; +} + +static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) +{ + void* buf = _alloc_box(qhdl->pool); + memcpy(buf, data, qhdl->item_sz); + if ( !in_isr ) + { + os_mbx_send(qhdl->mbox, buf, 0xFFFF); + } + else + { + isr_mbx_send(qhdl->mbox, buf); + } + return true; +} + +static inline bool osal_queue_empty(osal_queue_t qhdl) +{ + return os_mbx_check(qhdl->mbox) == qhdl->depth; +} + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/uCNC/src/tinyusb/src/portable/espressif/esp32sx/dcd_esp32sx.c b/uCNC/src/tinyusb/src/portable/espressif/esp32sx/dcd_esp32sx.c index 991a96a06..ee88b031a 100644 --- a/uCNC/src/tinyusb/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/uCNC/src/tinyusb/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -40,7 +40,7 @@ #include "soc/usb_periph.h" #include "soc/periph_defs.h" // for interrupt source -#include "device/dcd.h" +#include "../../../device/dcd.h" // Max number of bi-directional endpoints including EP0 // Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0 @@ -55,12 +55,12 @@ typedef struct { - uint8_t *buffer; - // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API - uint16_t total_len; - uint16_t queued_len; - uint16_t max_size; - bool short_packet; + uint8_t *buffer; + // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API + uint16_t total_len; + uint16_t queued_len; + uint16_t max_size; + bool short_packet; } xfer_ctl_t; static const char *TAG = "TUSB:DCD"; @@ -77,89 +77,89 @@ static uint8_t _allocated_fifos = 1; // FIFO0 is always in use // Will either return an unused FIFO number, or 0 if all are used. static uint8_t get_free_fifo(void) { - if (_allocated_fifos < EP_FIFO_NUM) - return _allocated_fifos++; - return 0; + if (_allocated_fifos < EP_FIFO_NUM) + return _allocated_fifos++; + return 0; } // Setup the control endpoint 0. static void bus_reset(void) { - for (int ep_num = 0; ep_num < USB_OUT_EP_NUM; ep_num++) - { - USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK - } - - // clear device address - USB0.dcfg &= ~USB_DEVADDR_M; - - USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M; - USB0.doepmsk = USB_SETUPMSK_M | USB_XFERCOMPLMSK; - USB0.diepmsk = USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/; - - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO MAX | - // --------------- - // | ... | - // --------------- y + x + 16 + GRXFSIZ - // | IN FIFO 2 | - // --------------- x + 16 + GRXFSIZ - // | IN FIFO 1 | - // --------------- 16 + GRXFSIZ - // | IN FIFO 0 | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): - // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN - // - // - All EP OUT shared a unique OUT FIFO which uses - // * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets). - // * 2 locations for OUT endpoint control words. - // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes) - // * 1 location for global NAK (not required/used here). - // * It is recommended to allocate 2 times the largest packet size, therefore - // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52 - USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10, - USB0.grstctl |= USB_TXFFLSH_M; // Flush fifo - USB0.grxfsiz = 52; - - // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL); - - // Ready to receive SETUP packet - USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M; - - USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M; + for (int ep_num = 0; ep_num < USB_OUT_EP_NUM; ep_num++) + { + USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK + } + + // clear device address + USB0.dcfg &= ~USB_DEVADDR_M; + + USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M; + USB0.doepmsk = USB_SETUPMSK_M | USB_XFERCOMPLMSK; + USB0.diepmsk = USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/; + + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO MAX | + // --------------- + // | ... | + // --------------- y + x + 16 + GRXFSIZ + // | IN FIFO 2 | + // --------------- x + 16 + GRXFSIZ + // | IN FIFO 1 | + // --------------- 16 + GRXFSIZ + // | IN FIFO 0 | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): + // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN + // + // - All EP OUT shared a unique OUT FIFO which uses + // * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets). + // * 2 locations for OUT endpoint control words. + // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes) + // * 1 location for global NAK (not required/used here). + // * It is recommended to allocate 2 times the largest packet size, therefore + // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52 + USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10, + USB0.grstctl |= USB_TXFFLSH_M; // Flush fifo + USB0.grxfsiz = 52; + + // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) + USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL); + + // Ready to receive SETUP packet + USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M; + + USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M; } static void enum_done_processing(void) { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); - // On current silicon on the Full Speed core, speed is fixed to Full Speed. - // However, keep for debugging and in case Low Speed is ever supported. - uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V); - - // Maximum packet size for EP 0 is set for both directions by writing DIEPCTL - if (enum_spd == 0x03) - { // Full-Speed (PHY on 48 MHz) - USB0.in_ep_reg[0].diepctl &= ~USB_D_MPS0_V; // 64 bytes - USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall - xfer_status[0][TUSB_DIR_OUT].max_size = 64; - xfer_status[0][TUSB_DIR_IN].max_size = 64; - } - else - { - USB0.in_ep_reg[0].diepctl |= USB_D_MPS0_V; // 8 bytes - USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall - xfer_status[0][TUSB_DIR_OUT].max_size = 8; - xfer_status[0][TUSB_DIR_IN].max_size = 8; - } + ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then"); + // On current silicon on the Full Speed core, speed is fixed to Full Speed. + // However, keep for debugging and in case Low Speed is ever supported. + uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V); + + // Maximum packet size for EP 0 is set for both directions by writing DIEPCTL + if (enum_spd == 0x03) + { // Full-Speed (PHY on 48 MHz) + USB0.in_ep_reg[0].diepctl &= ~USB_D_MPS0_V; // 64 bytes + USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall + xfer_status[0][TUSB_DIR_OUT].max_size = 64; + xfer_status[0][TUSB_DIR_IN].max_size = 64; + } + else + { + USB0.in_ep_reg[0].diepctl |= USB_D_MPS0_V; // 8 bytes + USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall + xfer_status[0][TUSB_DIR_OUT].max_size = 8; + xfer_status[0][TUSB_DIR_IN].max_size = 8; + } } /*------------------------------------------------------------------*/ @@ -167,83 +167,83 @@ static void enum_done_processing(void) *------------------------------------------------------------------*/ void dcd_init(uint8_t rhport) { - ESP_LOGV(TAG, "DCD init - Start"); - - // A. Disconnect - ESP_LOGV(TAG, "DCD init - Soft DISCONNECT and Setting up"); - USB0.dctl |= USB_SFTDISCON_M; // Soft disconnect - - // B. Programming DCFG - /* If USB host misbehaves during status portion of control xfer - (non zero-length packet), send STALL back and discard. Full speed. */ - USB0.dcfg |= USB_NZSTSOUTHSHK_M | // NonZero .... STALL - (3 << 0); // dev speed: fullspeed 1.1 on 48 mhz // TODO no value in usb_reg.h (IDF-1476) - - USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON - USB0.gusbcfg |= USB_FORCEDEVMODE_M; // force devmode - USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); // no overrides - - // C. Setting SNAKs, then connect - for (int n = 0; n < USB_OUT_EP_NUM; n++) - { - USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK - } - - // D. Interruption masking - USB0.gintmsk = 0; // mask all - USB0.gotgint = ~0U; // clear OTG ints - USB0.gintsts = ~0U; // clear pending ints - USB0.gintmsk = USB_OTGINTMSK_M | - USB_MODEMISMSK_M | - USB_RXFLVIMSK_M | - USB_ERLYSUSPMSK_M | - USB_USBSUSPMSK_M | - USB_USBRSTMSK_M | - USB_ENUMDONEMSK_M | - USB_RESETDETMSK_M | - USB_DISCONNINTMSK_M; // host most only - - dcd_connect(rhport); + ESP_LOGV(TAG, "DCD init - Start"); + + // A. Disconnect + ESP_LOGV(TAG, "DCD init - Soft DISCONNECT and Setting up"); + USB0.dctl |= USB_SFTDISCON_M; // Soft disconnect + + // B. Programming DCFG + /* If USB host misbehaves during status portion of control xfer + (non zero-length packet), send STALL back and discard. Full speed. */ + USB0.dcfg |= USB_NZSTSOUTHSHK_M | // NonZero .... STALL + (3 << 0); // dev speed: fullspeed 1.1 on 48 mhz // TODO no value in usb_reg.h (IDF-1476) + + USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON + USB0.gusbcfg |= USB_FORCEDEVMODE_M; // force devmode + USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); // no overrides + + // C. Setting SNAKs, then connect + for (int n = 0; n < USB_OUT_EP_NUM; n++) + { + USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK + } + + // D. Interruption masking + USB0.gintmsk = 0; // mask all + USB0.gotgint = ~0U; // clear OTG ints + USB0.gintsts = ~0U; // clear pending ints + USB0.gintmsk = USB_OTGINTMSK_M | + USB_MODEMISMSK_M | + USB_RXFLVIMSK_M | + USB_ERLYSUSPMSK_M | + USB_USBSUSPMSK_M | + USB_USBRSTMSK_M | + USB_ENUMDONEMSK_M | + USB_RESETDETMSK_M | + USB_DISCONNINTMSK_M; // host most only + + dcd_connect(rhport); } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void)rhport; - ESP_LOGV(TAG, "DCD init - Set address : %u", dev_addr); - USB0.dcfg |= ((dev_addr & USB_DEVADDR_V) << USB_DEVADDR_S); - // Response with status after changing device address - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); + (void)rhport; + ESP_LOGV(TAG, "DCD init - Set address : %u", dev_addr); + USB0.dcfg |= ((dev_addr & USB_DEVADDR_V) << USB_DEVADDR_S); + // Response with status after changing device address + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } void dcd_remote_wakeup(uint8_t rhport) { - (void)rhport; + (void)rhport; - // set remote wakeup - USB0.dctl |= USB_RMTWKUPSIG_M; + // set remote wakeup + USB0.dctl |= USB_RMTWKUPSIG_M; - // enable SOF to detect bus resume - USB0.gintsts = USB_SOF_M; - USB0.gintmsk |= USB_SOFMSK_M; + // enable SOF to detect bus resume + USB0.gintsts = USB_SOF_M; + USB0.gintmsk |= USB_SOFMSK_M; - // Per specs: remote wakeup signal bit must be clear within 1-15ms - vTaskDelay(pdMS_TO_TICKS(1)); + // Per specs: remote wakeup signal bit must be clear within 1-15ms + vTaskDelay(pdMS_TO_TICKS(1)); - USB0.dctl &= ~USB_RMTWKUPSIG_M; + USB0.dctl &= ~USB_RMTWKUPSIG_M; } // connect by enabling internal pull-up resistor on D+/D- void dcd_connect(uint8_t rhport) { - (void)rhport; - USB0.dctl &= ~USB_SFTDISCON_M; + (void)rhport; + USB0.dctl &= ~USB_SFTDISCON_M; } // disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { - (void)rhport; - USB0.dctl |= USB_SFTDISCON_M; + (void)rhport; + USB0.dctl |= USB_SFTDISCON_M; } /*------------------------------------------------------------------*/ @@ -252,149 +252,149 @@ void dcd_disconnect(uint8_t rhport) bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { - ESP_LOGV(TAG, "DCD endpoint opened"); - (void)rhport; - - usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); - usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); - - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - - TU_ASSERT(epnum < EP_MAX); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = tu_edpt_packet_size(desc_edpt); - - if (dir == TUSB_DIR_OUT) - { - out_ep[epnum].doepctl |= USB_USBACTEP1_M | - desc_edpt->bmAttributes.xfer << USB_EPTYPE1_S | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_DO_SETD0PID1_M : 0) | - xfer->max_size << USB_MPS1_S; - USB0.daintmsk |= (1 << (16 + epnum)); - } - else - { - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO MAX | - // --------------- - // | ... | - // --------------- y + x + 16 + GRXFSIZ - // | IN FIFO 2 | - // --------------- x + 16 + GRXFSIZ - // | IN FIFO 1 | - // --------------- 16 + GRXFSIZ - // | IN FIFO 0 | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints - // - Size : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1) - // - Offset: GRXFSIZ + 16 + Size*(epnum-1) - // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". - - uint8_t fifo_num = get_free_fifo(); - TU_ASSERT(fifo_num != 0); - - in_ep[epnum].diepctl &= ~(USB_D_TXFNUM1_M | USB_D_EPTYPE1_M | USB_DI_SETD0PID1 | USB_D_MPS1_M); - in_ep[epnum].diepctl |= USB_D_USBACTEP1_M | - fifo_num << USB_D_TXFNUM1_S | - desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) | - xfer->max_size << 0; - - USB0.daintmsk |= (1 << (0 + epnum)); - - // Both TXFD and TXSA are in unit of 32-bit words. - // IN FIFO 0 was configured during enumeration, hence the "+ 16". - uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16; - uint16_t const fifo_size = (EP_FIFO_SIZE / 4 - allocated_size) / (EP_FIFO_NUM - 1); - uint32_t const fifo_offset = allocated_size + fifo_size * (fifo_num - 1); - - // DIEPTXF starts at FIFO #1. - USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset; - } - return true; + ESP_LOGV(TAG, "DCD endpoint opened"); + (void)rhport; + + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + TU_ASSERT(epnum < EP_MAX); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = tu_edpt_packet_size(desc_edpt); + + if (dir == TUSB_DIR_OUT) + { + out_ep[epnum].doepctl |= USB_USBACTEP1_M | + desc_edpt->bmAttributes.xfer << USB_EPTYPE1_S | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_DO_SETD0PID1_M : 0) | + xfer->max_size << USB_MPS1_S; + USB0.daintmsk |= (1 << (16 + epnum)); + } + else + { + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO MAX | + // --------------- + // | ... | + // --------------- y + x + 16 + GRXFSIZ + // | IN FIFO 2 | + // --------------- x + 16 + GRXFSIZ + // | IN FIFO 1 | + // --------------- 16 + GRXFSIZ + // | IN FIFO 0 | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints + // - Size : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1) + // - Offset: GRXFSIZ + 16 + Size*(epnum-1) + // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". + + uint8_t fifo_num = get_free_fifo(); + TU_ASSERT(fifo_num != 0); + + in_ep[epnum].diepctl &= ~(USB_D_TXFNUM1_M | USB_D_EPTYPE1_M | USB_DI_SETD0PID1 | USB_D_MPS1_M); + in_ep[epnum].diepctl |= USB_D_USBACTEP1_M | + fifo_num << USB_D_TXFNUM1_S | + desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) | + xfer->max_size << 0; + + USB0.daintmsk |= (1 << (0 + epnum)); + + // Both TXFD and TXSA are in unit of 32-bit words. + // IN FIFO 0 was configured during enumeration, hence the "+ 16". + uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16; + uint16_t const fifo_size = (EP_FIFO_SIZE / 4 - allocated_size) / (EP_FIFO_NUM - 1); + uint32_t const fifo_offset = allocated_size + fifo_size * (fifo_num - 1); + + // DIEPTXF starts at FIFO #1. + USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset; + } + return true; } void dcd_edpt_close_all(uint8_t rhport) { - (void)rhport; + (void)rhport; - usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); - usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); - // Disable non-control interrupt - USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M; + // Disable non-control interrupt + USB0.daintmsk = USB_OUTEPMSK0_M | USB_INEPMSK0_M; - for (uint8_t n = 1; n < EP_MAX; n++) - { - // disable OUT endpoint - out_ep[n].doepctl = 0; - xfer_status[n][TUSB_DIR_OUT].max_size = 0; + for (uint8_t n = 1; n < EP_MAX; n++) + { + // disable OUT endpoint + out_ep[n].doepctl = 0; + xfer_status[n][TUSB_DIR_OUT].max_size = 0; - // disable IN endpoint - in_ep[n].diepctl = 0; - xfer_status[n][TUSB_DIR_IN].max_size = 0; - } + // disable IN endpoint + in_ep[n].diepctl = 0; + xfer_status[n][TUSB_DIR_IN].max_size = 0; + } - _allocated_fifos = 1; + _allocated_fifos = 1; } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API - xfer->total_len = total_bytes; - xfer->queued_len = 0; - xfer->short_packet = false; - - uint16_t num_packets = (total_bytes / xfer->max_size); - uint8_t short_packet_size = total_bytes % xfer->max_size; - - // Zero-size packet is special case. - if (short_packet_size > 0 || (total_bytes == 0)) - { - num_packets++; - } - - ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i", - epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"), - num_packets, total_bytes); - - // IN and OUT endpoint xfers are interrupt-driven, we just schedule them - // here. - if (dir == TUSB_DIR_IN) - { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes; - USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK - - // Enable fifo empty interrupt only if there are something to put in the fifo. - if (total_bytes != 0) - { - USB0.dtknqr4_fifoemptymsk |= (1 << epnum); - } - } - else - { - // Each complete packet for OUT xfers triggers XFRC. - USB0.out_ep_reg[epnum].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); - USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M; - } - return true; + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->short_packet = false; + + uint16_t num_packets = (total_bytes / xfer->max_size); + uint8_t short_packet_size = total_bytes % xfer->max_size; + + // Zero-size packet is special case. + if (short_packet_size > 0 || (total_bytes == 0)) + { + num_packets++; + } + + ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i", + epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"), + num_packets, total_bytes); + + // IN and OUT endpoint xfers are interrupt-driven, we just schedule them + // here. + if (dir == TUSB_DIR_IN) + { + // A full IN transfer (multiple packets, possibly) triggers XFRC. + USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes; + USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK + + // Enable fifo empty interrupt only if there are something to put in the fifo. + if (total_bytes != 0) + { + USB0.dtknqr4_fifoemptymsk |= (1 << epnum); + } + } + else + { + // Each complete packet for OUT xfers triggers XFRC. + USB0.out_ep_reg[epnum].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); + USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M; + } + return true; } #if 0 // TODO support dcd_edpt_xfer_fifo API @@ -406,135 +406,135 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); - usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (dir == TUSB_DIR_IN) - { - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(in_ep[epnum].diepctl & USB_D_EPENA1_M)) - { - in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M); - } - else - { - // Stop transmitting packets and NAK IN xfers. - in_ep[epnum].diepctl |= USB_DI_SNAK1_M; - while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) - ; - - // Disable the endpoint. Note that both SNAK and STALL are set here. - in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | USB_D_EPDIS1_M); - while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0) - ; - in_ep[epnum].diepint = USB_D_EPDISBLD0_M; - } - - // Flush the FIFO, and wait until we have confirmed it cleared. - uint8_t const fifo_num = ((in_ep[epnum].diepctl >> USB_D_TXFNUM1_S) & USB_D_TXFNUM1_V); - USB0.grstctl |= (fifo_num << USB_TXFNUM_S); - USB0.grstctl |= USB_TXFFLSH_M; - while ((USB0.grstctl & USB_TXFFLSH_M) != 0) - ; - } - else - { - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) - { - out_ep[epnum].doepctl |= USB_STALL0_M; - } - else - { - // Asserting GONAK is required to STALL an OUT endpoint. - // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt - // anyway, and it can't be cleared by user code. If this while loop never - // finishes, we have bigger problems than just the stack. - USB0.dctl |= USB_SGOUTNAK_M; - while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0) - ; - - // Ditto here- disable the endpoint. Note that only STALL and not SNAK - // is set here. - out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M); - while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0) - ; - out_ep[epnum].doepint = USB_EPDISBLD0_M; - - // Allow other OUT endpoints to keep receiving. - USB0.dctl |= USB_CGOUTNAK_M; - } - } + (void)rhport; + + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (dir == TUSB_DIR_IN) + { + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(in_ep[epnum].diepctl & USB_D_EPENA1_M)) + { + in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M); + } + else + { + // Stop transmitting packets and NAK IN xfers. + in_ep[epnum].diepctl |= USB_DI_SNAK1_M; + while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) + ; + + // Disable the endpoint. Note that both SNAK and STALL are set here. + in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | USB_D_EPDIS1_M); + while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0) + ; + in_ep[epnum].diepint = USB_D_EPDISBLD0_M; + } + + // Flush the FIFO, and wait until we have confirmed it cleared. + uint8_t const fifo_num = ((in_ep[epnum].diepctl >> USB_D_TXFNUM1_S) & USB_D_TXFNUM1_V); + USB0.grstctl |= (fifo_num << USB_TXFNUM_S); + USB0.grstctl |= USB_TXFFLSH_M; + while ((USB0.grstctl & USB_TXFFLSH_M) != 0) + ; + } + else + { + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) + { + out_ep[epnum].doepctl |= USB_STALL0_M; + } + else + { + // Asserting GONAK is required to STALL an OUT endpoint. + // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt + // anyway, and it can't be cleared by user code. If this while loop never + // finishes, we have bigger problems than just the stack. + USB0.dctl |= USB_SGOUTNAK_M; + while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0) + ; + + // Ditto here- disable the endpoint. Note that only STALL and not SNAK + // is set here. + out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M); + while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0) + ; + out_ep[epnum].doepint = USB_EPDISBLD0_M; + + // Allow other OUT endpoints to keep receiving. + USB0.dctl |= USB_CGOUTNAK_M; + } + } } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); - usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (dir == TUSB_DIR_IN) - { - in_ep[epnum].diepctl &= ~USB_D_STALL1_M; - - uint8_t eptype = (in_ep[epnum].diepctl & USB_D_EPTYPE1_M) >> USB_D_EPTYPE1_S; - // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt - // and bulk endpoints. - if (eptype == 2 || eptype == 3) - { - in_ep[epnum].diepctl |= USB_DI_SETD0PID1_M; - } - } - else - { - out_ep[epnum].doepctl &= ~USB_STALL1_M; - - uint8_t eptype = (out_ep[epnum].doepctl & USB_EPTYPE1_M) >> USB_EPTYPE1_S; - // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt - // and bulk endpoints. - if (eptype == 2 || eptype == 3) - { - out_ep[epnum].doepctl |= USB_DO_SETD0PID1_M; - } - } + (void)rhport; + + usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]); + usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (dir == TUSB_DIR_IN) + { + in_ep[epnum].diepctl &= ~USB_D_STALL1_M; + + uint8_t eptype = (in_ep[epnum].diepctl & USB_D_EPTYPE1_M) >> USB_D_EPTYPE1_S; + // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt + // and bulk endpoints. + if (eptype == 2 || eptype == 3) + { + in_ep[epnum].diepctl |= USB_DI_SETD0PID1_M; + } + } + else + { + out_ep[epnum].doepctl &= ~USB_STALL1_M; + + uint8_t eptype = (out_ep[epnum].doepctl & USB_EPTYPE1_M) >> USB_EPTYPE1_S; + // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt + // and bulk endpoints. + if (eptype == 2 || eptype == 3) + { + out_ep[epnum].doepctl |= USB_DO_SETD0PID1_M; + } + } } /*------------------------------------------------------------------*/ static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ uint16_t xfer_size) { - ESP_EARLY_LOGV(TAG, "USB - receive_packet"); - volatile uint32_t *rx_fifo = USB0.fifo[0]; - - // See above TODO - // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos; - // xfer->queued_len = xfer->total_len - remaining; - - uint16_t remaining = xfer->total_len - xfer->queued_len; - uint16_t to_recv_size; - - if (remaining <= xfer->max_size) - { - // Avoid buffer overflow. - to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; - } - else - { - // Room for full packet, choose recv_size based on what the microcontroller - // claims. - to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; - } - - // Common buffer read + ESP_EARLY_LOGV(TAG, "USB - receive_packet"); + volatile uint32_t *rx_fifo = USB0.fifo[0]; + + // See above TODO + // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos; + // xfer->queued_len = xfer->total_len - remaining; + + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint16_t to_recv_size; + + if (remaining <= xfer->max_size) + { + // Avoid buffer overflow. + to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; + } + else + { + // Room for full packet, choose recv_size based on what the microcontroller + // claims. + to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; + } + + // Common buffer read #if 0 // TODO support dcd_edpt_xfer_fifo API if (xfer->ff) { @@ -543,61 +543,61 @@ static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ } else #endif - { - uint8_t to_recv_rem = to_recv_size % 4; - uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem; - - // Do not assume xfer buffer is aligned. - uint8_t *base = (xfer->buffer + xfer->queued_len); - - // This for loop always runs at least once- skip if less than 4 bytes - // to collect. - if (to_recv_size >= 4) - { - for (uint16_t i = 0; i < to_recv_size_aligned; i += 4) - { - uint32_t tmp = (*rx_fifo); - base[i] = tmp & 0x000000FF; - base[i + 1] = (tmp & 0x0000FF00) >> 8; - base[i + 2] = (tmp & 0x00FF0000) >> 16; - base[i + 3] = (tmp & 0xFF000000) >> 24; - } - } - - // Do not read invalid bytes from RX FIFO. - if (to_recv_rem != 0) - { - uint32_t tmp = (*rx_fifo); - uint8_t *last_32b_bound = base + to_recv_size_aligned; - - last_32b_bound[0] = tmp & 0x000000FF; - if (to_recv_rem > 1) - { - last_32b_bound[1] = (tmp & 0x0000FF00) >> 8; - } - if (to_recv_rem > 2) - { - last_32b_bound[2] = (tmp & 0x00FF0000) >> 16; - } - } - } - - xfer->queued_len += xfer_size; - - // Per USB spec, a short OUT packet (including length 0) is always - // indicative of the end of a transfer (at least for ctl, bulk, int). - xfer->short_packet = (xfer_size < xfer->max_size); + { + uint8_t to_recv_rem = to_recv_size % 4; + uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem; + + // Do not assume xfer buffer is aligned. + uint8_t *base = (xfer->buffer + xfer->queued_len); + + // This for loop always runs at least once- skip if less than 4 bytes + // to collect. + if (to_recv_size >= 4) + { + for (uint16_t i = 0; i < to_recv_size_aligned; i += 4) + { + uint32_t tmp = (*rx_fifo); + base[i] = tmp & 0x000000FF; + base[i + 1] = (tmp & 0x0000FF00) >> 8; + base[i + 2] = (tmp & 0x00FF0000) >> 16; + base[i + 3] = (tmp & 0xFF000000) >> 24; + } + } + + // Do not read invalid bytes from RX FIFO. + if (to_recv_rem != 0) + { + uint32_t tmp = (*rx_fifo); + uint8_t *last_32b_bound = base + to_recv_size_aligned; + + last_32b_bound[0] = tmp & 0x000000FF; + if (to_recv_rem > 1) + { + last_32b_bound[1] = (tmp & 0x0000FF00) >> 8; + } + if (to_recv_rem > 2) + { + last_32b_bound[2] = (tmp & 0x00FF0000) >> 16; + } + } + } + + xfer->queued_len += xfer_size; + + // Per USB spec, a short OUT packet (including length 0) is always + // indicative of the end of a transfer (at least for ctl, bulk, int). + xfer->short_packet = (xfer_size < xfer->max_size); } static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, uint8_t fifo_num) { - ESP_EARLY_LOGV(TAG, "USB - transmit_packet"); - volatile uint32_t *tx_fifo = USB0.fifo[fifo_num]; + ESP_EARLY_LOGV(TAG, "USB - transmit_packet"); + volatile uint32_t *tx_fifo = USB0.fifo[fifo_num]; - uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S; - xfer->queued_len = xfer->total_len - remaining; + uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S; + xfer->queued_len = xfer->total_len - remaining; - uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining; + uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining; #if 0 // TODO support dcd_edpt_xfer_fifo API if (xfer->ff) @@ -606,313 +606,313 @@ static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, } else #endif - { - uint8_t to_xfer_rem = to_xfer_size % 4; - uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem; - - // Buffer might not be aligned to 32b, so we need to force alignment - // by copying to a temp var. - uint8_t *base = (xfer->buffer + xfer->queued_len); - - // This for loop always runs at least once- skip if less than 4 bytes - // to send off. - if (to_xfer_size >= 4) - { - for (uint16_t i = 0; i < to_xfer_size_aligned; i += 4) - { - uint32_t tmp = base[i] | (base[i + 1] << 8) | - (base[i + 2] << 16) | (base[i + 3] << 24); - (*tx_fifo) = tmp; - } - } - - // Do not read beyond end of buffer if not divisible by 4. - if (to_xfer_rem != 0) - { - uint32_t tmp = 0; - uint8_t *last_32b_bound = base + to_xfer_size_aligned; - - tmp |= last_32b_bound[0]; - if (to_xfer_rem > 1) - { - tmp |= (last_32b_bound[1] << 8); - } - if (to_xfer_rem > 2) - { - tmp |= (last_32b_bound[2] << 16); - } - - (*tx_fifo) = tmp; - } - } + { + uint8_t to_xfer_rem = to_xfer_size % 4; + uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem; + + // Buffer might not be aligned to 32b, so we need to force alignment + // by copying to a temp var. + uint8_t *base = (xfer->buffer + xfer->queued_len); + + // This for loop always runs at least once- skip if less than 4 bytes + // to send off. + if (to_xfer_size >= 4) + { + for (uint16_t i = 0; i < to_xfer_size_aligned; i += 4) + { + uint32_t tmp = base[i] | (base[i + 1] << 8) | + (base[i + 2] << 16) | (base[i + 3] << 24); + (*tx_fifo) = tmp; + } + } + + // Do not read beyond end of buffer if not divisible by 4. + if (to_xfer_rem != 0) + { + uint32_t tmp = 0; + uint8_t *last_32b_bound = base + to_xfer_size_aligned; + + tmp |= last_32b_bound[0]; + if (to_xfer_rem > 1) + { + tmp |= (last_32b_bound[1] << 8); + } + if (to_xfer_rem > 2) + { + tmp |= (last_32b_bound[2] << 16); + } + + (*tx_fifo) = tmp; + } + } } static void read_rx_fifo(void) { - // Pop control word off FIFO (completed xfers will have 2 control words, - // we only pop one ctl word each interrupt). - uint32_t const ctl_word = USB0.grxstsp; - uint8_t const pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S; - uint8_t const epnum = (ctl_word & USB_CHNUM_M) >> USB_CHNUM_S; - uint16_t const bcnt = (ctl_word & USB_BCNT_M) >> USB_BCNT_S; - - switch (pktsts) - { - case 0x01: // Global OUT NAK (Interrupt) - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK"); - break; - - case 0x02: - { // Out packet recvd - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet"); - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - receive_packet(xfer, bcnt); - } - break; - - case 0x03: // Out packet done (Interrupt) - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done"); - break; - - case 0x04: // Step 2: Setup transaction completed (Interrupt) - // After this event, OEPINT interrupt will occur with SETUP bit set - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done"); - USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M; - break; - - case 0x06: - { // Step1: Setup data packet received - volatile uint32_t *rx_fifo = USB0.fifo[0]; - - // We can receive up to three setup packets in succession, but - // only the last one is valid. Therefore we just overwrite it - _setup_packet[0] = (*rx_fifo); - _setup_packet[1] = (*rx_fifo); - - ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]); - } - break; - - default: // Invalid, do something here, like breakpoint? - TU_BREAKPOINT(); - break; - } + // Pop control word off FIFO (completed xfers will have 2 control words, + // we only pop one ctl word each interrupt). + uint32_t const ctl_word = USB0.grxstsp; + uint8_t const pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S; + uint8_t const epnum = (ctl_word & USB_CHNUM_M) >> USB_CHNUM_S; + uint16_t const bcnt = (ctl_word & USB_BCNT_M) >> USB_BCNT_S; + + switch (pktsts) + { + case 0x01: // Global OUT NAK (Interrupt) + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK"); + break; + + case 0x02: + { // Out packet recvd + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet"); + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + receive_packet(xfer, bcnt); + } + break; + + case 0x03: // Out packet done (Interrupt) + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done"); + break; + + case 0x04: // Step 2: Setup transaction completed (Interrupt) + // After this event, OEPINT interrupt will occur with SETUP bit set + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done"); + USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M; + break; + + case 0x06: + { // Step1: Setup data packet received + volatile uint32_t *rx_fifo = USB0.fifo[0]; + + // We can receive up to three setup packets in succession, but + // only the last one is valid. Therefore we just overwrite it + _setup_packet[0] = (*rx_fifo); + _setup_packet[1] = (*rx_fifo); + + ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]); + } + break; + + default: // Invalid, do something here, like breakpoint? + TU_BREAKPOINT(); + break; + } } static void handle_epout_ints(void) { - // GINTSTS will be cleared with DAINT == 0 - // DAINT for a given EP clears when DOEPINTx is cleared. - // DOEPINT will be cleared when DAINT's out bits are cleared. - for (int n = 0; n < USB_OUT_EP_NUM; n++) - { - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - - if (USB0.daint & (1 << (16 + n))) - { - // SETUP packet Setup Phase done. - if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) - { - USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear - dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); - } - - // OUT XFER complete (single packet).q - if (USB0.out_ep_reg[n].doepint & USB_XFERCOMPL0_M) - { - - ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - XFER complete (single packet)"); - USB0.out_ep_reg[n].doepint = USB_XFERCOMPL0_M; - - // Transfer complete if short packet or total len is transferred - if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) - { - xfer->short_packet = false; - dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true); - } - else - { - // Schedule another packet to be received. - USB0.out_ep_reg[n].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); - USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M; - } - } - } - } + // GINTSTS will be cleared with DAINT == 0 + // DAINT for a given EP clears when DOEPINTx is cleared. + // DOEPINT will be cleared when DAINT's out bits are cleared. + for (int n = 0; n < USB_OUT_EP_NUM; n++) + { + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + + if (USB0.daint & (1 << (16 + n))) + { + // SETUP packet Setup Phase done. + if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) + { + USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear + dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true); + } + + // OUT XFER complete (single packet).q + if (USB0.out_ep_reg[n].doepint & USB_XFERCOMPL0_M) + { + + ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - XFER complete (single packet)"); + USB0.out_ep_reg[n].doepint = USB_XFERCOMPL0_M; + + // Transfer complete if short packet or total len is transferred + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) + { + xfer->short_packet = false; + dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true); + } + else + { + // Schedule another packet to be received. + USB0.out_ep_reg[n].doeptsiz |= USB_PKTCNT0_M | ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S); + USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M; + } + } + } + } } static void handle_epin_ints(void) { - // GINTSTS will be cleared with DAINT == 0 - // DAINT for a given EP clears when DIEPINTx is cleared. - // IEPINT will be cleared when DAINT's out bits are cleared. - for (uint32_t n = 0; n < USB_IN_EP_NUM; n++) - { - xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN]; - - if (USB0.daint & (1 << (0 + n))) - { - ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP IN %u", n); - // IN XFER complete (entire xfer). - if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) - { - ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!"); - USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M; - dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - - // XFER FIFO empty - if (USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M) - { - ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!"); - USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M; - transmit_packet(xfer, &USB0.in_ep_reg[n], n); - - // Turn off TXFE if all bytes are written. - if (xfer->queued_len == xfer->total_len) - { - USB0.dtknqr4_fifoemptymsk &= ~(1 << n); - } - } - - // XFER Timeout - if (USB0.in_ep_reg[n].diepint & USB_D_TIMEOUT0_M) - { - // Clear interrupt or enpoint will hang. - USB0.in_ep_reg[n].diepint = USB_D_TIMEOUT0_M; - // Maybe retry? - } - } - } + // GINTSTS will be cleared with DAINT == 0 + // DAINT for a given EP clears when DIEPINTx is cleared. + // IEPINT will be cleared when DAINT's out bits are cleared. + for (uint32_t n = 0; n < USB_IN_EP_NUM; n++) + { + xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN]; + + if (USB0.daint & (1 << (0 + n))) + { + ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP IN %u", n); + // IN XFER complete (entire xfer). + if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) + { + ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!"); + USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M; + dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + + // XFER FIFO empty + if (USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M) + { + ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!"); + USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M; + transmit_packet(xfer, &USB0.in_ep_reg[n], n); + + // Turn off TXFE if all bytes are written. + if (xfer->queued_len == xfer->total_len) + { + USB0.dtknqr4_fifoemptymsk &= ~(1 << n); + } + } + + // XFER Timeout + if (USB0.in_ep_reg[n].diepint & USB_D_TIMEOUT0_M) + { + // Clear interrupt or enpoint will hang. + USB0.in_ep_reg[n].diepint = USB_D_TIMEOUT0_M; + // Maybe retry? + } + } + } } static void _dcd_int_handler(void *arg) { - (void)arg; - uint8_t const rhport = 0; - - const uint32_t int_msk = USB0.gintmsk; - const uint32_t int_status = USB0.gintsts & int_msk; - - if (int_status & USB_USBRST_M) - { - // start of reset - ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset"); - USB0.gintsts = USB_USBRST_M; - // FIFOs will be reassigned when the endpoints are reopen - _allocated_fifos = 1; - bus_reset(); - } - - if (int_status & USB_RESETDET_M) - { - ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend"); - USB0.gintsts = USB_RESETDET_M; - bus_reset(); - } - - if (int_status & USB_ENUMDONE_M) - { - // ENUMDNE detects speed of the link. For full-speed, we - // always expect the same value. This interrupt is considered - // the end of reset. - USB0.gintsts = USB_ENUMDONE_M; - enum_done_processing(); - dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); - } - - if (int_status & USB_USBSUSP_M) - { - USB0.gintsts = USB_USBSUSP_M; - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); - } - - if (int_status & USB_WKUPINT_M) - { - USB0.gintsts = USB_WKUPINT_M; - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); - } - - if (int_status & USB_OTGINT_M) - { - // OTG INT bit is read-only - ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected"); - - uint32_t const otg_int = USB0.gotgint; - - if (otg_int & USB_SESENDDET_M) - { - dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); - } - - USB0.gotgint = otg_int; - } - - if (int_status & USB_SOF_M) - { - USB0.gintsts = USB_SOF_M; - - // Disable SOF interrupt since currently only used for remote wakeup detection - USB0.gintmsk &= ~USB_SOFMSK_M; - - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); - } - - if (int_status & USB_RXFLVI_M) - { - // RXFLVL bit is read-only - ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!"); - - // Mask out RXFLVL while reading data from FIFO - USB0.gintmsk &= ~USB_RXFLVIMSK_M; - read_rx_fifo(); - USB0.gintmsk |= USB_RXFLVIMSK_M; - } - - // OUT endpoint interrupt handling. - if (int_status & USB_OEPINT_M) - { - // OEPINT is read-only - ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!"); - handle_epout_ints(); - } - - // IN endpoint interrupt handling. - if (int_status & USB_IEPINT_M) - { - // IEPINT bit read-only - ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!"); - handle_epin_ints(); - } - - // Without handling - USB0.gintsts |= USB_CURMOD_INT_M | - USB_MODEMIS_M | - USB_OTGINT_M | - USB_NPTXFEMP_M | - USB_GINNAKEFF_M | - USB_GOUTNAKEFF | - USB_ERLYSUSP_M | - USB_USBSUSP_M | - USB_ISOOUTDROP_M | - USB_EOPF_M | - USB_EPMIS_M | - USB_INCOMPISOIN_M | - USB_INCOMPIP_M | - USB_FETSUSP_M | - USB_PTXFEMP_M; + (void)arg; + uint8_t const rhport = 0; + + const uint32_t int_msk = USB0.gintmsk; + const uint32_t int_status = USB0.gintsts & int_msk; + + if (int_status & USB_USBRST_M) + { + // start of reset + ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset"); + USB0.gintsts = USB_USBRST_M; + // FIFOs will be reassigned when the endpoints are reopen + _allocated_fifos = 1; + bus_reset(); + } + + if (int_status & USB_RESETDET_M) + { + ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend"); + USB0.gintsts = USB_RESETDET_M; + bus_reset(); + } + + if (int_status & USB_ENUMDONE_M) + { + // ENUMDNE detects speed of the link. For full-speed, we + // always expect the same value. This interrupt is considered + // the end of reset. + USB0.gintsts = USB_ENUMDONE_M; + enum_done_processing(); + dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); + } + + if (int_status & USB_USBSUSP_M) + { + USB0.gintsts = USB_USBSUSP_M; + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + + if (int_status & USB_WKUPINT_M) + { + USB0.gintsts = USB_WKUPINT_M; + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + + if (int_status & USB_OTGINT_M) + { + // OTG INT bit is read-only + ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected"); + + uint32_t const otg_int = USB0.gotgint; + + if (otg_int & USB_SESENDDET_M) + { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + + USB0.gotgint = otg_int; + } + + if (int_status & USB_SOF_M) + { + USB0.gintsts = USB_SOF_M; + + // Disable SOF interrupt since currently only used for remote wakeup detection + USB0.gintmsk &= ~USB_SOFMSK_M; + + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } + + if (int_status & USB_RXFLVI_M) + { + // RXFLVL bit is read-only + ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!"); + + // Mask out RXFLVL while reading data from FIFO + USB0.gintmsk &= ~USB_RXFLVIMSK_M; + read_rx_fifo(); + USB0.gintmsk |= USB_RXFLVIMSK_M; + } + + // OUT endpoint interrupt handling. + if (int_status & USB_OEPINT_M) + { + // OEPINT is read-only + ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!"); + handle_epout_ints(); + } + + // IN endpoint interrupt handling. + if (int_status & USB_IEPINT_M) + { + // IEPINT bit read-only + ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!"); + handle_epin_ints(); + } + + // Without handling + USB0.gintsts |= USB_CURMOD_INT_M | + USB_MODEMIS_M | + USB_OTGINT_M | + USB_NPTXFEMP_M | + USB_GINNAKEFF_M | + USB_GOUTNAKEFF | + USB_ERLYSUSP_M | + USB_USBSUSP_M | + USB_ISOOUTDROP_M | + USB_EOPF_M | + USB_EPMIS_M | + USB_INCOMPISOIN_M | + USB_INCOMPIP_M | + USB_FETSUSP_M | + USB_PTXFEMP_M; } void dcd_int_enable(uint8_t rhport) { - (void)rhport; - esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)_dcd_int_handler, NULL, &usb_ih); + (void)rhport; + esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)_dcd_int_handler, NULL, &usb_ih); } void dcd_int_disable(uint8_t rhport) { - (void)rhport; - esp_intr_free(usb_ih); + (void)rhport; + esp_intr_free(usb_ih); } #endif // #if OPT_MCU_ESP32S2 || OPT_MCU_ESP32S3 diff --git a/uCNC/src/tinyusb/src/portable/microchip/samd/dcd_samd.c b/uCNC/src/tinyusb/src/portable/microchip/samd/dcd_samd.c index 99715fe5c..30df39a69 100644 --- a/uCNC/src/tinyusb/src/portable/microchip/samd/dcd_samd.c +++ b/uCNC/src/tinyusb/src/portable/microchip/samd/dcd_samd.c @@ -27,9 +27,9 @@ #include "../../../tusb_option.h" #if TUSB_OPT_DEVICE_ENABLED && \ - (CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ - CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ - CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21) + (CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ + CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ + CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21) #include "sam.h" #include "../../../device/dcd.h" @@ -52,27 +52,27 @@ static TU_ATTR_ALIGNED(4) uint8_t _setup_packet[8 + 2]; // ready for receiving SETUP packet static inline void prepare_setup(void) { - // Only make sure the EP0 OUT buffer is ready - sram_registers[0][0].ADDR.reg = (uint32_t)_setup_packet; - sram_registers[0][0].PCKSIZE.bit.MULTI_PACKET_SIZE = sizeof(tusb_control_request_t); - sram_registers[0][0].PCKSIZE.bit.BYTE_COUNT = 0; + // Only make sure the EP0 OUT buffer is ready + sram_registers[0][0].ADDR.reg = (uint32_t)_setup_packet; + sram_registers[0][0].PCKSIZE.bit.MULTI_PACKET_SIZE = sizeof(tusb_control_request_t); + sram_registers[0][0].PCKSIZE.bit.BYTE_COUNT = 0; } // Setup the control endpoint 0. static void bus_reset(void) { - // Max size of packets is 64 bytes. - UsbDeviceDescBank *bank_out = &sram_registers[0][TUSB_DIR_OUT]; - bank_out->PCKSIZE.bit.SIZE = 0x3; - UsbDeviceDescBank *bank_in = &sram_registers[0][TUSB_DIR_IN]; - bank_in->PCKSIZE.bit.SIZE = 0x3; - - UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[0]; - ep->EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0x1) | USB_DEVICE_EPCFG_EPTYPE1(0x1); - ep->EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1 | USB_DEVICE_EPINTENSET_RXSTP; - - // Prepare for setup packet - prepare_setup(); + // Max size of packets is 64 bytes. + UsbDeviceDescBank *bank_out = &sram_registers[0][TUSB_DIR_OUT]; + bank_out->PCKSIZE.bit.SIZE = 0x3; + UsbDeviceDescBank *bank_in = &sram_registers[0][TUSB_DIR_IN]; + bank_in->PCKSIZE.bit.SIZE = 0x3; + + UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[0]; + ep->EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0x1) | USB_DEVICE_EPCFG_EPTYPE1(0x1); + ep->EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1 | USB_DEVICE_EPINTENSET_RXSTP; + + // Prepare for setup packet + prepare_setup(); } /*------------------------------------------------------------------*/ @@ -80,69 +80,69 @@ static void bus_reset(void) *------------------------------------------------------------------*/ void dcd_init(uint8_t rhport) { - (void)rhport; - - // Reset to get in a clean state. - USB->DEVICE.CTRLA.bit.SWRST = true; - while (USB->DEVICE.SYNCBUSY.bit.SWRST == 0) - { - } - while (USB->DEVICE.SYNCBUSY.bit.SWRST == 1) - { - } - - USB->DEVICE.PADCAL.bit.TRANSP = (*((uint32_t *)USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos; - USB->DEVICE.PADCAL.bit.TRANSN = (*((uint32_t *)USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos; - USB->DEVICE.PADCAL.bit.TRIM = (*((uint32_t *)USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos; - - USB->DEVICE.QOSCTRL.bit.CQOS = 3; // High Quality - USB->DEVICE.QOSCTRL.bit.DQOS = 3; // High Quality - - // Configure registers - USB->DEVICE.DESCADD.reg = (uint32_t)&sram_registers; - USB->DEVICE.CTRLB.reg = USB_DEVICE_CTRLB_SPDCONF_FS; - USB->DEVICE.CTRLA.reg = USB_CTRLA_MODE_DEVICE | USB_CTRLA_ENABLE | USB_CTRLA_RUNSTDBY; - while (USB->DEVICE.SYNCBUSY.bit.ENABLE == 1) - { - } - - USB->DEVICE.INTFLAG.reg |= USB->DEVICE.INTFLAG.reg; // clear pending - USB->DEVICE.INTENSET.reg = /* USB_DEVICE_INTENSET_SOF | */ USB_DEVICE_INTENSET_EORST; + (void)rhport; + + // Reset to get in a clean state. + USB->DEVICE.CTRLA.bit.SWRST = true; + while (USB->DEVICE.SYNCBUSY.bit.SWRST == 0) + { + } + while (USB->DEVICE.SYNCBUSY.bit.SWRST == 1) + { + } + + USB->DEVICE.PADCAL.bit.TRANSP = (*((uint32_t *)USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos; + USB->DEVICE.PADCAL.bit.TRANSN = (*((uint32_t *)USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos; + USB->DEVICE.PADCAL.bit.TRIM = (*((uint32_t *)USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos; + + USB->DEVICE.QOSCTRL.bit.CQOS = 3; // High Quality + USB->DEVICE.QOSCTRL.bit.DQOS = 3; // High Quality + + // Configure registers + USB->DEVICE.DESCADD.reg = (uint32_t)&sram_registers; + USB->DEVICE.CTRLB.reg = USB_DEVICE_CTRLB_SPDCONF_FS; + USB->DEVICE.CTRLA.reg = USB_CTRLA_MODE_DEVICE | USB_CTRLA_ENABLE | USB_CTRLA_RUNSTDBY; + while (USB->DEVICE.SYNCBUSY.bit.ENABLE == 1) + { + } + + USB->DEVICE.INTFLAG.reg |= USB->DEVICE.INTFLAG.reg; // clear pending + USB->DEVICE.INTENSET.reg = /* USB_DEVICE_INTENSET_SOF | */ USB_DEVICE_INTENSET_EORST; } #if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X void dcd_int_enable(uint8_t rhport) { - (void)rhport; - NVIC_EnableIRQ(USB_0_IRQn); - NVIC_EnableIRQ(USB_1_IRQn); - NVIC_EnableIRQ(USB_2_IRQn); - NVIC_EnableIRQ(USB_3_IRQn); + (void)rhport; + NVIC_EnableIRQ(USB_0_IRQn); + NVIC_EnableIRQ(USB_1_IRQn); + NVIC_EnableIRQ(USB_2_IRQn); + NVIC_EnableIRQ(USB_3_IRQn); } void dcd_int_disable(uint8_t rhport) { - (void)rhport; - NVIC_DisableIRQ(USB_3_IRQn); - NVIC_DisableIRQ(USB_2_IRQn); - NVIC_DisableIRQ(USB_1_IRQn); - NVIC_DisableIRQ(USB_0_IRQn); + (void)rhport; + NVIC_DisableIRQ(USB_3_IRQn); + NVIC_DisableIRQ(USB_2_IRQn); + NVIC_DisableIRQ(USB_1_IRQn); + NVIC_DisableIRQ(USB_0_IRQn); } #elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ - CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21 + CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21 void dcd_int_enable(uint8_t rhport) { - (void)rhport; - NVIC_EnableIRQ(USB_IRQn); + (void)rhport; + NVIC_EnableIRQ(USB_IRQn); } void dcd_int_disable(uint8_t rhport) { - (void)rhport; - NVIC_DisableIRQ(USB_IRQn); + (void)rhport; + NVIC_DisableIRQ(USB_IRQn); } #else @@ -153,37 +153,37 @@ void dcd_int_disable(uint8_t rhport) void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void)dev_addr; + (void)dev_addr; - // Response with zlp status - dcd_edpt_xfer(rhport, 0x80, NULL, 0); + // Response with zlp status + dcd_edpt_xfer(rhport, 0x80, NULL, 0); - // DCD can only set address after status for this request is complete - // do it at dcd_edpt0_status_complete() + // DCD can only set address after status for this request is complete + // do it at dcd_edpt0_status_complete() - // Enable SUSPEND interrupt since the bus signal D+/D- are stable now. - USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTENCLR_SUSPEND; // clear pending - USB->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + // Enable SUSPEND interrupt since the bus signal D+/D- are stable now. + USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTENCLR_SUSPEND; // clear pending + USB->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; } void dcd_remote_wakeup(uint8_t rhport) { - (void)rhport; - USB->DEVICE.CTRLB.bit.UPRSM = 1; + (void)rhport; + USB->DEVICE.CTRLB.bit.UPRSM = 1; } // disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { - (void)rhport; - USB->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + (void)rhport; + USB->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; } // connect by enabling internal pull-up resistor on D+/D- void dcd_connect(uint8_t rhport) { - (void)rhport; - USB->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + (void)rhport; + USB->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; } /*------------------------------------------------------------------*/ @@ -194,140 +194,140 @@ void dcd_connect(uint8_t rhport) // May help DCD to prepare for next control transfer, this API is optional. void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { - (void)rhport; - - if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && - request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && - request->bRequest == TUSB_REQ_SET_ADDRESS) - { - uint8_t const dev_addr = (uint8_t)request->wValue; - USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN; - } - - // Just finished status stage, prepare for next setup packet - // Note: we may already prepare setup when queueing the control status. - // but it has no harm to do it again here - prepare_setup(); + (void)rhport; + + if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && + request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && + request->bRequest == TUSB_REQ_SET_ADDRESS) + { + uint8_t const dev_addr = (uint8_t)request->wValue; + USB->DEVICE.DADD.reg = USB_DEVICE_DADD_DADD(dev_addr) | USB_DEVICE_DADD_ADDEN; + } + + // Just finished status stage, prepare for next setup packet + // Note: we may already prepare setup when queueing the control status. + // but it has no harm to do it again here + prepare_setup(); } bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - - UsbDeviceDescBank *bank = &sram_registers[epnum][dir]; - uint32_t size_value = 0; - while (size_value < 7) - { - if (1 << (size_value + 3) == tu_edpt_packet_size(desc_edpt)) - { - break; - } - size_value++; - } - - // unsupported endpoint size - if (size_value == 7 && tu_edpt_packet_size(desc_edpt) != 1023) - return false; - - bank->PCKSIZE.bit.SIZE = size_value; - - UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; - - if (dir == TUSB_DIR_OUT) - { - ep->EPCFG.bit.EPTYPE0 = desc_edpt->bmAttributes.xfer + 1; - ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0 | USB_DEVICE_EPSTATUSCLR_DTGLOUT; // clear stall & dtoggle - ep->EPINTENSET.bit.TRCPT0 = true; - } - else - { - ep->EPCFG.bit.EPTYPE1 = desc_edpt->bmAttributes.xfer + 1; - ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1 | USB_DEVICE_EPSTATUSCLR_DTGLIN; // clear stall & dtoggle - ep->EPINTENSET.bit.TRCPT1 = true; - } - - return true; + (void)rhport; + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + UsbDeviceDescBank *bank = &sram_registers[epnum][dir]; + uint32_t size_value = 0; + while (size_value < 7) + { + if (1 << (size_value + 3) == tu_edpt_packet_size(desc_edpt)) + { + break; + } + size_value++; + } + + // unsupported endpoint size + if (size_value == 7 && tu_edpt_packet_size(desc_edpt) != 1023) + return false; + + bank->PCKSIZE.bit.SIZE = size_value; + + UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; + + if (dir == TUSB_DIR_OUT) + { + ep->EPCFG.bit.EPTYPE0 = desc_edpt->bmAttributes.xfer + 1; + ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0 | USB_DEVICE_EPSTATUSCLR_DTGLOUT; // clear stall & dtoggle + ep->EPINTENSET.bit.TRCPT0 = true; + } + else + { + ep->EPCFG.bit.EPTYPE1 = desc_edpt->bmAttributes.xfer + 1; + ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1 | USB_DEVICE_EPSTATUSCLR_DTGLIN; // clear stall & dtoggle + ep->EPINTENSET.bit.TRCPT1 = true; + } + + return true; } void dcd_edpt_close_all(uint8_t rhport) { - (void)rhport; - // TODO implement dcd_edpt_close_all() + (void)rhport; + // TODO implement dcd_edpt_close_all() } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - UsbDeviceDescBank *bank = &sram_registers[epnum][dir]; - UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; - - bank->ADDR.reg = (uint32_t)buffer; - - // A SETUP token can occur immediately after an ZLP Status. - // So make sure we have a valid buffer for setup packet. - // Status = ZLP EP0 with direction opposite to one in the dir bit of current setup - if ((epnum == 0) && (buffer == NULL) && (total_bytes == 0) && (dir != tu_edpt_dir(_setup_packet[0]))) - { - prepare_setup(); - } - - if (dir == TUSB_DIR_OUT) - { - bank->PCKSIZE.bit.MULTI_PACKET_SIZE = total_bytes; - bank->PCKSIZE.bit.BYTE_COUNT = 0; - ep->EPSTATUSCLR.reg |= USB_DEVICE_EPSTATUSCLR_BK0RDY; - ep->EPINTFLAG.reg |= USB_DEVICE_EPINTFLAG_TRFAIL0; - } - else - { - bank->PCKSIZE.bit.MULTI_PACKET_SIZE = 0; - bank->PCKSIZE.bit.BYTE_COUNT = total_bytes; - ep->EPSTATUSSET.reg |= USB_DEVICE_EPSTATUSSET_BK1RDY; - ep->EPINTFLAG.reg |= USB_DEVICE_EPINTFLAG_TRFAIL1; - } - - return true; + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + UsbDeviceDescBank *bank = &sram_registers[epnum][dir]; + UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; + + bank->ADDR.reg = (uint32_t)buffer; + + // A SETUP token can occur immediately after an ZLP Status. + // So make sure we have a valid buffer for setup packet. + // Status = ZLP EP0 with direction opposite to one in the dir bit of current setup + if ((epnum == 0) && (buffer == NULL) && (total_bytes == 0) && (dir != tu_edpt_dir(_setup_packet[0]))) + { + prepare_setup(); + } + + if (dir == TUSB_DIR_OUT) + { + bank->PCKSIZE.bit.MULTI_PACKET_SIZE = total_bytes; + bank->PCKSIZE.bit.BYTE_COUNT = 0; + ep->EPSTATUSCLR.reg |= USB_DEVICE_EPSTATUSCLR_BK0RDY; + ep->EPINTFLAG.reg |= USB_DEVICE_EPINTFLAG_TRFAIL0; + } + else + { + bank->PCKSIZE.bit.MULTI_PACKET_SIZE = 0; + bank->PCKSIZE.bit.BYTE_COUNT = total_bytes; + ep->EPSTATUSSET.reg |= USB_DEVICE_EPSTATUSSET_BK1RDY; + ep->EPINTFLAG.reg |= USB_DEVICE_EPINTFLAG_TRFAIL1; + } + + return true; } void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; - - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) - { - ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1; - } - else - { - ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0; - } + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; + + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) + { + ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1; + } + else + { + ep->EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0; + } } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; - - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) - { - ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1 | USB_DEVICE_EPSTATUSCLR_DTGLIN; - } - else - { - ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0 | USB_DEVICE_EPSTATUSCLR_DTGLOUT; - } + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; + + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) + { + ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1 | USB_DEVICE_EPSTATUSCLR_DTGLIN; + } + else + { + ep->EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0 | USB_DEVICE_EPSTATUSCLR_DTGLOUT; + } } //--------------------------------------------------------------------+ @@ -335,107 +335,107 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) //--------------------------------------------------------------------+ void maybe_transfer_complete(void) { - uint32_t epints = USB->DEVICE.EPINTSMRY.reg; + uint32_t epints = USB->DEVICE.EPINTSMRY.reg; - for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) - { - if ((epints & (1 << epnum)) == 0) - { - continue; - } + for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) + { + if ((epints & (1 << epnum)) == 0) + { + continue; + } - UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; - uint32_t epintflag = ep->EPINTFLAG.reg; + UsbDeviceEndpoint *ep = &USB->DEVICE.DeviceEndpoint[epnum]; + uint32_t epintflag = ep->EPINTFLAG.reg; - // Handle IN completions - if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT1) != 0) - { - UsbDeviceDescBank *bank = &sram_registers[epnum][TUSB_DIR_IN]; - uint16_t const total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT; + // Handle IN completions + if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT1) != 0) + { + UsbDeviceDescBank *bank = &sram_registers[epnum][TUSB_DIR_IN]; + uint16_t const total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT; - dcd_event_xfer_complete(0, epnum | TUSB_DIR_IN_MASK, total_transfer_size, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(0, epnum | TUSB_DIR_IN_MASK, total_transfer_size, XFER_RESULT_SUCCESS, true); - ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; - } + ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; + } - // Handle OUT completions - if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT0) != 0) - { - UsbDeviceDescBank *bank = &sram_registers[epnum][TUSB_DIR_OUT]; - uint16_t const total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT; + // Handle OUT completions + if ((epintflag & USB_DEVICE_EPINTFLAG_TRCPT0) != 0) + { + UsbDeviceDescBank *bank = &sram_registers[epnum][TUSB_DIR_OUT]; + uint16_t const total_transfer_size = bank->PCKSIZE.bit.BYTE_COUNT; - dcd_event_xfer_complete(0, epnum, total_transfer_size, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(0, epnum, total_transfer_size, XFER_RESULT_SUCCESS, true); - ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; - } - } + ep->EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; + } + } } void dcd_int_handler(uint8_t rhport) { - (void)rhport; - - uint32_t int_status = USB->DEVICE.INTFLAG.reg & USB->DEVICE.INTENSET.reg; - - // Start of Frame - if (int_status & USB_DEVICE_INTFLAG_SOF) - { - USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; - dcd_event_bus_signal(0, DCD_EVENT_SOF, true); - } - - // SAMD doesn't distinguish between Suspend and Disconnect state. - // Both condition will cause SUSPEND interrupt triggered. - // To prevent being triggered when D+/D- are not stable, SUSPEND interrupt is only - // enabled when we received SET_ADDRESS request and cleared on Bus Reset - if (int_status & USB_DEVICE_INTFLAG_SUSPEND) - { - USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; - - // Enable wakeup interrupt - USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; // clear pending - USB->DEVICE.INTENSET.reg = USB_DEVICE_INTFLAG_WAKEUP; - - dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); - } - - // Wakeup interrupt is only enabled when we got suspended. - // Wakeup interrupt will disable itself - if (int_status & USB_DEVICE_INTFLAG_WAKEUP) - { - USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; - - // disable wakeup interrupt itself - USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP; - dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); - } - - // Enable of Reset - if (int_status & USB_DEVICE_INTFLAG_EORST) - { - USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; - - // Disable both suspend and wakeup interrupt - USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_SUSPEND; - - bus_reset(); - dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); - } - - // Handle SETUP packet - if (USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.bit.RXSTP) - { - // This copies the data elsewhere so we can reuse the buffer. - dcd_event_setup_received(0, _setup_packet, true); - - // Although Setup packet only set RXSTP bit, - // TRCPT0 bit could already be set by previous ZLP OUT Status (not handled until now). - // Since control status complete event is optional, we can just clear TRCPT0 and skip the status event - USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP | USB_DEVICE_EPINTFLAG_TRCPT0; - } - - // Handle complete transfer - maybe_transfer_complete(); + (void)rhport; + + uint32_t int_status = USB->DEVICE.INTFLAG.reg & USB->DEVICE.INTENSET.reg; + + // Start of Frame + if (int_status & USB_DEVICE_INTFLAG_SOF) + { + USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; + dcd_event_bus_signal(0, DCD_EVENT_SOF, true); + } + + // SAMD doesn't distinguish between Suspend and Disconnect state. + // Both condition will cause SUSPEND interrupt triggered. + // To prevent being triggered when D+/D- are not stable, SUSPEND interrupt is only + // enabled when we received SET_ADDRESS request and cleared on Bus Reset + if (int_status & USB_DEVICE_INTFLAG_SUSPEND) + { + USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; + + // Enable wakeup interrupt + USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; // clear pending + USB->DEVICE.INTENSET.reg = USB_DEVICE_INTFLAG_WAKEUP; + + dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); + } + + // Wakeup interrupt is only enabled when we got suspended. + // Wakeup interrupt will disable itself + if (int_status & USB_DEVICE_INTFLAG_WAKEUP) + { + USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; + + // disable wakeup interrupt itself + USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP; + dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); + } + + // Enable of Reset + if (int_status & USB_DEVICE_INTFLAG_EORST) + { + USB->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; + + // Disable both suspend and wakeup interrupt + USB->DEVICE.INTENCLR.reg = USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_SUSPEND; + + bus_reset(); + dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); + } + + // Handle SETUP packet + if (USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.bit.RXSTP) + { + // This copies the data elsewhere so we can reuse the buffer. + dcd_event_setup_received(0, _setup_packet, true); + + // Although Setup packet only set RXSTP bit, + // TRCPT0 bit could already be set by previous ZLP OUT Status (not handled until now). + // Since control status complete event is optional, we can just clear TRCPT0 and skip the status event + USB->DEVICE.DeviceEndpoint[0].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP | USB_DEVICE_EPINTFLAG_TRCPT0; + } + + // Handle complete transfer + maybe_transfer_complete(); } #endif diff --git a/uCNC/src/tinyusb/src/portable/microchip/samg/dcd_samg.c b/uCNC/src/tinyusb/src/portable/microchip/samg/dcd_samg.c deleted file mode 100644 index 8f3021b04..000000000 --- a/uCNC/src/tinyusb/src/portable/microchip/samg/dcd_samg.c +++ /dev/null @@ -1,500 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "../../../tusb_option.h" - -#if CFG_TUSB_MCU == OPT_MCU_SAMG - -#include "sam.h" -#include "device/dcd.h" - -// TODO should support (SAM3S || SAM4S || SAM4E || SAMG55) - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ - -#define EP_COUNT 6 - -// Transfer descriptor -typedef struct -{ - uint8_t *buffer; - // tu_fifo_t* ff; // TODO support dcd_edpt_xfer_fifo API - uint16_t total_len; - volatile uint16_t actual_len; - uint16_t epsize; -} xfer_desc_t; - -// Endpoint 0-5, each can only be either OUT or In -xfer_desc_t _dcd_xfer[EP_COUNT]; - -void xfer_epsize_set(xfer_desc_t *xfer, uint16_t epsize) -{ - xfer->epsize = epsize; -} - -void xfer_begin(xfer_desc_t *xfer, uint8_t *buffer, uint16_t total_bytes) -{ - xfer->buffer = buffer; - // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API - xfer->total_len = total_bytes; - xfer->actual_len = 0; -} - -void xfer_end(xfer_desc_t *xfer) -{ - xfer->buffer = NULL; - // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API - xfer->total_len = 0; - xfer->actual_len = 0; -} - -uint16_t xfer_packet_len(xfer_desc_t *xfer) -{ - // also cover zero-length packet - return tu_min16(xfer->total_len - xfer->actual_len, xfer->epsize); -} - -void xfer_packet_done(xfer_desc_t *xfer) -{ - uint16_t const xact_len = xfer_packet_len(xfer); - - xfer->buffer += xact_len; - xfer->actual_len += xact_len; -} - -//------------- Transaction helpers -------------// - -// Write data to EP FIFO, return number of written bytes -static void xact_ep_write(uint8_t epnum, uint8_t *buffer, uint16_t xact_len) -{ - for (uint16_t i = 0; i < xact_len; i++) - { - UDP->UDP_FDR[epnum] = (uint32_t)buffer[i]; - } -} - -// Read data from EP FIFO -static void xact_ep_read(uint8_t epnum, uint8_t *buffer, uint16_t xact_len) -{ - for (uint16_t i = 0; i < xact_len; i++) - { - buffer[i] = (uint8_t)UDP->UDP_FDR[epnum]; - } -} - -//! Bitmap for all status bits in CSR that are not affected by a value 1. -#define CSR_NO_EFFECT_1_ALL (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 | UDP_CSR_STALLSENT | UDP_CSR_RXSETUP | UDP_CSR_TXCOMP) - -// Per Specs: CSR need synchronization each write -static inline void csr_write(uint8_t epnum, uint32_t value) -{ - uint32_t const csr = value; - UDP->UDP_CSR[epnum] = csr; - - volatile uint32_t nop_count; - for (nop_count = 0; nop_count < 20; nop_count++) - __NOP(); -} - -// Per Specs: CSR need synchronization each write -static inline void csr_set(uint8_t epnum, uint32_t mask) -{ - csr_write(epnum, UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL | mask); -} - -// Per Specs: CSR need synchronization each write -static inline void csr_clear(uint8_t epnum, uint32_t mask) -{ - csr_write(epnum, (UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL) & ~mask); -} - -/*------------------------------------------------------------------*/ -/* Device API - *------------------------------------------------------------------*/ - -// Set up endpoint 0, clear all other endpoints -static void bus_reset(void) -{ - tu_memclr(_dcd_xfer, sizeof(_dcd_xfer)); - - xfer_epsize_set(&_dcd_xfer[0], CFG_TUD_ENDPOINT0_SIZE); - - // Enable EP0 control - csr_write(0, UDP_CSR_EPEDS_Msk); - - // Enable interrupt : EP0, Suspend, Resume, Wakeup - UDP->UDP_IER = UDP_IER_EP0INT_Msk | UDP_IER_RXSUSP_Msk | UDP_IER_RXRSM_Msk | UDP_IER_WAKEUP_Msk; - - // Enable transceiver - UDP->UDP_TXVC &= ~UDP_TXVC_TXVDIS_Msk; -} - -// Initialize controller to device mode -void dcd_init(uint8_t rhport) -{ - tu_memclr(_dcd_xfer, sizeof(_dcd_xfer)); - dcd_connect(rhport); -} - -// Enable device interrupt -void dcd_int_enable(uint8_t rhport) -{ - (void)rhport; - NVIC_EnableIRQ(UDP_IRQn); -} - -// Disable device interrupt -void dcd_int_disable(uint8_t rhport) -{ - (void)rhport; - NVIC_DisableIRQ(UDP_IRQn); -} - -// Receive Set Address request, mcu port must also include status IN response -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - (void)dev_addr; - - // Response with zlp status - dcd_edpt_xfer(rhport, 0x80, NULL, 0); - - // DCD can only set address after status for this request is complete. - // do it at dcd_edpt0_status_complete() -} - -// Wake up host -void dcd_remote_wakeup(uint8_t rhport) -{ - (void)rhport; -} - -void dcd_connect(uint8_t rhport) -{ - (void)rhport; - - // Enable pull-up, disable transceiver - UDP->UDP_TXVC = UDP_TXVC_PUON | UDP_TXVC_TXVDIS_Msk; -} - -void dcd_disconnect(uint8_t rhport) -{ - (void)rhport; - - // disable both pullup and transceiver - UDP->UDP_TXVC = UDP_TXVC_TXVDIS_Msk; -} - -//--------------------------------------------------------------------+ -// Endpoint API -//--------------------------------------------------------------------+ - -// Invoked when a control transfer's status stage is complete. -// May help DCD to prepare for next control transfer, this API is optional. -void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) -{ - (void)rhport; - - if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && - request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) - { - if (request->bRequest == TUSB_REQ_SET_ADDRESS) - { - uint8_t const dev_addr = (uint8_t)request->wValue; - - // Enable addressed state - UDP->UDP_GLB_STAT |= UDP_GLB_STAT_FADDEN_Msk; - - // Set new address & Function enable bit - UDP->UDP_FADDR = UDP_FADDR_FEN_Msk | UDP_FADDR_FADD(dev_addr); - } - else if (request->bRequest == TUSB_REQ_SET_CONFIGURATION) - { - // Configured State - UDP->UDP_GLB_STAT |= UDP_GLB_STAT_CONFG_Msk; - } - } -} - -// Configure endpoint's registers according to descriptor -// SAMG doesn't support a same endpoint number with IN and OUT -// e.g EP1 OUT & EP1 IN cannot exist together -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) -{ - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress); - - // TODO Isochronous is not supported yet - TU_VERIFY(ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); - TU_VERIFY(epnum < EP_COUNT); - - // Must not already enabled - TU_ASSERT((UDP->UDP_CSR[epnum] & UDP_CSR_EPEDS_Msk) == 0); - - xfer_epsize_set(&_dcd_xfer[epnum], tu_edpt_packet_size(ep_desc)); - - // Configure type and enable EP - csr_write(epnum, UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4 * dir)); - - // Enable EP Interrupt for IN - if (dir == TUSB_DIR_IN) - UDP->UDP_IER |= (1 << epnum); - - return true; -} - -void dcd_edpt_close_all(uint8_t rhport) -{ - (void)rhport; - // TODO implement dcd_edpt_close_all() -} - -// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) -{ - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_desc_t *xfer = &_dcd_xfer[epnum]; - xfer_begin(xfer, buffer, total_bytes); - - if (dir == TUSB_DIR_OUT) - { - // Enable interrupt when starting OUT transfer - if (epnum != 0) - UDP->UDP_IER |= (1 << epnum); - } - else - { - xact_ep_write(epnum, xfer->buffer, xfer_packet_len(xfer)); - - // TX ready for transfer - csr_set(epnum, UDP_CSR_TXPKTRDY_Msk); - } - - return true; -} - -#if 0 // TODO support dcd_edpt_xfer_fifo API -bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ - (void) rhport; - return true; -} -#endif - -// Stall endpoint -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - - // For EP0 USBD will stall both EP0 Out and In with 0x00 and 0x80 - // only handle one by skipping 0x80 - if (ep_addr == tu_edpt_addr(0, TUSB_DIR_IN_MASK)) - return; - - uint8_t const epnum = tu_edpt_number(ep_addr); - - // Set force stall bit - csr_set(epnum, UDP_CSR_FORCESTALL_Msk); -} - -// clear stall, data toggle is also reset to DATA0 -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - - // clear stall - csr_clear(epnum, UDP_CSR_FORCESTALL_Msk); - - // must also reset EP to clear data toggle - UDP->UDP_RST_EP |= (1 << epnum); - UDP->UDP_RST_EP &= ~(1 << epnum); -} - -//--------------------------------------------------------------------+ -// ISR -//--------------------------------------------------------------------+ -void dcd_int_handler(uint8_t rhport) -{ - uint32_t const intr_mask = UDP->UDP_IMR; - uint32_t const intr_status = UDP->UDP_ISR & intr_mask; - - // clear interrupt - UDP->UDP_ICR = intr_status; - - // Bus reset - if (intr_status & UDP_ISR_ENDBUSRES_Msk) - { - bus_reset(); - dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); - } - - // SOF - // if (intr_status & UDP_ISR_SOFINT_Msk) dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); - - // Suspend - if (intr_status & UDP_ISR_RXSUSP_Msk) - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); - - // Resume - if (intr_status & UDP_ISR_RXRSM_Msk) - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); - - // Wakeup - if (intr_status & UDP_ISR_WAKEUP_Msk) - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); - - //------------- Endpoints -------------// - - if (intr_status & TU_BIT(0)) - { - // setup packet - if (UDP->UDP_CSR[0] & UDP_CSR_RXSETUP) - { - // get setup from FIFO - uint8_t setup[8]; - for (uint8_t i = 0; i < sizeof(setup); i++) - { - setup[i] = (uint8_t)UDP->UDP_FDR[0]; - } - - // notify usbd - dcd_event_setup_received(rhport, setup, true); - - // Set EP direction bit according to DATA stage - // MUST only be set before RXSETUP is clear per specs - if (tu_edpt_dir(setup[0])) - { - csr_set(0, UDP_CSR_DIR_Msk); - } - else - { - csr_clear(0, UDP_CSR_DIR_Msk); - } - - // Clear Setup, stall and other on-going transfer bits - csr_clear(0, UDP_CSR_RXSETUP_Msk | UDP_CSR_TXPKTRDY_Msk | UDP_CSR_TXCOMP_Msk | UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 | UDP_CSR_STALLSENT_Msk | UDP_CSR_FORCESTALL_Msk); - } - } - - for (uint8_t epnum = 0; epnum < EP_COUNT; epnum++) - { - if (intr_status & TU_BIT(epnum)) - { - xfer_desc_t *xfer = &_dcd_xfer[epnum]; - - //------------- Endpoint IN -------------// - if (UDP->UDP_CSR[epnum] & UDP_CSR_TXCOMP_Msk) - { - xfer_packet_done(xfer); - - uint16_t const xact_len = xfer_packet_len(xfer); - - if (xact_len) - { - // write to EP fifo -#if 0 // TODO support dcd_edpt_xfer_fifo - if (xfer->ff) - { - tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *) &UDP->UDP_FDR[epnum], xact_len); - } - else -#endif - { - xact_ep_write(epnum, xfer->buffer, xact_len); - } - - // TX ready for transfer - csr_set(epnum, UDP_CSR_TXPKTRDY_Msk); - } - else - { - // xfer is complete - dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true); - - // Required since control OUT can happen right after before stack handle this event - xfer_end(xfer); - } - - // Clear TX Complete bit - csr_clear(epnum, UDP_CSR_TXCOMP_Msk); - } - - //------------- Endpoint OUT -------------// - // Ping-Pong is a MUST for Bulk/Iso - // NOTE: When both Bank0 and Bank1 are both set, there is no way to know which one comes first - uint32_t const banks_complete = UDP->UDP_CSR[epnum] & (UDP_CSR_RX_DATA_BK0_Msk | UDP_CSR_RX_DATA_BK1_Msk); - if (banks_complete) - { - uint16_t const xact_len = (uint16_t)((UDP->UDP_CSR[epnum] & UDP_CSR_RXBYTECNT_Msk) >> UDP_CSR_RXBYTECNT_Pos); - - // Read from EP fifo -#if 0 // TODO support dcd_edpt_xfer_fifo API - if (xfer->ff) - { - tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *) &UDP->UDP_FDR[epnum], xact_len); - } - else -#endif - { - xact_ep_read(epnum, xfer->buffer, xact_len); - } - - xfer_packet_done(xfer); - - if (0 == xfer_packet_len(xfer)) - { - // Disable OUT EP interrupt when transfer is complete - if (epnum != 0) - UDP->UDP_IDR |= (1 << epnum); - - dcd_event_xfer_complete(rhport, epnum, xfer->actual_len, XFER_RESULT_SUCCESS, true); - xfer_end(xfer); - } - - // Clear DATA Bank0/1 bit - csr_clear(epnum, banks_complete); - } - - // Stall sent to host - if (UDP->UDP_CSR[epnum] & UDP_CSR_STALLSENT_Msk) - { - csr_clear(epnum, UDP_CSR_STALLSENT_Msk); - } - } - } -} - -#endif diff --git a/uCNC/src/tinyusb/src/portable/microchip/samx7x/common_usb_regs.h b/uCNC/src/tinyusb/src/portable/microchip/samx7x/common_usb_regs.h deleted file mode 100644 index 765e939d4..000000000 --- a/uCNC/src/tinyusb/src/portable/microchip/samx7x/common_usb_regs.h +++ /dev/null @@ -1,2072 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Microchip Technology Inc. - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2021, HiFiPhile - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _COMMON_USB_REGS_H_ -#define _COMMON_USB_REGS_H_ - -#if CFG_TUSB_MCU == OPT_MCU_SAMX7X - -/* -------- DEVDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Device DMA Channel Next Descriptor Address Register -------- */ - -#define DEVDMANXTDSC_OFFSET (0x00) /**< (DEVDMANXTDSC) Device DMA Channel Next Descriptor Address Register Offset */ - -#define DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (DEVDMANXTDSC) Next Descriptor Address Position */ -#define DEVDMANXTDSC_NXT_DSC_ADD (_U_(0xFFFFFFFF) << DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< (DEVDMANXTDSC) Next Descriptor Address Mask */ -#define DEVDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (DEVDMANXTDSC) Register Mask */ - -/* -------- DEVDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Device DMA Channel Address Register -------- */ - -#define DEVDMAADDRESS_OFFSET (0x04) /**< (DEVDMAADDRESS) Device DMA Channel Address Register Offset */ - -#define DEVDMAADDRESS_BUFF_ADD_Pos 0 /**< (DEVDMAADDRESS) Buffer Address Position */ -#define DEVDMAADDRESS_BUFF_ADD (_U_(0xFFFFFFFF) << DEVDMAADDRESS_BUFF_ADD_Pos) /**< (DEVDMAADDRESS) Buffer Address Mask */ -#define DEVDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (DEVDMAADDRESS) Register Mask */ - -/* -------- DEVDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Device DMA Channel Control Register -------- */ - -#define DEVDMACONTROL_OFFSET (0x08) /**< (DEVDMACONTROL) Device DMA Channel Control Register Offset */ - -#define DEVDMACONTROL_CHANN_ENB_Pos 0 /**< (DEVDMACONTROL) Channel Enable Command Position */ -#define DEVDMACONTROL_CHANN_ENB (_U_(0x1) << DEVDMACONTROL_CHANN_ENB_Pos) /**< (DEVDMACONTROL) Channel Enable Command Mask */ -#define DEVDMACONTROL_LDNXT_DSC_Pos 1 /**< (DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ -#define DEVDMACONTROL_LDNXT_DSC (_U_(0x1) << DEVDMACONTROL_LDNXT_DSC_Pos) /**< (DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ -#define DEVDMACONTROL_END_TR_EN_Pos 2 /**< (DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ -#define DEVDMACONTROL_END_TR_EN (_U_(0x1) << DEVDMACONTROL_END_TR_EN_Pos) /**< (DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ -#define DEVDMACONTROL_END_B_EN_Pos 3 /**< (DEVDMACONTROL) End of Buffer Enable Control Position */ -#define DEVDMACONTROL_END_B_EN (_U_(0x1) << DEVDMACONTROL_END_B_EN_Pos) /**< (DEVDMACONTROL) End of Buffer Enable Control Mask */ -#define DEVDMACONTROL_END_TR_IT_Pos 4 /**< (DEVDMACONTROL) End of Transfer Interrupt Enable Position */ -#define DEVDMACONTROL_END_TR_IT (_U_(0x1) << DEVDMACONTROL_END_TR_IT_Pos) /**< (DEVDMACONTROL) End of Transfer Interrupt Enable Mask */ -#define DEVDMACONTROL_END_BUFFIT_Pos 5 /**< (DEVDMACONTROL) End of Buffer Interrupt Enable Position */ -#define DEVDMACONTROL_END_BUFFIT (_U_(0x1) << DEVDMACONTROL_END_BUFFIT_Pos) /**< (DEVDMACONTROL) End of Buffer Interrupt Enable Mask */ -#define DEVDMACONTROL_DESC_LD_IT_Pos 6 /**< (DEVDMACONTROL) Descriptor Loaded Interrupt Enable Position */ -#define DEVDMACONTROL_DESC_LD_IT (_U_(0x1) << DEVDMACONTROL_DESC_LD_IT_Pos) /**< (DEVDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ -#define DEVDMACONTROL_BURST_LCK_Pos 7 /**< (DEVDMACONTROL) Burst Lock Enable Position */ -#define DEVDMACONTROL_BURST_LCK (_U_(0x1) << DEVDMACONTROL_BURST_LCK_Pos) /**< (DEVDMACONTROL) Burst Lock Enable Mask */ -#define DEVDMACONTROL_BUFF_LENGTH_Pos 16 /**< (DEVDMACONTROL) Buffer Byte Length (Write-only) Position */ -#define DEVDMACONTROL_BUFF_LENGTH (_U_(0xFFFF) << DEVDMACONTROL_BUFF_LENGTH_Pos) /**< (DEVDMACONTROL) Buffer Byte Length (Write-only) Mask */ -#define DEVDMACONTROL_Msk _U_(0xFFFF00FF) /**< (DEVDMACONTROL) Register Mask */ - -/* -------- DEVDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Device DMA Channel Status Register -------- */ - -#define DEVDMASTATUS_OFFSET (0x0C) /**< (DEVDMASTATUS) Device DMA Channel Status Register Offset */ - -#define DEVDMASTATUS_CHANN_ENB_Pos 0 /**< (DEVDMASTATUS) Channel Enable Status Position */ -#define DEVDMASTATUS_CHANN_ENB (_U_(0x1) << DEVDMASTATUS_CHANN_ENB_Pos) /**< (DEVDMASTATUS) Channel Enable Status Mask */ -#define DEVDMASTATUS_CHANN_ACT_Pos 1 /**< (DEVDMASTATUS) Channel Active Status Position */ -#define DEVDMASTATUS_CHANN_ACT (_U_(0x1) << DEVDMASTATUS_CHANN_ACT_Pos) /**< (DEVDMASTATUS) Channel Active Status Mask */ -#define DEVDMASTATUS_END_TR_ST_Pos 4 /**< (DEVDMASTATUS) End of Channel Transfer Status Position */ -#define DEVDMASTATUS_END_TR_ST (_U_(0x1) << DEVDMASTATUS_END_TR_ST_Pos) /**< (DEVDMASTATUS) End of Channel Transfer Status Mask */ -#define DEVDMASTATUS_END_BF_ST_Pos 5 /**< (DEVDMASTATUS) End of Channel Buffer Status Position */ -#define DEVDMASTATUS_END_BF_ST (_U_(0x1) << DEVDMASTATUS_END_BF_ST_Pos) /**< (DEVDMASTATUS) End of Channel Buffer Status Mask */ -#define DEVDMASTATUS_DESC_LDST_Pos 6 /**< (DEVDMASTATUS) Descriptor Loaded Status Position */ -#define DEVDMASTATUS_DESC_LDST (_U_(0x1) << DEVDMASTATUS_DESC_LDST_Pos) /**< (DEVDMASTATUS) Descriptor Loaded Status Mask */ -#define DEVDMASTATUS_BUFF_COUNT_Pos 16 /**< (DEVDMASTATUS) Buffer Byte Count Position */ -#define DEVDMASTATUS_BUFF_COUNT (_U_(0xFFFF) << DEVDMASTATUS_BUFF_COUNT_Pos) /**< (DEVDMASTATUS) Buffer Byte Count Mask */ -#define DEVDMASTATUS_Msk _U_(0xFFFF0073) /**< (DEVDMASTATUS) Register Mask */ - -/* -------- HSTDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Host DMA Channel Next Descriptor Address Register -------- */ - -#define HSTDMANXTDSC_OFFSET (0x00) /**< (HSTDMANXTDSC) Host DMA Channel Next Descriptor Address Register Offset */ - -#define HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (HSTDMANXTDSC) Next Descriptor Address Position */ -#define HSTDMANXTDSC_NXT_DSC_ADD (_U_(0xFFFFFFFF) << HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< (HSTDMANXTDSC) Next Descriptor Address Mask */ -#define HSTDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (HSTDMANXTDSC) Register Mask */ - -/* -------- HSTDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Host DMA Channel Address Register -------- */ - -#define HSTDMAADDRESS_OFFSET (0x04) /**< (HSTDMAADDRESS) Host DMA Channel Address Register Offset */ - -#define HSTDMAADDRESS_BUFF_ADD_Pos 0 /**< (HSTDMAADDRESS) Buffer Address Position */ -#define HSTDMAADDRESS_BUFF_ADD (_U_(0xFFFFFFFF) << HSTDMAADDRESS_BUFF_ADD_Pos) /**< (HSTDMAADDRESS) Buffer Address Mask */ -#define HSTDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (HSTDMAADDRESS) Register Mask */ - -/* -------- HSTDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Host DMA Channel Control Register -------- */ - -#define HSTDMACONTROL_OFFSET (0x08) /**< (HSTDMACONTROL) Host DMA Channel Control Register Offset */ - -#define HSTDMACONTROL_CHANN_ENB_Pos 0 /**< (HSTDMACONTROL) Channel Enable Command Position */ -#define HSTDMACONTROL_CHANN_ENB (_U_(0x1) << HSTDMACONTROL_CHANN_ENB_Pos) /**< (HSTDMACONTROL) Channel Enable Command Mask */ -#define HSTDMACONTROL_LDNXT_DSC_Pos 1 /**< (HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ -#define HSTDMACONTROL_LDNXT_DSC (_U_(0x1) << HSTDMACONTROL_LDNXT_DSC_Pos) /**< (HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ -#define HSTDMACONTROL_END_TR_EN_Pos 2 /**< (HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ -#define HSTDMACONTROL_END_TR_EN (_U_(0x1) << HSTDMACONTROL_END_TR_EN_Pos) /**< (HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ -#define HSTDMACONTROL_END_B_EN_Pos 3 /**< (HSTDMACONTROL) End of Buffer Enable Control Position */ -#define HSTDMACONTROL_END_B_EN (_U_(0x1) << HSTDMACONTROL_END_B_EN_Pos) /**< (HSTDMACONTROL) End of Buffer Enable Control Mask */ -#define HSTDMACONTROL_END_TR_IT_Pos 4 /**< (HSTDMACONTROL) End of Transfer Interrupt Enable Position */ -#define HSTDMACONTROL_END_TR_IT (_U_(0x1) << HSTDMACONTROL_END_TR_IT_Pos) /**< (HSTDMACONTROL) End of Transfer Interrupt Enable Mask */ -#define HSTDMACONTROL_END_BUFFIT_Pos 5 /**< (HSTDMACONTROL) End of Buffer Interrupt Enable Position */ -#define HSTDMACONTROL_END_BUFFIT (_U_(0x1) << HSTDMACONTROL_END_BUFFIT_Pos) /**< (HSTDMACONTROL) End of Buffer Interrupt Enable Mask */ -#define HSTDMACONTROL_DESC_LD_IT_Pos 6 /**< (HSTDMACONTROL) Descriptor Loaded Interrupt Enable Position */ -#define HSTDMACONTROL_DESC_LD_IT (_U_(0x1) << HSTDMACONTROL_DESC_LD_IT_Pos) /**< (HSTDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ -#define HSTDMACONTROL_BURST_LCK_Pos 7 /**< (HSTDMACONTROL) Burst Lock Enable Position */ -#define HSTDMACONTROL_BURST_LCK (_U_(0x1) << HSTDMACONTROL_BURST_LCK_Pos) /**< (HSTDMACONTROL) Burst Lock Enable Mask */ -#define HSTDMACONTROL_BUFF_LENGTH_Pos 16 /**< (HSTDMACONTROL) Buffer Byte Length (Write-only) Position */ -#define HSTDMACONTROL_BUFF_LENGTH (_U_(0xFFFF) << HSTDMACONTROL_BUFF_LENGTH_Pos) /**< (HSTDMACONTROL) Buffer Byte Length (Write-only) Mask */ -#define HSTDMACONTROL_Msk _U_(0xFFFF00FF) /**< (HSTDMACONTROL) Register Mask */ - -/* -------- HSTDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Host DMA Channel Status Register -------- */ - -#define HSTDMASTATUS_OFFSET (0x0C) /**< (HSTDMASTATUS) Host DMA Channel Status Register Offset */ - -#define HSTDMASTATUS_CHANN_ENB_Pos 0 /**< (HSTDMASTATUS) Channel Enable Status Position */ -#define HSTDMASTATUS_CHANN_ENB (_U_(0x1) << HSTDMASTATUS_CHANN_ENB_Pos) /**< (HSTDMASTATUS) Channel Enable Status Mask */ -#define HSTDMASTATUS_CHANN_ACT_Pos 1 /**< (HSTDMASTATUS) Channel Active Status Position */ -#define HSTDMASTATUS_CHANN_ACT (_U_(0x1) << HSTDMASTATUS_CHANN_ACT_Pos) /**< (HSTDMASTATUS) Channel Active Status Mask */ -#define HSTDMASTATUS_END_TR_ST_Pos 4 /**< (HSTDMASTATUS) End of Channel Transfer Status Position */ -#define HSTDMASTATUS_END_TR_ST (_U_(0x1) << HSTDMASTATUS_END_TR_ST_Pos) /**< (HSTDMASTATUS) End of Channel Transfer Status Mask */ -#define HSTDMASTATUS_END_BF_ST_Pos 5 /**< (HSTDMASTATUS) End of Channel Buffer Status Position */ -#define HSTDMASTATUS_END_BF_ST (_U_(0x1) << HSTDMASTATUS_END_BF_ST_Pos) /**< (HSTDMASTATUS) End of Channel Buffer Status Mask */ -#define HSTDMASTATUS_DESC_LDST_Pos 6 /**< (HSTDMASTATUS) Descriptor Loaded Status Position */ -#define HSTDMASTATUS_DESC_LDST (_U_(0x1) << HSTDMASTATUS_DESC_LDST_Pos) /**< (HSTDMASTATUS) Descriptor Loaded Status Mask */ -#define HSTDMASTATUS_BUFF_COUNT_Pos 16 /**< (HSTDMASTATUS) Buffer Byte Count Position */ -#define HSTDMASTATUS_BUFF_COUNT (_U_(0xFFFF) << HSTDMASTATUS_BUFF_COUNT_Pos) /**< (HSTDMASTATUS) Buffer Byte Count Mask */ -#define HSTDMASTATUS_Msk _U_(0xFFFF0073) /**< (HSTDMASTATUS) Register Mask */ - -/* -------- DEVCTRL : (USBHS Offset: 0x00) (R/W 32) Device General Control Register -------- */ - -#define DEVCTRL_OFFSET (0x00) /**< (DEVCTRL) Device General Control Register Offset */ - -#define DEVCTRL_UADD_Pos 0 /**< (DEVCTRL) USB Address Position */ -#define DEVCTRL_UADD (_U_(0x7F) << DEVCTRL_UADD_Pos) /**< (DEVCTRL) USB Address Mask */ -#define DEVCTRL_ADDEN_Pos 7 /**< (DEVCTRL) Address Enable Position */ -#define DEVCTRL_ADDEN (_U_(0x1) << DEVCTRL_ADDEN_Pos) /**< (DEVCTRL) Address Enable Mask */ -#define DEVCTRL_DETACH_Pos 8 /**< (DEVCTRL) Detach Position */ -#define DEVCTRL_DETACH (_U_(0x1) << DEVCTRL_DETACH_Pos) /**< (DEVCTRL) Detach Mask */ -#define DEVCTRL_RMWKUP_Pos 9 /**< (DEVCTRL) Remote Wake-Up Position */ -#define DEVCTRL_RMWKUP (_U_(0x1) << DEVCTRL_RMWKUP_Pos) /**< (DEVCTRL) Remote Wake-Up Mask */ -#define DEVCTRL_SPDCONF_Pos 10 /**< (DEVCTRL) Mode Configuration Position */ -#define DEVCTRL_SPDCONF (_U_(0x3) << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) Mode Configuration Mask */ -#define DEVCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ -#define DEVCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (DEVCTRL) For a better consumption, if high speed is not needed. */ -#define DEVCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (DEVCTRL) Forced high speed. */ -#define DEVCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ -#define DEVCTRL_SPDCONF_NORMAL (DEVCTRL_SPDCONF_NORMAL_Val << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. Position */ -#define DEVCTRL_SPDCONF_LOW_POWER (DEVCTRL_SPDCONF_LOW_POWER_Val << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) For a better consumption, if high speed is not needed. Position */ -#define DEVCTRL_SPDCONF_HIGH_SPEED (DEVCTRL_SPDCONF_HIGH_SPEED_Val << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) Forced high speed. Position */ -#define DEVCTRL_SPDCONF_FORCED_FS (DEVCTRL_SPDCONF_FORCED_FS_Val << DEVCTRL_SPDCONF_Pos) /**< (DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. Position */ -#define DEVCTRL_LS_Pos 12 /**< (DEVCTRL) Low-Speed Mode Force Position */ -#define DEVCTRL_LS (_U_(0x1) << DEVCTRL_LS_Pos) /**< (DEVCTRL) Low-Speed Mode Force Mask */ -#define DEVCTRL_TSTJ_Pos 13 /**< (DEVCTRL) Test mode J Position */ -#define DEVCTRL_TSTJ (_U_(0x1) << DEVCTRL_TSTJ_Pos) /**< (DEVCTRL) Test mode J Mask */ -#define DEVCTRL_TSTK_Pos 14 /**< (DEVCTRL) Test mode K Position */ -#define DEVCTRL_TSTK (_U_(0x1) << DEVCTRL_TSTK_Pos) /**< (DEVCTRL) Test mode K Mask */ -#define DEVCTRL_TSTPCKT_Pos 15 /**< (DEVCTRL) Test packet mode Position */ -#define DEVCTRL_TSTPCKT (_U_(0x1) << DEVCTRL_TSTPCKT_Pos) /**< (DEVCTRL) Test packet mode Mask */ -#define DEVCTRL_OPMODE2_Pos 16 /**< (DEVCTRL) Specific Operational mode Position */ -#define DEVCTRL_OPMODE2 (_U_(0x1) << DEVCTRL_OPMODE2_Pos) /**< (DEVCTRL) Specific Operational mode Mask */ -#define DEVCTRL_Msk _U_(0x1FFFF) /**< (DEVCTRL) Register Mask */ - -#define DEVCTRL_OPMODE_Pos 16 /**< (DEVCTRL Position) Specific Operational mode */ -#define DEVCTRL_OPMODE (_U_(0x1) << DEVCTRL_OPMODE_Pos) /**< (DEVCTRL Mask) OPMODE */ - -/* -------- DEVISR : (USBHS Offset: 0x04) (R/ 32) Device Global Interrupt Status Register -------- */ - -#define DEVISR_OFFSET (0x04) /**< (DEVISR) Device Global Interrupt Status Register Offset */ - -#define DEVISR_SUSP_Pos 0 /**< (DEVISR) Suspend Interrupt Position */ -#define DEVISR_SUSP (_U_(0x1) << DEVISR_SUSP_Pos) /**< (DEVISR) Suspend Interrupt Mask */ -#define DEVISR_MSOF_Pos 1 /**< (DEVISR) Micro Start of Frame Interrupt Position */ -#define DEVISR_MSOF (_U_(0x1) << DEVISR_MSOF_Pos) /**< (DEVISR) Micro Start of Frame Interrupt Mask */ -#define DEVISR_SOF_Pos 2 /**< (DEVISR) Start of Frame Interrupt Position */ -#define DEVISR_SOF (_U_(0x1) << DEVISR_SOF_Pos) /**< (DEVISR) Start of Frame Interrupt Mask */ -#define DEVISR_EORST_Pos 3 /**< (DEVISR) End of Reset Interrupt Position */ -#define DEVISR_EORST (_U_(0x1) << DEVISR_EORST_Pos) /**< (DEVISR) End of Reset Interrupt Mask */ -#define DEVISR_WAKEUP_Pos 4 /**< (DEVISR) Wake-Up Interrupt Position */ -#define DEVISR_WAKEUP (_U_(0x1) << DEVISR_WAKEUP_Pos) /**< (DEVISR) Wake-Up Interrupt Mask */ -#define DEVISR_EORSM_Pos 5 /**< (DEVISR) End of Resume Interrupt Position */ -#define DEVISR_EORSM (_U_(0x1) << DEVISR_EORSM_Pos) /**< (DEVISR) End of Resume Interrupt Mask */ -#define DEVISR_UPRSM_Pos 6 /**< (DEVISR) Upstream Resume Interrupt Position */ -#define DEVISR_UPRSM (_U_(0x1) << DEVISR_UPRSM_Pos) /**< (DEVISR) Upstream Resume Interrupt Mask */ -#define DEVISR_PEP_0_Pos 12 /**< (DEVISR) Endpoint 0 Interrupt Position */ -#define DEVISR_PEP_0 (_U_(0x1) << DEVISR_PEP_0_Pos) /**< (DEVISR) Endpoint 0 Interrupt Mask */ -#define DEVISR_PEP_1_Pos 13 /**< (DEVISR) Endpoint 1 Interrupt Position */ -#define DEVISR_PEP_1 (_U_(0x1) << DEVISR_PEP_1_Pos) /**< (DEVISR) Endpoint 1 Interrupt Mask */ -#define DEVISR_PEP_2_Pos 14 /**< (DEVISR) Endpoint 2 Interrupt Position */ -#define DEVISR_PEP_2 (_U_(0x1) << DEVISR_PEP_2_Pos) /**< (DEVISR) Endpoint 2 Interrupt Mask */ -#define DEVISR_PEP_3_Pos 15 /**< (DEVISR) Endpoint 3 Interrupt Position */ -#define DEVISR_PEP_3 (_U_(0x1) << DEVISR_PEP_3_Pos) /**< (DEVISR) Endpoint 3 Interrupt Mask */ -#define DEVISR_PEP_4_Pos 16 /**< (DEVISR) Endpoint 4 Interrupt Position */ -#define DEVISR_PEP_4 (_U_(0x1) << DEVISR_PEP_4_Pos) /**< (DEVISR) Endpoint 4 Interrupt Mask */ -#define DEVISR_PEP_5_Pos 17 /**< (DEVISR) Endpoint 5 Interrupt Position */ -#define DEVISR_PEP_5 (_U_(0x1) << DEVISR_PEP_5_Pos) /**< (DEVISR) Endpoint 5 Interrupt Mask */ -#define DEVISR_PEP_6_Pos 18 /**< (DEVISR) Endpoint 6 Interrupt Position */ -#define DEVISR_PEP_6 (_U_(0x1) << DEVISR_PEP_6_Pos) /**< (DEVISR) Endpoint 6 Interrupt Mask */ -#define DEVISR_PEP_7_Pos 19 /**< (DEVISR) Endpoint 7 Interrupt Position */ -#define DEVISR_PEP_7 (_U_(0x1) << DEVISR_PEP_7_Pos) /**< (DEVISR) Endpoint 7 Interrupt Mask */ -#define DEVISR_PEP_8_Pos 20 /**< (DEVISR) Endpoint 8 Interrupt Position */ -#define DEVISR_PEP_8 (_U_(0x1) << DEVISR_PEP_8_Pos) /**< (DEVISR) Endpoint 8 Interrupt Mask */ -#define DEVISR_PEP_9_Pos 21 /**< (DEVISR) Endpoint 9 Interrupt Position */ -#define DEVISR_PEP_9 (_U_(0x1) << DEVISR_PEP_9_Pos) /**< (DEVISR) Endpoint 9 Interrupt Mask */ -#define DEVISR_DMA_1_Pos 25 /**< (DEVISR) DMA Channel 1 Interrupt Position */ -#define DEVISR_DMA_1 (_U_(0x1) << DEVISR_DMA_1_Pos) /**< (DEVISR) DMA Channel 1 Interrupt Mask */ -#define DEVISR_DMA_2_Pos 26 /**< (DEVISR) DMA Channel 2 Interrupt Position */ -#define DEVISR_DMA_2 (_U_(0x1) << DEVISR_DMA_2_Pos) /**< (DEVISR) DMA Channel 2 Interrupt Mask */ -#define DEVISR_DMA_3_Pos 27 /**< (DEVISR) DMA Channel 3 Interrupt Position */ -#define DEVISR_DMA_3 (_U_(0x1) << DEVISR_DMA_3_Pos) /**< (DEVISR) DMA Channel 3 Interrupt Mask */ -#define DEVISR_DMA_4_Pos 28 /**< (DEVISR) DMA Channel 4 Interrupt Position */ -#define DEVISR_DMA_4 (_U_(0x1) << DEVISR_DMA_4_Pos) /**< (DEVISR) DMA Channel 4 Interrupt Mask */ -#define DEVISR_DMA_5_Pos 29 /**< (DEVISR) DMA Channel 5 Interrupt Position */ -#define DEVISR_DMA_5 (_U_(0x1) << DEVISR_DMA_5_Pos) /**< (DEVISR) DMA Channel 5 Interrupt Mask */ -#define DEVISR_DMA_6_Pos 30 /**< (DEVISR) DMA Channel 6 Interrupt Position */ -#define DEVISR_DMA_6 (_U_(0x1) << DEVISR_DMA_6_Pos) /**< (DEVISR) DMA Channel 6 Interrupt Mask */ -#define DEVISR_DMA_7_Pos 31 /**< (DEVISR) DMA Channel 7 Interrupt Position */ -#define DEVISR_DMA_7 (_U_(0x1) << DEVISR_DMA_7_Pos) /**< (DEVISR) DMA Channel 7 Interrupt Mask */ -#define DEVISR_Msk _U_(0xFE3FF07F) /**< (DEVISR) Register Mask */ - -#define DEVISR_PEP__Pos 12 /**< (DEVISR Position) Endpoint x Interrupt */ -#define DEVISR_PEP_ (_U_(0x3FF) << DEVISR_PEP__Pos) /**< (DEVISR Mask) PEP_ */ -#define DEVISR_DMA__Pos 25 /**< (DEVISR Position) DMA Channel 7 Interrupt */ -#define DEVISR_DMA_ (_U_(0x7F) << DEVISR_DMA__Pos) /**< (DEVISR Mask) DMA_ */ - -/* -------- DEVICR : (USBHS Offset: 0x08) (/W 32) Device Global Interrupt Clear Register -------- */ - -#define DEVICR_OFFSET (0x08) /**< (DEVICR) Device Global Interrupt Clear Register Offset */ - -#define DEVICR_SUSPC_Pos 0 /**< (DEVICR) Suspend Interrupt Clear Position */ -#define DEVICR_SUSPC (_U_(0x1) << DEVICR_SUSPC_Pos) /**< (DEVICR) Suspend Interrupt Clear Mask */ -#define DEVICR_MSOFC_Pos 1 /**< (DEVICR) Micro Start of Frame Interrupt Clear Position */ -#define DEVICR_MSOFC (_U_(0x1) << DEVICR_MSOFC_Pos) /**< (DEVICR) Micro Start of Frame Interrupt Clear Mask */ -#define DEVICR_SOFC_Pos 2 /**< (DEVICR) Start of Frame Interrupt Clear Position */ -#define DEVICR_SOFC (_U_(0x1) << DEVICR_SOFC_Pos) /**< (DEVICR) Start of Frame Interrupt Clear Mask */ -#define DEVICR_EORSTC_Pos 3 /**< (DEVICR) End of Reset Interrupt Clear Position */ -#define DEVICR_EORSTC (_U_(0x1) << DEVICR_EORSTC_Pos) /**< (DEVICR) End of Reset Interrupt Clear Mask */ -#define DEVICR_WAKEUPC_Pos 4 /**< (DEVICR) Wake-Up Interrupt Clear Position */ -#define DEVICR_WAKEUPC (_U_(0x1) << DEVICR_WAKEUPC_Pos) /**< (DEVICR) Wake-Up Interrupt Clear Mask */ -#define DEVICR_EORSMC_Pos 5 /**< (DEVICR) End of Resume Interrupt Clear Position */ -#define DEVICR_EORSMC (_U_(0x1) << DEVICR_EORSMC_Pos) /**< (DEVICR) End of Resume Interrupt Clear Mask */ -#define DEVICR_UPRSMC_Pos 6 /**< (DEVICR) Upstream Resume Interrupt Clear Position */ -#define DEVICR_UPRSMC (_U_(0x1) << DEVICR_UPRSMC_Pos) /**< (DEVICR) Upstream Resume Interrupt Clear Mask */ -#define DEVICR_Msk _U_(0x7F) /**< (DEVICR) Register Mask */ - -/* -------- DEVIFR : (USBHS Offset: 0x0c) (/W 32) Device Global Interrupt Set Register -------- */ - -#define DEVIFR_OFFSET (0x0C) /**< (DEVIFR) Device Global Interrupt Set Register Offset */ - -#define DEVIFR_SUSPS_Pos 0 /**< (DEVIFR) Suspend Interrupt Set Position */ -#define DEVIFR_SUSPS (_U_(0x1) << DEVIFR_SUSPS_Pos) /**< (DEVIFR) Suspend Interrupt Set Mask */ -#define DEVIFR_MSOFS_Pos 1 /**< (DEVIFR) Micro Start of Frame Interrupt Set Position */ -#define DEVIFR_MSOFS (_U_(0x1) << DEVIFR_MSOFS_Pos) /**< (DEVIFR) Micro Start of Frame Interrupt Set Mask */ -#define DEVIFR_SOFS_Pos 2 /**< (DEVIFR) Start of Frame Interrupt Set Position */ -#define DEVIFR_SOFS (_U_(0x1) << DEVIFR_SOFS_Pos) /**< (DEVIFR) Start of Frame Interrupt Set Mask */ -#define DEVIFR_EORSTS_Pos 3 /**< (DEVIFR) End of Reset Interrupt Set Position */ -#define DEVIFR_EORSTS (_U_(0x1) << DEVIFR_EORSTS_Pos) /**< (DEVIFR) End of Reset Interrupt Set Mask */ -#define DEVIFR_WAKEUPS_Pos 4 /**< (DEVIFR) Wake-Up Interrupt Set Position */ -#define DEVIFR_WAKEUPS (_U_(0x1) << DEVIFR_WAKEUPS_Pos) /**< (DEVIFR) Wake-Up Interrupt Set Mask */ -#define DEVIFR_EORSMS_Pos 5 /**< (DEVIFR) End of Resume Interrupt Set Position */ -#define DEVIFR_EORSMS (_U_(0x1) << DEVIFR_EORSMS_Pos) /**< (DEVIFR) End of Resume Interrupt Set Mask */ -#define DEVIFR_UPRSMS_Pos 6 /**< (DEVIFR) Upstream Resume Interrupt Set Position */ -#define DEVIFR_UPRSMS (_U_(0x1) << DEVIFR_UPRSMS_Pos) /**< (DEVIFR) Upstream Resume Interrupt Set Mask */ -#define DEVIFR_DMA_1_Pos 25 /**< (DEVIFR) DMA Channel 1 Interrupt Set Position */ -#define DEVIFR_DMA_1 (_U_(0x1) << DEVIFR_DMA_1_Pos) /**< (DEVIFR) DMA Channel 1 Interrupt Set Mask */ -#define DEVIFR_DMA_2_Pos 26 /**< (DEVIFR) DMA Channel 2 Interrupt Set Position */ -#define DEVIFR_DMA_2 (_U_(0x1) << DEVIFR_DMA_2_Pos) /**< (DEVIFR) DMA Channel 2 Interrupt Set Mask */ -#define DEVIFR_DMA_3_Pos 27 /**< (DEVIFR) DMA Channel 3 Interrupt Set Position */ -#define DEVIFR_DMA_3 (_U_(0x1) << DEVIFR_DMA_3_Pos) /**< (DEVIFR) DMA Channel 3 Interrupt Set Mask */ -#define DEVIFR_DMA_4_Pos 28 /**< (DEVIFR) DMA Channel 4 Interrupt Set Position */ -#define DEVIFR_DMA_4 (_U_(0x1) << DEVIFR_DMA_4_Pos) /**< (DEVIFR) DMA Channel 4 Interrupt Set Mask */ -#define DEVIFR_DMA_5_Pos 29 /**< (DEVIFR) DMA Channel 5 Interrupt Set Position */ -#define DEVIFR_DMA_5 (_U_(0x1) << DEVIFR_DMA_5_Pos) /**< (DEVIFR) DMA Channel 5 Interrupt Set Mask */ -#define DEVIFR_DMA_6_Pos 30 /**< (DEVIFR) DMA Channel 6 Interrupt Set Position */ -#define DEVIFR_DMA_6 (_U_(0x1) << DEVIFR_DMA_6_Pos) /**< (DEVIFR) DMA Channel 6 Interrupt Set Mask */ -#define DEVIFR_DMA_7_Pos 31 /**< (DEVIFR) DMA Channel 7 Interrupt Set Position */ -#define DEVIFR_DMA_7 (_U_(0x1) << DEVIFR_DMA_7_Pos) /**< (DEVIFR) DMA Channel 7 Interrupt Set Mask */ -#define DEVIFR_Msk _U_(0xFE00007F) /**< (DEVIFR) Register Mask */ - -#define DEVIFR_DMA__Pos 25 /**< (DEVIFR Position) DMA Channel 7 Interrupt Set */ -#define DEVIFR_DMA_ (_U_(0x7F) << DEVIFR_DMA__Pos) /**< (DEVIFR Mask) DMA_ */ - -/* -------- DEVIMR : (USBHS Offset: 0x10) (R/ 32) Device Global Interrupt Mask Register -------- */ - -#define DEVIMR_OFFSET (0x10) /**< (DEVIMR) Device Global Interrupt Mask Register Offset */ - -#define DEVIMR_SUSPE_Pos 0 /**< (DEVIMR) Suspend Interrupt Mask Position */ -#define DEVIMR_SUSPE (_U_(0x1) << DEVIMR_SUSPE_Pos) /**< (DEVIMR) Suspend Interrupt Mask Mask */ -#define DEVIMR_MSOFE_Pos 1 /**< (DEVIMR) Micro Start of Frame Interrupt Mask Position */ -#define DEVIMR_MSOFE (_U_(0x1) << DEVIMR_MSOFE_Pos) /**< (DEVIMR) Micro Start of Frame Interrupt Mask Mask */ -#define DEVIMR_SOFE_Pos 2 /**< (DEVIMR) Start of Frame Interrupt Mask Position */ -#define DEVIMR_SOFE (_U_(0x1) << DEVIMR_SOFE_Pos) /**< (DEVIMR) Start of Frame Interrupt Mask Mask */ -#define DEVIMR_EORSTE_Pos 3 /**< (DEVIMR) End of Reset Interrupt Mask Position */ -#define DEVIMR_EORSTE (_U_(0x1) << DEVIMR_EORSTE_Pos) /**< (DEVIMR) End of Reset Interrupt Mask Mask */ -#define DEVIMR_WAKEUPE_Pos 4 /**< (DEVIMR) Wake-Up Interrupt Mask Position */ -#define DEVIMR_WAKEUPE (_U_(0x1) << DEVIMR_WAKEUPE_Pos) /**< (DEVIMR) Wake-Up Interrupt Mask Mask */ -#define DEVIMR_EORSME_Pos 5 /**< (DEVIMR) End of Resume Interrupt Mask Position */ -#define DEVIMR_EORSME (_U_(0x1) << DEVIMR_EORSME_Pos) /**< (DEVIMR) End of Resume Interrupt Mask Mask */ -#define DEVIMR_UPRSME_Pos 6 /**< (DEVIMR) Upstream Resume Interrupt Mask Position */ -#define DEVIMR_UPRSME (_U_(0x1) << DEVIMR_UPRSME_Pos) /**< (DEVIMR) Upstream Resume Interrupt Mask Mask */ -#define DEVIMR_PEP_0_Pos 12 /**< (DEVIMR) Endpoint 0 Interrupt Mask Position */ -#define DEVIMR_PEP_0 (_U_(0x1) << DEVIMR_PEP_0_Pos) /**< (DEVIMR) Endpoint 0 Interrupt Mask Mask */ -#define DEVIMR_PEP_1_Pos 13 /**< (DEVIMR) Endpoint 1 Interrupt Mask Position */ -#define DEVIMR_PEP_1 (_U_(0x1) << DEVIMR_PEP_1_Pos) /**< (DEVIMR) Endpoint 1 Interrupt Mask Mask */ -#define DEVIMR_PEP_2_Pos 14 /**< (DEVIMR) Endpoint 2 Interrupt Mask Position */ -#define DEVIMR_PEP_2 (_U_(0x1) << DEVIMR_PEP_2_Pos) /**< (DEVIMR) Endpoint 2 Interrupt Mask Mask */ -#define DEVIMR_PEP_3_Pos 15 /**< (DEVIMR) Endpoint 3 Interrupt Mask Position */ -#define DEVIMR_PEP_3 (_U_(0x1) << DEVIMR_PEP_3_Pos) /**< (DEVIMR) Endpoint 3 Interrupt Mask Mask */ -#define DEVIMR_PEP_4_Pos 16 /**< (DEVIMR) Endpoint 4 Interrupt Mask Position */ -#define DEVIMR_PEP_4 (_U_(0x1) << DEVIMR_PEP_4_Pos) /**< (DEVIMR) Endpoint 4 Interrupt Mask Mask */ -#define DEVIMR_PEP_5_Pos 17 /**< (DEVIMR) Endpoint 5 Interrupt Mask Position */ -#define DEVIMR_PEP_5 (_U_(0x1) << DEVIMR_PEP_5_Pos) /**< (DEVIMR) Endpoint 5 Interrupt Mask Mask */ -#define DEVIMR_PEP_6_Pos 18 /**< (DEVIMR) Endpoint 6 Interrupt Mask Position */ -#define DEVIMR_PEP_6 (_U_(0x1) << DEVIMR_PEP_6_Pos) /**< (DEVIMR) Endpoint 6 Interrupt Mask Mask */ -#define DEVIMR_PEP_7_Pos 19 /**< (DEVIMR) Endpoint 7 Interrupt Mask Position */ -#define DEVIMR_PEP_7 (_U_(0x1) << DEVIMR_PEP_7_Pos) /**< (DEVIMR) Endpoint 7 Interrupt Mask Mask */ -#define DEVIMR_PEP_8_Pos 20 /**< (DEVIMR) Endpoint 8 Interrupt Mask Position */ -#define DEVIMR_PEP_8 (_U_(0x1) << DEVIMR_PEP_8_Pos) /**< (DEVIMR) Endpoint 8 Interrupt Mask Mask */ -#define DEVIMR_PEP_9_Pos 21 /**< (DEVIMR) Endpoint 9 Interrupt Mask Position */ -#define DEVIMR_PEP_9 (_U_(0x1) << DEVIMR_PEP_9_Pos) /**< (DEVIMR) Endpoint 9 Interrupt Mask Mask */ -#define DEVIMR_DMA_1_Pos 25 /**< (DEVIMR) DMA Channel 1 Interrupt Mask Position */ -#define DEVIMR_DMA_1 (_U_(0x1) << DEVIMR_DMA_1_Pos) /**< (DEVIMR) DMA Channel 1 Interrupt Mask Mask */ -#define DEVIMR_DMA_2_Pos 26 /**< (DEVIMR) DMA Channel 2 Interrupt Mask Position */ -#define DEVIMR_DMA_2 (_U_(0x1) << DEVIMR_DMA_2_Pos) /**< (DEVIMR) DMA Channel 2 Interrupt Mask Mask */ -#define DEVIMR_DMA_3_Pos 27 /**< (DEVIMR) DMA Channel 3 Interrupt Mask Position */ -#define DEVIMR_DMA_3 (_U_(0x1) << DEVIMR_DMA_3_Pos) /**< (DEVIMR) DMA Channel 3 Interrupt Mask Mask */ -#define DEVIMR_DMA_4_Pos 28 /**< (DEVIMR) DMA Channel 4 Interrupt Mask Position */ -#define DEVIMR_DMA_4 (_U_(0x1) << DEVIMR_DMA_4_Pos) /**< (DEVIMR) DMA Channel 4 Interrupt Mask Mask */ -#define DEVIMR_DMA_5_Pos 29 /**< (DEVIMR) DMA Channel 5 Interrupt Mask Position */ -#define DEVIMR_DMA_5 (_U_(0x1) << DEVIMR_DMA_5_Pos) /**< (DEVIMR) DMA Channel 5 Interrupt Mask Mask */ -#define DEVIMR_DMA_6_Pos 30 /**< (DEVIMR) DMA Channel 6 Interrupt Mask Position */ -#define DEVIMR_DMA_6 (_U_(0x1) << DEVIMR_DMA_6_Pos) /**< (DEVIMR) DMA Channel 6 Interrupt Mask Mask */ -#define DEVIMR_DMA_7_Pos 31 /**< (DEVIMR) DMA Channel 7 Interrupt Mask Position */ -#define DEVIMR_DMA_7 (_U_(0x1) << DEVIMR_DMA_7_Pos) /**< (DEVIMR) DMA Channel 7 Interrupt Mask Mask */ -#define DEVIMR_Msk _U_(0xFE3FF07F) /**< (DEVIMR) Register Mask */ - -#define DEVIMR_PEP__Pos 12 /**< (DEVIMR Position) Endpoint x Interrupt Mask */ -#define DEVIMR_PEP_ (_U_(0x3FF) << DEVIMR_PEP__Pos) /**< (DEVIMR Mask) PEP_ */ -#define DEVIMR_DMA__Pos 25 /**< (DEVIMR Position) DMA Channel 7 Interrupt Mask */ -#define DEVIMR_DMA_ (_U_(0x7F) << DEVIMR_DMA__Pos) /**< (DEVIMR Mask) DMA_ */ - -/* -------- DEVIDR : (USBHS Offset: 0x14) (/W 32) Device Global Interrupt Disable Register -------- */ - -#define DEVIDR_OFFSET (0x14) /**< (DEVIDR) Device Global Interrupt Disable Register Offset */ - -#define DEVIDR_SUSPEC_Pos 0 /**< (DEVIDR) Suspend Interrupt Disable Position */ -#define DEVIDR_SUSPEC (_U_(0x1) << DEVIDR_SUSPEC_Pos) /**< (DEVIDR) Suspend Interrupt Disable Mask */ -#define DEVIDR_MSOFEC_Pos 1 /**< (DEVIDR) Micro Start of Frame Interrupt Disable Position */ -#define DEVIDR_MSOFEC (_U_(0x1) << DEVIDR_MSOFEC_Pos) /**< (DEVIDR) Micro Start of Frame Interrupt Disable Mask */ -#define DEVIDR_SOFEC_Pos 2 /**< (DEVIDR) Start of Frame Interrupt Disable Position */ -#define DEVIDR_SOFEC (_U_(0x1) << DEVIDR_SOFEC_Pos) /**< (DEVIDR) Start of Frame Interrupt Disable Mask */ -#define DEVIDR_EORSTEC_Pos 3 /**< (DEVIDR) End of Reset Interrupt Disable Position */ -#define DEVIDR_EORSTEC (_U_(0x1) << DEVIDR_EORSTEC_Pos) /**< (DEVIDR) End of Reset Interrupt Disable Mask */ -#define DEVIDR_WAKEUPEC_Pos 4 /**< (DEVIDR) Wake-Up Interrupt Disable Position */ -#define DEVIDR_WAKEUPEC (_U_(0x1) << DEVIDR_WAKEUPEC_Pos) /**< (DEVIDR) Wake-Up Interrupt Disable Mask */ -#define DEVIDR_EORSMEC_Pos 5 /**< (DEVIDR) End of Resume Interrupt Disable Position */ -#define DEVIDR_EORSMEC (_U_(0x1) << DEVIDR_EORSMEC_Pos) /**< (DEVIDR) End of Resume Interrupt Disable Mask */ -#define DEVIDR_UPRSMEC_Pos 6 /**< (DEVIDR) Upstream Resume Interrupt Disable Position */ -#define DEVIDR_UPRSMEC (_U_(0x1) << DEVIDR_UPRSMEC_Pos) /**< (DEVIDR) Upstream Resume Interrupt Disable Mask */ -#define DEVIDR_PEP_0_Pos 12 /**< (DEVIDR) Endpoint 0 Interrupt Disable Position */ -#define DEVIDR_PEP_0 (_U_(0x1) << DEVIDR_PEP_0_Pos) /**< (DEVIDR) Endpoint 0 Interrupt Disable Mask */ -#define DEVIDR_PEP_1_Pos 13 /**< (DEVIDR) Endpoint 1 Interrupt Disable Position */ -#define DEVIDR_PEP_1 (_U_(0x1) << DEVIDR_PEP_1_Pos) /**< (DEVIDR) Endpoint 1 Interrupt Disable Mask */ -#define DEVIDR_PEP_2_Pos 14 /**< (DEVIDR) Endpoint 2 Interrupt Disable Position */ -#define DEVIDR_PEP_2 (_U_(0x1) << DEVIDR_PEP_2_Pos) /**< (DEVIDR) Endpoint 2 Interrupt Disable Mask */ -#define DEVIDR_PEP_3_Pos 15 /**< (DEVIDR) Endpoint 3 Interrupt Disable Position */ -#define DEVIDR_PEP_3 (_U_(0x1) << DEVIDR_PEP_3_Pos) /**< (DEVIDR) Endpoint 3 Interrupt Disable Mask */ -#define DEVIDR_PEP_4_Pos 16 /**< (DEVIDR) Endpoint 4 Interrupt Disable Position */ -#define DEVIDR_PEP_4 (_U_(0x1) << DEVIDR_PEP_4_Pos) /**< (DEVIDR) Endpoint 4 Interrupt Disable Mask */ -#define DEVIDR_PEP_5_Pos 17 /**< (DEVIDR) Endpoint 5 Interrupt Disable Position */ -#define DEVIDR_PEP_5 (_U_(0x1) << DEVIDR_PEP_5_Pos) /**< (DEVIDR) Endpoint 5 Interrupt Disable Mask */ -#define DEVIDR_PEP_6_Pos 18 /**< (DEVIDR) Endpoint 6 Interrupt Disable Position */ -#define DEVIDR_PEP_6 (_U_(0x1) << DEVIDR_PEP_6_Pos) /**< (DEVIDR) Endpoint 6 Interrupt Disable Mask */ -#define DEVIDR_PEP_7_Pos 19 /**< (DEVIDR) Endpoint 7 Interrupt Disable Position */ -#define DEVIDR_PEP_7 (_U_(0x1) << DEVIDR_PEP_7_Pos) /**< (DEVIDR) Endpoint 7 Interrupt Disable Mask */ -#define DEVIDR_PEP_8_Pos 20 /**< (DEVIDR) Endpoint 8 Interrupt Disable Position */ -#define DEVIDR_PEP_8 (_U_(0x1) << DEVIDR_PEP_8_Pos) /**< (DEVIDR) Endpoint 8 Interrupt Disable Mask */ -#define DEVIDR_PEP_9_Pos 21 /**< (DEVIDR) Endpoint 9 Interrupt Disable Position */ -#define DEVIDR_PEP_9 (_U_(0x1) << DEVIDR_PEP_9_Pos) /**< (DEVIDR) Endpoint 9 Interrupt Disable Mask */ -#define DEVIDR_DMA_1_Pos 25 /**< (DEVIDR) DMA Channel 1 Interrupt Disable Position */ -#define DEVIDR_DMA_1 (_U_(0x1) << DEVIDR_DMA_1_Pos) /**< (DEVIDR) DMA Channel 1 Interrupt Disable Mask */ -#define DEVIDR_DMA_2_Pos 26 /**< (DEVIDR) DMA Channel 2 Interrupt Disable Position */ -#define DEVIDR_DMA_2 (_U_(0x1) << DEVIDR_DMA_2_Pos) /**< (DEVIDR) DMA Channel 2 Interrupt Disable Mask */ -#define DEVIDR_DMA_3_Pos 27 /**< (DEVIDR) DMA Channel 3 Interrupt Disable Position */ -#define DEVIDR_DMA_3 (_U_(0x1) << DEVIDR_DMA_3_Pos) /**< (DEVIDR) DMA Channel 3 Interrupt Disable Mask */ -#define DEVIDR_DMA_4_Pos 28 /**< (DEVIDR) DMA Channel 4 Interrupt Disable Position */ -#define DEVIDR_DMA_4 (_U_(0x1) << DEVIDR_DMA_4_Pos) /**< (DEVIDR) DMA Channel 4 Interrupt Disable Mask */ -#define DEVIDR_DMA_5_Pos 29 /**< (DEVIDR) DMA Channel 5 Interrupt Disable Position */ -#define DEVIDR_DMA_5 (_U_(0x1) << DEVIDR_DMA_5_Pos) /**< (DEVIDR) DMA Channel 5 Interrupt Disable Mask */ -#define DEVIDR_DMA_6_Pos 30 /**< (DEVIDR) DMA Channel 6 Interrupt Disable Position */ -#define DEVIDR_DMA_6 (_U_(0x1) << DEVIDR_DMA_6_Pos) /**< (DEVIDR) DMA Channel 6 Interrupt Disable Mask */ -#define DEVIDR_DMA_7_Pos 31 /**< (DEVIDR) DMA Channel 7 Interrupt Disable Position */ -#define DEVIDR_DMA_7 (_U_(0x1) << DEVIDR_DMA_7_Pos) /**< (DEVIDR) DMA Channel 7 Interrupt Disable Mask */ -#define DEVIDR_Msk _U_(0xFE3FF07F) /**< (DEVIDR) Register Mask */ - -#define DEVIDR_PEP__Pos 12 /**< (DEVIDR Position) Endpoint x Interrupt Disable */ -#define DEVIDR_PEP_ (_U_(0x3FF) << DEVIDR_PEP__Pos) /**< (DEVIDR Mask) PEP_ */ -#define DEVIDR_DMA__Pos 25 /**< (DEVIDR Position) DMA Channel 7 Interrupt Disable */ -#define DEVIDR_DMA_ (_U_(0x7F) << DEVIDR_DMA__Pos) /**< (DEVIDR Mask) DMA_ */ - -/* -------- DEVIER : (USBHS Offset: 0x18) (/W 32) Device Global Interrupt Enable Register -------- */ - -#define DEVIER_OFFSET (0x18) /**< (DEVIER) Device Global Interrupt Enable Register Offset */ - -#define DEVIER_SUSPES_Pos 0 /**< (DEVIER) Suspend Interrupt Enable Position */ -#define DEVIER_SUSPES (_U_(0x1) << DEVIER_SUSPES_Pos) /**< (DEVIER) Suspend Interrupt Enable Mask */ -#define DEVIER_MSOFES_Pos 1 /**< (DEVIER) Micro Start of Frame Interrupt Enable Position */ -#define DEVIER_MSOFES (_U_(0x1) << DEVIER_MSOFES_Pos) /**< (DEVIER) Micro Start of Frame Interrupt Enable Mask */ -#define DEVIER_SOFES_Pos 2 /**< (DEVIER) Start of Frame Interrupt Enable Position */ -#define DEVIER_SOFES (_U_(0x1) << DEVIER_SOFES_Pos) /**< (DEVIER) Start of Frame Interrupt Enable Mask */ -#define DEVIER_EORSTES_Pos 3 /**< (DEVIER) End of Reset Interrupt Enable Position */ -#define DEVIER_EORSTES (_U_(0x1) << DEVIER_EORSTES_Pos) /**< (DEVIER) End of Reset Interrupt Enable Mask */ -#define DEVIER_WAKEUPES_Pos 4 /**< (DEVIER) Wake-Up Interrupt Enable Position */ -#define DEVIER_WAKEUPES (_U_(0x1) << DEVIER_WAKEUPES_Pos) /**< (DEVIER) Wake-Up Interrupt Enable Mask */ -#define DEVIER_EORSMES_Pos 5 /**< (DEVIER) End of Resume Interrupt Enable Position */ -#define DEVIER_EORSMES (_U_(0x1) << DEVIER_EORSMES_Pos) /**< (DEVIER) End of Resume Interrupt Enable Mask */ -#define DEVIER_UPRSMES_Pos 6 /**< (DEVIER) Upstream Resume Interrupt Enable Position */ -#define DEVIER_UPRSMES (_U_(0x1) << DEVIER_UPRSMES_Pos) /**< (DEVIER) Upstream Resume Interrupt Enable Mask */ -#define DEVIER_PEP_0_Pos 12 /**< (DEVIER) Endpoint 0 Interrupt Enable Position */ -#define DEVIER_PEP_0 (_U_(0x1) << DEVIER_PEP_0_Pos) /**< (DEVIER) Endpoint 0 Interrupt Enable Mask */ -#define DEVIER_PEP_1_Pos 13 /**< (DEVIER) Endpoint 1 Interrupt Enable Position */ -#define DEVIER_PEP_1 (_U_(0x1) << DEVIER_PEP_1_Pos) /**< (DEVIER) Endpoint 1 Interrupt Enable Mask */ -#define DEVIER_PEP_2_Pos 14 /**< (DEVIER) Endpoint 2 Interrupt Enable Position */ -#define DEVIER_PEP_2 (_U_(0x1) << DEVIER_PEP_2_Pos) /**< (DEVIER) Endpoint 2 Interrupt Enable Mask */ -#define DEVIER_PEP_3_Pos 15 /**< (DEVIER) Endpoint 3 Interrupt Enable Position */ -#define DEVIER_PEP_3 (_U_(0x1) << DEVIER_PEP_3_Pos) /**< (DEVIER) Endpoint 3 Interrupt Enable Mask */ -#define DEVIER_PEP_4_Pos 16 /**< (DEVIER) Endpoint 4 Interrupt Enable Position */ -#define DEVIER_PEP_4 (_U_(0x1) << DEVIER_PEP_4_Pos) /**< (DEVIER) Endpoint 4 Interrupt Enable Mask */ -#define DEVIER_PEP_5_Pos 17 /**< (DEVIER) Endpoint 5 Interrupt Enable Position */ -#define DEVIER_PEP_5 (_U_(0x1) << DEVIER_PEP_5_Pos) /**< (DEVIER) Endpoint 5 Interrupt Enable Mask */ -#define DEVIER_PEP_6_Pos 18 /**< (DEVIER) Endpoint 6 Interrupt Enable Position */ -#define DEVIER_PEP_6 (_U_(0x1) << DEVIER_PEP_6_Pos) /**< (DEVIER) Endpoint 6 Interrupt Enable Mask */ -#define DEVIER_PEP_7_Pos 19 /**< (DEVIER) Endpoint 7 Interrupt Enable Position */ -#define DEVIER_PEP_7 (_U_(0x1) << DEVIER_PEP_7_Pos) /**< (DEVIER) Endpoint 7 Interrupt Enable Mask */ -#define DEVIER_PEP_8_Pos 20 /**< (DEVIER) Endpoint 8 Interrupt Enable Position */ -#define DEVIER_PEP_8 (_U_(0x1) << DEVIER_PEP_8_Pos) /**< (DEVIER) Endpoint 8 Interrupt Enable Mask */ -#define DEVIER_PEP_9_Pos 21 /**< (DEVIER) Endpoint 9 Interrupt Enable Position */ -#define DEVIER_PEP_9 (_U_(0x1) << DEVIER_PEP_9_Pos) /**< (DEVIER) Endpoint 9 Interrupt Enable Mask */ -#define DEVIER_DMA_1_Pos 25 /**< (DEVIER) DMA Channel 1 Interrupt Enable Position */ -#define DEVIER_DMA_1 (_U_(0x1) << DEVIER_DMA_1_Pos) /**< (DEVIER) DMA Channel 1 Interrupt Enable Mask */ -#define DEVIER_DMA_2_Pos 26 /**< (DEVIER) DMA Channel 2 Interrupt Enable Position */ -#define DEVIER_DMA_2 (_U_(0x1) << DEVIER_DMA_2_Pos) /**< (DEVIER) DMA Channel 2 Interrupt Enable Mask */ -#define DEVIER_DMA_3_Pos 27 /**< (DEVIER) DMA Channel 3 Interrupt Enable Position */ -#define DEVIER_DMA_3 (_U_(0x1) << DEVIER_DMA_3_Pos) /**< (DEVIER) DMA Channel 3 Interrupt Enable Mask */ -#define DEVIER_DMA_4_Pos 28 /**< (DEVIER) DMA Channel 4 Interrupt Enable Position */ -#define DEVIER_DMA_4 (_U_(0x1) << DEVIER_DMA_4_Pos) /**< (DEVIER) DMA Channel 4 Interrupt Enable Mask */ -#define DEVIER_DMA_5_Pos 29 /**< (DEVIER) DMA Channel 5 Interrupt Enable Position */ -#define DEVIER_DMA_5 (_U_(0x1) << DEVIER_DMA_5_Pos) /**< (DEVIER) DMA Channel 5 Interrupt Enable Mask */ -#define DEVIER_DMA_6_Pos 30 /**< (DEVIER) DMA Channel 6 Interrupt Enable Position */ -#define DEVIER_DMA_6 (_U_(0x1) << DEVIER_DMA_6_Pos) /**< (DEVIER) DMA Channel 6 Interrupt Enable Mask */ -#define DEVIER_DMA_7_Pos 31 /**< (DEVIER) DMA Channel 7 Interrupt Enable Position */ -#define DEVIER_DMA_7 (_U_(0x1) << DEVIER_DMA_7_Pos) /**< (DEVIER) DMA Channel 7 Interrupt Enable Mask */ -#define DEVIER_Msk _U_(0xFE3FF07F) /**< (DEVIER) Register Mask */ - -#define DEVIER_PEP__Pos 12 /**< (DEVIER Position) Endpoint x Interrupt Enable */ -#define DEVIER_PEP_ (_U_(0x3FF) << DEVIER_PEP__Pos) /**< (DEVIER Mask) PEP_ */ -#define DEVIER_DMA__Pos 25 /**< (DEVIER Position) DMA Channel 7 Interrupt Enable */ -#define DEVIER_DMA_ (_U_(0x7F) << DEVIER_DMA__Pos) /**< (DEVIER Mask) DMA_ */ - -/* -------- DEVEPT : (USBHS Offset: 0x1c) (R/W 32) Device Endpoint Register -------- */ - -#define DEVEPT_OFFSET (0x1C) /**< (DEVEPT) Device Endpoint Register Offset */ - -#define DEVEPT_EPEN0_Pos 0 /**< (DEVEPT) Endpoint 0 Enable Position */ -#define DEVEPT_EPEN0 (_U_(0x1) << DEVEPT_EPEN0_Pos) /**< (DEVEPT) Endpoint 0 Enable Mask */ -#define DEVEPT_EPEN1_Pos 1 /**< (DEVEPT) Endpoint 1 Enable Position */ -#define DEVEPT_EPEN1 (_U_(0x1) << DEVEPT_EPEN1_Pos) /**< (DEVEPT) Endpoint 1 Enable Mask */ -#define DEVEPT_EPEN2_Pos 2 /**< (DEVEPT) Endpoint 2 Enable Position */ -#define DEVEPT_EPEN2 (_U_(0x1) << DEVEPT_EPEN2_Pos) /**< (DEVEPT) Endpoint 2 Enable Mask */ -#define DEVEPT_EPEN3_Pos 3 /**< (DEVEPT) Endpoint 3 Enable Position */ -#define DEVEPT_EPEN3 (_U_(0x1) << DEVEPT_EPEN3_Pos) /**< (DEVEPT) Endpoint 3 Enable Mask */ -#define DEVEPT_EPEN4_Pos 4 /**< (DEVEPT) Endpoint 4 Enable Position */ -#define DEVEPT_EPEN4 (_U_(0x1) << DEVEPT_EPEN4_Pos) /**< (DEVEPT) Endpoint 4 Enable Mask */ -#define DEVEPT_EPEN5_Pos 5 /**< (DEVEPT) Endpoint 5 Enable Position */ -#define DEVEPT_EPEN5 (_U_(0x1) << DEVEPT_EPEN5_Pos) /**< (DEVEPT) Endpoint 5 Enable Mask */ -#define DEVEPT_EPEN6_Pos 6 /**< (DEVEPT) Endpoint 6 Enable Position */ -#define DEVEPT_EPEN6 (_U_(0x1) << DEVEPT_EPEN6_Pos) /**< (DEVEPT) Endpoint 6 Enable Mask */ -#define DEVEPT_EPEN7_Pos 7 /**< (DEVEPT) Endpoint 7 Enable Position */ -#define DEVEPT_EPEN7 (_U_(0x1) << DEVEPT_EPEN7_Pos) /**< (DEVEPT) Endpoint 7 Enable Mask */ -#define DEVEPT_EPEN8_Pos 8 /**< (DEVEPT) Endpoint 8 Enable Position */ -#define DEVEPT_EPEN8 (_U_(0x1) << DEVEPT_EPEN8_Pos) /**< (DEVEPT) Endpoint 8 Enable Mask */ -#define DEVEPT_EPEN9_Pos 9 /**< (DEVEPT) Endpoint 9 Enable Position */ -#define DEVEPT_EPEN9 (_U_(0x1) << DEVEPT_EPEN9_Pos) /**< (DEVEPT) Endpoint 9 Enable Mask */ -#define DEVEPT_EPRST0_Pos 16 /**< (DEVEPT) Endpoint 0 Reset Position */ -#define DEVEPT_EPRST0 (_U_(0x1) << DEVEPT_EPRST0_Pos) /**< (DEVEPT) Endpoint 0 Reset Mask */ -#define DEVEPT_EPRST1_Pos 17 /**< (DEVEPT) Endpoint 1 Reset Position */ -#define DEVEPT_EPRST1 (_U_(0x1) << DEVEPT_EPRST1_Pos) /**< (DEVEPT) Endpoint 1 Reset Mask */ -#define DEVEPT_EPRST2_Pos 18 /**< (DEVEPT) Endpoint 2 Reset Position */ -#define DEVEPT_EPRST2 (_U_(0x1) << DEVEPT_EPRST2_Pos) /**< (DEVEPT) Endpoint 2 Reset Mask */ -#define DEVEPT_EPRST3_Pos 19 /**< (DEVEPT) Endpoint 3 Reset Position */ -#define DEVEPT_EPRST3 (_U_(0x1) << DEVEPT_EPRST3_Pos) /**< (DEVEPT) Endpoint 3 Reset Mask */ -#define DEVEPT_EPRST4_Pos 20 /**< (DEVEPT) Endpoint 4 Reset Position */ -#define DEVEPT_EPRST4 (_U_(0x1) << DEVEPT_EPRST4_Pos) /**< (DEVEPT) Endpoint 4 Reset Mask */ -#define DEVEPT_EPRST5_Pos 21 /**< (DEVEPT) Endpoint 5 Reset Position */ -#define DEVEPT_EPRST5 (_U_(0x1) << DEVEPT_EPRST5_Pos) /**< (DEVEPT) Endpoint 5 Reset Mask */ -#define DEVEPT_EPRST6_Pos 22 /**< (DEVEPT) Endpoint 6 Reset Position */ -#define DEVEPT_EPRST6 (_U_(0x1) << DEVEPT_EPRST6_Pos) /**< (DEVEPT) Endpoint 6 Reset Mask */ -#define DEVEPT_EPRST7_Pos 23 /**< (DEVEPT) Endpoint 7 Reset Position */ -#define DEVEPT_EPRST7 (_U_(0x1) << DEVEPT_EPRST7_Pos) /**< (DEVEPT) Endpoint 7 Reset Mask */ -#define DEVEPT_EPRST8_Pos 24 /**< (DEVEPT) Endpoint 8 Reset Position */ -#define DEVEPT_EPRST8 (_U_(0x1) << DEVEPT_EPRST8_Pos) /**< (DEVEPT) Endpoint 8 Reset Mask */ -#define DEVEPT_EPRST9_Pos 25 /**< (DEVEPT) Endpoint 9 Reset Position */ -#define DEVEPT_EPRST9 (_U_(0x1) << DEVEPT_EPRST9_Pos) /**< (DEVEPT) Endpoint 9 Reset Mask */ -#define DEVEPT_Msk _U_(0x3FF03FF) /**< (DEVEPT) Register Mask */ - -#define DEVEPT_EPEN_Pos 0 /**< (DEVEPT Position) Endpoint x Enable */ -#define DEVEPT_EPEN (_U_(0x3FF) << DEVEPT_EPEN_Pos) /**< (DEVEPT Mask) EPEN */ -#define DEVEPT_EPRST_Pos 16 /**< (DEVEPT Position) Endpoint 9 Reset */ -#define DEVEPT_EPRST (_U_(0x3FF) << DEVEPT_EPRST_Pos) /**< (DEVEPT Mask) EPRST */ - -/* -------- DEVFNUM : (USBHS Offset: 0x20) (R/ 32) Device Frame Number Register -------- */ - -#define DEVFNUM_OFFSET (0x20) /**< (DEVFNUM) Device Frame Number Register Offset */ - -#define DEVFNUM_MFNUM_Pos 0 /**< (DEVFNUM) Micro Frame Number Position */ -#define DEVFNUM_MFNUM (_U_(0x7) << DEVFNUM_MFNUM_Pos) /**< (DEVFNUM) Micro Frame Number Mask */ -#define DEVFNUM_FNUM_Pos 3 /**< (DEVFNUM) Frame Number Position */ -#define DEVFNUM_FNUM (_U_(0x7FF) << DEVFNUM_FNUM_Pos) /**< (DEVFNUM) Frame Number Mask */ -#define DEVFNUM_FNCERR_Pos 15 /**< (DEVFNUM) Frame Number CRC Error Position */ -#define DEVFNUM_FNCERR (_U_(0x1) << DEVFNUM_FNCERR_Pos) /**< (DEVFNUM) Frame Number CRC Error Mask */ -#define DEVFNUM_Msk _U_(0xBFFF) /**< (DEVFNUM) Register Mask */ - -/* -------- DEVEPTCFG : (USBHS Offset: 0x100) (R/W 32) Device Endpoint Configuration Register -------- */ - -#define DEVEPTCFG_OFFSET (0x100) /**< (DEVEPTCFG) Device Endpoint Configuration Register Offset */ - -#define DEVEPTCFG_ALLOC_Pos 1 /**< (DEVEPTCFG) Endpoint Memory Allocate Position */ -#define DEVEPTCFG_ALLOC (_U_(0x1) << DEVEPTCFG_ALLOC_Pos) /**< (DEVEPTCFG) Endpoint Memory Allocate Mask */ -#define DEVEPTCFG_EPBK_Pos 2 /**< (DEVEPTCFG) Endpoint Banks Position */ -#define DEVEPTCFG_EPBK (_U_(0x3) << DEVEPTCFG_EPBK_Pos) /**< (DEVEPTCFG) Endpoint Banks Mask */ -#define DEVEPTCFG_EPBK_1_BANK_Val _U_(0x0) /**< (DEVEPTCFG) Single-bank endpoint */ -#define DEVEPTCFG_EPBK_2_BANK_Val _U_(0x1) /**< (DEVEPTCFG) Double-bank endpoint */ -#define DEVEPTCFG_EPBK_3_BANK_Val _U_(0x2) /**< (DEVEPTCFG) Triple-bank endpoint */ -#define DEVEPTCFG_EPBK_1_BANK (DEVEPTCFG_EPBK_1_BANK_Val << DEVEPTCFG_EPBK_Pos) /**< (DEVEPTCFG) Single-bank endpoint Position */ -#define DEVEPTCFG_EPBK_2_BANK (DEVEPTCFG_EPBK_2_BANK_Val << DEVEPTCFG_EPBK_Pos) /**< (DEVEPTCFG) Double-bank endpoint Position */ -#define DEVEPTCFG_EPBK_3_BANK (DEVEPTCFG_EPBK_3_BANK_Val << DEVEPTCFG_EPBK_Pos) /**< (DEVEPTCFG) Triple-bank endpoint Position */ -#define DEVEPTCFG_EPSIZE_Pos 4 /**< (DEVEPTCFG) Endpoint Size Position */ -#define DEVEPTCFG_EPSIZE (_U_(0x7) << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) Endpoint Size Mask */ -#define DEVEPTCFG_EPSIZE_8_BYTE_Val _U_(0x0) /**< (DEVEPTCFG) 8 bytes */ -#define DEVEPTCFG_EPSIZE_16_BYTE_Val _U_(0x1) /**< (DEVEPTCFG) 16 bytes */ -#define DEVEPTCFG_EPSIZE_32_BYTE_Val _U_(0x2) /**< (DEVEPTCFG) 32 bytes */ -#define DEVEPTCFG_EPSIZE_64_BYTE_Val _U_(0x3) /**< (DEVEPTCFG) 64 bytes */ -#define DEVEPTCFG_EPSIZE_128_BYTE_Val _U_(0x4) /**< (DEVEPTCFG) 128 bytes */ -#define DEVEPTCFG_EPSIZE_256_BYTE_Val _U_(0x5) /**< (DEVEPTCFG) 256 bytes */ -#define DEVEPTCFG_EPSIZE_512_BYTE_Val _U_(0x6) /**< (DEVEPTCFG) 512 bytes */ -#define DEVEPTCFG_EPSIZE_1024_BYTE_Val _U_(0x7) /**< (DEVEPTCFG) 1024 bytes */ -#define DEVEPTCFG_EPSIZE_8_BYTE (DEVEPTCFG_EPSIZE_8_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 8 bytes Position */ -#define DEVEPTCFG_EPSIZE_16_BYTE (DEVEPTCFG_EPSIZE_16_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 16 bytes Position */ -#define DEVEPTCFG_EPSIZE_32_BYTE (DEVEPTCFG_EPSIZE_32_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 32 bytes Position */ -#define DEVEPTCFG_EPSIZE_64_BYTE (DEVEPTCFG_EPSIZE_64_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 64 bytes Position */ -#define DEVEPTCFG_EPSIZE_128_BYTE (DEVEPTCFG_EPSIZE_128_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 128 bytes Position */ -#define DEVEPTCFG_EPSIZE_256_BYTE (DEVEPTCFG_EPSIZE_256_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 256 bytes Position */ -#define DEVEPTCFG_EPSIZE_512_BYTE (DEVEPTCFG_EPSIZE_512_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 512 bytes Position */ -#define DEVEPTCFG_EPSIZE_1024_BYTE (DEVEPTCFG_EPSIZE_1024_BYTE_Val << DEVEPTCFG_EPSIZE_Pos) /**< (DEVEPTCFG) 1024 bytes Position */ -#define DEVEPTCFG_EPDIR_Pos 8 /**< (DEVEPTCFG) Endpoint Direction Position */ -#define DEVEPTCFG_EPDIR (_U_(0x1) << DEVEPTCFG_EPDIR_Pos) /**< (DEVEPTCFG) Endpoint Direction Mask */ -#define DEVEPTCFG_EPDIR_OUT_Val _U_(0x0) /**< (DEVEPTCFG) The endpoint direction is OUT. */ -#define DEVEPTCFG_EPDIR_IN_Val _U_(0x1) /**< (DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). */ -#define DEVEPTCFG_EPDIR_OUT (DEVEPTCFG_EPDIR_OUT_Val << DEVEPTCFG_EPDIR_Pos) /**< (DEVEPTCFG) The endpoint direction is OUT. Position */ -#define DEVEPTCFG_EPDIR_IN (DEVEPTCFG_EPDIR_IN_Val << DEVEPTCFG_EPDIR_Pos) /**< (DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). Position */ -#define DEVEPTCFG_AUTOSW_Pos 9 /**< (DEVEPTCFG) Automatic Switch Position */ -#define DEVEPTCFG_AUTOSW (_U_(0x1) << DEVEPTCFG_AUTOSW_Pos) /**< (DEVEPTCFG) Automatic Switch Mask */ -#define DEVEPTCFG_EPTYPE_Pos 11 /**< (DEVEPTCFG) Endpoint Type Position */ -#define DEVEPTCFG_EPTYPE (_U_(0x3) << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Endpoint Type Mask */ -#define DEVEPTCFG_EPTYPE_CTRL_Val _U_(0x0) /**< (DEVEPTCFG) Control */ -#define DEVEPTCFG_EPTYPE_ISO_Val _U_(0x1) /**< (DEVEPTCFG) Isochronous */ -#define DEVEPTCFG_EPTYPE_BLK_Val _U_(0x2) /**< (DEVEPTCFG) Bulk */ -#define DEVEPTCFG_EPTYPE_INTRPT_Val _U_(0x3) /**< (DEVEPTCFG) Interrupt */ -#define DEVEPTCFG_EPTYPE_CTRL (DEVEPTCFG_EPTYPE_CTRL_Val << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Control Position */ -#define DEVEPTCFG_EPTYPE_ISO (DEVEPTCFG_EPTYPE_ISO_Val << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Isochronous Position */ -#define DEVEPTCFG_EPTYPE_BLK (DEVEPTCFG_EPTYPE_BLK_Val << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Bulk Position */ -#define DEVEPTCFG_EPTYPE_INTRPT (DEVEPTCFG_EPTYPE_INTRPT_Val << DEVEPTCFG_EPTYPE_Pos) /**< (DEVEPTCFG) Interrupt Position */ -#define DEVEPTCFG_NBTRANS_Pos 13 /**< (DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Position */ -#define DEVEPTCFG_NBTRANS (_U_(0x3) << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Mask */ -#define DEVEPTCFG_NBTRANS_0_TRANS_Val _U_(0x0) /**< (DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ -#define DEVEPTCFG_NBTRANS_1_TRANS_Val _U_(0x1) /**< (DEVEPTCFG) Default value: one transaction per microframe. */ -#define DEVEPTCFG_NBTRANS_2_TRANS_Val _U_(0x2) /**< (DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. */ -#define DEVEPTCFG_NBTRANS_3_TRANS_Val _U_(0x3) /**< (DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. */ -#define DEVEPTCFG_NBTRANS_0_TRANS (DEVEPTCFG_NBTRANS_0_TRANS_Val << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. Position */ -#define DEVEPTCFG_NBTRANS_1_TRANS (DEVEPTCFG_NBTRANS_1_TRANS_Val << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Default value: one transaction per microframe. Position */ -#define DEVEPTCFG_NBTRANS_2_TRANS (DEVEPTCFG_NBTRANS_2_TRANS_Val << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. Position */ -#define DEVEPTCFG_NBTRANS_3_TRANS (DEVEPTCFG_NBTRANS_3_TRANS_Val << DEVEPTCFG_NBTRANS_Pos) /**< (DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. Position */ -#define DEVEPTCFG_Msk _U_(0x7B7E) /**< (DEVEPTCFG) Register Mask */ - -/* -------- DEVEPTISR : (USBHS Offset: 0x130) (R/ 32) Device Endpoint Interrupt Status Register -------- */ - -#define DEVEPTISR_OFFSET (0x130) /**< (DEVEPTISR) Device Endpoint Interrupt Status Register Offset */ - -#define DEVEPTISR_TXINI_Pos 0 /**< (DEVEPTISR) Transmitted IN Data Interrupt Position */ -#define DEVEPTISR_TXINI (_U_(0x1) << DEVEPTISR_TXINI_Pos) /**< (DEVEPTISR) Transmitted IN Data Interrupt Mask */ -#define DEVEPTISR_RXOUTI_Pos 1 /**< (DEVEPTISR) Received OUT Data Interrupt Position */ -#define DEVEPTISR_RXOUTI (_U_(0x1) << DEVEPTISR_RXOUTI_Pos) /**< (DEVEPTISR) Received OUT Data Interrupt Mask */ -#define DEVEPTISR_OVERFI_Pos 5 /**< (DEVEPTISR) Overflow Interrupt Position */ -#define DEVEPTISR_OVERFI (_U_(0x1) << DEVEPTISR_OVERFI_Pos) /**< (DEVEPTISR) Overflow Interrupt Mask */ -#define DEVEPTISR_SHORTPACKET_Pos 7 /**< (DEVEPTISR) Short Packet Interrupt Position */ -#define DEVEPTISR_SHORTPACKET (_U_(0x1) << DEVEPTISR_SHORTPACKET_Pos) /**< (DEVEPTISR) Short Packet Interrupt Mask */ -#define DEVEPTISR_DTSEQ_Pos 8 /**< (DEVEPTISR) Data Toggle Sequence Position */ -#define DEVEPTISR_DTSEQ (_U_(0x3) << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Data Toggle Sequence Mask */ -#define DEVEPTISR_DTSEQ_DATA0_Val _U_(0x0) /**< (DEVEPTISR) Data0 toggle sequence */ -#define DEVEPTISR_DTSEQ_DATA1_Val _U_(0x1) /**< (DEVEPTISR) Data1 toggle sequence */ -#define DEVEPTISR_DTSEQ_DATA2_Val _U_(0x2) /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ -#define DEVEPTISR_DTSEQ_MDATA_Val _U_(0x3) /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ -#define DEVEPTISR_DTSEQ_DATA0 (DEVEPTISR_DTSEQ_DATA0_Val << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Data0 toggle sequence Position */ -#define DEVEPTISR_DTSEQ_DATA1 (DEVEPTISR_DTSEQ_DATA1_Val << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Data1 toggle sequence Position */ -#define DEVEPTISR_DTSEQ_DATA2 (DEVEPTISR_DTSEQ_DATA2_Val << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ -#define DEVEPTISR_DTSEQ_MDATA (DEVEPTISR_DTSEQ_MDATA_Val << DEVEPTISR_DTSEQ_Pos) /**< (DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ -#define DEVEPTISR_NBUSYBK_Pos 12 /**< (DEVEPTISR) Number of Busy Banks Position */ -#define DEVEPTISR_NBUSYBK (_U_(0x3) << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) Number of Busy Banks Mask */ -#define DEVEPTISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (DEVEPTISR) 0 busy bank (all banks free) */ -#define DEVEPTISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (DEVEPTISR) 1 busy bank */ -#define DEVEPTISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (DEVEPTISR) 2 busy banks */ -#define DEVEPTISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (DEVEPTISR) 3 busy banks */ -#define DEVEPTISR_NBUSYBK_0_BUSY (DEVEPTISR_NBUSYBK_0_BUSY_Val << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) 0 busy bank (all banks free) Position */ -#define DEVEPTISR_NBUSYBK_1_BUSY (DEVEPTISR_NBUSYBK_1_BUSY_Val << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) 1 busy bank Position */ -#define DEVEPTISR_NBUSYBK_2_BUSY (DEVEPTISR_NBUSYBK_2_BUSY_Val << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) 2 busy banks Position */ -#define DEVEPTISR_NBUSYBK_3_BUSY (DEVEPTISR_NBUSYBK_3_BUSY_Val << DEVEPTISR_NBUSYBK_Pos) /**< (DEVEPTISR) 3 busy banks Position */ -#define DEVEPTISR_CURRBK_Pos 14 /**< (DEVEPTISR) Current Bank Position */ -#define DEVEPTISR_CURRBK (_U_(0x3) << DEVEPTISR_CURRBK_Pos) /**< (DEVEPTISR) Current Bank Mask */ -#define DEVEPTISR_CURRBK_BANK0_Val _U_(0x0) /**< (DEVEPTISR) Current bank is bank0 */ -#define DEVEPTISR_CURRBK_BANK1_Val _U_(0x1) /**< (DEVEPTISR) Current bank is bank1 */ -#define DEVEPTISR_CURRBK_BANK2_Val _U_(0x2) /**< (DEVEPTISR) Current bank is bank2 */ -#define DEVEPTISR_CURRBK_BANK0 (DEVEPTISR_CURRBK_BANK0_Val << DEVEPTISR_CURRBK_Pos) /**< (DEVEPTISR) Current bank is bank0 Position */ -#define DEVEPTISR_CURRBK_BANK1 (DEVEPTISR_CURRBK_BANK1_Val << DEVEPTISR_CURRBK_Pos) /**< (DEVEPTISR) Current bank is bank1 Position */ -#define DEVEPTISR_CURRBK_BANK2 (DEVEPTISR_CURRBK_BANK2_Val << DEVEPTISR_CURRBK_Pos) /**< (DEVEPTISR) Current bank is bank2 Position */ -#define DEVEPTISR_RWALL_Pos 16 /**< (DEVEPTISR) Read/Write Allowed Position */ -#define DEVEPTISR_RWALL (_U_(0x1) << DEVEPTISR_RWALL_Pos) /**< (DEVEPTISR) Read/Write Allowed Mask */ -#define DEVEPTISR_CFGOK_Pos 18 /**< (DEVEPTISR) Configuration OK Status Position */ -#define DEVEPTISR_CFGOK (_U_(0x1) << DEVEPTISR_CFGOK_Pos) /**< (DEVEPTISR) Configuration OK Status Mask */ -#define DEVEPTISR_BYCT_Pos 20 /**< (DEVEPTISR) Byte Count Position */ -#define DEVEPTISR_BYCT (_U_(0x7FF) << DEVEPTISR_BYCT_Pos) /**< (DEVEPTISR) Byte Count Mask */ -#define DEVEPTISR_Msk _U_(0x7FF5F3A3) /**< (DEVEPTISR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTISR_CTRL_RXSTPI_Pos 2 /**< (DEVEPTISR) Received SETUP Interrupt Position */ -#define DEVEPTISR_CTRL_RXSTPI (_U_(0x1) << DEVEPTISR_CTRL_RXSTPI_Pos) /**< (DEVEPTISR) Received SETUP Interrupt Mask */ -#define DEVEPTISR_CTRL_NAKOUTI_Pos 3 /**< (DEVEPTISR) NAKed OUT Interrupt Position */ -#define DEVEPTISR_CTRL_NAKOUTI (_U_(0x1) << DEVEPTISR_CTRL_NAKOUTI_Pos) /**< (DEVEPTISR) NAKed OUT Interrupt Mask */ -#define DEVEPTISR_CTRL_NAKINI_Pos 4 /**< (DEVEPTISR) NAKed IN Interrupt Position */ -#define DEVEPTISR_CTRL_NAKINI (_U_(0x1) << DEVEPTISR_CTRL_NAKINI_Pos) /**< (DEVEPTISR) NAKed IN Interrupt Mask */ -#define DEVEPTISR_CTRL_STALLEDI_Pos 6 /**< (DEVEPTISR) STALLed Interrupt Position */ -#define DEVEPTISR_CTRL_STALLEDI (_U_(0x1) << DEVEPTISR_CTRL_STALLEDI_Pos) /**< (DEVEPTISR) STALLed Interrupt Mask */ -#define DEVEPTISR_CTRL_CTRLDIR_Pos 17 /**< (DEVEPTISR) Control Direction Position */ -#define DEVEPTISR_CTRL_CTRLDIR (_U_(0x1) << DEVEPTISR_CTRL_CTRLDIR_Pos) /**< (DEVEPTISR) Control Direction Mask */ -#define DEVEPTISR_CTRL_Msk _U_(0x2005C) /**< (DEVEPTISR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTISR_ISO_UNDERFI_Pos 2 /**< (DEVEPTISR) Underflow Interrupt Position */ -#define DEVEPTISR_ISO_UNDERFI (_U_(0x1) << DEVEPTISR_ISO_UNDERFI_Pos) /**< (DEVEPTISR) Underflow Interrupt Mask */ -#define DEVEPTISR_ISO_HBISOINERRI_Pos 3 /**< (DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ -#define DEVEPTISR_ISO_HBISOINERRI (_U_(0x1) << DEVEPTISR_ISO_HBISOINERRI_Pos) /**< (DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ -#define DEVEPTISR_ISO_HBISOFLUSHI_Pos 4 /**< (DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Position */ -#define DEVEPTISR_ISO_HBISOFLUSHI (_U_(0x1) << DEVEPTISR_ISO_HBISOFLUSHI_Pos) /**< (DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Mask */ -#define DEVEPTISR_ISO_CRCERRI_Pos 6 /**< (DEVEPTISR) CRC Error Interrupt Position */ -#define DEVEPTISR_ISO_CRCERRI (_U_(0x1) << DEVEPTISR_ISO_CRCERRI_Pos) /**< (DEVEPTISR) CRC Error Interrupt Mask */ -#define DEVEPTISR_ISO_ERRORTRANS_Pos 10 /**< (DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Position */ -#define DEVEPTISR_ISO_ERRORTRANS (_U_(0x1) << DEVEPTISR_ISO_ERRORTRANS_Pos) /**< (DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Mask */ -#define DEVEPTISR_ISO_Msk _U_(0x45C) /**< (DEVEPTISR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTISR_BLK_RXSTPI_Pos 2 /**< (DEVEPTISR) Received SETUP Interrupt Position */ -#define DEVEPTISR_BLK_RXSTPI (_U_(0x1) << DEVEPTISR_BLK_RXSTPI_Pos) /**< (DEVEPTISR) Received SETUP Interrupt Mask */ -#define DEVEPTISR_BLK_NAKOUTI_Pos 3 /**< (DEVEPTISR) NAKed OUT Interrupt Position */ -#define DEVEPTISR_BLK_NAKOUTI (_U_(0x1) << DEVEPTISR_BLK_NAKOUTI_Pos) /**< (DEVEPTISR) NAKed OUT Interrupt Mask */ -#define DEVEPTISR_BLK_NAKINI_Pos 4 /**< (DEVEPTISR) NAKed IN Interrupt Position */ -#define DEVEPTISR_BLK_NAKINI (_U_(0x1) << DEVEPTISR_BLK_NAKINI_Pos) /**< (DEVEPTISR) NAKed IN Interrupt Mask */ -#define DEVEPTISR_BLK_STALLEDI_Pos 6 /**< (DEVEPTISR) STALLed Interrupt Position */ -#define DEVEPTISR_BLK_STALLEDI (_U_(0x1) << DEVEPTISR_BLK_STALLEDI_Pos) /**< (DEVEPTISR) STALLed Interrupt Mask */ -#define DEVEPTISR_BLK_CTRLDIR_Pos 17 /**< (DEVEPTISR) Control Direction Position */ -#define DEVEPTISR_BLK_CTRLDIR (_U_(0x1) << DEVEPTISR_BLK_CTRLDIR_Pos) /**< (DEVEPTISR) Control Direction Mask */ -#define DEVEPTISR_BLK_Msk _U_(0x2005C) /**< (DEVEPTISR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTISR_INTRPT_RXSTPI_Pos 2 /**< (DEVEPTISR) Received SETUP Interrupt Position */ -#define DEVEPTISR_INTRPT_RXSTPI (_U_(0x1) << DEVEPTISR_INTRPT_RXSTPI_Pos) /**< (DEVEPTISR) Received SETUP Interrupt Mask */ -#define DEVEPTISR_INTRPT_NAKOUTI_Pos 3 /**< (DEVEPTISR) NAKed OUT Interrupt Position */ -#define DEVEPTISR_INTRPT_NAKOUTI (_U_(0x1) << DEVEPTISR_INTRPT_NAKOUTI_Pos) /**< (DEVEPTISR) NAKed OUT Interrupt Mask */ -#define DEVEPTISR_INTRPT_NAKINI_Pos 4 /**< (DEVEPTISR) NAKed IN Interrupt Position */ -#define DEVEPTISR_INTRPT_NAKINI (_U_(0x1) << DEVEPTISR_INTRPT_NAKINI_Pos) /**< (DEVEPTISR) NAKed IN Interrupt Mask */ -#define DEVEPTISR_INTRPT_STALLEDI_Pos 6 /**< (DEVEPTISR) STALLed Interrupt Position */ -#define DEVEPTISR_INTRPT_STALLEDI (_U_(0x1) << DEVEPTISR_INTRPT_STALLEDI_Pos) /**< (DEVEPTISR) STALLed Interrupt Mask */ -#define DEVEPTISR_INTRPT_CTRLDIR_Pos 17 /**< (DEVEPTISR) Control Direction Position */ -#define DEVEPTISR_INTRPT_CTRLDIR (_U_(0x1) << DEVEPTISR_INTRPT_CTRLDIR_Pos) /**< (DEVEPTISR) Control Direction Mask */ -#define DEVEPTISR_INTRPT_Msk _U_(0x2005C) /**< (DEVEPTISR_INTRPT) Register Mask */ - -/* -------- DEVEPTICR : (USBHS Offset: 0x160) (/W 32) Device Endpoint Interrupt Clear Register -------- */ - -#define DEVEPTICR_OFFSET (0x160) /**< (DEVEPTICR) Device Endpoint Interrupt Clear Register Offset */ - -#define DEVEPTICR_TXINIC_Pos 0 /**< (DEVEPTICR) Transmitted IN Data Interrupt Clear Position */ -#define DEVEPTICR_TXINIC (_U_(0x1) << DEVEPTICR_TXINIC_Pos) /**< (DEVEPTICR) Transmitted IN Data Interrupt Clear Mask */ -#define DEVEPTICR_RXOUTIC_Pos 1 /**< (DEVEPTICR) Received OUT Data Interrupt Clear Position */ -#define DEVEPTICR_RXOUTIC (_U_(0x1) << DEVEPTICR_RXOUTIC_Pos) /**< (DEVEPTICR) Received OUT Data Interrupt Clear Mask */ -#define DEVEPTICR_OVERFIC_Pos 5 /**< (DEVEPTICR) Overflow Interrupt Clear Position */ -#define DEVEPTICR_OVERFIC (_U_(0x1) << DEVEPTICR_OVERFIC_Pos) /**< (DEVEPTICR) Overflow Interrupt Clear Mask */ -#define DEVEPTICR_SHORTPACKETC_Pos 7 /**< (DEVEPTICR) Short Packet Interrupt Clear Position */ -#define DEVEPTICR_SHORTPACKETC (_U_(0x1) << DEVEPTICR_SHORTPACKETC_Pos) /**< (DEVEPTICR) Short Packet Interrupt Clear Mask */ -#define DEVEPTICR_Msk _U_(0xA3) /**< (DEVEPTICR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTICR_CTRL_RXSTPIC_Pos 2 /**< (DEVEPTICR) Received SETUP Interrupt Clear Position */ -#define DEVEPTICR_CTRL_RXSTPIC (_U_(0x1) << DEVEPTICR_CTRL_RXSTPIC_Pos) /**< (DEVEPTICR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTICR_CTRL_NAKOUTIC_Pos 3 /**< (DEVEPTICR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTICR_CTRL_NAKOUTIC (_U_(0x1) << DEVEPTICR_CTRL_NAKOUTIC_Pos) /**< (DEVEPTICR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTICR_CTRL_NAKINIC_Pos 4 /**< (DEVEPTICR) NAKed IN Interrupt Clear Position */ -#define DEVEPTICR_CTRL_NAKINIC (_U_(0x1) << DEVEPTICR_CTRL_NAKINIC_Pos) /**< (DEVEPTICR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTICR_CTRL_STALLEDIC_Pos 6 /**< (DEVEPTICR) STALLed Interrupt Clear Position */ -#define DEVEPTICR_CTRL_STALLEDIC (_U_(0x1) << DEVEPTICR_CTRL_STALLEDIC_Pos) /**< (DEVEPTICR) STALLed Interrupt Clear Mask */ -#define DEVEPTICR_CTRL_Msk _U_(0x5C) /**< (DEVEPTICR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTICR_ISO_UNDERFIC_Pos 2 /**< (DEVEPTICR) Underflow Interrupt Clear Position */ -#define DEVEPTICR_ISO_UNDERFIC (_U_(0x1) << DEVEPTICR_ISO_UNDERFIC_Pos) /**< (DEVEPTICR) Underflow Interrupt Clear Mask */ -#define DEVEPTICR_ISO_HBISOINERRIC_Pos 3 /**< (DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ -#define DEVEPTICR_ISO_HBISOINERRIC (_U_(0x1) << DEVEPTICR_ISO_HBISOINERRIC_Pos) /**< (DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ -#define DEVEPTICR_ISO_HBISOFLUSHIC_Pos 4 /**< (DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ -#define DEVEPTICR_ISO_HBISOFLUSHIC (_U_(0x1) << DEVEPTICR_ISO_HBISOFLUSHIC_Pos) /**< (DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ -#define DEVEPTICR_ISO_CRCERRIC_Pos 6 /**< (DEVEPTICR) CRC Error Interrupt Clear Position */ -#define DEVEPTICR_ISO_CRCERRIC (_U_(0x1) << DEVEPTICR_ISO_CRCERRIC_Pos) /**< (DEVEPTICR) CRC Error Interrupt Clear Mask */ -#define DEVEPTICR_ISO_Msk _U_(0x5C) /**< (DEVEPTICR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTICR_BLK_RXSTPIC_Pos 2 /**< (DEVEPTICR) Received SETUP Interrupt Clear Position */ -#define DEVEPTICR_BLK_RXSTPIC (_U_(0x1) << DEVEPTICR_BLK_RXSTPIC_Pos) /**< (DEVEPTICR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTICR_BLK_NAKOUTIC_Pos 3 /**< (DEVEPTICR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTICR_BLK_NAKOUTIC (_U_(0x1) << DEVEPTICR_BLK_NAKOUTIC_Pos) /**< (DEVEPTICR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTICR_BLK_NAKINIC_Pos 4 /**< (DEVEPTICR) NAKed IN Interrupt Clear Position */ -#define DEVEPTICR_BLK_NAKINIC (_U_(0x1) << DEVEPTICR_BLK_NAKINIC_Pos) /**< (DEVEPTICR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTICR_BLK_STALLEDIC_Pos 6 /**< (DEVEPTICR) STALLed Interrupt Clear Position */ -#define DEVEPTICR_BLK_STALLEDIC (_U_(0x1) << DEVEPTICR_BLK_STALLEDIC_Pos) /**< (DEVEPTICR) STALLed Interrupt Clear Mask */ -#define DEVEPTICR_BLK_Msk _U_(0x5C) /**< (DEVEPTICR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTICR_INTRPT_RXSTPIC_Pos 2 /**< (DEVEPTICR) Received SETUP Interrupt Clear Position */ -#define DEVEPTICR_INTRPT_RXSTPIC (_U_(0x1) << DEVEPTICR_INTRPT_RXSTPIC_Pos) /**< (DEVEPTICR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTICR_INTRPT_NAKOUTIC_Pos 3 /**< (DEVEPTICR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTICR_INTRPT_NAKOUTIC (_U_(0x1) << DEVEPTICR_INTRPT_NAKOUTIC_Pos) /**< (DEVEPTICR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTICR_INTRPT_NAKINIC_Pos 4 /**< (DEVEPTICR) NAKed IN Interrupt Clear Position */ -#define DEVEPTICR_INTRPT_NAKINIC (_U_(0x1) << DEVEPTICR_INTRPT_NAKINIC_Pos) /**< (DEVEPTICR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTICR_INTRPT_STALLEDIC_Pos 6 /**< (DEVEPTICR) STALLed Interrupt Clear Position */ -#define DEVEPTICR_INTRPT_STALLEDIC (_U_(0x1) << DEVEPTICR_INTRPT_STALLEDIC_Pos) /**< (DEVEPTICR) STALLed Interrupt Clear Mask */ -#define DEVEPTICR_INTRPT_Msk _U_(0x5C) /**< (DEVEPTICR_INTRPT) Register Mask */ - -/* -------- DEVEPTIFR : (USBHS Offset: 0x190) (/W 32) Device Endpoint Interrupt Set Register -------- */ - -#define DEVEPTIFR_OFFSET (0x190) /**< (DEVEPTIFR) Device Endpoint Interrupt Set Register Offset */ - -#define DEVEPTIFR_TXINIS_Pos 0 /**< (DEVEPTIFR) Transmitted IN Data Interrupt Set Position */ -#define DEVEPTIFR_TXINIS (_U_(0x1) << DEVEPTIFR_TXINIS_Pos) /**< (DEVEPTIFR) Transmitted IN Data Interrupt Set Mask */ -#define DEVEPTIFR_RXOUTIS_Pos 1 /**< (DEVEPTIFR) Received OUT Data Interrupt Set Position */ -#define DEVEPTIFR_RXOUTIS (_U_(0x1) << DEVEPTIFR_RXOUTIS_Pos) /**< (DEVEPTIFR) Received OUT Data Interrupt Set Mask */ -#define DEVEPTIFR_OVERFIS_Pos 5 /**< (DEVEPTIFR) Overflow Interrupt Set Position */ -#define DEVEPTIFR_OVERFIS (_U_(0x1) << DEVEPTIFR_OVERFIS_Pos) /**< (DEVEPTIFR) Overflow Interrupt Set Mask */ -#define DEVEPTIFR_SHORTPACKETS_Pos 7 /**< (DEVEPTIFR) Short Packet Interrupt Set Position */ -#define DEVEPTIFR_SHORTPACKETS (_U_(0x1) << DEVEPTIFR_SHORTPACKETS_Pos) /**< (DEVEPTIFR) Short Packet Interrupt Set Mask */ -#define DEVEPTIFR_NBUSYBKS_Pos 12 /**< (DEVEPTIFR) Number of Busy Banks Interrupt Set Position */ -#define DEVEPTIFR_NBUSYBKS (_U_(0x1) << DEVEPTIFR_NBUSYBKS_Pos) /**< (DEVEPTIFR) Number of Busy Banks Interrupt Set Mask */ -#define DEVEPTIFR_Msk _U_(0x10A3) /**< (DEVEPTIFR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTIFR_CTRL_RXSTPIS_Pos 2 /**< (DEVEPTIFR) Received SETUP Interrupt Set Position */ -#define DEVEPTIFR_CTRL_RXSTPIS (_U_(0x1) << DEVEPTIFR_CTRL_RXSTPIS_Pos) /**< (DEVEPTIFR) Received SETUP Interrupt Set Mask */ -#define DEVEPTIFR_CTRL_NAKOUTIS_Pos 3 /**< (DEVEPTIFR) NAKed OUT Interrupt Set Position */ -#define DEVEPTIFR_CTRL_NAKOUTIS (_U_(0x1) << DEVEPTIFR_CTRL_NAKOUTIS_Pos) /**< (DEVEPTIFR) NAKed OUT Interrupt Set Mask */ -#define DEVEPTIFR_CTRL_NAKINIS_Pos 4 /**< (DEVEPTIFR) NAKed IN Interrupt Set Position */ -#define DEVEPTIFR_CTRL_NAKINIS (_U_(0x1) << DEVEPTIFR_CTRL_NAKINIS_Pos) /**< (DEVEPTIFR) NAKed IN Interrupt Set Mask */ -#define DEVEPTIFR_CTRL_STALLEDIS_Pos 6 /**< (DEVEPTIFR) STALLed Interrupt Set Position */ -#define DEVEPTIFR_CTRL_STALLEDIS (_U_(0x1) << DEVEPTIFR_CTRL_STALLEDIS_Pos) /**< (DEVEPTIFR) STALLed Interrupt Set Mask */ -#define DEVEPTIFR_CTRL_Msk _U_(0x5C) /**< (DEVEPTIFR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTIFR_ISO_UNDERFIS_Pos 2 /**< (DEVEPTIFR) Underflow Interrupt Set Position */ -#define DEVEPTIFR_ISO_UNDERFIS (_U_(0x1) << DEVEPTIFR_ISO_UNDERFIS_Pos) /**< (DEVEPTIFR) Underflow Interrupt Set Mask */ -#define DEVEPTIFR_ISO_HBISOINERRIS_Pos 3 /**< (DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Position */ -#define DEVEPTIFR_ISO_HBISOINERRIS (_U_(0x1) << DEVEPTIFR_ISO_HBISOINERRIS_Pos) /**< (DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Mask */ -#define DEVEPTIFR_ISO_HBISOFLUSHIS_Pos 4 /**< (DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Position */ -#define DEVEPTIFR_ISO_HBISOFLUSHIS (_U_(0x1) << DEVEPTIFR_ISO_HBISOFLUSHIS_Pos) /**< (DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Mask */ -#define DEVEPTIFR_ISO_CRCERRIS_Pos 6 /**< (DEVEPTIFR) CRC Error Interrupt Set Position */ -#define DEVEPTIFR_ISO_CRCERRIS (_U_(0x1) << DEVEPTIFR_ISO_CRCERRIS_Pos) /**< (DEVEPTIFR) CRC Error Interrupt Set Mask */ -#define DEVEPTIFR_ISO_Msk _U_(0x5C) /**< (DEVEPTIFR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTIFR_BLK_RXSTPIS_Pos 2 /**< (DEVEPTIFR) Received SETUP Interrupt Set Position */ -#define DEVEPTIFR_BLK_RXSTPIS (_U_(0x1) << DEVEPTIFR_BLK_RXSTPIS_Pos) /**< (DEVEPTIFR) Received SETUP Interrupt Set Mask */ -#define DEVEPTIFR_BLK_NAKOUTIS_Pos 3 /**< (DEVEPTIFR) NAKed OUT Interrupt Set Position */ -#define DEVEPTIFR_BLK_NAKOUTIS (_U_(0x1) << DEVEPTIFR_BLK_NAKOUTIS_Pos) /**< (DEVEPTIFR) NAKed OUT Interrupt Set Mask */ -#define DEVEPTIFR_BLK_NAKINIS_Pos 4 /**< (DEVEPTIFR) NAKed IN Interrupt Set Position */ -#define DEVEPTIFR_BLK_NAKINIS (_U_(0x1) << DEVEPTIFR_BLK_NAKINIS_Pos) /**< (DEVEPTIFR) NAKed IN Interrupt Set Mask */ -#define DEVEPTIFR_BLK_STALLEDIS_Pos 6 /**< (DEVEPTIFR) STALLed Interrupt Set Position */ -#define DEVEPTIFR_BLK_STALLEDIS (_U_(0x1) << DEVEPTIFR_BLK_STALLEDIS_Pos) /**< (DEVEPTIFR) STALLed Interrupt Set Mask */ -#define DEVEPTIFR_BLK_Msk _U_(0x5C) /**< (DEVEPTIFR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTIFR_INTRPT_RXSTPIS_Pos 2 /**< (DEVEPTIFR) Received SETUP Interrupt Set Position */ -#define DEVEPTIFR_INTRPT_RXSTPIS (_U_(0x1) << DEVEPTIFR_INTRPT_RXSTPIS_Pos) /**< (DEVEPTIFR) Received SETUP Interrupt Set Mask */ -#define DEVEPTIFR_INTRPT_NAKOUTIS_Pos 3 /**< (DEVEPTIFR) NAKed OUT Interrupt Set Position */ -#define DEVEPTIFR_INTRPT_NAKOUTIS (_U_(0x1) << DEVEPTIFR_INTRPT_NAKOUTIS_Pos) /**< (DEVEPTIFR) NAKed OUT Interrupt Set Mask */ -#define DEVEPTIFR_INTRPT_NAKINIS_Pos 4 /**< (DEVEPTIFR) NAKed IN Interrupt Set Position */ -#define DEVEPTIFR_INTRPT_NAKINIS (_U_(0x1) << DEVEPTIFR_INTRPT_NAKINIS_Pos) /**< (DEVEPTIFR) NAKed IN Interrupt Set Mask */ -#define DEVEPTIFR_INTRPT_STALLEDIS_Pos 6 /**< (DEVEPTIFR) STALLed Interrupt Set Position */ -#define DEVEPTIFR_INTRPT_STALLEDIS (_U_(0x1) << DEVEPTIFR_INTRPT_STALLEDIS_Pos) /**< (DEVEPTIFR) STALLed Interrupt Set Mask */ -#define DEVEPTIFR_INTRPT_Msk _U_(0x5C) /**< (DEVEPTIFR_INTRPT) Register Mask */ - -/* -------- DEVEPTIMR : (USBHS Offset: 0x1c0) (R/ 32) Device Endpoint Interrupt Mask Register -------- */ - -#define DEVEPTIMR_OFFSET (0x1C0) /**< (DEVEPTIMR) Device Endpoint Interrupt Mask Register Offset */ - -#define DEVEPTIMR_TXINE_Pos 0 /**< (DEVEPTIMR) Transmitted IN Data Interrupt Position */ -#define DEVEPTIMR_TXINE (_U_(0x1) << DEVEPTIMR_TXINE_Pos) /**< (DEVEPTIMR) Transmitted IN Data Interrupt Mask */ -#define DEVEPTIMR_RXOUTE_Pos 1 /**< (DEVEPTIMR) Received OUT Data Interrupt Position */ -#define DEVEPTIMR_RXOUTE (_U_(0x1) << DEVEPTIMR_RXOUTE_Pos) /**< (DEVEPTIMR) Received OUT Data Interrupt Mask */ -#define DEVEPTIMR_OVERFE_Pos 5 /**< (DEVEPTIMR) Overflow Interrupt Position */ -#define DEVEPTIMR_OVERFE (_U_(0x1) << DEVEPTIMR_OVERFE_Pos) /**< (DEVEPTIMR) Overflow Interrupt Mask */ -#define DEVEPTIMR_SHORTPACKETE_Pos 7 /**< (DEVEPTIMR) Short Packet Interrupt Position */ -#define DEVEPTIMR_SHORTPACKETE (_U_(0x1) << DEVEPTIMR_SHORTPACKETE_Pos) /**< (DEVEPTIMR) Short Packet Interrupt Mask */ -#define DEVEPTIMR_NBUSYBKE_Pos 12 /**< (DEVEPTIMR) Number of Busy Banks Interrupt Position */ -#define DEVEPTIMR_NBUSYBKE (_U_(0x1) << DEVEPTIMR_NBUSYBKE_Pos) /**< (DEVEPTIMR) Number of Busy Banks Interrupt Mask */ -#define DEVEPTIMR_KILLBK_Pos 13 /**< (DEVEPTIMR) Kill IN Bank Position */ -#define DEVEPTIMR_KILLBK (_U_(0x1) << DEVEPTIMR_KILLBK_Pos) /**< (DEVEPTIMR) Kill IN Bank Mask */ -#define DEVEPTIMR_FIFOCON_Pos 14 /**< (DEVEPTIMR) FIFO Control Position */ -#define DEVEPTIMR_FIFOCON (_U_(0x1) << DEVEPTIMR_FIFOCON_Pos) /**< (DEVEPTIMR) FIFO Control Mask */ -#define DEVEPTIMR_EPDISHDMA_Pos 16 /**< (DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Position */ -#define DEVEPTIMR_EPDISHDMA (_U_(0x1) << DEVEPTIMR_EPDISHDMA_Pos) /**< (DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Mask */ -#define DEVEPTIMR_RSTDT_Pos 18 /**< (DEVEPTIMR) Reset Data Toggle Position */ -#define DEVEPTIMR_RSTDT (_U_(0x1) << DEVEPTIMR_RSTDT_Pos) /**< (DEVEPTIMR) Reset Data Toggle Mask */ -#define DEVEPTIMR_Msk _U_(0x570A3) /**< (DEVEPTIMR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTIMR_CTRL_RXSTPE_Pos 2 /**< (DEVEPTIMR) Received SETUP Interrupt Position */ -#define DEVEPTIMR_CTRL_RXSTPE (_U_(0x1) << DEVEPTIMR_CTRL_RXSTPE_Pos) /**< (DEVEPTIMR) Received SETUP Interrupt Mask */ -#define DEVEPTIMR_CTRL_NAKOUTE_Pos 3 /**< (DEVEPTIMR) NAKed OUT Interrupt Position */ -#define DEVEPTIMR_CTRL_NAKOUTE (_U_(0x1) << DEVEPTIMR_CTRL_NAKOUTE_Pos) /**< (DEVEPTIMR) NAKed OUT Interrupt Mask */ -#define DEVEPTIMR_CTRL_NAKINE_Pos 4 /**< (DEVEPTIMR) NAKed IN Interrupt Position */ -#define DEVEPTIMR_CTRL_NAKINE (_U_(0x1) << DEVEPTIMR_CTRL_NAKINE_Pos) /**< (DEVEPTIMR) NAKed IN Interrupt Mask */ -#define DEVEPTIMR_CTRL_STALLEDE_Pos 6 /**< (DEVEPTIMR) STALLed Interrupt Position */ -#define DEVEPTIMR_CTRL_STALLEDE (_U_(0x1) << DEVEPTIMR_CTRL_STALLEDE_Pos) /**< (DEVEPTIMR) STALLed Interrupt Mask */ -#define DEVEPTIMR_CTRL_NYETDIS_Pos 17 /**< (DEVEPTIMR) NYET Token Disable Position */ -#define DEVEPTIMR_CTRL_NYETDIS (_U_(0x1) << DEVEPTIMR_CTRL_NYETDIS_Pos) /**< (DEVEPTIMR) NYET Token Disable Mask */ -#define DEVEPTIMR_CTRL_STALLRQ_Pos 19 /**< (DEVEPTIMR) STALL Request Position */ -#define DEVEPTIMR_CTRL_STALLRQ (_U_(0x1) << DEVEPTIMR_CTRL_STALLRQ_Pos) /**< (DEVEPTIMR) STALL Request Mask */ -#define DEVEPTIMR_CTRL_Msk _U_(0xA005C) /**< (DEVEPTIMR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTIMR_ISO_UNDERFE_Pos 2 /**< (DEVEPTIMR) Underflow Interrupt Position */ -#define DEVEPTIMR_ISO_UNDERFE (_U_(0x1) << DEVEPTIMR_ISO_UNDERFE_Pos) /**< (DEVEPTIMR) Underflow Interrupt Mask */ -#define DEVEPTIMR_ISO_HBISOINERRE_Pos 3 /**< (DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ -#define DEVEPTIMR_ISO_HBISOINERRE (_U_(0x1) << DEVEPTIMR_ISO_HBISOINERRE_Pos) /**< (DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ -#define DEVEPTIMR_ISO_HBISOFLUSHE_Pos 4 /**< (DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Position */ -#define DEVEPTIMR_ISO_HBISOFLUSHE (_U_(0x1) << DEVEPTIMR_ISO_HBISOFLUSHE_Pos) /**< (DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Mask */ -#define DEVEPTIMR_ISO_CRCERRE_Pos 6 /**< (DEVEPTIMR) CRC Error Interrupt Position */ -#define DEVEPTIMR_ISO_CRCERRE (_U_(0x1) << DEVEPTIMR_ISO_CRCERRE_Pos) /**< (DEVEPTIMR) CRC Error Interrupt Mask */ -#define DEVEPTIMR_ISO_MDATAE_Pos 8 /**< (DEVEPTIMR) MData Interrupt Position */ -#define DEVEPTIMR_ISO_MDATAE (_U_(0x1) << DEVEPTIMR_ISO_MDATAE_Pos) /**< (DEVEPTIMR) MData Interrupt Mask */ -#define DEVEPTIMR_ISO_DATAXE_Pos 9 /**< (DEVEPTIMR) DataX Interrupt Position */ -#define DEVEPTIMR_ISO_DATAXE (_U_(0x1) << DEVEPTIMR_ISO_DATAXE_Pos) /**< (DEVEPTIMR) DataX Interrupt Mask */ -#define DEVEPTIMR_ISO_ERRORTRANSE_Pos 10 /**< (DEVEPTIMR) Transaction Error Interrupt Position */ -#define DEVEPTIMR_ISO_ERRORTRANSE (_U_(0x1) << DEVEPTIMR_ISO_ERRORTRANSE_Pos) /**< (DEVEPTIMR) Transaction Error Interrupt Mask */ -#define DEVEPTIMR_ISO_Msk _U_(0x75C) /**< (DEVEPTIMR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTIMR_BLK_RXSTPE_Pos 2 /**< (DEVEPTIMR) Received SETUP Interrupt Position */ -#define DEVEPTIMR_BLK_RXSTPE (_U_(0x1) << DEVEPTIMR_BLK_RXSTPE_Pos) /**< (DEVEPTIMR) Received SETUP Interrupt Mask */ -#define DEVEPTIMR_BLK_NAKOUTE_Pos 3 /**< (DEVEPTIMR) NAKed OUT Interrupt Position */ -#define DEVEPTIMR_BLK_NAKOUTE (_U_(0x1) << DEVEPTIMR_BLK_NAKOUTE_Pos) /**< (DEVEPTIMR) NAKed OUT Interrupt Mask */ -#define DEVEPTIMR_BLK_NAKINE_Pos 4 /**< (DEVEPTIMR) NAKed IN Interrupt Position */ -#define DEVEPTIMR_BLK_NAKINE (_U_(0x1) << DEVEPTIMR_BLK_NAKINE_Pos) /**< (DEVEPTIMR) NAKed IN Interrupt Mask */ -#define DEVEPTIMR_BLK_STALLEDE_Pos 6 /**< (DEVEPTIMR) STALLed Interrupt Position */ -#define DEVEPTIMR_BLK_STALLEDE (_U_(0x1) << DEVEPTIMR_BLK_STALLEDE_Pos) /**< (DEVEPTIMR) STALLed Interrupt Mask */ -#define DEVEPTIMR_BLK_NYETDIS_Pos 17 /**< (DEVEPTIMR) NYET Token Disable Position */ -#define DEVEPTIMR_BLK_NYETDIS (_U_(0x1) << DEVEPTIMR_BLK_NYETDIS_Pos) /**< (DEVEPTIMR) NYET Token Disable Mask */ -#define DEVEPTIMR_BLK_STALLRQ_Pos 19 /**< (DEVEPTIMR) STALL Request Position */ -#define DEVEPTIMR_BLK_STALLRQ (_U_(0x1) << DEVEPTIMR_BLK_STALLRQ_Pos) /**< (DEVEPTIMR) STALL Request Mask */ -#define DEVEPTIMR_BLK_Msk _U_(0xA005C) /**< (DEVEPTIMR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTIMR_INTRPT_RXSTPE_Pos 2 /**< (DEVEPTIMR) Received SETUP Interrupt Position */ -#define DEVEPTIMR_INTRPT_RXSTPE (_U_(0x1) << DEVEPTIMR_INTRPT_RXSTPE_Pos) /**< (DEVEPTIMR) Received SETUP Interrupt Mask */ -#define DEVEPTIMR_INTRPT_NAKOUTE_Pos 3 /**< (DEVEPTIMR) NAKed OUT Interrupt Position */ -#define DEVEPTIMR_INTRPT_NAKOUTE (_U_(0x1) << DEVEPTIMR_INTRPT_NAKOUTE_Pos) /**< (DEVEPTIMR) NAKed OUT Interrupt Mask */ -#define DEVEPTIMR_INTRPT_NAKINE_Pos 4 /**< (DEVEPTIMR) NAKed IN Interrupt Position */ -#define DEVEPTIMR_INTRPT_NAKINE (_U_(0x1) << DEVEPTIMR_INTRPT_NAKINE_Pos) /**< (DEVEPTIMR) NAKed IN Interrupt Mask */ -#define DEVEPTIMR_INTRPT_STALLEDE_Pos 6 /**< (DEVEPTIMR) STALLed Interrupt Position */ -#define DEVEPTIMR_INTRPT_STALLEDE (_U_(0x1) << DEVEPTIMR_INTRPT_STALLEDE_Pos) /**< (DEVEPTIMR) STALLed Interrupt Mask */ -#define DEVEPTIMR_INTRPT_NYETDIS_Pos 17 /**< (DEVEPTIMR) NYET Token Disable Position */ -#define DEVEPTIMR_INTRPT_NYETDIS (_U_(0x1) << DEVEPTIMR_INTRPT_NYETDIS_Pos) /**< (DEVEPTIMR) NYET Token Disable Mask */ -#define DEVEPTIMR_INTRPT_STALLRQ_Pos 19 /**< (DEVEPTIMR) STALL Request Position */ -#define DEVEPTIMR_INTRPT_STALLRQ (_U_(0x1) << DEVEPTIMR_INTRPT_STALLRQ_Pos) /**< (DEVEPTIMR) STALL Request Mask */ -#define DEVEPTIMR_INTRPT_Msk _U_(0xA005C) /**< (DEVEPTIMR_INTRPT) Register Mask */ - -/* -------- DEVEPTIER : (USBHS Offset: 0x1f0) (/W 32) Device Endpoint Interrupt Enable Register -------- */ - -#define DEVEPTIER_OFFSET (0x1F0) /**< (DEVEPTIER) Device Endpoint Interrupt Enable Register Offset */ - -#define DEVEPTIER_TXINES_Pos 0 /**< (DEVEPTIER) Transmitted IN Data Interrupt Enable Position */ -#define DEVEPTIER_TXINES (_U_(0x1) << DEVEPTIER_TXINES_Pos) /**< (DEVEPTIER) Transmitted IN Data Interrupt Enable Mask */ -#define DEVEPTIER_RXOUTES_Pos 1 /**< (DEVEPTIER) Received OUT Data Interrupt Enable Position */ -#define DEVEPTIER_RXOUTES (_U_(0x1) << DEVEPTIER_RXOUTES_Pos) /**< (DEVEPTIER) Received OUT Data Interrupt Enable Mask */ -#define DEVEPTIER_OVERFES_Pos 5 /**< (DEVEPTIER) Overflow Interrupt Enable Position */ -#define DEVEPTIER_OVERFES (_U_(0x1) << DEVEPTIER_OVERFES_Pos) /**< (DEVEPTIER) Overflow Interrupt Enable Mask */ -#define DEVEPTIER_SHORTPACKETES_Pos 7 /**< (DEVEPTIER) Short Packet Interrupt Enable Position */ -#define DEVEPTIER_SHORTPACKETES (_U_(0x1) << DEVEPTIER_SHORTPACKETES_Pos) /**< (DEVEPTIER) Short Packet Interrupt Enable Mask */ -#define DEVEPTIER_NBUSYBKES_Pos 12 /**< (DEVEPTIER) Number of Busy Banks Interrupt Enable Position */ -#define DEVEPTIER_NBUSYBKES (_U_(0x1) << DEVEPTIER_NBUSYBKES_Pos) /**< (DEVEPTIER) Number of Busy Banks Interrupt Enable Mask */ -#define DEVEPTIER_KILLBKS_Pos 13 /**< (DEVEPTIER) Kill IN Bank Position */ -#define DEVEPTIER_KILLBKS (_U_(0x1) << DEVEPTIER_KILLBKS_Pos) /**< (DEVEPTIER) Kill IN Bank Mask */ -#define DEVEPTIER_FIFOCONS_Pos 14 /**< (DEVEPTIER) FIFO Control Position */ -#define DEVEPTIER_FIFOCONS (_U_(0x1) << DEVEPTIER_FIFOCONS_Pos) /**< (DEVEPTIER) FIFO Control Mask */ -#define DEVEPTIER_EPDISHDMAS_Pos 16 /**< (DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Position */ -#define DEVEPTIER_EPDISHDMAS (_U_(0x1) << DEVEPTIER_EPDISHDMAS_Pos) /**< (DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Mask */ -#define DEVEPTIER_RSTDTS_Pos 18 /**< (DEVEPTIER) Reset Data Toggle Enable Position */ -#define DEVEPTIER_RSTDTS (_U_(0x1) << DEVEPTIER_RSTDTS_Pos) /**< (DEVEPTIER) Reset Data Toggle Enable Mask */ -#define DEVEPTIER_Msk _U_(0x570A3) /**< (DEVEPTIER) Register Mask */ - -/* CTRL mode */ -#define DEVEPTIER_CTRL_RXSTPES_Pos 2 /**< (DEVEPTIER) Received SETUP Interrupt Enable Position */ -#define DEVEPTIER_CTRL_RXSTPES (_U_(0x1) << DEVEPTIER_CTRL_RXSTPES_Pos) /**< (DEVEPTIER) Received SETUP Interrupt Enable Mask */ -#define DEVEPTIER_CTRL_NAKOUTES_Pos 3 /**< (DEVEPTIER) NAKed OUT Interrupt Enable Position */ -#define DEVEPTIER_CTRL_NAKOUTES (_U_(0x1) << DEVEPTIER_CTRL_NAKOUTES_Pos) /**< (DEVEPTIER) NAKed OUT Interrupt Enable Mask */ -#define DEVEPTIER_CTRL_NAKINES_Pos 4 /**< (DEVEPTIER) NAKed IN Interrupt Enable Position */ -#define DEVEPTIER_CTRL_NAKINES (_U_(0x1) << DEVEPTIER_CTRL_NAKINES_Pos) /**< (DEVEPTIER) NAKed IN Interrupt Enable Mask */ -#define DEVEPTIER_CTRL_STALLEDES_Pos 6 /**< (DEVEPTIER) STALLed Interrupt Enable Position */ -#define DEVEPTIER_CTRL_STALLEDES (_U_(0x1) << DEVEPTIER_CTRL_STALLEDES_Pos) /**< (DEVEPTIER) STALLed Interrupt Enable Mask */ -#define DEVEPTIER_CTRL_NYETDISS_Pos 17 /**< (DEVEPTIER) NYET Token Disable Enable Position */ -#define DEVEPTIER_CTRL_NYETDISS (_U_(0x1) << DEVEPTIER_CTRL_NYETDISS_Pos) /**< (DEVEPTIER) NYET Token Disable Enable Mask */ -#define DEVEPTIER_CTRL_STALLRQS_Pos 19 /**< (DEVEPTIER) STALL Request Enable Position */ -#define DEVEPTIER_CTRL_STALLRQS (_U_(0x1) << DEVEPTIER_CTRL_STALLRQS_Pos) /**< (DEVEPTIER) STALL Request Enable Mask */ -#define DEVEPTIER_CTRL_Msk _U_(0xA005C) /**< (DEVEPTIER_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTIER_ISO_UNDERFES_Pos 2 /**< (DEVEPTIER) Underflow Interrupt Enable Position */ -#define DEVEPTIER_ISO_UNDERFES (_U_(0x1) << DEVEPTIER_ISO_UNDERFES_Pos) /**< (DEVEPTIER) Underflow Interrupt Enable Mask */ -#define DEVEPTIER_ISO_HBISOINERRES_Pos 3 /**< (DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Position */ -#define DEVEPTIER_ISO_HBISOINERRES (_U_(0x1) << DEVEPTIER_ISO_HBISOINERRES_Pos) /**< (DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Mask */ -#define DEVEPTIER_ISO_HBISOFLUSHES_Pos 4 /**< (DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Position */ -#define DEVEPTIER_ISO_HBISOFLUSHES (_U_(0x1) << DEVEPTIER_ISO_HBISOFLUSHES_Pos) /**< (DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Mask */ -#define DEVEPTIER_ISO_CRCERRES_Pos 6 /**< (DEVEPTIER) CRC Error Interrupt Enable Position */ -#define DEVEPTIER_ISO_CRCERRES (_U_(0x1) << DEVEPTIER_ISO_CRCERRES_Pos) /**< (DEVEPTIER) CRC Error Interrupt Enable Mask */ -#define DEVEPTIER_ISO_MDATAES_Pos 8 /**< (DEVEPTIER) MData Interrupt Enable Position */ -#define DEVEPTIER_ISO_MDATAES (_U_(0x1) << DEVEPTIER_ISO_MDATAES_Pos) /**< (DEVEPTIER) MData Interrupt Enable Mask */ -#define DEVEPTIER_ISO_DATAXES_Pos 9 /**< (DEVEPTIER) DataX Interrupt Enable Position */ -#define DEVEPTIER_ISO_DATAXES (_U_(0x1) << DEVEPTIER_ISO_DATAXES_Pos) /**< (DEVEPTIER) DataX Interrupt Enable Mask */ -#define DEVEPTIER_ISO_ERRORTRANSES_Pos 10 /**< (DEVEPTIER) Transaction Error Interrupt Enable Position */ -#define DEVEPTIER_ISO_ERRORTRANSES (_U_(0x1) << DEVEPTIER_ISO_ERRORTRANSES_Pos) /**< (DEVEPTIER) Transaction Error Interrupt Enable Mask */ -#define DEVEPTIER_ISO_Msk _U_(0x75C) /**< (DEVEPTIER_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTIER_BLK_RXSTPES_Pos 2 /**< (DEVEPTIER) Received SETUP Interrupt Enable Position */ -#define DEVEPTIER_BLK_RXSTPES (_U_(0x1) << DEVEPTIER_BLK_RXSTPES_Pos) /**< (DEVEPTIER) Received SETUP Interrupt Enable Mask */ -#define DEVEPTIER_BLK_NAKOUTES_Pos 3 /**< (DEVEPTIER) NAKed OUT Interrupt Enable Position */ -#define DEVEPTIER_BLK_NAKOUTES (_U_(0x1) << DEVEPTIER_BLK_NAKOUTES_Pos) /**< (DEVEPTIER) NAKed OUT Interrupt Enable Mask */ -#define DEVEPTIER_BLK_NAKINES_Pos 4 /**< (DEVEPTIER) NAKed IN Interrupt Enable Position */ -#define DEVEPTIER_BLK_NAKINES (_U_(0x1) << DEVEPTIER_BLK_NAKINES_Pos) /**< (DEVEPTIER) NAKed IN Interrupt Enable Mask */ -#define DEVEPTIER_BLK_STALLEDES_Pos 6 /**< (DEVEPTIER) STALLed Interrupt Enable Position */ -#define DEVEPTIER_BLK_STALLEDES (_U_(0x1) << DEVEPTIER_BLK_STALLEDES_Pos) /**< (DEVEPTIER) STALLed Interrupt Enable Mask */ -#define DEVEPTIER_BLK_NYETDISS_Pos 17 /**< (DEVEPTIER) NYET Token Disable Enable Position */ -#define DEVEPTIER_BLK_NYETDISS (_U_(0x1) << DEVEPTIER_BLK_NYETDISS_Pos) /**< (DEVEPTIER) NYET Token Disable Enable Mask */ -#define DEVEPTIER_BLK_STALLRQS_Pos 19 /**< (DEVEPTIER) STALL Request Enable Position */ -#define DEVEPTIER_BLK_STALLRQS (_U_(0x1) << DEVEPTIER_BLK_STALLRQS_Pos) /**< (DEVEPTIER) STALL Request Enable Mask */ -#define DEVEPTIER_BLK_Msk _U_(0xA005C) /**< (DEVEPTIER_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTIER_INTRPT_RXSTPES_Pos 2 /**< (DEVEPTIER) Received SETUP Interrupt Enable Position */ -#define DEVEPTIER_INTRPT_RXSTPES (_U_(0x1) << DEVEPTIER_INTRPT_RXSTPES_Pos) /**< (DEVEPTIER) Received SETUP Interrupt Enable Mask */ -#define DEVEPTIER_INTRPT_NAKOUTES_Pos 3 /**< (DEVEPTIER) NAKed OUT Interrupt Enable Position */ -#define DEVEPTIER_INTRPT_NAKOUTES (_U_(0x1) << DEVEPTIER_INTRPT_NAKOUTES_Pos) /**< (DEVEPTIER) NAKed OUT Interrupt Enable Mask */ -#define DEVEPTIER_INTRPT_NAKINES_Pos 4 /**< (DEVEPTIER) NAKed IN Interrupt Enable Position */ -#define DEVEPTIER_INTRPT_NAKINES (_U_(0x1) << DEVEPTIER_INTRPT_NAKINES_Pos) /**< (DEVEPTIER) NAKed IN Interrupt Enable Mask */ -#define DEVEPTIER_INTRPT_STALLEDES_Pos 6 /**< (DEVEPTIER) STALLed Interrupt Enable Position */ -#define DEVEPTIER_INTRPT_STALLEDES (_U_(0x1) << DEVEPTIER_INTRPT_STALLEDES_Pos) /**< (DEVEPTIER) STALLed Interrupt Enable Mask */ -#define DEVEPTIER_INTRPT_NYETDISS_Pos 17 /**< (DEVEPTIER) NYET Token Disable Enable Position */ -#define DEVEPTIER_INTRPT_NYETDISS (_U_(0x1) << DEVEPTIER_INTRPT_NYETDISS_Pos) /**< (DEVEPTIER) NYET Token Disable Enable Mask */ -#define DEVEPTIER_INTRPT_STALLRQS_Pos 19 /**< (DEVEPTIER) STALL Request Enable Position */ -#define DEVEPTIER_INTRPT_STALLRQS (_U_(0x1) << DEVEPTIER_INTRPT_STALLRQS_Pos) /**< (DEVEPTIER) STALL Request Enable Mask */ -#define DEVEPTIER_INTRPT_Msk _U_(0xA005C) /**< (DEVEPTIER_INTRPT) Register Mask */ - -/* -------- DEVEPTIDR : (USBHS Offset: 0x220) (/W 32) Device Endpoint Interrupt Disable Register -------- */ - -#define DEVEPTIDR_OFFSET (0x220) /**< (DEVEPTIDR) Device Endpoint Interrupt Disable Register Offset */ - -#define DEVEPTIDR_TXINEC_Pos 0 /**< (DEVEPTIDR) Transmitted IN Interrupt Clear Position */ -#define DEVEPTIDR_TXINEC (_U_(0x1) << DEVEPTIDR_TXINEC_Pos) /**< (DEVEPTIDR) Transmitted IN Interrupt Clear Mask */ -#define DEVEPTIDR_RXOUTEC_Pos 1 /**< (DEVEPTIDR) Received OUT Data Interrupt Clear Position */ -#define DEVEPTIDR_RXOUTEC (_U_(0x1) << DEVEPTIDR_RXOUTEC_Pos) /**< (DEVEPTIDR) Received OUT Data Interrupt Clear Mask */ -#define DEVEPTIDR_OVERFEC_Pos 5 /**< (DEVEPTIDR) Overflow Interrupt Clear Position */ -#define DEVEPTIDR_OVERFEC (_U_(0x1) << DEVEPTIDR_OVERFEC_Pos) /**< (DEVEPTIDR) Overflow Interrupt Clear Mask */ -#define DEVEPTIDR_SHORTPACKETEC_Pos 7 /**< (DEVEPTIDR) Shortpacket Interrupt Clear Position */ -#define DEVEPTIDR_SHORTPACKETEC (_U_(0x1) << DEVEPTIDR_SHORTPACKETEC_Pos) /**< (DEVEPTIDR) Shortpacket Interrupt Clear Mask */ -#define DEVEPTIDR_NBUSYBKEC_Pos 12 /**< (DEVEPTIDR) Number of Busy Banks Interrupt Clear Position */ -#define DEVEPTIDR_NBUSYBKEC (_U_(0x1) << DEVEPTIDR_NBUSYBKEC_Pos) /**< (DEVEPTIDR) Number of Busy Banks Interrupt Clear Mask */ -#define DEVEPTIDR_FIFOCONC_Pos 14 /**< (DEVEPTIDR) FIFO Control Clear Position */ -#define DEVEPTIDR_FIFOCONC (_U_(0x1) << DEVEPTIDR_FIFOCONC_Pos) /**< (DEVEPTIDR) FIFO Control Clear Mask */ -#define DEVEPTIDR_EPDISHDMAC_Pos 16 /**< (DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Position */ -#define DEVEPTIDR_EPDISHDMAC (_U_(0x1) << DEVEPTIDR_EPDISHDMAC_Pos) /**< (DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Mask */ -#define DEVEPTIDR_Msk _U_(0x150A3) /**< (DEVEPTIDR) Register Mask */ - -/* CTRL mode */ -#define DEVEPTIDR_CTRL_RXSTPEC_Pos 2 /**< (DEVEPTIDR) Received SETUP Interrupt Clear Position */ -#define DEVEPTIDR_CTRL_RXSTPEC (_U_(0x1) << DEVEPTIDR_CTRL_RXSTPEC_Pos) /**< (DEVEPTIDR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTIDR_CTRL_NAKOUTEC_Pos 3 /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTIDR_CTRL_NAKOUTEC (_U_(0x1) << DEVEPTIDR_CTRL_NAKOUTEC_Pos) /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTIDR_CTRL_NAKINEC_Pos 4 /**< (DEVEPTIDR) NAKed IN Interrupt Clear Position */ -#define DEVEPTIDR_CTRL_NAKINEC (_U_(0x1) << DEVEPTIDR_CTRL_NAKINEC_Pos) /**< (DEVEPTIDR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTIDR_CTRL_STALLEDEC_Pos 6 /**< (DEVEPTIDR) STALLed Interrupt Clear Position */ -#define DEVEPTIDR_CTRL_STALLEDEC (_U_(0x1) << DEVEPTIDR_CTRL_STALLEDEC_Pos) /**< (DEVEPTIDR) STALLed Interrupt Clear Mask */ -#define DEVEPTIDR_CTRL_NYETDISC_Pos 17 /**< (DEVEPTIDR) NYET Token Disable Clear Position */ -#define DEVEPTIDR_CTRL_NYETDISC (_U_(0x1) << DEVEPTIDR_CTRL_NYETDISC_Pos) /**< (DEVEPTIDR) NYET Token Disable Clear Mask */ -#define DEVEPTIDR_CTRL_STALLRQC_Pos 19 /**< (DEVEPTIDR) STALL Request Clear Position */ -#define DEVEPTIDR_CTRL_STALLRQC (_U_(0x1) << DEVEPTIDR_CTRL_STALLRQC_Pos) /**< (DEVEPTIDR) STALL Request Clear Mask */ -#define DEVEPTIDR_CTRL_Msk _U_(0xA005C) /**< (DEVEPTIDR_CTRL) Register Mask */ - -/* ISO mode */ -#define DEVEPTIDR_ISO_UNDERFEC_Pos 2 /**< (DEVEPTIDR) Underflow Interrupt Clear Position */ -#define DEVEPTIDR_ISO_UNDERFEC (_U_(0x1) << DEVEPTIDR_ISO_UNDERFEC_Pos) /**< (DEVEPTIDR) Underflow Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_HBISOINERREC_Pos 3 /**< (DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ -#define DEVEPTIDR_ISO_HBISOINERREC (_U_(0x1) << DEVEPTIDR_ISO_HBISOINERREC_Pos) /**< (DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_HBISOFLUSHEC_Pos 4 /**< (DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ -#define DEVEPTIDR_ISO_HBISOFLUSHEC (_U_(0x1) << DEVEPTIDR_ISO_HBISOFLUSHEC_Pos) /**< (DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_MDATAEC_Pos 8 /**< (DEVEPTIDR) MData Interrupt Clear Position */ -#define DEVEPTIDR_ISO_MDATAEC (_U_(0x1) << DEVEPTIDR_ISO_MDATAEC_Pos) /**< (DEVEPTIDR) MData Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_DATAXEC_Pos 9 /**< (DEVEPTIDR) DataX Interrupt Clear Position */ -#define DEVEPTIDR_ISO_DATAXEC (_U_(0x1) << DEVEPTIDR_ISO_DATAXEC_Pos) /**< (DEVEPTIDR) DataX Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_ERRORTRANSEC_Pos 10 /**< (DEVEPTIDR) Transaction Error Interrupt Clear Position */ -#define DEVEPTIDR_ISO_ERRORTRANSEC (_U_(0x1) << DEVEPTIDR_ISO_ERRORTRANSEC_Pos) /**< (DEVEPTIDR) Transaction Error Interrupt Clear Mask */ -#define DEVEPTIDR_ISO_Msk _U_(0x71C) /**< (DEVEPTIDR_ISO) Register Mask */ - -/* BLK mode */ -#define DEVEPTIDR_BLK_RXSTPEC_Pos 2 /**< (DEVEPTIDR) Received SETUP Interrupt Clear Position */ -#define DEVEPTIDR_BLK_RXSTPEC (_U_(0x1) << DEVEPTIDR_BLK_RXSTPEC_Pos) /**< (DEVEPTIDR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTIDR_BLK_NAKOUTEC_Pos 3 /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTIDR_BLK_NAKOUTEC (_U_(0x1) << DEVEPTIDR_BLK_NAKOUTEC_Pos) /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTIDR_BLK_NAKINEC_Pos 4 /**< (DEVEPTIDR) NAKed IN Interrupt Clear Position */ -#define DEVEPTIDR_BLK_NAKINEC (_U_(0x1) << DEVEPTIDR_BLK_NAKINEC_Pos) /**< (DEVEPTIDR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTIDR_BLK_STALLEDEC_Pos 6 /**< (DEVEPTIDR) STALLed Interrupt Clear Position */ -#define DEVEPTIDR_BLK_STALLEDEC (_U_(0x1) << DEVEPTIDR_BLK_STALLEDEC_Pos) /**< (DEVEPTIDR) STALLed Interrupt Clear Mask */ -#define DEVEPTIDR_BLK_NYETDISC_Pos 17 /**< (DEVEPTIDR) NYET Token Disable Clear Position */ -#define DEVEPTIDR_BLK_NYETDISC (_U_(0x1) << DEVEPTIDR_BLK_NYETDISC_Pos) /**< (DEVEPTIDR) NYET Token Disable Clear Mask */ -#define DEVEPTIDR_BLK_STALLRQC_Pos 19 /**< (DEVEPTIDR) STALL Request Clear Position */ -#define DEVEPTIDR_BLK_STALLRQC (_U_(0x1) << DEVEPTIDR_BLK_STALLRQC_Pos) /**< (DEVEPTIDR) STALL Request Clear Mask */ -#define DEVEPTIDR_BLK_Msk _U_(0xA005C) /**< (DEVEPTIDR_BLK) Register Mask */ - -/* INTRPT mode */ -#define DEVEPTIDR_INTRPT_RXSTPEC_Pos 2 /**< (DEVEPTIDR) Received SETUP Interrupt Clear Position */ -#define DEVEPTIDR_INTRPT_RXSTPEC (_U_(0x1) << DEVEPTIDR_INTRPT_RXSTPEC_Pos) /**< (DEVEPTIDR) Received SETUP Interrupt Clear Mask */ -#define DEVEPTIDR_INTRPT_NAKOUTEC_Pos 3 /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Position */ -#define DEVEPTIDR_INTRPT_NAKOUTEC (_U_(0x1) << DEVEPTIDR_INTRPT_NAKOUTEC_Pos) /**< (DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ -#define DEVEPTIDR_INTRPT_NAKINEC_Pos 4 /**< (DEVEPTIDR) NAKed IN Interrupt Clear Position */ -#define DEVEPTIDR_INTRPT_NAKINEC (_U_(0x1) << DEVEPTIDR_INTRPT_NAKINEC_Pos) /**< (DEVEPTIDR) NAKed IN Interrupt Clear Mask */ -#define DEVEPTIDR_INTRPT_STALLEDEC_Pos 6 /**< (DEVEPTIDR) STALLed Interrupt Clear Position */ -#define DEVEPTIDR_INTRPT_STALLEDEC (_U_(0x1) << DEVEPTIDR_INTRPT_STALLEDEC_Pos) /**< (DEVEPTIDR) STALLed Interrupt Clear Mask */ -#define DEVEPTIDR_INTRPT_NYETDISC_Pos 17 /**< (DEVEPTIDR) NYET Token Disable Clear Position */ -#define DEVEPTIDR_INTRPT_NYETDISC (_U_(0x1) << DEVEPTIDR_INTRPT_NYETDISC_Pos) /**< (DEVEPTIDR) NYET Token Disable Clear Mask */ -#define DEVEPTIDR_INTRPT_STALLRQC_Pos 19 /**< (DEVEPTIDR) STALL Request Clear Position */ -#define DEVEPTIDR_INTRPT_STALLRQC (_U_(0x1) << DEVEPTIDR_INTRPT_STALLRQC_Pos) /**< (DEVEPTIDR) STALL Request Clear Mask */ -#define DEVEPTIDR_INTRPT_Msk _U_(0xA005C) /**< (DEVEPTIDR_INTRPT) Register Mask */ - -/* -------- HSTCTRL : (USBHS Offset: 0x400) (R/W 32) Host General Control Register -------- */ - -#define HSTCTRL_OFFSET (0x400) /**< (HSTCTRL) Host General Control Register Offset */ - -#define HSTCTRL_SOFE_Pos 8 /**< (HSTCTRL) Start of Frame Generation Enable Position */ -#define HSTCTRL_SOFE (_U_(0x1) << HSTCTRL_SOFE_Pos) /**< (HSTCTRL) Start of Frame Generation Enable Mask */ -#define HSTCTRL_RESET_Pos 9 /**< (HSTCTRL) Send USB Reset Position */ -#define HSTCTRL_RESET (_U_(0x1) << HSTCTRL_RESET_Pos) /**< (HSTCTRL) Send USB Reset Mask */ -#define HSTCTRL_RESUME_Pos 10 /**< (HSTCTRL) Send USB Resume Position */ -#define HSTCTRL_RESUME (_U_(0x1) << HSTCTRL_RESUME_Pos) /**< (HSTCTRL) Send USB Resume Mask */ -#define HSTCTRL_SPDCONF_Pos 12 /**< (HSTCTRL) Mode Configuration Position */ -#define HSTCTRL_SPDCONF (_U_(0x3) << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) Mode Configuration Mask */ -#define HSTCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ -#define HSTCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (HSTCTRL) For a better consumption, if high speed is not needed. */ -#define HSTCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (HSTCTRL) Forced high speed. */ -#define HSTCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ -#define HSTCTRL_SPDCONF_NORMAL (HSTCTRL_SPDCONF_NORMAL_Val << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. Position */ -#define HSTCTRL_SPDCONF_LOW_POWER (HSTCTRL_SPDCONF_LOW_POWER_Val << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) For a better consumption, if high speed is not needed. Position */ -#define HSTCTRL_SPDCONF_HIGH_SPEED (HSTCTRL_SPDCONF_HIGH_SPEED_Val << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) Forced high speed. Position */ -#define HSTCTRL_SPDCONF_FORCED_FS (HSTCTRL_SPDCONF_FORCED_FS_Val << HSTCTRL_SPDCONF_Pos) /**< (HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. Position */ -#define HSTCTRL_Msk _U_(0x3700) /**< (HSTCTRL) Register Mask */ - -/* -------- HSTISR : (USBHS Offset: 0x404) (R/ 32) Host Global Interrupt Status Register -------- */ - -#define HSTISR_OFFSET (0x404) /**< (HSTISR) Host Global Interrupt Status Register Offset */ - -#define HSTISR_DCONNI_Pos 0 /**< (HSTISR) Device Connection Interrupt Position */ -#define HSTISR_DCONNI (_U_(0x1) << HSTISR_DCONNI_Pos) /**< (HSTISR) Device Connection Interrupt Mask */ -#define HSTISR_DDISCI_Pos 1 /**< (HSTISR) Device Disconnection Interrupt Position */ -#define HSTISR_DDISCI (_U_(0x1) << HSTISR_DDISCI_Pos) /**< (HSTISR) Device Disconnection Interrupt Mask */ -#define HSTISR_RSTI_Pos 2 /**< (HSTISR) USB Reset Sent Interrupt Position */ -#define HSTISR_RSTI (_U_(0x1) << HSTISR_RSTI_Pos) /**< (HSTISR) USB Reset Sent Interrupt Mask */ -#define HSTISR_RSMEDI_Pos 3 /**< (HSTISR) Downstream Resume Sent Interrupt Position */ -#define HSTISR_RSMEDI (_U_(0x1) << HSTISR_RSMEDI_Pos) /**< (HSTISR) Downstream Resume Sent Interrupt Mask */ -#define HSTISR_RXRSMI_Pos 4 /**< (HSTISR) Upstream Resume Received Interrupt Position */ -#define HSTISR_RXRSMI (_U_(0x1) << HSTISR_RXRSMI_Pos) /**< (HSTISR) Upstream Resume Received Interrupt Mask */ -#define HSTISR_HSOFI_Pos 5 /**< (HSTISR) Host Start of Frame Interrupt Position */ -#define HSTISR_HSOFI (_U_(0x1) << HSTISR_HSOFI_Pos) /**< (HSTISR) Host Start of Frame Interrupt Mask */ -#define HSTISR_HWUPI_Pos 6 /**< (HSTISR) Host Wake-Up Interrupt Position */ -#define HSTISR_HWUPI (_U_(0x1) << HSTISR_HWUPI_Pos) /**< (HSTISR) Host Wake-Up Interrupt Mask */ -#define HSTISR_PEP_0_Pos 8 /**< (HSTISR) Pipe 0 Interrupt Position */ -#define HSTISR_PEP_0 (_U_(0x1) << HSTISR_PEP_0_Pos) /**< (HSTISR) Pipe 0 Interrupt Mask */ -#define HSTISR_PEP_1_Pos 9 /**< (HSTISR) Pipe 1 Interrupt Position */ -#define HSTISR_PEP_1 (_U_(0x1) << HSTISR_PEP_1_Pos) /**< (HSTISR) Pipe 1 Interrupt Mask */ -#define HSTISR_PEP_2_Pos 10 /**< (HSTISR) Pipe 2 Interrupt Position */ -#define HSTISR_PEP_2 (_U_(0x1) << HSTISR_PEP_2_Pos) /**< (HSTISR) Pipe 2 Interrupt Mask */ -#define HSTISR_PEP_3_Pos 11 /**< (HSTISR) Pipe 3 Interrupt Position */ -#define HSTISR_PEP_3 (_U_(0x1) << HSTISR_PEP_3_Pos) /**< (HSTISR) Pipe 3 Interrupt Mask */ -#define HSTISR_PEP_4_Pos 12 /**< (HSTISR) Pipe 4 Interrupt Position */ -#define HSTISR_PEP_4 (_U_(0x1) << HSTISR_PEP_4_Pos) /**< (HSTISR) Pipe 4 Interrupt Mask */ -#define HSTISR_PEP_5_Pos 13 /**< (HSTISR) Pipe 5 Interrupt Position */ -#define HSTISR_PEP_5 (_U_(0x1) << HSTISR_PEP_5_Pos) /**< (HSTISR) Pipe 5 Interrupt Mask */ -#define HSTISR_PEP_6_Pos 14 /**< (HSTISR) Pipe 6 Interrupt Position */ -#define HSTISR_PEP_6 (_U_(0x1) << HSTISR_PEP_6_Pos) /**< (HSTISR) Pipe 6 Interrupt Mask */ -#define HSTISR_PEP_7_Pos 15 /**< (HSTISR) Pipe 7 Interrupt Position */ -#define HSTISR_PEP_7 (_U_(0x1) << HSTISR_PEP_7_Pos) /**< (HSTISR) Pipe 7 Interrupt Mask */ -#define HSTISR_PEP_8_Pos 16 /**< (HSTISR) Pipe 8 Interrupt Position */ -#define HSTISR_PEP_8 (_U_(0x1) << HSTISR_PEP_8_Pos) /**< (HSTISR) Pipe 8 Interrupt Mask */ -#define HSTISR_PEP_9_Pos 17 /**< (HSTISR) Pipe 9 Interrupt Position */ -#define HSTISR_PEP_9 (_U_(0x1) << HSTISR_PEP_9_Pos) /**< (HSTISR) Pipe 9 Interrupt Mask */ -#define HSTISR_DMA_0_Pos 25 /**< (HSTISR) DMA Channel 0 Interrupt Position */ -#define HSTISR_DMA_0 (_U_(0x1) << HSTISR_DMA_0_Pos) /**< (HSTISR) DMA Channel 0 Interrupt Mask */ -#define HSTISR_DMA_1_Pos 26 /**< (HSTISR) DMA Channel 1 Interrupt Position */ -#define HSTISR_DMA_1 (_U_(0x1) << HSTISR_DMA_1_Pos) /**< (HSTISR) DMA Channel 1 Interrupt Mask */ -#define HSTISR_DMA_2_Pos 27 /**< (HSTISR) DMA Channel 2 Interrupt Position */ -#define HSTISR_DMA_2 (_U_(0x1) << HSTISR_DMA_2_Pos) /**< (HSTISR) DMA Channel 2 Interrupt Mask */ -#define HSTISR_DMA_3_Pos 28 /**< (HSTISR) DMA Channel 3 Interrupt Position */ -#define HSTISR_DMA_3 (_U_(0x1) << HSTISR_DMA_3_Pos) /**< (HSTISR) DMA Channel 3 Interrupt Mask */ -#define HSTISR_DMA_4_Pos 29 /**< (HSTISR) DMA Channel 4 Interrupt Position */ -#define HSTISR_DMA_4 (_U_(0x1) << HSTISR_DMA_4_Pos) /**< (HSTISR) DMA Channel 4 Interrupt Mask */ -#define HSTISR_DMA_5_Pos 30 /**< (HSTISR) DMA Channel 5 Interrupt Position */ -#define HSTISR_DMA_5 (_U_(0x1) << HSTISR_DMA_5_Pos) /**< (HSTISR) DMA Channel 5 Interrupt Mask */ -#define HSTISR_DMA_6_Pos 31 /**< (HSTISR) DMA Channel 6 Interrupt Position */ -#define HSTISR_DMA_6 (_U_(0x1) << HSTISR_DMA_6_Pos) /**< (HSTISR) DMA Channel 6 Interrupt Mask */ -#define HSTISR_Msk _U_(0xFE03FF7F) /**< (HSTISR) Register Mask */ - -#define HSTISR_PEP__Pos 8 /**< (HSTISR Position) Pipe x Interrupt */ -#define HSTISR_PEP_ (_U_(0x3FF) << HSTISR_PEP__Pos) /**< (HSTISR Mask) PEP_ */ -#define HSTISR_DMA__Pos 25 /**< (HSTISR Position) DMA Channel 6 Interrupt */ -#define HSTISR_DMA_ (_U_(0x7F) << HSTISR_DMA__Pos) /**< (HSTISR Mask) DMA_ */ - -/* -------- HSTICR : (USBHS Offset: 0x408) (/W 32) Host Global Interrupt Clear Register -------- */ - -#define HSTICR_OFFSET (0x408) /**< (HSTICR) Host Global Interrupt Clear Register Offset */ - -#define HSTICR_DCONNIC_Pos 0 /**< (HSTICR) Device Connection Interrupt Clear Position */ -#define HSTICR_DCONNIC (_U_(0x1) << HSTICR_DCONNIC_Pos) /**< (HSTICR) Device Connection Interrupt Clear Mask */ -#define HSTICR_DDISCIC_Pos 1 /**< (HSTICR) Device Disconnection Interrupt Clear Position */ -#define HSTICR_DDISCIC (_U_(0x1) << HSTICR_DDISCIC_Pos) /**< (HSTICR) Device Disconnection Interrupt Clear Mask */ -#define HSTICR_RSTIC_Pos 2 /**< (HSTICR) USB Reset Sent Interrupt Clear Position */ -#define HSTICR_RSTIC (_U_(0x1) << HSTICR_RSTIC_Pos) /**< (HSTICR) USB Reset Sent Interrupt Clear Mask */ -#define HSTICR_RSMEDIC_Pos 3 /**< (HSTICR) Downstream Resume Sent Interrupt Clear Position */ -#define HSTICR_RSMEDIC (_U_(0x1) << HSTICR_RSMEDIC_Pos) /**< (HSTICR) Downstream Resume Sent Interrupt Clear Mask */ -#define HSTICR_RXRSMIC_Pos 4 /**< (HSTICR) Upstream Resume Received Interrupt Clear Position */ -#define HSTICR_RXRSMIC (_U_(0x1) << HSTICR_RXRSMIC_Pos) /**< (HSTICR) Upstream Resume Received Interrupt Clear Mask */ -#define HSTICR_HSOFIC_Pos 5 /**< (HSTICR) Host Start of Frame Interrupt Clear Position */ -#define HSTICR_HSOFIC (_U_(0x1) << HSTICR_HSOFIC_Pos) /**< (HSTICR) Host Start of Frame Interrupt Clear Mask */ -#define HSTICR_HWUPIC_Pos 6 /**< (HSTICR) Host Wake-Up Interrupt Clear Position */ -#define HSTICR_HWUPIC (_U_(0x1) << HSTICR_HWUPIC_Pos) /**< (HSTICR) Host Wake-Up Interrupt Clear Mask */ -#define HSTICR_Msk _U_(0x7F) /**< (HSTICR) Register Mask */ - -/* -------- HSTIFR : (USBHS Offset: 0x40c) (/W 32) Host Global Interrupt Set Register -------- */ - -#define HSTIFR_OFFSET (0x40C) /**< (HSTIFR) Host Global Interrupt Set Register Offset */ - -#define HSTIFR_DCONNIS_Pos 0 /**< (HSTIFR) Device Connection Interrupt Set Position */ -#define HSTIFR_DCONNIS (_U_(0x1) << HSTIFR_DCONNIS_Pos) /**< (HSTIFR) Device Connection Interrupt Set Mask */ -#define HSTIFR_DDISCIS_Pos 1 /**< (HSTIFR) Device Disconnection Interrupt Set Position */ -#define HSTIFR_DDISCIS (_U_(0x1) << HSTIFR_DDISCIS_Pos) /**< (HSTIFR) Device Disconnection Interrupt Set Mask */ -#define HSTIFR_RSTIS_Pos 2 /**< (HSTIFR) USB Reset Sent Interrupt Set Position */ -#define HSTIFR_RSTIS (_U_(0x1) << HSTIFR_RSTIS_Pos) /**< (HSTIFR) USB Reset Sent Interrupt Set Mask */ -#define HSTIFR_RSMEDIS_Pos 3 /**< (HSTIFR) Downstream Resume Sent Interrupt Set Position */ -#define HSTIFR_RSMEDIS (_U_(0x1) << HSTIFR_RSMEDIS_Pos) /**< (HSTIFR) Downstream Resume Sent Interrupt Set Mask */ -#define HSTIFR_RXRSMIS_Pos 4 /**< (HSTIFR) Upstream Resume Received Interrupt Set Position */ -#define HSTIFR_RXRSMIS (_U_(0x1) << HSTIFR_RXRSMIS_Pos) /**< (HSTIFR) Upstream Resume Received Interrupt Set Mask */ -#define HSTIFR_HSOFIS_Pos 5 /**< (HSTIFR) Host Start of Frame Interrupt Set Position */ -#define HSTIFR_HSOFIS (_U_(0x1) << HSTIFR_HSOFIS_Pos) /**< (HSTIFR) Host Start of Frame Interrupt Set Mask */ -#define HSTIFR_HWUPIS_Pos 6 /**< (HSTIFR) Host Wake-Up Interrupt Set Position */ -#define HSTIFR_HWUPIS (_U_(0x1) << HSTIFR_HWUPIS_Pos) /**< (HSTIFR) Host Wake-Up Interrupt Set Mask */ -#define HSTIFR_DMA_0_Pos 25 /**< (HSTIFR) DMA Channel 0 Interrupt Set Position */ -#define HSTIFR_DMA_0 (_U_(0x1) << HSTIFR_DMA_0_Pos) /**< (HSTIFR) DMA Channel 0 Interrupt Set Mask */ -#define HSTIFR_DMA_1_Pos 26 /**< (HSTIFR) DMA Channel 1 Interrupt Set Position */ -#define HSTIFR_DMA_1 (_U_(0x1) << HSTIFR_DMA_1_Pos) /**< (HSTIFR) DMA Channel 1 Interrupt Set Mask */ -#define HSTIFR_DMA_2_Pos 27 /**< (HSTIFR) DMA Channel 2 Interrupt Set Position */ -#define HSTIFR_DMA_2 (_U_(0x1) << HSTIFR_DMA_2_Pos) /**< (HSTIFR) DMA Channel 2 Interrupt Set Mask */ -#define HSTIFR_DMA_3_Pos 28 /**< (HSTIFR) DMA Channel 3 Interrupt Set Position */ -#define HSTIFR_DMA_3 (_U_(0x1) << HSTIFR_DMA_3_Pos) /**< (HSTIFR) DMA Channel 3 Interrupt Set Mask */ -#define HSTIFR_DMA_4_Pos 29 /**< (HSTIFR) DMA Channel 4 Interrupt Set Position */ -#define HSTIFR_DMA_4 (_U_(0x1) << HSTIFR_DMA_4_Pos) /**< (HSTIFR) DMA Channel 4 Interrupt Set Mask */ -#define HSTIFR_DMA_5_Pos 30 /**< (HSTIFR) DMA Channel 5 Interrupt Set Position */ -#define HSTIFR_DMA_5 (_U_(0x1) << HSTIFR_DMA_5_Pos) /**< (HSTIFR) DMA Channel 5 Interrupt Set Mask */ -#define HSTIFR_DMA_6_Pos 31 /**< (HSTIFR) DMA Channel 6 Interrupt Set Position */ -#define HSTIFR_DMA_6 (_U_(0x1) << HSTIFR_DMA_6_Pos) /**< (HSTIFR) DMA Channel 6 Interrupt Set Mask */ -#define HSTIFR_Msk _U_(0xFE00007F) /**< (HSTIFR) Register Mask */ - -#define HSTIFR_DMA__Pos 25 /**< (HSTIFR Position) DMA Channel 6 Interrupt Set */ -#define HSTIFR_DMA_ (_U_(0x7F) << HSTIFR_DMA__Pos) /**< (HSTIFR Mask) DMA_ */ - -/* -------- HSTIMR : (USBHS Offset: 0x410) (R/ 32) Host Global Interrupt Mask Register -------- */ - -#define HSTIMR_OFFSET (0x410) /**< (HSTIMR) Host Global Interrupt Mask Register Offset */ - -#define HSTIMR_DCONNIE_Pos 0 /**< (HSTIMR) Device Connection Interrupt Enable Position */ -#define HSTIMR_DCONNIE (_U_(0x1) << HSTIMR_DCONNIE_Pos) /**< (HSTIMR) Device Connection Interrupt Enable Mask */ -#define HSTIMR_DDISCIE_Pos 1 /**< (HSTIMR) Device Disconnection Interrupt Enable Position */ -#define HSTIMR_DDISCIE (_U_(0x1) << HSTIMR_DDISCIE_Pos) /**< (HSTIMR) Device Disconnection Interrupt Enable Mask */ -#define HSTIMR_RSTIE_Pos 2 /**< (HSTIMR) USB Reset Sent Interrupt Enable Position */ -#define HSTIMR_RSTIE (_U_(0x1) << HSTIMR_RSTIE_Pos) /**< (HSTIMR) USB Reset Sent Interrupt Enable Mask */ -#define HSTIMR_RSMEDIE_Pos 3 /**< (HSTIMR) Downstream Resume Sent Interrupt Enable Position */ -#define HSTIMR_RSMEDIE (_U_(0x1) << HSTIMR_RSMEDIE_Pos) /**< (HSTIMR) Downstream Resume Sent Interrupt Enable Mask */ -#define HSTIMR_RXRSMIE_Pos 4 /**< (HSTIMR) Upstream Resume Received Interrupt Enable Position */ -#define HSTIMR_RXRSMIE (_U_(0x1) << HSTIMR_RXRSMIE_Pos) /**< (HSTIMR) Upstream Resume Received Interrupt Enable Mask */ -#define HSTIMR_HSOFIE_Pos 5 /**< (HSTIMR) Host Start of Frame Interrupt Enable Position */ -#define HSTIMR_HSOFIE (_U_(0x1) << HSTIMR_HSOFIE_Pos) /**< (HSTIMR) Host Start of Frame Interrupt Enable Mask */ -#define HSTIMR_HWUPIE_Pos 6 /**< (HSTIMR) Host Wake-Up Interrupt Enable Position */ -#define HSTIMR_HWUPIE (_U_(0x1) << HSTIMR_HWUPIE_Pos) /**< (HSTIMR) Host Wake-Up Interrupt Enable Mask */ -#define HSTIMR_PEP_0_Pos 8 /**< (HSTIMR) Pipe 0 Interrupt Enable Position */ -#define HSTIMR_PEP_0 (_U_(0x1) << HSTIMR_PEP_0_Pos) /**< (HSTIMR) Pipe 0 Interrupt Enable Mask */ -#define HSTIMR_PEP_1_Pos 9 /**< (HSTIMR) Pipe 1 Interrupt Enable Position */ -#define HSTIMR_PEP_1 (_U_(0x1) << HSTIMR_PEP_1_Pos) /**< (HSTIMR) Pipe 1 Interrupt Enable Mask */ -#define HSTIMR_PEP_2_Pos 10 /**< (HSTIMR) Pipe 2 Interrupt Enable Position */ -#define HSTIMR_PEP_2 (_U_(0x1) << HSTIMR_PEP_2_Pos) /**< (HSTIMR) Pipe 2 Interrupt Enable Mask */ -#define HSTIMR_PEP_3_Pos 11 /**< (HSTIMR) Pipe 3 Interrupt Enable Position */ -#define HSTIMR_PEP_3 (_U_(0x1) << HSTIMR_PEP_3_Pos) /**< (HSTIMR) Pipe 3 Interrupt Enable Mask */ -#define HSTIMR_PEP_4_Pos 12 /**< (HSTIMR) Pipe 4 Interrupt Enable Position */ -#define HSTIMR_PEP_4 (_U_(0x1) << HSTIMR_PEP_4_Pos) /**< (HSTIMR) Pipe 4 Interrupt Enable Mask */ -#define HSTIMR_PEP_5_Pos 13 /**< (HSTIMR) Pipe 5 Interrupt Enable Position */ -#define HSTIMR_PEP_5 (_U_(0x1) << HSTIMR_PEP_5_Pos) /**< (HSTIMR) Pipe 5 Interrupt Enable Mask */ -#define HSTIMR_PEP_6_Pos 14 /**< (HSTIMR) Pipe 6 Interrupt Enable Position */ -#define HSTIMR_PEP_6 (_U_(0x1) << HSTIMR_PEP_6_Pos) /**< (HSTIMR) Pipe 6 Interrupt Enable Mask */ -#define HSTIMR_PEP_7_Pos 15 /**< (HSTIMR) Pipe 7 Interrupt Enable Position */ -#define HSTIMR_PEP_7 (_U_(0x1) << HSTIMR_PEP_7_Pos) /**< (HSTIMR) Pipe 7 Interrupt Enable Mask */ -#define HSTIMR_PEP_8_Pos 16 /**< (HSTIMR) Pipe 8 Interrupt Enable Position */ -#define HSTIMR_PEP_8 (_U_(0x1) << HSTIMR_PEP_8_Pos) /**< (HSTIMR) Pipe 8 Interrupt Enable Mask */ -#define HSTIMR_PEP_9_Pos 17 /**< (HSTIMR) Pipe 9 Interrupt Enable Position */ -#define HSTIMR_PEP_9 (_U_(0x1) << HSTIMR_PEP_9_Pos) /**< (HSTIMR) Pipe 9 Interrupt Enable Mask */ -#define HSTIMR_DMA_0_Pos 25 /**< (HSTIMR) DMA Channel 0 Interrupt Enable Position */ -#define HSTIMR_DMA_0 (_U_(0x1) << HSTIMR_DMA_0_Pos) /**< (HSTIMR) DMA Channel 0 Interrupt Enable Mask */ -#define HSTIMR_DMA_1_Pos 26 /**< (HSTIMR) DMA Channel 1 Interrupt Enable Position */ -#define HSTIMR_DMA_1 (_U_(0x1) << HSTIMR_DMA_1_Pos) /**< (HSTIMR) DMA Channel 1 Interrupt Enable Mask */ -#define HSTIMR_DMA_2_Pos 27 /**< (HSTIMR) DMA Channel 2 Interrupt Enable Position */ -#define HSTIMR_DMA_2 (_U_(0x1) << HSTIMR_DMA_2_Pos) /**< (HSTIMR) DMA Channel 2 Interrupt Enable Mask */ -#define HSTIMR_DMA_3_Pos 28 /**< (HSTIMR) DMA Channel 3 Interrupt Enable Position */ -#define HSTIMR_DMA_3 (_U_(0x1) << HSTIMR_DMA_3_Pos) /**< (HSTIMR) DMA Channel 3 Interrupt Enable Mask */ -#define HSTIMR_DMA_4_Pos 29 /**< (HSTIMR) DMA Channel 4 Interrupt Enable Position */ -#define HSTIMR_DMA_4 (_U_(0x1) << HSTIMR_DMA_4_Pos) /**< (HSTIMR) DMA Channel 4 Interrupt Enable Mask */ -#define HSTIMR_DMA_5_Pos 30 /**< (HSTIMR) DMA Channel 5 Interrupt Enable Position */ -#define HSTIMR_DMA_5 (_U_(0x1) << HSTIMR_DMA_5_Pos) /**< (HSTIMR) DMA Channel 5 Interrupt Enable Mask */ -#define HSTIMR_DMA_6_Pos 31 /**< (HSTIMR) DMA Channel 6 Interrupt Enable Position */ -#define HSTIMR_DMA_6 (_U_(0x1) << HSTIMR_DMA_6_Pos) /**< (HSTIMR) DMA Channel 6 Interrupt Enable Mask */ -#define HSTIMR_Msk _U_(0xFE03FF7F) /**< (HSTIMR) Register Mask */ - -#define HSTIMR_PEP__Pos 8 /**< (HSTIMR Position) Pipe x Interrupt Enable */ -#define HSTIMR_PEP_ (_U_(0x3FF) << HSTIMR_PEP__Pos) /**< (HSTIMR Mask) PEP_ */ -#define HSTIMR_DMA__Pos 25 /**< (HSTIMR Position) DMA Channel 6 Interrupt Enable */ -#define HSTIMR_DMA_ (_U_(0x7F) << HSTIMR_DMA__Pos) /**< (HSTIMR Mask) DMA_ */ - -/* -------- HSTIDR : (USBHS Offset: 0x414) (/W 32) Host Global Interrupt Disable Register -------- */ - -#define HSTIDR_OFFSET (0x414) /**< (HSTIDR) Host Global Interrupt Disable Register Offset */ - -#define HSTIDR_DCONNIEC_Pos 0 /**< (HSTIDR) Device Connection Interrupt Disable Position */ -#define HSTIDR_DCONNIEC (_U_(0x1) << HSTIDR_DCONNIEC_Pos) /**< (HSTIDR) Device Connection Interrupt Disable Mask */ -#define HSTIDR_DDISCIEC_Pos 1 /**< (HSTIDR) Device Disconnection Interrupt Disable Position */ -#define HSTIDR_DDISCIEC (_U_(0x1) << HSTIDR_DDISCIEC_Pos) /**< (HSTIDR) Device Disconnection Interrupt Disable Mask */ -#define HSTIDR_RSTIEC_Pos 2 /**< (HSTIDR) USB Reset Sent Interrupt Disable Position */ -#define HSTIDR_RSTIEC (_U_(0x1) << HSTIDR_RSTIEC_Pos) /**< (HSTIDR) USB Reset Sent Interrupt Disable Mask */ -#define HSTIDR_RSMEDIEC_Pos 3 /**< (HSTIDR) Downstream Resume Sent Interrupt Disable Position */ -#define HSTIDR_RSMEDIEC (_U_(0x1) << HSTIDR_RSMEDIEC_Pos) /**< (HSTIDR) Downstream Resume Sent Interrupt Disable Mask */ -#define HSTIDR_RXRSMIEC_Pos 4 /**< (HSTIDR) Upstream Resume Received Interrupt Disable Position */ -#define HSTIDR_RXRSMIEC (_U_(0x1) << HSTIDR_RXRSMIEC_Pos) /**< (HSTIDR) Upstream Resume Received Interrupt Disable Mask */ -#define HSTIDR_HSOFIEC_Pos 5 /**< (HSTIDR) Host Start of Frame Interrupt Disable Position */ -#define HSTIDR_HSOFIEC (_U_(0x1) << HSTIDR_HSOFIEC_Pos) /**< (HSTIDR) Host Start of Frame Interrupt Disable Mask */ -#define HSTIDR_HWUPIEC_Pos 6 /**< (HSTIDR) Host Wake-Up Interrupt Disable Position */ -#define HSTIDR_HWUPIEC (_U_(0x1) << HSTIDR_HWUPIEC_Pos) /**< (HSTIDR) Host Wake-Up Interrupt Disable Mask */ -#define HSTIDR_PEP_0_Pos 8 /**< (HSTIDR) Pipe 0 Interrupt Disable Position */ -#define HSTIDR_PEP_0 (_U_(0x1) << HSTIDR_PEP_0_Pos) /**< (HSTIDR) Pipe 0 Interrupt Disable Mask */ -#define HSTIDR_PEP_1_Pos 9 /**< (HSTIDR) Pipe 1 Interrupt Disable Position */ -#define HSTIDR_PEP_1 (_U_(0x1) << HSTIDR_PEP_1_Pos) /**< (HSTIDR) Pipe 1 Interrupt Disable Mask */ -#define HSTIDR_PEP_2_Pos 10 /**< (HSTIDR) Pipe 2 Interrupt Disable Position */ -#define HSTIDR_PEP_2 (_U_(0x1) << HSTIDR_PEP_2_Pos) /**< (HSTIDR) Pipe 2 Interrupt Disable Mask */ -#define HSTIDR_PEP_3_Pos 11 /**< (HSTIDR) Pipe 3 Interrupt Disable Position */ -#define HSTIDR_PEP_3 (_U_(0x1) << HSTIDR_PEP_3_Pos) /**< (HSTIDR) Pipe 3 Interrupt Disable Mask */ -#define HSTIDR_PEP_4_Pos 12 /**< (HSTIDR) Pipe 4 Interrupt Disable Position */ -#define HSTIDR_PEP_4 (_U_(0x1) << HSTIDR_PEP_4_Pos) /**< (HSTIDR) Pipe 4 Interrupt Disable Mask */ -#define HSTIDR_PEP_5_Pos 13 /**< (HSTIDR) Pipe 5 Interrupt Disable Position */ -#define HSTIDR_PEP_5 (_U_(0x1) << HSTIDR_PEP_5_Pos) /**< (HSTIDR) Pipe 5 Interrupt Disable Mask */ -#define HSTIDR_PEP_6_Pos 14 /**< (HSTIDR) Pipe 6 Interrupt Disable Position */ -#define HSTIDR_PEP_6 (_U_(0x1) << HSTIDR_PEP_6_Pos) /**< (HSTIDR) Pipe 6 Interrupt Disable Mask */ -#define HSTIDR_PEP_7_Pos 15 /**< (HSTIDR) Pipe 7 Interrupt Disable Position */ -#define HSTIDR_PEP_7 (_U_(0x1) << HSTIDR_PEP_7_Pos) /**< (HSTIDR) Pipe 7 Interrupt Disable Mask */ -#define HSTIDR_PEP_8_Pos 16 /**< (HSTIDR) Pipe 8 Interrupt Disable Position */ -#define HSTIDR_PEP_8 (_U_(0x1) << HSTIDR_PEP_8_Pos) /**< (HSTIDR) Pipe 8 Interrupt Disable Mask */ -#define HSTIDR_PEP_9_Pos 17 /**< (HSTIDR) Pipe 9 Interrupt Disable Position */ -#define HSTIDR_PEP_9 (_U_(0x1) << HSTIDR_PEP_9_Pos) /**< (HSTIDR) Pipe 9 Interrupt Disable Mask */ -#define HSTIDR_DMA_0_Pos 25 /**< (HSTIDR) DMA Channel 0 Interrupt Disable Position */ -#define HSTIDR_DMA_0 (_U_(0x1) << HSTIDR_DMA_0_Pos) /**< (HSTIDR) DMA Channel 0 Interrupt Disable Mask */ -#define HSTIDR_DMA_1_Pos 26 /**< (HSTIDR) DMA Channel 1 Interrupt Disable Position */ -#define HSTIDR_DMA_1 (_U_(0x1) << HSTIDR_DMA_1_Pos) /**< (HSTIDR) DMA Channel 1 Interrupt Disable Mask */ -#define HSTIDR_DMA_2_Pos 27 /**< (HSTIDR) DMA Channel 2 Interrupt Disable Position */ -#define HSTIDR_DMA_2 (_U_(0x1) << HSTIDR_DMA_2_Pos) /**< (HSTIDR) DMA Channel 2 Interrupt Disable Mask */ -#define HSTIDR_DMA_3_Pos 28 /**< (HSTIDR) DMA Channel 3 Interrupt Disable Position */ -#define HSTIDR_DMA_3 (_U_(0x1) << HSTIDR_DMA_3_Pos) /**< (HSTIDR) DMA Channel 3 Interrupt Disable Mask */ -#define HSTIDR_DMA_4_Pos 29 /**< (HSTIDR) DMA Channel 4 Interrupt Disable Position */ -#define HSTIDR_DMA_4 (_U_(0x1) << HSTIDR_DMA_4_Pos) /**< (HSTIDR) DMA Channel 4 Interrupt Disable Mask */ -#define HSTIDR_DMA_5_Pos 30 /**< (HSTIDR) DMA Channel 5 Interrupt Disable Position */ -#define HSTIDR_DMA_5 (_U_(0x1) << HSTIDR_DMA_5_Pos) /**< (HSTIDR) DMA Channel 5 Interrupt Disable Mask */ -#define HSTIDR_DMA_6_Pos 31 /**< (HSTIDR) DMA Channel 6 Interrupt Disable Position */ -#define HSTIDR_DMA_6 (_U_(0x1) << HSTIDR_DMA_6_Pos) /**< (HSTIDR) DMA Channel 6 Interrupt Disable Mask */ -#define HSTIDR_Msk _U_(0xFE03FF7F) /**< (HSTIDR) Register Mask */ - -#define HSTIDR_PEP__Pos 8 /**< (HSTIDR Position) Pipe x Interrupt Disable */ -#define HSTIDR_PEP_ (_U_(0x3FF) << HSTIDR_PEP__Pos) /**< (HSTIDR Mask) PEP_ */ -#define HSTIDR_DMA__Pos 25 /**< (HSTIDR Position) DMA Channel 6 Interrupt Disable */ -#define HSTIDR_DMA_ (_U_(0x7F) << HSTIDR_DMA__Pos) /**< (HSTIDR Mask) DMA_ */ - -/* -------- HSTIER : (USBHS Offset: 0x418) (/W 32) Host Global Interrupt Enable Register -------- */ - -#define HSTIER_OFFSET (0x418) /**< (HSTIER) Host Global Interrupt Enable Register Offset */ - -#define HSTIER_DCONNIES_Pos 0 /**< (HSTIER) Device Connection Interrupt Enable Position */ -#define HSTIER_DCONNIES (_U_(0x1) << HSTIER_DCONNIES_Pos) /**< (HSTIER) Device Connection Interrupt Enable Mask */ -#define HSTIER_DDISCIES_Pos 1 /**< (HSTIER) Device Disconnection Interrupt Enable Position */ -#define HSTIER_DDISCIES (_U_(0x1) << HSTIER_DDISCIES_Pos) /**< (HSTIER) Device Disconnection Interrupt Enable Mask */ -#define HSTIER_RSTIES_Pos 2 /**< (HSTIER) USB Reset Sent Interrupt Enable Position */ -#define HSTIER_RSTIES (_U_(0x1) << HSTIER_RSTIES_Pos) /**< (HSTIER) USB Reset Sent Interrupt Enable Mask */ -#define HSTIER_RSMEDIES_Pos 3 /**< (HSTIER) Downstream Resume Sent Interrupt Enable Position */ -#define HSTIER_RSMEDIES (_U_(0x1) << HSTIER_RSMEDIES_Pos) /**< (HSTIER) Downstream Resume Sent Interrupt Enable Mask */ -#define HSTIER_RXRSMIES_Pos 4 /**< (HSTIER) Upstream Resume Received Interrupt Enable Position */ -#define HSTIER_RXRSMIES (_U_(0x1) << HSTIER_RXRSMIES_Pos) /**< (HSTIER) Upstream Resume Received Interrupt Enable Mask */ -#define HSTIER_HSOFIES_Pos 5 /**< (HSTIER) Host Start of Frame Interrupt Enable Position */ -#define HSTIER_HSOFIES (_U_(0x1) << HSTIER_HSOFIES_Pos) /**< (HSTIER) Host Start of Frame Interrupt Enable Mask */ -#define HSTIER_HWUPIES_Pos 6 /**< (HSTIER) Host Wake-Up Interrupt Enable Position */ -#define HSTIER_HWUPIES (_U_(0x1) << HSTIER_HWUPIES_Pos) /**< (HSTIER) Host Wake-Up Interrupt Enable Mask */ -#define HSTIER_PEP_0_Pos 8 /**< (HSTIER) Pipe 0 Interrupt Enable Position */ -#define HSTIER_PEP_0 (_U_(0x1) << HSTIER_PEP_0_Pos) /**< (HSTIER) Pipe 0 Interrupt Enable Mask */ -#define HSTIER_PEP_1_Pos 9 /**< (HSTIER) Pipe 1 Interrupt Enable Position */ -#define HSTIER_PEP_1 (_U_(0x1) << HSTIER_PEP_1_Pos) /**< (HSTIER) Pipe 1 Interrupt Enable Mask */ -#define HSTIER_PEP_2_Pos 10 /**< (HSTIER) Pipe 2 Interrupt Enable Position */ -#define HSTIER_PEP_2 (_U_(0x1) << HSTIER_PEP_2_Pos) /**< (HSTIER) Pipe 2 Interrupt Enable Mask */ -#define HSTIER_PEP_3_Pos 11 /**< (HSTIER) Pipe 3 Interrupt Enable Position */ -#define HSTIER_PEP_3 (_U_(0x1) << HSTIER_PEP_3_Pos) /**< (HSTIER) Pipe 3 Interrupt Enable Mask */ -#define HSTIER_PEP_4_Pos 12 /**< (HSTIER) Pipe 4 Interrupt Enable Position */ -#define HSTIER_PEP_4 (_U_(0x1) << HSTIER_PEP_4_Pos) /**< (HSTIER) Pipe 4 Interrupt Enable Mask */ -#define HSTIER_PEP_5_Pos 13 /**< (HSTIER) Pipe 5 Interrupt Enable Position */ -#define HSTIER_PEP_5 (_U_(0x1) << HSTIER_PEP_5_Pos) /**< (HSTIER) Pipe 5 Interrupt Enable Mask */ -#define HSTIER_PEP_6_Pos 14 /**< (HSTIER) Pipe 6 Interrupt Enable Position */ -#define HSTIER_PEP_6 (_U_(0x1) << HSTIER_PEP_6_Pos) /**< (HSTIER) Pipe 6 Interrupt Enable Mask */ -#define HSTIER_PEP_7_Pos 15 /**< (HSTIER) Pipe 7 Interrupt Enable Position */ -#define HSTIER_PEP_7 (_U_(0x1) << HSTIER_PEP_7_Pos) /**< (HSTIER) Pipe 7 Interrupt Enable Mask */ -#define HSTIER_PEP_8_Pos 16 /**< (HSTIER) Pipe 8 Interrupt Enable Position */ -#define HSTIER_PEP_8 (_U_(0x1) << HSTIER_PEP_8_Pos) /**< (HSTIER) Pipe 8 Interrupt Enable Mask */ -#define HSTIER_PEP_9_Pos 17 /**< (HSTIER) Pipe 9 Interrupt Enable Position */ -#define HSTIER_PEP_9 (_U_(0x1) << HSTIER_PEP_9_Pos) /**< (HSTIER) Pipe 9 Interrupt Enable Mask */ -#define HSTIER_DMA_0_Pos 25 /**< (HSTIER) DMA Channel 0 Interrupt Enable Position */ -#define HSTIER_DMA_0 (_U_(0x1) << HSTIER_DMA_0_Pos) /**< (HSTIER) DMA Channel 0 Interrupt Enable Mask */ -#define HSTIER_DMA_1_Pos 26 /**< (HSTIER) DMA Channel 1 Interrupt Enable Position */ -#define HSTIER_DMA_1 (_U_(0x1) << HSTIER_DMA_1_Pos) /**< (HSTIER) DMA Channel 1 Interrupt Enable Mask */ -#define HSTIER_DMA_2_Pos 27 /**< (HSTIER) DMA Channel 2 Interrupt Enable Position */ -#define HSTIER_DMA_2 (_U_(0x1) << HSTIER_DMA_2_Pos) /**< (HSTIER) DMA Channel 2 Interrupt Enable Mask */ -#define HSTIER_DMA_3_Pos 28 /**< (HSTIER) DMA Channel 3 Interrupt Enable Position */ -#define HSTIER_DMA_3 (_U_(0x1) << HSTIER_DMA_3_Pos) /**< (HSTIER) DMA Channel 3 Interrupt Enable Mask */ -#define HSTIER_DMA_4_Pos 29 /**< (HSTIER) DMA Channel 4 Interrupt Enable Position */ -#define HSTIER_DMA_4 (_U_(0x1) << HSTIER_DMA_4_Pos) /**< (HSTIER) DMA Channel 4 Interrupt Enable Mask */ -#define HSTIER_DMA_5_Pos 30 /**< (HSTIER) DMA Channel 5 Interrupt Enable Position */ -#define HSTIER_DMA_5 (_U_(0x1) << HSTIER_DMA_5_Pos) /**< (HSTIER) DMA Channel 5 Interrupt Enable Mask */ -#define HSTIER_DMA_6_Pos 31 /**< (HSTIER) DMA Channel 6 Interrupt Enable Position */ -#define HSTIER_DMA_6 (_U_(0x1) << HSTIER_DMA_6_Pos) /**< (HSTIER) DMA Channel 6 Interrupt Enable Mask */ -#define HSTIER_Msk _U_(0xFE03FF7F) /**< (HSTIER) Register Mask */ - -#define HSTIER_PEP__Pos 8 /**< (HSTIER Position) Pipe x Interrupt Enable */ -#define HSTIER_PEP_ (_U_(0x3FF) << HSTIER_PEP__Pos) /**< (HSTIER Mask) PEP_ */ -#define HSTIER_DMA__Pos 25 /**< (HSTIER Position) DMA Channel 6 Interrupt Enable */ -#define HSTIER_DMA_ (_U_(0x7F) << HSTIER_DMA__Pos) /**< (HSTIER Mask) DMA_ */ - -/* -------- HSTPIP : (USBHS Offset: 0x41c) (R/W 32) Host Pipe Register -------- */ - -#define HSTPIP_OFFSET (0x41C) /**< (HSTPIP) Host Pipe Register Offset */ - -#define HSTPIP_PEN0_Pos 0 /**< (HSTPIP) Pipe 0 Enable Position */ -#define HSTPIP_PEN0 (_U_(0x1) << HSTPIP_PEN0_Pos) /**< (HSTPIP) Pipe 0 Enable Mask */ -#define HSTPIP_PEN1_Pos 1 /**< (HSTPIP) Pipe 1 Enable Position */ -#define HSTPIP_PEN1 (_U_(0x1) << HSTPIP_PEN1_Pos) /**< (HSTPIP) Pipe 1 Enable Mask */ -#define HSTPIP_PEN2_Pos 2 /**< (HSTPIP) Pipe 2 Enable Position */ -#define HSTPIP_PEN2 (_U_(0x1) << HSTPIP_PEN2_Pos) /**< (HSTPIP) Pipe 2 Enable Mask */ -#define HSTPIP_PEN3_Pos 3 /**< (HSTPIP) Pipe 3 Enable Position */ -#define HSTPIP_PEN3 (_U_(0x1) << HSTPIP_PEN3_Pos) /**< (HSTPIP) Pipe 3 Enable Mask */ -#define HSTPIP_PEN4_Pos 4 /**< (HSTPIP) Pipe 4 Enable Position */ -#define HSTPIP_PEN4 (_U_(0x1) << HSTPIP_PEN4_Pos) /**< (HSTPIP) Pipe 4 Enable Mask */ -#define HSTPIP_PEN5_Pos 5 /**< (HSTPIP) Pipe 5 Enable Position */ -#define HSTPIP_PEN5 (_U_(0x1) << HSTPIP_PEN5_Pos) /**< (HSTPIP) Pipe 5 Enable Mask */ -#define HSTPIP_PEN6_Pos 6 /**< (HSTPIP) Pipe 6 Enable Position */ -#define HSTPIP_PEN6 (_U_(0x1) << HSTPIP_PEN6_Pos) /**< (HSTPIP) Pipe 6 Enable Mask */ -#define HSTPIP_PEN7_Pos 7 /**< (HSTPIP) Pipe 7 Enable Position */ -#define HSTPIP_PEN7 (_U_(0x1) << HSTPIP_PEN7_Pos) /**< (HSTPIP) Pipe 7 Enable Mask */ -#define HSTPIP_PEN8_Pos 8 /**< (HSTPIP) Pipe 8 Enable Position */ -#define HSTPIP_PEN8 (_U_(0x1) << HSTPIP_PEN8_Pos) /**< (HSTPIP) Pipe 8 Enable Mask */ -#define HSTPIP_PRST0_Pos 16 /**< (HSTPIP) Pipe 0 Reset Position */ -#define HSTPIP_PRST0 (_U_(0x1) << HSTPIP_PRST0_Pos) /**< (HSTPIP) Pipe 0 Reset Mask */ -#define HSTPIP_PRST1_Pos 17 /**< (HSTPIP) Pipe 1 Reset Position */ -#define HSTPIP_PRST1 (_U_(0x1) << HSTPIP_PRST1_Pos) /**< (HSTPIP) Pipe 1 Reset Mask */ -#define HSTPIP_PRST2_Pos 18 /**< (HSTPIP) Pipe 2 Reset Position */ -#define HSTPIP_PRST2 (_U_(0x1) << HSTPIP_PRST2_Pos) /**< (HSTPIP) Pipe 2 Reset Mask */ -#define HSTPIP_PRST3_Pos 19 /**< (HSTPIP) Pipe 3 Reset Position */ -#define HSTPIP_PRST3 (_U_(0x1) << HSTPIP_PRST3_Pos) /**< (HSTPIP) Pipe 3 Reset Mask */ -#define HSTPIP_PRST4_Pos 20 /**< (HSTPIP) Pipe 4 Reset Position */ -#define HSTPIP_PRST4 (_U_(0x1) << HSTPIP_PRST4_Pos) /**< (HSTPIP) Pipe 4 Reset Mask */ -#define HSTPIP_PRST5_Pos 21 /**< (HSTPIP) Pipe 5 Reset Position */ -#define HSTPIP_PRST5 (_U_(0x1) << HSTPIP_PRST5_Pos) /**< (HSTPIP) Pipe 5 Reset Mask */ -#define HSTPIP_PRST6_Pos 22 /**< (HSTPIP) Pipe 6 Reset Position */ -#define HSTPIP_PRST6 (_U_(0x1) << HSTPIP_PRST6_Pos) /**< (HSTPIP) Pipe 6 Reset Mask */ -#define HSTPIP_PRST7_Pos 23 /**< (HSTPIP) Pipe 7 Reset Position */ -#define HSTPIP_PRST7 (_U_(0x1) << HSTPIP_PRST7_Pos) /**< (HSTPIP) Pipe 7 Reset Mask */ -#define HSTPIP_PRST8_Pos 24 /**< (HSTPIP) Pipe 8 Reset Position */ -#define HSTPIP_PRST8 (_U_(0x1) << HSTPIP_PRST8_Pos) /**< (HSTPIP) Pipe 8 Reset Mask */ -#define HSTPIP_Msk _U_(0x1FF01FF) /**< (HSTPIP) Register Mask */ - -#define HSTPIP_PEN_Pos 0 /**< (HSTPIP Position) Pipe x Enable */ -#define HSTPIP_PEN (_U_(0x1FF) << HSTPIP_PEN_Pos) /**< (HSTPIP Mask) PEN */ -#define HSTPIP_PRST_Pos 16 /**< (HSTPIP Position) Pipe 8 Reset */ -#define HSTPIP_PRST (_U_(0x1FF) << HSTPIP_PRST_Pos) /**< (HSTPIP Mask) PRST */ - -/* -------- HSTFNUM : (USBHS Offset: 0x420) (R/W 32) Host Frame Number Register -------- */ - -#define HSTFNUM_OFFSET (0x420) /**< (HSTFNUM) Host Frame Number Register Offset */ - -#define HSTFNUM_MFNUM_Pos 0 /**< (HSTFNUM) Micro Frame Number Position */ -#define HSTFNUM_MFNUM (_U_(0x7) << HSTFNUM_MFNUM_Pos) /**< (HSTFNUM) Micro Frame Number Mask */ -#define HSTFNUM_FNUM_Pos 3 /**< (HSTFNUM) Frame Number Position */ -#define HSTFNUM_FNUM (_U_(0x7FF) << HSTFNUM_FNUM_Pos) /**< (HSTFNUM) Frame Number Mask */ -#define HSTFNUM_FLENHIGH_Pos 16 /**< (HSTFNUM) Frame Length Position */ -#define HSTFNUM_FLENHIGH (_U_(0xFF) << HSTFNUM_FLENHIGH_Pos) /**< (HSTFNUM) Frame Length Mask */ -#define HSTFNUM_Msk _U_(0xFF3FFF) /**< (HSTFNUM) Register Mask */ - -/* -------- HSTADDR1 : (USBHS Offset: 0x424) (R/W 32) Host Address 1 Register -------- */ - -#define HSTADDR1_OFFSET (0x424) /**< (HSTADDR1) Host Address 1 Register Offset */ - -#define HSTADDR1_HSTADDRP0_Pos 0 /**< (HSTADDR1) USB Host Address Position */ -#define HSTADDR1_HSTADDRP0 (_U_(0x7F) << HSTADDR1_HSTADDRP0_Pos) /**< (HSTADDR1) USB Host Address Mask */ -#define HSTADDR1_HSTADDRP1_Pos 8 /**< (HSTADDR1) USB Host Address Position */ -#define HSTADDR1_HSTADDRP1 (_U_(0x7F) << HSTADDR1_HSTADDRP1_Pos) /**< (HSTADDR1) USB Host Address Mask */ -#define HSTADDR1_HSTADDRP2_Pos 16 /**< (HSTADDR1) USB Host Address Position */ -#define HSTADDR1_HSTADDRP2 (_U_(0x7F) << HSTADDR1_HSTADDRP2_Pos) /**< (HSTADDR1) USB Host Address Mask */ -#define HSTADDR1_HSTADDRP3_Pos 24 /**< (HSTADDR1) USB Host Address Position */ -#define HSTADDR1_HSTADDRP3 (_U_(0x7F) << HSTADDR1_HSTADDRP3_Pos) /**< (HSTADDR1) USB Host Address Mask */ -#define HSTADDR1_Msk _U_(0x7F7F7F7F) /**< (HSTADDR1) Register Mask */ - -/* -------- HSTADDR2 : (USBHS Offset: 0x428) (R/W 32) Host Address 2 Register -------- */ - -#define HSTADDR2_OFFSET (0x428) /**< (HSTADDR2) Host Address 2 Register Offset */ - -#define HSTADDR2_HSTADDRP4_Pos 0 /**< (HSTADDR2) USB Host Address Position */ -#define HSTADDR2_HSTADDRP4 (_U_(0x7F) << HSTADDR2_HSTADDRP4_Pos) /**< (HSTADDR2) USB Host Address Mask */ -#define HSTADDR2_HSTADDRP5_Pos 8 /**< (HSTADDR2) USB Host Address Position */ -#define HSTADDR2_HSTADDRP5 (_U_(0x7F) << HSTADDR2_HSTADDRP5_Pos) /**< (HSTADDR2) USB Host Address Mask */ -#define HSTADDR2_HSTADDRP6_Pos 16 /**< (HSTADDR2) USB Host Address Position */ -#define HSTADDR2_HSTADDRP6 (_U_(0x7F) << HSTADDR2_HSTADDRP6_Pos) /**< (HSTADDR2) USB Host Address Mask */ -#define HSTADDR2_HSTADDRP7_Pos 24 /**< (HSTADDR2) USB Host Address Position */ -#define HSTADDR2_HSTADDRP7 (_U_(0x7F) << HSTADDR2_HSTADDRP7_Pos) /**< (HSTADDR2) USB Host Address Mask */ -#define HSTADDR2_Msk _U_(0x7F7F7F7F) /**< (HSTADDR2) Register Mask */ - -/* -------- HSTADDR3 : (USBHS Offset: 0x42c) (R/W 32) Host Address 3 Register -------- */ - -#define HSTADDR3_OFFSET (0x42C) /**< (HSTADDR3) Host Address 3 Register Offset */ - -#define HSTADDR3_HSTADDRP8_Pos 0 /**< (HSTADDR3) USB Host Address Position */ -#define HSTADDR3_HSTADDRP8 (_U_(0x7F) << HSTADDR3_HSTADDRP8_Pos) /**< (HSTADDR3) USB Host Address Mask */ -#define HSTADDR3_HSTADDRP9_Pos 8 /**< (HSTADDR3) USB Host Address Position */ -#define HSTADDR3_HSTADDRP9 (_U_(0x7F) << HSTADDR3_HSTADDRP9_Pos) /**< (HSTADDR3) USB Host Address Mask */ -#define HSTADDR3_Msk _U_(0x7F7F) /**< (HSTADDR3) Register Mask */ - -/* -------- HSTPIPCFG : (USBHS Offset: 0x500) (R/W 32) Host Pipe Configuration Register -------- */ - -#define HSTPIPCFG_OFFSET (0x500) /**< (HSTPIPCFG) Host Pipe Configuration Register Offset */ - -#define HSTPIPCFG_ALLOC_Pos 1 /**< (HSTPIPCFG) Pipe Memory Allocate Position */ -#define HSTPIPCFG_ALLOC (_U_(0x1) << HSTPIPCFG_ALLOC_Pos) /**< (HSTPIPCFG) Pipe Memory Allocate Mask */ -#define HSTPIPCFG_PBK_Pos 2 /**< (HSTPIPCFG) Pipe Banks Position */ -#define HSTPIPCFG_PBK (_U_(0x3) << HSTPIPCFG_PBK_Pos) /**< (HSTPIPCFG) Pipe Banks Mask */ -#define HSTPIPCFG_PBK_1_BANK_Val _U_(0x0) /**< (HSTPIPCFG) Single-bank pipe */ -#define HSTPIPCFG_PBK_2_BANK_Val _U_(0x1) /**< (HSTPIPCFG) Double-bank pipe */ -#define HSTPIPCFG_PBK_3_BANK_Val _U_(0x2) /**< (HSTPIPCFG) Triple-bank pipe */ -#define HSTPIPCFG_PBK_1_BANK (HSTPIPCFG_PBK_1_BANK_Val << HSTPIPCFG_PBK_Pos) /**< (HSTPIPCFG) Single-bank pipe Position */ -#define HSTPIPCFG_PBK_2_BANK (HSTPIPCFG_PBK_2_BANK_Val << HSTPIPCFG_PBK_Pos) /**< (HSTPIPCFG) Double-bank pipe Position */ -#define HSTPIPCFG_PBK_3_BANK (HSTPIPCFG_PBK_3_BANK_Val << HSTPIPCFG_PBK_Pos) /**< (HSTPIPCFG) Triple-bank pipe Position */ -#define HSTPIPCFG_PSIZE_Pos 4 /**< (HSTPIPCFG) Pipe Size Position */ -#define HSTPIPCFG_PSIZE (_U_(0x7) << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) Pipe Size Mask */ -#define HSTPIPCFG_PSIZE_8_BYTE_Val _U_(0x0) /**< (HSTPIPCFG) 8 bytes */ -#define HSTPIPCFG_PSIZE_16_BYTE_Val _U_(0x1) /**< (HSTPIPCFG) 16 bytes */ -#define HSTPIPCFG_PSIZE_32_BYTE_Val _U_(0x2) /**< (HSTPIPCFG) 32 bytes */ -#define HSTPIPCFG_PSIZE_64_BYTE_Val _U_(0x3) /**< (HSTPIPCFG) 64 bytes */ -#define HSTPIPCFG_PSIZE_128_BYTE_Val _U_(0x4) /**< (HSTPIPCFG) 128 bytes */ -#define HSTPIPCFG_PSIZE_256_BYTE_Val _U_(0x5) /**< (HSTPIPCFG) 256 bytes */ -#define HSTPIPCFG_PSIZE_512_BYTE_Val _U_(0x6) /**< (HSTPIPCFG) 512 bytes */ -#define HSTPIPCFG_PSIZE_1024_BYTE_Val _U_(0x7) /**< (HSTPIPCFG) 1024 bytes */ -#define HSTPIPCFG_PSIZE_8_BYTE (HSTPIPCFG_PSIZE_8_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 8 bytes Position */ -#define HSTPIPCFG_PSIZE_16_BYTE (HSTPIPCFG_PSIZE_16_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 16 bytes Position */ -#define HSTPIPCFG_PSIZE_32_BYTE (HSTPIPCFG_PSIZE_32_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 32 bytes Position */ -#define HSTPIPCFG_PSIZE_64_BYTE (HSTPIPCFG_PSIZE_64_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 64 bytes Position */ -#define HSTPIPCFG_PSIZE_128_BYTE (HSTPIPCFG_PSIZE_128_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 128 bytes Position */ -#define HSTPIPCFG_PSIZE_256_BYTE (HSTPIPCFG_PSIZE_256_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 256 bytes Position */ -#define HSTPIPCFG_PSIZE_512_BYTE (HSTPIPCFG_PSIZE_512_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 512 bytes Position */ -#define HSTPIPCFG_PSIZE_1024_BYTE (HSTPIPCFG_PSIZE_1024_BYTE_Val << HSTPIPCFG_PSIZE_Pos) /**< (HSTPIPCFG) 1024 bytes Position */ -#define HSTPIPCFG_PTOKEN_Pos 8 /**< (HSTPIPCFG) Pipe Token Position */ -#define HSTPIPCFG_PTOKEN (_U_(0x3) << HSTPIPCFG_PTOKEN_Pos) /**< (HSTPIPCFG) Pipe Token Mask */ -#define HSTPIPCFG_PTOKEN_SETUP_Val _U_(0x0) /**< (HSTPIPCFG) SETUP */ -#define HSTPIPCFG_PTOKEN_IN_Val _U_(0x1) /**< (HSTPIPCFG) IN */ -#define HSTPIPCFG_PTOKEN_OUT_Val _U_(0x2) /**< (HSTPIPCFG) OUT */ -#define HSTPIPCFG_PTOKEN_SETUP (HSTPIPCFG_PTOKEN_SETUP_Val << HSTPIPCFG_PTOKEN_Pos) /**< (HSTPIPCFG) SETUP Position */ -#define HSTPIPCFG_PTOKEN_IN (HSTPIPCFG_PTOKEN_IN_Val << HSTPIPCFG_PTOKEN_Pos) /**< (HSTPIPCFG) IN Position */ -#define HSTPIPCFG_PTOKEN_OUT (HSTPIPCFG_PTOKEN_OUT_Val << HSTPIPCFG_PTOKEN_Pos) /**< (HSTPIPCFG) OUT Position */ -#define HSTPIPCFG_AUTOSW_Pos 10 /**< (HSTPIPCFG) Automatic Switch Position */ -#define HSTPIPCFG_AUTOSW (_U_(0x1) << HSTPIPCFG_AUTOSW_Pos) /**< (HSTPIPCFG) Automatic Switch Mask */ -#define HSTPIPCFG_PTYPE_Pos 12 /**< (HSTPIPCFG) Pipe Type Position */ -#define HSTPIPCFG_PTYPE (_U_(0x3) << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Pipe Type Mask */ -#define HSTPIPCFG_PTYPE_CTRL_Val _U_(0x0) /**< (HSTPIPCFG) Control */ -#define HSTPIPCFG_PTYPE_ISO_Val _U_(0x1) /**< (HSTPIPCFG) Isochronous */ -#define HSTPIPCFG_PTYPE_BLK_Val _U_(0x2) /**< (HSTPIPCFG) Bulk */ -#define HSTPIPCFG_PTYPE_INTRPT_Val _U_(0x3) /**< (HSTPIPCFG) Interrupt */ -#define HSTPIPCFG_PTYPE_CTRL (HSTPIPCFG_PTYPE_CTRL_Val << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Control Position */ -#define HSTPIPCFG_PTYPE_ISO (HSTPIPCFG_PTYPE_ISO_Val << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Isochronous Position */ -#define HSTPIPCFG_PTYPE_BLK (HSTPIPCFG_PTYPE_BLK_Val << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Bulk Position */ -#define HSTPIPCFG_PTYPE_INTRPT (HSTPIPCFG_PTYPE_INTRPT_Val << HSTPIPCFG_PTYPE_Pos) /**< (HSTPIPCFG) Interrupt Position */ -#define HSTPIPCFG_PEPNUM_Pos 16 /**< (HSTPIPCFG) Pipe Endpoint Number Position */ -#define HSTPIPCFG_PEPNUM (_U_(0xF) << HSTPIPCFG_PEPNUM_Pos) /**< (HSTPIPCFG) Pipe Endpoint Number Mask */ -#define HSTPIPCFG_INTFRQ_Pos 24 /**< (HSTPIPCFG) Pipe Interrupt Request Frequency Position */ -#define HSTPIPCFG_INTFRQ (_U_(0xFF) << HSTPIPCFG_INTFRQ_Pos) /**< (HSTPIPCFG) Pipe Interrupt Request Frequency Mask */ -#define HSTPIPCFG_Msk _U_(0xFF0F377E) /**< (HSTPIPCFG) Register Mask */ - -/* CTRL_BULK mode */ -#define HSTPIPCFG_CTRL_BULK_PINGEN_Pos 20 /**< (HSTPIPCFG) Ping Enable Position */ -#define HSTPIPCFG_CTRL_BULK_PINGEN (_U_(0x1) << HSTPIPCFG_CTRL_BULK_PINGEN_Pos) /**< (HSTPIPCFG) Ping Enable Mask */ -#define HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos 24 /**< (HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Position */ -#define HSTPIPCFG_CTRL_BULK_BINTERVAL (_U_(0xFF) << HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos) /**< (HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Mask */ -#define HSTPIPCFG_CTRL_BULK_Msk _U_(0xFF100000) /**< (HSTPIPCFG_CTRL_BULK) Register Mask */ - -/* -------- HSTPIPISR : (USBHS Offset: 0x530) (R/ 32) Host Pipe Status Register -------- */ - -#define HSTPIPISR_OFFSET (0x530) /**< (HSTPIPISR) Host Pipe Status Register Offset */ - -#define HSTPIPISR_RXINI_Pos 0 /**< (HSTPIPISR) Received IN Data Interrupt Position */ -#define HSTPIPISR_RXINI (_U_(0x1) << HSTPIPISR_RXINI_Pos) /**< (HSTPIPISR) Received IN Data Interrupt Mask */ -#define HSTPIPISR_TXOUTI_Pos 1 /**< (HSTPIPISR) Transmitted OUT Data Interrupt Position */ -#define HSTPIPISR_TXOUTI (_U_(0x1) << HSTPIPISR_TXOUTI_Pos) /**< (HSTPIPISR) Transmitted OUT Data Interrupt Mask */ -#define HSTPIPISR_PERRI_Pos 3 /**< (HSTPIPISR) Pipe Error Interrupt Position */ -#define HSTPIPISR_PERRI (_U_(0x1) << HSTPIPISR_PERRI_Pos) /**< (HSTPIPISR) Pipe Error Interrupt Mask */ -#define HSTPIPISR_NAKEDI_Pos 4 /**< (HSTPIPISR) NAKed Interrupt Position */ -#define HSTPIPISR_NAKEDI (_U_(0x1) << HSTPIPISR_NAKEDI_Pos) /**< (HSTPIPISR) NAKed Interrupt Mask */ -#define HSTPIPISR_OVERFI_Pos 5 /**< (HSTPIPISR) Overflow Interrupt Position */ -#define HSTPIPISR_OVERFI (_U_(0x1) << HSTPIPISR_OVERFI_Pos) /**< (HSTPIPISR) Overflow Interrupt Mask */ -#define HSTPIPISR_SHORTPACKETI_Pos 7 /**< (HSTPIPISR) Short Packet Interrupt Position */ -#define HSTPIPISR_SHORTPACKETI (_U_(0x1) << HSTPIPISR_SHORTPACKETI_Pos) /**< (HSTPIPISR) Short Packet Interrupt Mask */ -#define HSTPIPISR_DTSEQ_Pos 8 /**< (HSTPIPISR) Data Toggle Sequence Position */ -#define HSTPIPISR_DTSEQ (_U_(0x3) << HSTPIPISR_DTSEQ_Pos) /**< (HSTPIPISR) Data Toggle Sequence Mask */ -#define HSTPIPISR_DTSEQ_DATA0_Val _U_(0x0) /**< (HSTPIPISR) Data0 toggle sequence */ -#define HSTPIPISR_DTSEQ_DATA1_Val _U_(0x1) /**< (HSTPIPISR) Data1 toggle sequence */ -#define HSTPIPISR_DTSEQ_DATA0 (HSTPIPISR_DTSEQ_DATA0_Val << HSTPIPISR_DTSEQ_Pos) /**< (HSTPIPISR) Data0 toggle sequence Position */ -#define HSTPIPISR_DTSEQ_DATA1 (HSTPIPISR_DTSEQ_DATA1_Val << HSTPIPISR_DTSEQ_Pos) /**< (HSTPIPISR) Data1 toggle sequence Position */ -#define HSTPIPISR_NBUSYBK_Pos 12 /**< (HSTPIPISR) Number of Busy Banks Position */ -#define HSTPIPISR_NBUSYBK (_U_(0x3) << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) Number of Busy Banks Mask */ -#define HSTPIPISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (HSTPIPISR) 0 busy bank (all banks free) */ -#define HSTPIPISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (HSTPIPISR) 1 busy bank */ -#define HSTPIPISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (HSTPIPISR) 2 busy banks */ -#define HSTPIPISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (HSTPIPISR) 3 busy banks */ -#define HSTPIPISR_NBUSYBK_0_BUSY (HSTPIPISR_NBUSYBK_0_BUSY_Val << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) 0 busy bank (all banks free) Position */ -#define HSTPIPISR_NBUSYBK_1_BUSY (HSTPIPISR_NBUSYBK_1_BUSY_Val << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) 1 busy bank Position */ -#define HSTPIPISR_NBUSYBK_2_BUSY (HSTPIPISR_NBUSYBK_2_BUSY_Val << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) 2 busy banks Position */ -#define HSTPIPISR_NBUSYBK_3_BUSY (HSTPIPISR_NBUSYBK_3_BUSY_Val << HSTPIPISR_NBUSYBK_Pos) /**< (HSTPIPISR) 3 busy banks Position */ -#define HSTPIPISR_CURRBK_Pos 14 /**< (HSTPIPISR) Current Bank Position */ -#define HSTPIPISR_CURRBK (_U_(0x3) << HSTPIPISR_CURRBK_Pos) /**< (HSTPIPISR) Current Bank Mask */ -#define HSTPIPISR_CURRBK_BANK0_Val _U_(0x0) /**< (HSTPIPISR) Current bank is bank0 */ -#define HSTPIPISR_CURRBK_BANK1_Val _U_(0x1) /**< (HSTPIPISR) Current bank is bank1 */ -#define HSTPIPISR_CURRBK_BANK2_Val _U_(0x2) /**< (HSTPIPISR) Current bank is bank2 */ -#define HSTPIPISR_CURRBK_BANK0 (HSTPIPISR_CURRBK_BANK0_Val << HSTPIPISR_CURRBK_Pos) /**< (HSTPIPISR) Current bank is bank0 Position */ -#define HSTPIPISR_CURRBK_BANK1 (HSTPIPISR_CURRBK_BANK1_Val << HSTPIPISR_CURRBK_Pos) /**< (HSTPIPISR) Current bank is bank1 Position */ -#define HSTPIPISR_CURRBK_BANK2 (HSTPIPISR_CURRBK_BANK2_Val << HSTPIPISR_CURRBK_Pos) /**< (HSTPIPISR) Current bank is bank2 Position */ -#define HSTPIPISR_RWALL_Pos 16 /**< (HSTPIPISR) Read/Write Allowed Position */ -#define HSTPIPISR_RWALL (_U_(0x1) << HSTPIPISR_RWALL_Pos) /**< (HSTPIPISR) Read/Write Allowed Mask */ -#define HSTPIPISR_CFGOK_Pos 18 /**< (HSTPIPISR) Configuration OK Status Position */ -#define HSTPIPISR_CFGOK (_U_(0x1) << HSTPIPISR_CFGOK_Pos) /**< (HSTPIPISR) Configuration OK Status Mask */ -#define HSTPIPISR_PBYCT_Pos 20 /**< (HSTPIPISR) Pipe Byte Count Position */ -#define HSTPIPISR_PBYCT (_U_(0x7FF) << HSTPIPISR_PBYCT_Pos) /**< (HSTPIPISR) Pipe Byte Count Mask */ -#define HSTPIPISR_Msk _U_(0x7FF5F3BB) /**< (HSTPIPISR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPISR_CTRL_TXSTPI_Pos 2 /**< (HSTPIPISR) Transmitted SETUP Interrupt Position */ -#define HSTPIPISR_CTRL_TXSTPI (_U_(0x1) << HSTPIPISR_CTRL_TXSTPI_Pos) /**< (HSTPIPISR) Transmitted SETUP Interrupt Mask */ -#define HSTPIPISR_CTRL_RXSTALLDI_Pos 6 /**< (HSTPIPISR) Received STALLed Interrupt Position */ -#define HSTPIPISR_CTRL_RXSTALLDI (_U_(0x1) << HSTPIPISR_CTRL_RXSTALLDI_Pos) /**< (HSTPIPISR) Received STALLed Interrupt Mask */ -#define HSTPIPISR_CTRL_Msk _U_(0x44) /**< (HSTPIPISR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPISR_ISO_UNDERFI_Pos 2 /**< (HSTPIPISR) Underflow Interrupt Position */ -#define HSTPIPISR_ISO_UNDERFI (_U_(0x1) << HSTPIPISR_ISO_UNDERFI_Pos) /**< (HSTPIPISR) Underflow Interrupt Mask */ -#define HSTPIPISR_ISO_CRCERRI_Pos 6 /**< (HSTPIPISR) CRC Error Interrupt Position */ -#define HSTPIPISR_ISO_CRCERRI (_U_(0x1) << HSTPIPISR_ISO_CRCERRI_Pos) /**< (HSTPIPISR) CRC Error Interrupt Mask */ -#define HSTPIPISR_ISO_Msk _U_(0x44) /**< (HSTPIPISR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPISR_BLK_TXSTPI_Pos 2 /**< (HSTPIPISR) Transmitted SETUP Interrupt Position */ -#define HSTPIPISR_BLK_TXSTPI (_U_(0x1) << HSTPIPISR_BLK_TXSTPI_Pos) /**< (HSTPIPISR) Transmitted SETUP Interrupt Mask */ -#define HSTPIPISR_BLK_RXSTALLDI_Pos 6 /**< (HSTPIPISR) Received STALLed Interrupt Position */ -#define HSTPIPISR_BLK_RXSTALLDI (_U_(0x1) << HSTPIPISR_BLK_RXSTALLDI_Pos) /**< (HSTPIPISR) Received STALLed Interrupt Mask */ -#define HSTPIPISR_BLK_Msk _U_(0x44) /**< (HSTPIPISR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPISR_INTRPT_UNDERFI_Pos 2 /**< (HSTPIPISR) Underflow Interrupt Position */ -#define HSTPIPISR_INTRPT_UNDERFI (_U_(0x1) << HSTPIPISR_INTRPT_UNDERFI_Pos) /**< (HSTPIPISR) Underflow Interrupt Mask */ -#define HSTPIPISR_INTRPT_RXSTALLDI_Pos 6 /**< (HSTPIPISR) Received STALLed Interrupt Position */ -#define HSTPIPISR_INTRPT_RXSTALLDI (_U_(0x1) << HSTPIPISR_INTRPT_RXSTALLDI_Pos) /**< (HSTPIPISR) Received STALLed Interrupt Mask */ -#define HSTPIPISR_INTRPT_Msk _U_(0x44) /**< (HSTPIPISR_INTRPT) Register Mask */ - -/* -------- HSTPIPICR : (USBHS Offset: 0x560) (/W 32) Host Pipe Clear Register -------- */ - -#define HSTPIPICR_OFFSET (0x560) /**< (HSTPIPICR) Host Pipe Clear Register Offset */ - -#define HSTPIPICR_RXINIC_Pos 0 /**< (HSTPIPICR) Received IN Data Interrupt Clear Position */ -#define HSTPIPICR_RXINIC (_U_(0x1) << HSTPIPICR_RXINIC_Pos) /**< (HSTPIPICR) Received IN Data Interrupt Clear Mask */ -#define HSTPIPICR_TXOUTIC_Pos 1 /**< (HSTPIPICR) Transmitted OUT Data Interrupt Clear Position */ -#define HSTPIPICR_TXOUTIC (_U_(0x1) << HSTPIPICR_TXOUTIC_Pos) /**< (HSTPIPICR) Transmitted OUT Data Interrupt Clear Mask */ -#define HSTPIPICR_NAKEDIC_Pos 4 /**< (HSTPIPICR) NAKed Interrupt Clear Position */ -#define HSTPIPICR_NAKEDIC (_U_(0x1) << HSTPIPICR_NAKEDIC_Pos) /**< (HSTPIPICR) NAKed Interrupt Clear Mask */ -#define HSTPIPICR_OVERFIC_Pos 5 /**< (HSTPIPICR) Overflow Interrupt Clear Position */ -#define HSTPIPICR_OVERFIC (_U_(0x1) << HSTPIPICR_OVERFIC_Pos) /**< (HSTPIPICR) Overflow Interrupt Clear Mask */ -#define HSTPIPICR_SHORTPACKETIC_Pos 7 /**< (HSTPIPICR) Short Packet Interrupt Clear Position */ -#define HSTPIPICR_SHORTPACKETIC (_U_(0x1) << HSTPIPICR_SHORTPACKETIC_Pos) /**< (HSTPIPICR) Short Packet Interrupt Clear Mask */ -#define HSTPIPICR_Msk _U_(0xB3) /**< (HSTPIPICR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPICR_CTRL_TXSTPIC_Pos 2 /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ -#define HSTPIPICR_CTRL_TXSTPIC (_U_(0x1) << HSTPIPICR_CTRL_TXSTPIC_Pos) /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ -#define HSTPIPICR_CTRL_RXSTALLDIC_Pos 6 /**< (HSTPIPICR) Received STALLed Interrupt Clear Position */ -#define HSTPIPICR_CTRL_RXSTALLDIC (_U_(0x1) << HSTPIPICR_CTRL_RXSTALLDIC_Pos) /**< (HSTPIPICR) Received STALLed Interrupt Clear Mask */ -#define HSTPIPICR_CTRL_Msk _U_(0x44) /**< (HSTPIPICR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPICR_ISO_UNDERFIC_Pos 2 /**< (HSTPIPICR) Underflow Interrupt Clear Position */ -#define HSTPIPICR_ISO_UNDERFIC (_U_(0x1) << HSTPIPICR_ISO_UNDERFIC_Pos) /**< (HSTPIPICR) Underflow Interrupt Clear Mask */ -#define HSTPIPICR_ISO_CRCERRIC_Pos 6 /**< (HSTPIPICR) CRC Error Interrupt Clear Position */ -#define HSTPIPICR_ISO_CRCERRIC (_U_(0x1) << HSTPIPICR_ISO_CRCERRIC_Pos) /**< (HSTPIPICR) CRC Error Interrupt Clear Mask */ -#define HSTPIPICR_ISO_Msk _U_(0x44) /**< (HSTPIPICR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPICR_BLK_TXSTPIC_Pos 2 /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ -#define HSTPIPICR_BLK_TXSTPIC (_U_(0x1) << HSTPIPICR_BLK_TXSTPIC_Pos) /**< (HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ -#define HSTPIPICR_BLK_RXSTALLDIC_Pos 6 /**< (HSTPIPICR) Received STALLed Interrupt Clear Position */ -#define HSTPIPICR_BLK_RXSTALLDIC (_U_(0x1) << HSTPIPICR_BLK_RXSTALLDIC_Pos) /**< (HSTPIPICR) Received STALLed Interrupt Clear Mask */ -#define HSTPIPICR_BLK_Msk _U_(0x44) /**< (HSTPIPICR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPICR_INTRPT_UNDERFIC_Pos 2 /**< (HSTPIPICR) Underflow Interrupt Clear Position */ -#define HSTPIPICR_INTRPT_UNDERFIC (_U_(0x1) << HSTPIPICR_INTRPT_UNDERFIC_Pos) /**< (HSTPIPICR) Underflow Interrupt Clear Mask */ -#define HSTPIPICR_INTRPT_RXSTALLDIC_Pos 6 /**< (HSTPIPICR) Received STALLed Interrupt Clear Position */ -#define HSTPIPICR_INTRPT_RXSTALLDIC (_U_(0x1) << HSTPIPICR_INTRPT_RXSTALLDIC_Pos) /**< (HSTPIPICR) Received STALLed Interrupt Clear Mask */ -#define HSTPIPICR_INTRPT_Msk _U_(0x44) /**< (HSTPIPICR_INTRPT) Register Mask */ - -/* -------- HSTPIPIFR : (USBHS Offset: 0x590) (/W 32) Host Pipe Set Register -------- */ - -#define HSTPIPIFR_OFFSET (0x590) /**< (HSTPIPIFR) Host Pipe Set Register Offset */ - -#define HSTPIPIFR_RXINIS_Pos 0 /**< (HSTPIPIFR) Received IN Data Interrupt Set Position */ -#define HSTPIPIFR_RXINIS (_U_(0x1) << HSTPIPIFR_RXINIS_Pos) /**< (HSTPIPIFR) Received IN Data Interrupt Set Mask */ -#define HSTPIPIFR_TXOUTIS_Pos 1 /**< (HSTPIPIFR) Transmitted OUT Data Interrupt Set Position */ -#define HSTPIPIFR_TXOUTIS (_U_(0x1) << HSTPIPIFR_TXOUTIS_Pos) /**< (HSTPIPIFR) Transmitted OUT Data Interrupt Set Mask */ -#define HSTPIPIFR_PERRIS_Pos 3 /**< (HSTPIPIFR) Pipe Error Interrupt Set Position */ -#define HSTPIPIFR_PERRIS (_U_(0x1) << HSTPIPIFR_PERRIS_Pos) /**< (HSTPIPIFR) Pipe Error Interrupt Set Mask */ -#define HSTPIPIFR_NAKEDIS_Pos 4 /**< (HSTPIPIFR) NAKed Interrupt Set Position */ -#define HSTPIPIFR_NAKEDIS (_U_(0x1) << HSTPIPIFR_NAKEDIS_Pos) /**< (HSTPIPIFR) NAKed Interrupt Set Mask */ -#define HSTPIPIFR_OVERFIS_Pos 5 /**< (HSTPIPIFR) Overflow Interrupt Set Position */ -#define HSTPIPIFR_OVERFIS (_U_(0x1) << HSTPIPIFR_OVERFIS_Pos) /**< (HSTPIPIFR) Overflow Interrupt Set Mask */ -#define HSTPIPIFR_SHORTPACKETIS_Pos 7 /**< (HSTPIPIFR) Short Packet Interrupt Set Position */ -#define HSTPIPIFR_SHORTPACKETIS (_U_(0x1) << HSTPIPIFR_SHORTPACKETIS_Pos) /**< (HSTPIPIFR) Short Packet Interrupt Set Mask */ -#define HSTPIPIFR_NBUSYBKS_Pos 12 /**< (HSTPIPIFR) Number of Busy Banks Set Position */ -#define HSTPIPIFR_NBUSYBKS (_U_(0x1) << HSTPIPIFR_NBUSYBKS_Pos) /**< (HSTPIPIFR) Number of Busy Banks Set Mask */ -#define HSTPIPIFR_Msk _U_(0x10BB) /**< (HSTPIPIFR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPIFR_CTRL_TXSTPIS_Pos 2 /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ -#define HSTPIPIFR_CTRL_TXSTPIS (_U_(0x1) << HSTPIPIFR_CTRL_TXSTPIS_Pos) /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ -#define HSTPIPIFR_CTRL_RXSTALLDIS_Pos 6 /**< (HSTPIPIFR) Received STALLed Interrupt Set Position */ -#define HSTPIPIFR_CTRL_RXSTALLDIS (_U_(0x1) << HSTPIPIFR_CTRL_RXSTALLDIS_Pos) /**< (HSTPIPIFR) Received STALLed Interrupt Set Mask */ -#define HSTPIPIFR_CTRL_Msk _U_(0x44) /**< (HSTPIPIFR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPIFR_ISO_UNDERFIS_Pos 2 /**< (HSTPIPIFR) Underflow Interrupt Set Position */ -#define HSTPIPIFR_ISO_UNDERFIS (_U_(0x1) << HSTPIPIFR_ISO_UNDERFIS_Pos) /**< (HSTPIPIFR) Underflow Interrupt Set Mask */ -#define HSTPIPIFR_ISO_CRCERRIS_Pos 6 /**< (HSTPIPIFR) CRC Error Interrupt Set Position */ -#define HSTPIPIFR_ISO_CRCERRIS (_U_(0x1) << HSTPIPIFR_ISO_CRCERRIS_Pos) /**< (HSTPIPIFR) CRC Error Interrupt Set Mask */ -#define HSTPIPIFR_ISO_Msk _U_(0x44) /**< (HSTPIPIFR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPIFR_BLK_TXSTPIS_Pos 2 /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ -#define HSTPIPIFR_BLK_TXSTPIS (_U_(0x1) << HSTPIPIFR_BLK_TXSTPIS_Pos) /**< (HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ -#define HSTPIPIFR_BLK_RXSTALLDIS_Pos 6 /**< (HSTPIPIFR) Received STALLed Interrupt Set Position */ -#define HSTPIPIFR_BLK_RXSTALLDIS (_U_(0x1) << HSTPIPIFR_BLK_RXSTALLDIS_Pos) /**< (HSTPIPIFR) Received STALLed Interrupt Set Mask */ -#define HSTPIPIFR_BLK_Msk _U_(0x44) /**< (HSTPIPIFR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPIFR_INTRPT_UNDERFIS_Pos 2 /**< (HSTPIPIFR) Underflow Interrupt Set Position */ -#define HSTPIPIFR_INTRPT_UNDERFIS (_U_(0x1) << HSTPIPIFR_INTRPT_UNDERFIS_Pos) /**< (HSTPIPIFR) Underflow Interrupt Set Mask */ -#define HSTPIPIFR_INTRPT_RXSTALLDIS_Pos 6 /**< (HSTPIPIFR) Received STALLed Interrupt Set Position */ -#define HSTPIPIFR_INTRPT_RXSTALLDIS (_U_(0x1) << HSTPIPIFR_INTRPT_RXSTALLDIS_Pos) /**< (HSTPIPIFR) Received STALLed Interrupt Set Mask */ -#define HSTPIPIFR_INTRPT_Msk _U_(0x44) /**< (HSTPIPIFR_INTRPT) Register Mask */ - -/* -------- HSTPIPIMR : (USBHS Offset: 0x5c0) (R/ 32) Host Pipe Mask Register -------- */ - -#define HSTPIPIMR_OFFSET (0x5C0) /**< (HSTPIPIMR) Host Pipe Mask Register Offset */ - -#define HSTPIPIMR_RXINE_Pos 0 /**< (HSTPIPIMR) Received IN Data Interrupt Enable Position */ -#define HSTPIPIMR_RXINE (_U_(0x1) << HSTPIPIMR_RXINE_Pos) /**< (HSTPIPIMR) Received IN Data Interrupt Enable Mask */ -#define HSTPIPIMR_TXOUTE_Pos 1 /**< (HSTPIPIMR) Transmitted OUT Data Interrupt Enable Position */ -#define HSTPIPIMR_TXOUTE (_U_(0x1) << HSTPIPIMR_TXOUTE_Pos) /**< (HSTPIPIMR) Transmitted OUT Data Interrupt Enable Mask */ -#define HSTPIPIMR_PERRE_Pos 3 /**< (HSTPIPIMR) Pipe Error Interrupt Enable Position */ -#define HSTPIPIMR_PERRE (_U_(0x1) << HSTPIPIMR_PERRE_Pos) /**< (HSTPIPIMR) Pipe Error Interrupt Enable Mask */ -#define HSTPIPIMR_NAKEDE_Pos 4 /**< (HSTPIPIMR) NAKed Interrupt Enable Position */ -#define HSTPIPIMR_NAKEDE (_U_(0x1) << HSTPIPIMR_NAKEDE_Pos) /**< (HSTPIPIMR) NAKed Interrupt Enable Mask */ -#define HSTPIPIMR_OVERFIE_Pos 5 /**< (HSTPIPIMR) Overflow Interrupt Enable Position */ -#define HSTPIPIMR_OVERFIE (_U_(0x1) << HSTPIPIMR_OVERFIE_Pos) /**< (HSTPIPIMR) Overflow Interrupt Enable Mask */ -#define HSTPIPIMR_SHORTPACKETIE_Pos 7 /**< (HSTPIPIMR) Short Packet Interrupt Enable Position */ -#define HSTPIPIMR_SHORTPACKETIE (_U_(0x1) << HSTPIPIMR_SHORTPACKETIE_Pos) /**< (HSTPIPIMR) Short Packet Interrupt Enable Mask */ -#define HSTPIPIMR_NBUSYBKE_Pos 12 /**< (HSTPIPIMR) Number of Busy Banks Interrupt Enable Position */ -#define HSTPIPIMR_NBUSYBKE (_U_(0x1) << HSTPIPIMR_NBUSYBKE_Pos) /**< (HSTPIPIMR) Number of Busy Banks Interrupt Enable Mask */ -#define HSTPIPIMR_FIFOCON_Pos 14 /**< (HSTPIPIMR) FIFO Control Position */ -#define HSTPIPIMR_FIFOCON (_U_(0x1) << HSTPIPIMR_FIFOCON_Pos) /**< (HSTPIPIMR) FIFO Control Mask */ -#define HSTPIPIMR_PDISHDMA_Pos 16 /**< (HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Position */ -#define HSTPIPIMR_PDISHDMA (_U_(0x1) << HSTPIPIMR_PDISHDMA_Pos) /**< (HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Mask */ -#define HSTPIPIMR_PFREEZE_Pos 17 /**< (HSTPIPIMR) Pipe Freeze Position */ -#define HSTPIPIMR_PFREEZE (_U_(0x1) << HSTPIPIMR_PFREEZE_Pos) /**< (HSTPIPIMR) Pipe Freeze Mask */ -#define HSTPIPIMR_RSTDT_Pos 18 /**< (HSTPIPIMR) Reset Data Toggle Position */ -#define HSTPIPIMR_RSTDT (_U_(0x1) << HSTPIPIMR_RSTDT_Pos) /**< (HSTPIPIMR) Reset Data Toggle Mask */ -#define HSTPIPIMR_Msk _U_(0x750BB) /**< (HSTPIPIMR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPIMR_CTRL_TXSTPE_Pos 2 /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ -#define HSTPIPIMR_CTRL_TXSTPE (_U_(0x1) << HSTPIPIMR_CTRL_TXSTPE_Pos) /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ -#define HSTPIPIMR_CTRL_RXSTALLDE_Pos 6 /**< (HSTPIPIMR) Received STALLed Interrupt Enable Position */ -#define HSTPIPIMR_CTRL_RXSTALLDE (_U_(0x1) << HSTPIPIMR_CTRL_RXSTALLDE_Pos) /**< (HSTPIPIMR) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIMR_CTRL_Msk _U_(0x44) /**< (HSTPIPIMR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPIMR_ISO_UNDERFIE_Pos 2 /**< (HSTPIPIMR) Underflow Interrupt Enable Position */ -#define HSTPIPIMR_ISO_UNDERFIE (_U_(0x1) << HSTPIPIMR_ISO_UNDERFIE_Pos) /**< (HSTPIPIMR) Underflow Interrupt Enable Mask */ -#define HSTPIPIMR_ISO_CRCERRE_Pos 6 /**< (HSTPIPIMR) CRC Error Interrupt Enable Position */ -#define HSTPIPIMR_ISO_CRCERRE (_U_(0x1) << HSTPIPIMR_ISO_CRCERRE_Pos) /**< (HSTPIPIMR) CRC Error Interrupt Enable Mask */ -#define HSTPIPIMR_ISO_Msk _U_(0x44) /**< (HSTPIPIMR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPIMR_BLK_TXSTPE_Pos 2 /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ -#define HSTPIPIMR_BLK_TXSTPE (_U_(0x1) << HSTPIPIMR_BLK_TXSTPE_Pos) /**< (HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ -#define HSTPIPIMR_BLK_RXSTALLDE_Pos 6 /**< (HSTPIPIMR) Received STALLed Interrupt Enable Position */ -#define HSTPIPIMR_BLK_RXSTALLDE (_U_(0x1) << HSTPIPIMR_BLK_RXSTALLDE_Pos) /**< (HSTPIPIMR) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIMR_BLK_Msk _U_(0x44) /**< (HSTPIPIMR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPIMR_INTRPT_UNDERFIE_Pos 2 /**< (HSTPIPIMR) Underflow Interrupt Enable Position */ -#define HSTPIPIMR_INTRPT_UNDERFIE (_U_(0x1) << HSTPIPIMR_INTRPT_UNDERFIE_Pos) /**< (HSTPIPIMR) Underflow Interrupt Enable Mask */ -#define HSTPIPIMR_INTRPT_RXSTALLDE_Pos 6 /**< (HSTPIPIMR) Received STALLed Interrupt Enable Position */ -#define HSTPIPIMR_INTRPT_RXSTALLDE (_U_(0x1) << HSTPIPIMR_INTRPT_RXSTALLDE_Pos) /**< (HSTPIPIMR) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIMR_INTRPT_Msk _U_(0x44) /**< (HSTPIPIMR_INTRPT) Register Mask */ - -/* -------- HSTPIPIER : (USBHS Offset: 0x5f0) (/W 32) Host Pipe Enable Register -------- */ - -#define HSTPIPIER_OFFSET (0x5F0) /**< (HSTPIPIER) Host Pipe Enable Register Offset */ - -#define HSTPIPIER_RXINES_Pos 0 /**< (HSTPIPIER) Received IN Data Interrupt Enable Position */ -#define HSTPIPIER_RXINES (_U_(0x1) << HSTPIPIER_RXINES_Pos) /**< (HSTPIPIER) Received IN Data Interrupt Enable Mask */ -#define HSTPIPIER_TXOUTES_Pos 1 /**< (HSTPIPIER) Transmitted OUT Data Interrupt Enable Position */ -#define HSTPIPIER_TXOUTES (_U_(0x1) << HSTPIPIER_TXOUTES_Pos) /**< (HSTPIPIER) Transmitted OUT Data Interrupt Enable Mask */ -#define HSTPIPIER_PERRES_Pos 3 /**< (HSTPIPIER) Pipe Error Interrupt Enable Position */ -#define HSTPIPIER_PERRES (_U_(0x1) << HSTPIPIER_PERRES_Pos) /**< (HSTPIPIER) Pipe Error Interrupt Enable Mask */ -#define HSTPIPIER_NAKEDES_Pos 4 /**< (HSTPIPIER) NAKed Interrupt Enable Position */ -#define HSTPIPIER_NAKEDES (_U_(0x1) << HSTPIPIER_NAKEDES_Pos) /**< (HSTPIPIER) NAKed Interrupt Enable Mask */ -#define HSTPIPIER_OVERFIES_Pos 5 /**< (HSTPIPIER) Overflow Interrupt Enable Position */ -#define HSTPIPIER_OVERFIES (_U_(0x1) << HSTPIPIER_OVERFIES_Pos) /**< (HSTPIPIER) Overflow Interrupt Enable Mask */ -#define HSTPIPIER_SHORTPACKETIES_Pos 7 /**< (HSTPIPIER) Short Packet Interrupt Enable Position */ -#define HSTPIPIER_SHORTPACKETIES (_U_(0x1) << HSTPIPIER_SHORTPACKETIES_Pos) /**< (HSTPIPIER) Short Packet Interrupt Enable Mask */ -#define HSTPIPIER_NBUSYBKES_Pos 12 /**< (HSTPIPIER) Number of Busy Banks Enable Position */ -#define HSTPIPIER_NBUSYBKES (_U_(0x1) << HSTPIPIER_NBUSYBKES_Pos) /**< (HSTPIPIER) Number of Busy Banks Enable Mask */ -#define HSTPIPIER_PDISHDMAS_Pos 16 /**< (HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Position */ -#define HSTPIPIER_PDISHDMAS (_U_(0x1) << HSTPIPIER_PDISHDMAS_Pos) /**< (HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Mask */ -#define HSTPIPIER_PFREEZES_Pos 17 /**< (HSTPIPIER) Pipe Freeze Enable Position */ -#define HSTPIPIER_PFREEZES (_U_(0x1) << HSTPIPIER_PFREEZES_Pos) /**< (HSTPIPIER) Pipe Freeze Enable Mask */ -#define HSTPIPIER_RSTDTS_Pos 18 /**< (HSTPIPIER) Reset Data Toggle Enable Position */ -#define HSTPIPIER_RSTDTS (_U_(0x1) << HSTPIPIER_RSTDTS_Pos) /**< (HSTPIPIER) Reset Data Toggle Enable Mask */ -#define HSTPIPIER_Msk _U_(0x710BB) /**< (HSTPIPIER) Register Mask */ - -/* CTRL mode */ -#define HSTPIPIER_CTRL_TXSTPES_Pos 2 /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ -#define HSTPIPIER_CTRL_TXSTPES (_U_(0x1) << HSTPIPIER_CTRL_TXSTPES_Pos) /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ -#define HSTPIPIER_CTRL_RXSTALLDES_Pos 6 /**< (HSTPIPIER) Received STALLed Interrupt Enable Position */ -#define HSTPIPIER_CTRL_RXSTALLDES (_U_(0x1) << HSTPIPIER_CTRL_RXSTALLDES_Pos) /**< (HSTPIPIER) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIER_CTRL_Msk _U_(0x44) /**< (HSTPIPIER_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPIER_ISO_UNDERFIES_Pos 2 /**< (HSTPIPIER) Underflow Interrupt Enable Position */ -#define HSTPIPIER_ISO_UNDERFIES (_U_(0x1) << HSTPIPIER_ISO_UNDERFIES_Pos) /**< (HSTPIPIER) Underflow Interrupt Enable Mask */ -#define HSTPIPIER_ISO_CRCERRES_Pos 6 /**< (HSTPIPIER) CRC Error Interrupt Enable Position */ -#define HSTPIPIER_ISO_CRCERRES (_U_(0x1) << HSTPIPIER_ISO_CRCERRES_Pos) /**< (HSTPIPIER) CRC Error Interrupt Enable Mask */ -#define HSTPIPIER_ISO_Msk _U_(0x44) /**< (HSTPIPIER_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPIER_BLK_TXSTPES_Pos 2 /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ -#define HSTPIPIER_BLK_TXSTPES (_U_(0x1) << HSTPIPIER_BLK_TXSTPES_Pos) /**< (HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ -#define HSTPIPIER_BLK_RXSTALLDES_Pos 6 /**< (HSTPIPIER) Received STALLed Interrupt Enable Position */ -#define HSTPIPIER_BLK_RXSTALLDES (_U_(0x1) << HSTPIPIER_BLK_RXSTALLDES_Pos) /**< (HSTPIPIER) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIER_BLK_Msk _U_(0x44) /**< (HSTPIPIER_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPIER_INTRPT_UNDERFIES_Pos 2 /**< (HSTPIPIER) Underflow Interrupt Enable Position */ -#define HSTPIPIER_INTRPT_UNDERFIES (_U_(0x1) << HSTPIPIER_INTRPT_UNDERFIES_Pos) /**< (HSTPIPIER) Underflow Interrupt Enable Mask */ -#define HSTPIPIER_INTRPT_RXSTALLDES_Pos 6 /**< (HSTPIPIER) Received STALLed Interrupt Enable Position */ -#define HSTPIPIER_INTRPT_RXSTALLDES (_U_(0x1) << HSTPIPIER_INTRPT_RXSTALLDES_Pos) /**< (HSTPIPIER) Received STALLed Interrupt Enable Mask */ -#define HSTPIPIER_INTRPT_Msk _U_(0x44) /**< (HSTPIPIER_INTRPT) Register Mask */ - -/* -------- HSTPIPIDR : (USBHS Offset: 0x620) (/W 32) Host Pipe Disable Register -------- */ - -#define HSTPIPIDR_OFFSET (0x620) /**< (HSTPIPIDR) Host Pipe Disable Register Offset */ - -#define HSTPIPIDR_RXINEC_Pos 0 /**< (HSTPIPIDR) Received IN Data Interrupt Disable Position */ -#define HSTPIPIDR_RXINEC (_U_(0x1) << HSTPIPIDR_RXINEC_Pos) /**< (HSTPIPIDR) Received IN Data Interrupt Disable Mask */ -#define HSTPIPIDR_TXOUTEC_Pos 1 /**< (HSTPIPIDR) Transmitted OUT Data Interrupt Disable Position */ -#define HSTPIPIDR_TXOUTEC (_U_(0x1) << HSTPIPIDR_TXOUTEC_Pos) /**< (HSTPIPIDR) Transmitted OUT Data Interrupt Disable Mask */ -#define HSTPIPIDR_PERREC_Pos 3 /**< (HSTPIPIDR) Pipe Error Interrupt Disable Position */ -#define HSTPIPIDR_PERREC (_U_(0x1) << HSTPIPIDR_PERREC_Pos) /**< (HSTPIPIDR) Pipe Error Interrupt Disable Mask */ -#define HSTPIPIDR_NAKEDEC_Pos 4 /**< (HSTPIPIDR) NAKed Interrupt Disable Position */ -#define HSTPIPIDR_NAKEDEC (_U_(0x1) << HSTPIPIDR_NAKEDEC_Pos) /**< (HSTPIPIDR) NAKed Interrupt Disable Mask */ -#define HSTPIPIDR_OVERFIEC_Pos 5 /**< (HSTPIPIDR) Overflow Interrupt Disable Position */ -#define HSTPIPIDR_OVERFIEC (_U_(0x1) << HSTPIPIDR_OVERFIEC_Pos) /**< (HSTPIPIDR) Overflow Interrupt Disable Mask */ -#define HSTPIPIDR_SHORTPACKETIEC_Pos 7 /**< (HSTPIPIDR) Short Packet Interrupt Disable Position */ -#define HSTPIPIDR_SHORTPACKETIEC (_U_(0x1) << HSTPIPIDR_SHORTPACKETIEC_Pos) /**< (HSTPIPIDR) Short Packet Interrupt Disable Mask */ -#define HSTPIPIDR_NBUSYBKEC_Pos 12 /**< (HSTPIPIDR) Number of Busy Banks Disable Position */ -#define HSTPIPIDR_NBUSYBKEC (_U_(0x1) << HSTPIPIDR_NBUSYBKEC_Pos) /**< (HSTPIPIDR) Number of Busy Banks Disable Mask */ -#define HSTPIPIDR_FIFOCONC_Pos 14 /**< (HSTPIPIDR) FIFO Control Disable Position */ -#define HSTPIPIDR_FIFOCONC (_U_(0x1) << HSTPIPIDR_FIFOCONC_Pos) /**< (HSTPIPIDR) FIFO Control Disable Mask */ -#define HSTPIPIDR_PDISHDMAC_Pos 16 /**< (HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Position */ -#define HSTPIPIDR_PDISHDMAC (_U_(0x1) << HSTPIPIDR_PDISHDMAC_Pos) /**< (HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Mask */ -#define HSTPIPIDR_PFREEZEC_Pos 17 /**< (HSTPIPIDR) Pipe Freeze Disable Position */ -#define HSTPIPIDR_PFREEZEC (_U_(0x1) << HSTPIPIDR_PFREEZEC_Pos) /**< (HSTPIPIDR) Pipe Freeze Disable Mask */ -#define HSTPIPIDR_Msk _U_(0x350BB) /**< (HSTPIPIDR) Register Mask */ - -/* CTRL mode */ -#define HSTPIPIDR_CTRL_TXSTPEC_Pos 2 /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ -#define HSTPIPIDR_CTRL_TXSTPEC (_U_(0x1) << HSTPIPIDR_CTRL_TXSTPEC_Pos) /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ -#define HSTPIPIDR_CTRL_RXSTALLDEC_Pos 6 /**< (HSTPIPIDR) Received STALLed Interrupt Disable Position */ -#define HSTPIPIDR_CTRL_RXSTALLDEC (_U_(0x1) << HSTPIPIDR_CTRL_RXSTALLDEC_Pos) /**< (HSTPIPIDR) Received STALLed Interrupt Disable Mask */ -#define HSTPIPIDR_CTRL_Msk _U_(0x44) /**< (HSTPIPIDR_CTRL) Register Mask */ - -/* ISO mode */ -#define HSTPIPIDR_ISO_UNDERFIEC_Pos 2 /**< (HSTPIPIDR) Underflow Interrupt Disable Position */ -#define HSTPIPIDR_ISO_UNDERFIEC (_U_(0x1) << HSTPIPIDR_ISO_UNDERFIEC_Pos) /**< (HSTPIPIDR) Underflow Interrupt Disable Mask */ -#define HSTPIPIDR_ISO_CRCERREC_Pos 6 /**< (HSTPIPIDR) CRC Error Interrupt Disable Position */ -#define HSTPIPIDR_ISO_CRCERREC (_U_(0x1) << HSTPIPIDR_ISO_CRCERREC_Pos) /**< (HSTPIPIDR) CRC Error Interrupt Disable Mask */ -#define HSTPIPIDR_ISO_Msk _U_(0x44) /**< (HSTPIPIDR_ISO) Register Mask */ - -/* BLK mode */ -#define HSTPIPIDR_BLK_TXSTPEC_Pos 2 /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ -#define HSTPIPIDR_BLK_TXSTPEC (_U_(0x1) << HSTPIPIDR_BLK_TXSTPEC_Pos) /**< (HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ -#define HSTPIPIDR_BLK_RXSTALLDEC_Pos 6 /**< (HSTPIPIDR) Received STALLed Interrupt Disable Position */ -#define HSTPIPIDR_BLK_RXSTALLDEC (_U_(0x1) << HSTPIPIDR_BLK_RXSTALLDEC_Pos) /**< (HSTPIPIDR) Received STALLed Interrupt Disable Mask */ -#define HSTPIPIDR_BLK_Msk _U_(0x44) /**< (HSTPIPIDR_BLK) Register Mask */ - -/* INTRPT mode */ -#define HSTPIPIDR_INTRPT_UNDERFIEC_Pos 2 /**< (HSTPIPIDR) Underflow Interrupt Disable Position */ -#define HSTPIPIDR_INTRPT_UNDERFIEC (_U_(0x1) << HSTPIPIDR_INTRPT_UNDERFIEC_Pos) /**< (HSTPIPIDR) Underflow Interrupt Disable Mask */ -#define HSTPIPIDR_INTRPT_RXSTALLDEC_Pos 6 /**< (HSTPIPIDR) Received STALLed Interrupt Disable Position */ -#define HSTPIPIDR_INTRPT_RXSTALLDEC (_U_(0x1) << HSTPIPIDR_INTRPT_RXSTALLDEC_Pos) /**< (HSTPIPIDR) Received STALLed Interrupt Disable Mask */ -#define HSTPIPIDR_INTRPT_Msk _U_(0x44) /**< (HSTPIPIDR_INTRPT) Register Mask */ - -/* -------- HSTPIPINRQ : (USBHS Offset: 0x650) (R/W 32) Host Pipe IN Request Register -------- */ - -#define HSTPIPINRQ_OFFSET (0x650) /**< (HSTPIPINRQ) Host Pipe IN Request Register Offset */ - -#define HSTPIPINRQ_INRQ_Pos 0 /**< (HSTPIPINRQ) IN Request Number before Freeze Position */ -#define HSTPIPINRQ_INRQ (_U_(0xFF) << HSTPIPINRQ_INRQ_Pos) /**< (HSTPIPINRQ) IN Request Number before Freeze Mask */ -#define HSTPIPINRQ_INMODE_Pos 8 /**< (HSTPIPINRQ) IN Request Mode Position */ -#define HSTPIPINRQ_INMODE (_U_(0x1) << HSTPIPINRQ_INMODE_Pos) /**< (HSTPIPINRQ) IN Request Mode Mask */ -#define HSTPIPINRQ_Msk _U_(0x1FF) /**< (HSTPIPINRQ) Register Mask */ - -/* -------- HSTPIPERR : (USBHS Offset: 0x680) (R/W 32) Host Pipe Error Register -------- */ - -#define HSTPIPERR_OFFSET (0x680) /**< (HSTPIPERR) Host Pipe Error Register Offset */ - -#define HSTPIPERR_DATATGL_Pos 0 /**< (HSTPIPERR) Data Toggle Error Position */ -#define HSTPIPERR_DATATGL (_U_(0x1) << HSTPIPERR_DATATGL_Pos) /**< (HSTPIPERR) Data Toggle Error Mask */ -#define HSTPIPERR_DATAPID_Pos 1 /**< (HSTPIPERR) Data PID Error Position */ -#define HSTPIPERR_DATAPID (_U_(0x1) << HSTPIPERR_DATAPID_Pos) /**< (HSTPIPERR) Data PID Error Mask */ -#define HSTPIPERR_PID_Pos 2 /**< (HSTPIPERR) Data PID Error Position */ -#define HSTPIPERR_PID (_U_(0x1) << HSTPIPERR_PID_Pos) /**< (HSTPIPERR) Data PID Error Mask */ -#define HSTPIPERR_TIMEOUT_Pos 3 /**< (HSTPIPERR) Time-Out Error Position */ -#define HSTPIPERR_TIMEOUT (_U_(0x1) << HSTPIPERR_TIMEOUT_Pos) /**< (HSTPIPERR) Time-Out Error Mask */ -#define HSTPIPERR_CRC16_Pos 4 /**< (HSTPIPERR) CRC16 Error Position */ -#define HSTPIPERR_CRC16 (_U_(0x1) << HSTPIPERR_CRC16_Pos) /**< (HSTPIPERR) CRC16 Error Mask */ -#define HSTPIPERR_COUNTER_Pos 5 /**< (HSTPIPERR) Error Counter Position */ -#define HSTPIPERR_COUNTER (_U_(0x3) << HSTPIPERR_COUNTER_Pos) /**< (HSTPIPERR) Error Counter Mask */ -#define HSTPIPERR_Msk _U_(0x7F) /**< (HSTPIPERR) Register Mask */ - -#define HSTPIPERR_CRC_Pos 4 /**< (HSTPIPERR Position) CRCx6 Error */ -#define HSTPIPERR_CRC (_U_(0x1) << HSTPIPERR_CRC_Pos) /**< (HSTPIPERR Mask) CRC */ - -/* -------- CTRL : (USBHS Offset: 0x800) (R/W 32) General Control Register -------- */ - -#define CTRL_OFFSET (0x800) /**< (CTRL) General Control Register Offset */ - -#define CTRL_RDERRE_Pos 4 /**< (CTRL) Remote Device Connection Error Interrupt Enable Position */ -#define CTRL_RDERRE (_U_(0x1) << CTRL_RDERRE_Pos) /**< (CTRL) Remote Device Connection Error Interrupt Enable Mask */ -#define CTRL_VBUSHWC_Pos 8 /**< (CTRL) VBUS Hardware Control Position */ -#define CTRL_VBUSHWC (_U_(0x1) << CTRL_VBUSHWC_Pos) /**< (CTRL) VBUS Hardware Control Mask */ -#define CTRL_FRZCLK_Pos 14 /**< (CTRL) Freeze USB Clock Position */ -#define CTRL_FRZCLK (_U_(0x1) << CTRL_FRZCLK_Pos) /**< (CTRL) Freeze USB Clock Mask */ -#define CTRL_USBE_Pos 15 /**< (CTRL) USBHS Enable Position */ -#define CTRL_USBE (_U_(0x1) << CTRL_USBE_Pos) /**< (CTRL) USBHS Enable Mask */ -#define CTRL_UID_Pos 24 /**< (CTRL) UID Pin Enable Position */ -#define CTRL_UID (_U_(0x1) << CTRL_UID_Pos) /**< (CTRL) UID Pin Enable Mask */ -#define CTRL_UIMOD_Pos 25 /**< (CTRL) USBHS Mode Position */ -#define CTRL_UIMOD (_U_(0x1) << CTRL_UIMOD_Pos) /**< (CTRL) USBHS Mode Mask */ -#define CTRL_UIMOD_HOST_Val _U_(0x0) /**< (CTRL) The module is in USB Host mode. */ -#define CTRL_UIMOD_DEVICE_Val _U_(0x1) /**< (CTRL) The module is in USB Device mode. */ -#define CTRL_UIMOD_HOST (CTRL_UIMOD_HOST_Val << CTRL_UIMOD_Pos) /**< (CTRL) The module is in USB Host mode. Position */ -#define CTRL_UIMOD_DEVICE (CTRL_UIMOD_DEVICE_Val << CTRL_UIMOD_Pos) /**< (CTRL) The module is in USB Device mode. Position */ -#define CTRL_Msk _U_(0x300C110) /**< (CTRL) Register Mask */ - -/* -------- SR : (USBHS Offset: 0x804) (R/ 32) General Status Register -------- */ - -#define SR_OFFSET (0x804) /**< (SR) General Status Register Offset */ - -#define SR_RDERRI_Pos 4 /**< (SR) Remote Device Connection Error Interrupt (Host mode only) Position */ -#define SR_RDERRI (_U_(0x1) << SR_RDERRI_Pos) /**< (SR) Remote Device Connection Error Interrupt (Host mode only) Mask */ -#define SR_SPEED_Pos 12 /**< (SR) Speed Status (Device mode only) Position */ -#define SR_SPEED (_U_(0x3) << SR_SPEED_Pos) /**< (SR) Speed Status (Device mode only) Mask */ -#define SR_SPEED_FULL_SPEED_Val _U_(0x0) /**< (SR) Full-Speed mode */ -#define SR_SPEED_HIGH_SPEED_Val _U_(0x1) /**< (SR) High-Speed mode */ -#define SR_SPEED_LOW_SPEED_Val _U_(0x2) /**< (SR) Low-Speed mode */ -#define SR_SPEED_FULL_SPEED (SR_SPEED_FULL_SPEED_Val << SR_SPEED_Pos) /**< (SR) Full-Speed mode Position */ -#define SR_SPEED_HIGH_SPEED (SR_SPEED_HIGH_SPEED_Val << SR_SPEED_Pos) /**< (SR) High-Speed mode Position */ -#define SR_SPEED_LOW_SPEED (SR_SPEED_LOW_SPEED_Val << SR_SPEED_Pos) /**< (SR) Low-Speed mode Position */ -#define SR_CLKUSABLE_Pos 14 /**< (SR) UTMI Clock Usable Position */ -#define SR_CLKUSABLE (_U_(0x1) << SR_CLKUSABLE_Pos) /**< (SR) UTMI Clock Usable Mask */ -#define SR_Msk _U_(0x7010) /**< (SR) Register Mask */ - -/* -------- SCR : (USBHS Offset: 0x808) (/W 32) General Status Clear Register -------- */ - -#define SCR_OFFSET (0x808) /**< (SCR) General Status Clear Register Offset */ - -#define SCR_RDERRIC_Pos 4 /**< (SCR) Remote Device Connection Error Interrupt Clear Position */ -#define SCR_RDERRIC (_U_(0x1) << SCR_RDERRIC_Pos) /**< (SCR) Remote Device Connection Error Interrupt Clear Mask */ -#define SCR_Msk _U_(0x10) /**< (SCR) Register Mask */ - -/* -------- SFR : (USBHS Offset: 0x80c) (/W 32) General Status Set Register -------- */ - -#define SFR_OFFSET (0x80C) /**< (SFR) General Status Set Register Offset */ - -#define SFR_RDERRIS_Pos 4 /**< (SFR) Remote Device Connection Error Interrupt Set Position */ -#define SFR_RDERRIS (_U_(0x1) << SFR_RDERRIS_Pos) /**< (SFR) Remote Device Connection Error Interrupt Set Mask */ -#define SFR_VBUSRQS_Pos 9 /**< (SFR) VBUS Request Set Position */ -#define SFR_VBUSRQS (_U_(0x1) << SFR_VBUSRQS_Pos) /**< (SFR) VBUS Request Set Mask */ -#define SFR_Msk _U_(0x210) /**< (SFR) Register Mask */ - -/** \brief DEVDMA hardware registers */ -typedef struct -{ - __IO uint32_t DEVDMANXTDSC; /**< (DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */ - __IO uint32_t DEVDMAADDRESS; /**< (DEVDMA Offset: 0x04) Device DMA Channel Address Register */ - __IO uint32_t DEVDMACONTROL; /**< (DEVDMA Offset: 0x08) Device DMA Channel Control Register */ - __IO uint32_t DEVDMASTATUS; /**< (DEVDMA Offset: 0x0C) Device DMA Channel Status Register */ -} devdma_t; - -/** \brief HSTDMA hardware registers */ -typedef struct -{ - __IO uint32_t HSTDMANXTDSC; /**< (HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */ - __IO uint32_t HSTDMAADDRESS; /**< (HSTDMA Offset: 0x04) Host DMA Channel Address Register */ - __IO uint32_t HSTDMACONTROL; /**< (HSTDMA Offset: 0x08) Host DMA Channel Control Register */ - __IO uint32_t HSTDMASTATUS; /**< (HSTDMA Offset: 0x0C) Host DMA Channel Status Register */ -} hstdma_t; - -/** \brief USBHS hardware registers */ -typedef struct -{ - __IO uint32_t DEVCTRL; /**< (USBHS Offset: 0x00) Device General Control Register */ - __I uint32_t DEVISR; /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */ - __O uint32_t DEVICR; /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */ - __O uint32_t DEVIFR; /**< (USBHS Offset: 0x0C) Device Global Interrupt Set Register */ - __I uint32_t DEVIMR; /**< (USBHS Offset: 0x10) Device Global Interrupt Mask Register */ - __O uint32_t DEVIDR; /**< (USBHS Offset: 0x14) Device Global Interrupt Disable Register */ - __O uint32_t DEVIER; /**< (USBHS Offset: 0x18) Device Global Interrupt Enable Register */ - __IO uint32_t DEVEPT; /**< (USBHS Offset: 0x1C) Device Endpoint Register */ - __I uint32_t DEVFNUM; /**< (USBHS Offset: 0x20) Device Frame Number Register */ - __I uint8_t Reserved1[220]; - __IO uint32_t DEVEPTCFG[10]; /**< (USBHS Offset: 0x100) Device Endpoint Configuration Register */ - __I uint8_t Reserved2[8]; - __I uint32_t DEVEPTISR[10]; /**< (USBHS Offset: 0x130) Device Endpoint Interrupt Status Register */ - __I uint8_t Reserved3[8]; - __O uint32_t DEVEPTICR[10]; /**< (USBHS Offset: 0x160) Device Endpoint Interrupt Clear Register */ - __I uint8_t Reserved4[8]; - __O uint32_t DEVEPTIFR[10]; /**< (USBHS Offset: 0x190) Device Endpoint Interrupt Set Register */ - __I uint8_t Reserved5[8]; - __I uint32_t DEVEPTIMR[10]; /**< (USBHS Offset: 0x1C0) Device Endpoint Interrupt Mask Register */ - __I uint8_t Reserved6[8]; - __O uint32_t DEVEPTIER[10]; /**< (USBHS Offset: 0x1F0) Device Endpoint Interrupt Enable Register */ - __I uint8_t Reserved7[8]; - __O uint32_t DEVEPTIDR[10]; /**< (USBHS Offset: 0x220) Device Endpoint Interrupt Disable Register */ - __I uint8_t Reserved8[200]; - devdma_t DEVDMA[7]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register */ - __I uint8_t Reserved9[128]; - __IO uint32_t HSTCTRL; /**< (USBHS Offset: 0x400) Host General Control Register */ - __I uint32_t HSTISR; /**< (USBHS Offset: 0x404) Host Global Interrupt Status Register */ - __O uint32_t HSTICR; /**< (USBHS Offset: 0x408) Host Global Interrupt Clear Register */ - __O uint32_t HSTIFR; /**< (USBHS Offset: 0x40C) Host Global Interrupt Set Register */ - __I uint32_t HSTIMR; /**< (USBHS Offset: 0x410) Host Global Interrupt Mask Register */ - __O uint32_t HSTIDR; /**< (USBHS Offset: 0x414) Host Global Interrupt Disable Register */ - __O uint32_t HSTIER; /**< (USBHS Offset: 0x418) Host Global Interrupt Enable Register */ - __IO uint32_t HSTPIP; /**< (USBHS Offset: 0x41C) Host Pipe Register */ - __IO uint32_t HSTFNUM; /**< (USBHS Offset: 0x420) Host Frame Number Register */ - __IO uint32_t HSTADDR1; /**< (USBHS Offset: 0x424) Host Address 1 Register */ - __IO uint32_t HSTADDR2; /**< (USBHS Offset: 0x428) Host Address 2 Register */ - __IO uint32_t HSTADDR3; /**< (USBHS Offset: 0x42C) Host Address 3 Register */ - __I uint8_t Reserved10[208]; - __IO uint32_t HSTPIPCFG[10]; /**< (USBHS Offset: 0x500) Host Pipe Configuration Register */ - __I uint8_t Reserved11[8]; - __I uint32_t HSTPIPISR[10]; /**< (USBHS Offset: 0x530) Host Pipe Status Register */ - __I uint8_t Reserved12[8]; - __O uint32_t HSTPIPICR[10]; /**< (USBHS Offset: 0x560) Host Pipe Clear Register */ - __I uint8_t Reserved13[8]; - __O uint32_t HSTPIPIFR[10]; /**< (USBHS Offset: 0x590) Host Pipe Set Register */ - __I uint8_t Reserved14[8]; - __I uint32_t HSTPIPIMR[10]; /**< (USBHS Offset: 0x5C0) Host Pipe Mask Register */ - __I uint8_t Reserved15[8]; - __O uint32_t HSTPIPIER[10]; /**< (USBHS Offset: 0x5F0) Host Pipe Enable Register */ - __I uint8_t Reserved16[8]; - __O uint32_t HSTPIPIDR[10]; /**< (USBHS Offset: 0x620) Host Pipe Disable Register */ - __I uint8_t Reserved17[8]; - __IO uint32_t HSTPIPINRQ[10]; /**< (USBHS Offset: 0x650) Host Pipe IN Request Register */ - __I uint8_t Reserved18[8]; - __IO uint32_t HSTPIPERR[10]; /**< (USBHS Offset: 0x680) Host Pipe Error Register */ - __I uint8_t Reserved19[104]; - hstdma_t HSTDMA[7]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register */ - __I uint8_t Reserved20[128]; - __IO uint32_t CTRL; /**< (USBHS Offset: 0x800) General Control Register */ - __I uint32_t SR; /**< (USBHS Offset: 0x804) General Status Register */ - __O uint32_t SCR; /**< (USBHS Offset: 0x808) General Status Clear Register */ - __O uint32_t SFR; /**< (USBHS Offset: 0x80C) General Status Set Register */ -} dcd_registers_t; - -#define USB_REG ((dcd_registers_t *)0x40038000U) /**< \brief (USBHS) Base Address */ - -#define EP_MAX 10 - -#define FIFO_RAM_ADDR 0xA0100000u - -// Errata: The DMA feature is not available for Pipe/Endpoint 7 -#define EP_DMA_SUPPORT(epnum) (epnum >= 1 && epnum <= 6) - -#else // TODO : SAM3U - -#endif - -#endif /* _COMMON_USB_REGS_H_ */ diff --git a/uCNC/src/tinyusb/src/portable/microchip/samx7x/dcd_samx7x.c b/uCNC/src/tinyusb/src/portable/microchip/samx7x/dcd_samx7x.c deleted file mode 100644 index 3c5d25b02..000000000 --- a/uCNC/src/tinyusb/src/portable/microchip/samx7x/dcd_samx7x.c +++ /dev/null @@ -1,794 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2018, hathach (tinyusb.org) - * Copyright (c) 2021, HiFiPhile - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "../../../tusb_option.h" - -#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_SAMX7X - -#include "device/dcd.h" -#include "sam.h" -#include "common_usb_regs.h" -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM DECLARATION -//--------------------------------------------------------------------+ - -// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval) -// We disable SOF for now until needed later on -#ifndef USE_SOF -#define USE_SOF 0 -#endif - -// Dual bank can imporve performance, but need 2 times bigger packet buffer -// As SAM7x has only 4KB packet buffer, use with caution ! -// Enable in FS mode as packets are smaller -#ifndef USE_DUAL_BANK -#if TUD_OPT_HIGH_SPEED -#define USE_DUAL_BANK 0 -#else -#define USE_DUAL_BANK 1 -#endif -#endif - -#define EP_GET_FIFO_PTR(ep, scale) (((TU_XSTRCAT(TU_STRCAT(uint, scale), _t)(*)[0x8000 / ((scale) / 8)]) FIFO_RAM_ADDR)[(ep)]) - -// DMA Channel Transfer Descriptor -typedef struct -{ - volatile uint32_t next_desc; - volatile uint32_t buff_addr; - volatile uint32_t chnl_ctrl; - uint32_t padding; -} dma_desc_t; - -// Transfer control context -typedef struct -{ - uint8_t *buffer; - uint16_t total_len; - uint16_t queued_len; - uint16_t max_packet_size; - uint8_t interval; - tu_fifo_t *fifo; -} xfer_ctl_t; - -static tusb_speed_t get_speed(void); -static void dcd_transmit_packet(xfer_ctl_t *xfer, uint8_t ep_ix); - -// DMA descriptors shouldn't be placed in ITCM ! -CFG_TUSB_MEM_SECTION static dma_desc_t dma_desc[6]; - -static xfer_ctl_t xfer_status[EP_MAX]; - -static const tusb_desc_endpoint_t ep0_desc = - { - .bEndpointAddress = 0x00, - .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, -}; - -TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, int32_t size) -{ - if (SCB->CCR & SCB_CCR_DC_Msk) - { - SCB_CleanInvalidateDCache_by_Addr(addr, size); - } - else - { - __DSB(); - __ISB(); - } -} -//------------------------------------------------------------------ -// Device API -//------------------------------------------------------------------ - -// Initialize controller to device mode -void dcd_init(uint8_t rhport) -{ - dcd_connect(rhport); -} - -// Enable device interrupt -void dcd_int_enable(uint8_t rhport) -{ - (void)rhport; - NVIC_EnableIRQ((IRQn_Type)ID_USBHS); -} - -// Disable device interrupt -void dcd_int_disable(uint8_t rhport) -{ - (void)rhport; - NVIC_DisableIRQ((IRQn_Type)ID_USBHS); -} - -// Receive Set Address request, mcu port must also include status IN response -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void)dev_addr; - // DCD can only set address after status for this request is complete - // do it at dcd_edpt0_status_complete() - - // Response with zlp status - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); -} - -// Wake up host -void dcd_remote_wakeup(uint8_t rhport) -{ - (void)rhport; - USB_REG->DEVCTRL |= DEVCTRL_RMWKUP; -} - -// Connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(uint8_t rhport) -{ - (void)rhport; - dcd_int_disable(rhport); - // Enable the USB controller in device mode - USB_REG->CTRL = CTRL_UIMOD | CTRL_USBE; - while (!(USB_REG->SR & SR_CLKUSABLE)) - ; -#if TUD_OPT_HIGH_SPEED - USB_REG->DEVCTRL &= ~DEVCTRL_SPDCONF; -#else - USB_REG->DEVCTRL |= DEVCTRL_SPDCONF_LOW_POWER; -#endif - // Enable the End Of Reset, Suspend & Wakeup interrupts - USB_REG->DEVIER = (DEVIER_EORSTES | DEVIER_SUSPES | DEVIER_WAKEUPES); -#if USE_SOF - USB_REG->DEVIER = DEVIER_SOFES; -#endif - // Clear the End Of Reset, SOF & Wakeup interrupts - USB_REG->DEVICR = (DEVICR_EORSTC | DEVICR_SOFC | DEVICR_WAKEUPC); - // Manually set the Suspend Interrupt - USB_REG->DEVIFR |= DEVIFR_SUSPS; - // Ack the Wakeup Interrupt - USB_REG->DEVICR = DEVICR_WAKEUPC; - // Attach the device - USB_REG->DEVCTRL &= ~DEVCTRL_DETACH; - // Freeze USB clock - USB_REG->CTRL |= CTRL_FRZCLK; -} - -// Disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(uint8_t rhport) -{ - (void)rhport; - dcd_int_disable(rhport); - // Disable all endpoints - USB_REG->DEVEPT &= ~(0x3FF << DEVEPT_EPEN0_Pos); - // Unfreeze USB clock - USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)) - ; - // Clear all the pending interrupts - USB_REG->DEVICR = DEVICR_Msk; - // Disable all interrupts - USB_REG->DEVIDR = DEVIDR_Msk; - // Detach the device - USB_REG->DEVCTRL |= DEVCTRL_DETACH; - // Disable the device address - USB_REG->DEVCTRL &= ~(DEVCTRL_ADDEN | DEVCTRL_UADD); -} - -static tusb_speed_t get_speed(void) -{ - switch (USB_REG->SR & SR_SPEED) - { - case SR_SPEED_FULL_SPEED: - default: - return TUSB_SPEED_FULL; - case SR_SPEED_HIGH_SPEED: - return TUSB_SPEED_HIGH; - case SR_SPEED_LOW_SPEED: - return TUSB_SPEED_LOW; - } -} - -static void dcd_ep_handler(uint8_t ep_ix) -{ - uint32_t int_status = USB_REG->DEVEPTISR[ep_ix]; - int_status &= USB_REG->DEVEPTIMR[ep_ix]; - - uint16_t count = (USB_REG->DEVEPTISR[ep_ix] & - DEVEPTISR_BYCT) >> - DEVEPTISR_BYCT_Pos; - xfer_ctl_t *xfer = &xfer_status[ep_ix]; - - if (ep_ix == 0U) - { - static uint8_t ctrl_dir; - - if (int_status & DEVEPTISR_CTRL_RXSTPI) - { - ctrl_dir = (USB_REG->DEVEPTISR[0] & DEVEPTISR_CTRL_CTRLDIR) >> DEVEPTISR_CTRL_CTRLDIR_Pos; - // Setup packet should always be 8 bytes. If not, ignore it, and try again. - if (count == 8) - { - uint8_t *ptr = EP_GET_FIFO_PTR(0, 8); - dcd_event_setup_received(0, ptr, true); - } - // Ack and disable SETUP interrupt - USB_REG->DEVEPTICR[0] = DEVEPTICR_CTRL_RXSTPIC; - USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_RXSTPEC; - } - if (int_status & DEVEPTISR_RXOUTI) - { - uint8_t *ptr = EP_GET_FIFO_PTR(0, 8); - - if (count && xfer->total_len) - { - uint16_t remain = xfer->total_len - xfer->queued_len; - if (count > remain) - { - count = remain; - } - if (xfer->buffer) - { - memcpy(xfer->buffer + xfer->queued_len, ptr, count); - } - else - { - tu_fifo_write_n(xfer->fifo, ptr, count); - } - xfer->queued_len = (uint16_t)(xfer->queued_len + count); - } - // Acknowledge the interrupt - USB_REG->DEVEPTICR[0] = DEVEPTICR_RXOUTIC; - if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) - { - // RX COMPLETE - dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true); - // Disable the interrupt - USB_REG->DEVEPTIDR[0] = DEVEPTIDR_RXOUTEC; - // Re-enable SETUP interrupt - if (ctrl_dir == 1) - { - USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; - } - } - } - if (int_status & DEVEPTISR_TXINI) - { - // Disable the interrupt - USB_REG->DEVEPTIDR[0] = DEVEPTIDR_TXINEC; - if ((xfer->total_len != xfer->queued_len)) - { - // TX not complete - dcd_transmit_packet(xfer, 0); - } - else - { - // TX complete - dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true); - // Re-enable SETUP interrupt - if (ctrl_dir == 0) - { - USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; - } - } - } - } - else - { - if (int_status & DEVEPTISR_RXOUTI) - { - if (count && xfer->total_len) - { - uint16_t remain = xfer->total_len - xfer->queued_len; - if (count > remain) - { - count = remain; - } - uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix, 8); - if (xfer->buffer) - { - memcpy(xfer->buffer + xfer->queued_len, ptr, count); - } - else - { - tu_fifo_write_n(xfer->fifo, ptr, count); - } - xfer->queued_len = (uint16_t)(xfer->queued_len + count); - } - // Clear the FIFO control flag to receive more data. - USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC; - // Acknowledge the interrupt - USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_RXOUTIC; - if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) - { - // RX COMPLETE - dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true); - // Disable the interrupt - USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_RXOUTEC; - // Though the host could still send, we don't know. - } - } - if (int_status & DEVEPTISR_TXINI) - { - // Acknowledge the interrupt - USB_REG->DEVEPTICR[ep_ix] = DEVEPTICR_TXINIC; - if ((xfer->total_len != xfer->queued_len)) - { - // TX not complete - dcd_transmit_packet(xfer, ep_ix); - } - else - { - // TX complete - dcd_event_xfer_complete(0, 0x80 + ep_ix, xfer->total_len, XFER_RESULT_SUCCESS, true); - // Disable the interrupt - USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_TXINEC; - } - } - } -} - -static void dcd_dma_handler(uint8_t ep_ix) -{ - uint32_t status = USB_REG->DEVDMA[ep_ix - 1].DEVDMASTATUS; - if (status & DEVDMASTATUS_CHANN_ENB) - { - return; // Ignore EOT_STA interrupt - } - // Disable DMA interrupt - USB_REG->DEVIDR = DEVIDR_DMA_1 << (ep_ix - 1); - - xfer_ctl_t *xfer = &xfer_status[ep_ix]; - uint16_t count = xfer->total_len - ((status & DEVDMASTATUS_BUFF_COUNT) >> DEVDMASTATUS_BUFF_COUNT_Pos); - if (USB_REG->DEVEPTCFG[ep_ix] & DEVEPTCFG_EPDIR) - { - dcd_event_xfer_complete(0, 0x80 + ep_ix, count, XFER_RESULT_SUCCESS, true); - } - else - { - dcd_event_xfer_complete(0, ep_ix, count, XFER_RESULT_SUCCESS, true); - } -} - -void dcd_int_handler(uint8_t rhport) -{ - (void)rhport; - uint32_t int_status = USB_REG->DEVISR; - int_status &= USB_REG->DEVIMR; - // End of reset interrupt - if (int_status & DEVISR_EORST) - { - // Unfreeze USB clock - USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)) - ; - // Reset all endpoints - for (int ep_ix = 1; ep_ix < EP_MAX; ep_ix++) - { - USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + ep_ix); - USB_REG->DEVEPT &= ~(1 << (DEVEPT_EPRST0_Pos + ep_ix)); - } - dcd_edpt_open(0, &ep0_desc); - USB_REG->DEVICR = DEVICR_EORSTC; - USB_REG->DEVICR = DEVICR_WAKEUPC; - USB_REG->DEVICR = DEVICR_SUSPC; - USB_REG->DEVIER = DEVIER_SUSPES; - - dcd_event_bus_reset(rhport, get_speed(), true); - } - // End of Wakeup interrupt - if (int_status & DEVISR_WAKEUP) - { - USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)) - ; - USB_REG->DEVICR = DEVICR_WAKEUPC; - USB_REG->DEVIDR = DEVIDR_WAKEUPEC; - USB_REG->DEVIER = DEVIER_SUSPES; - - dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); - } - // Suspend interrupt - if (int_status & DEVISR_SUSP) - { - // Unfreeze USB clock - USB_REG->CTRL &= ~CTRL_FRZCLK; - while (!(USB_REG->SR & SR_CLKUSABLE)) - ; - USB_REG->DEVICR = DEVICR_SUSPC; - USB_REG->DEVIDR = DEVIDR_SUSPEC; - USB_REG->DEVIER = DEVIER_WAKEUPES; - USB_REG->CTRL |= CTRL_FRZCLK; - - dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); - } -#if USE_SOF - if (int_status & DEVISR_SOF) - { - USB_REG->DEVICR = DEVICR_SOFC; - - dcd_event_bus_signal(0, DCD_EVENT_SOF, true); - } -#endif - // Endpoints interrupt - for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) - { - if (int_status & (DEVISR_PEP_0 << ep_ix)) - { - dcd_ep_handler(ep_ix); - } - } - // Endpoints DMA interrupt - for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++) - { - if (EP_DMA_SUPPORT(ep_ix)) - { - if (int_status & (DEVISR_DMA_1 << (ep_ix - 1))) - { - dcd_dma_handler(ep_ix); - } - } - } -} - -//--------------------------------------------------------------------+ -// Endpoint API -//--------------------------------------------------------------------+ -// Invoked when a control transfer's status stage is complete. -// May help DCD to prepare for next control transfer, this API is optional. -void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) -{ - (void)rhport; - - if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && - request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && - request->bRequest == TUSB_REQ_SET_ADDRESS) - { - uint8_t const dev_addr = (uint8_t)request->wValue; - - USB_REG->DEVCTRL |= dev_addr | DEVCTRL_ADDEN; - } -} - -// Configure endpoint's registers according to descriptor -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) -{ - (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress); - uint16_t const epMaxPktSize = tu_edpt_packet_size(ep_desc); - tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer; - uint8_t fifoSize = 0; // FIFO size - uint16_t defaultEndpointSize = 8; // Default size of Endpoint - // Find upper 2 power number of epMaxPktSize - if (epMaxPktSize) - { - while (defaultEndpointSize < epMaxPktSize) - { - fifoSize++; - defaultEndpointSize <<= 1; - } - } - xfer_status[epnum].max_packet_size = epMaxPktSize; - - USB_REG->DEVEPT |= 1 << (DEVEPT_EPRST0_Pos + epnum); - USB_REG->DEVEPT &= ~(1 << (DEVEPT_EPRST0_Pos + epnum)); - - if (epnum == 0) - { - // Enable the control endpoint - Endpoint 0 - USB_REG->DEVEPT |= DEVEPT_EPEN0; - // Configure the Endpoint 0 configuration register - USB_REG->DEVEPTCFG[0] = - ((fifoSize << DEVEPTCFG_EPSIZE_Pos) | - (TUSB_XFER_CONTROL << DEVEPTCFG_EPTYPE_Pos) | - (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | - DEVEPTCFG_ALLOC); - USB_REG->DEVEPTIER[0] = DEVEPTIER_RSTDTS; - USB_REG->DEVEPTIDR[0] = DEVEPTIDR_CTRL_STALLRQC; - if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[0] & DEVEPTISR_CFGOK)) - { - // Endpoint configuration is successful - USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; - // Enable Endpoint 0 Interrupts - USB_REG->DEVIER = DEVIER_PEP_0; - return true; - } - else - { - // Endpoint configuration is not successful - return false; - } - } - else - { - // Enable the endpoint - USB_REG->DEVEPT |= ((0x01 << epnum) << DEVEPT_EPEN0_Pos); - // Set up the maxpacket size, fifo start address fifosize - // and enable the interrupt. CLear the data toggle. - // AUTOSW is needed for DMA ack ! - USB_REG->DEVEPTCFG[epnum] = - ((fifoSize << DEVEPTCFG_EPSIZE_Pos) | - (eptype << DEVEPTCFG_EPTYPE_Pos) | - (DEVEPTCFG_EPBK_1_BANK << DEVEPTCFG_EPBK_Pos) | - DEVEPTCFG_AUTOSW | - ((dir & 0x01) << DEVEPTCFG_EPDIR_Pos)); - if (eptype == TUSB_XFER_ISOCHRONOUS) - { - USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_NBTRANS_1_TRANS; - } -#if USE_DUAL_BANK - if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK) - { - USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_EPBK_2_BANK; - } -#endif - USB_REG->DEVEPTCFG[epnum] |= DEVEPTCFG_ALLOC; - USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RSTDTS; - USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC; - if (DEVEPTISR_CFGOK == (USB_REG->DEVEPTISR[epnum] & DEVEPTISR_CFGOK)) - { - USB_REG->DEVIER = ((0x01 << epnum) << DEVIER_PEP_0_Pos); - return true; - } - else - { - // Endpoint configuration is not successful - return false; - } - } -} - -void dcd_edpt_close_all(uint8_t rhport) -{ - (void)rhport; - // TODO implement dcd_edpt_close_all() -} - -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - - // Disable endpoint interrupt - USB_REG->DEVIDR = 1 << (DEVIDR_PEP_0_Pos + epnum); - // Disable EP - USB_REG->DEVEPT &= ~(1 << (DEVEPT_EPEN0_Pos + epnum)); -} - -static void dcd_transmit_packet(xfer_ctl_t *xfer, uint8_t ep_ix) -{ - uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len); - if (len) - { - if (len > xfer->max_packet_size) - { - len = xfer->max_packet_size; - } - uint8_t *ptr = EP_GET_FIFO_PTR(ep_ix, 8); - if (xfer->buffer) - { - memcpy(ptr, xfer->buffer + xfer->queued_len, len); - } - else - { - tu_fifo_read_n(xfer->fifo, ptr, len); - } - __DSB(); - __ISB(); - xfer->queued_len = (uint16_t)(xfer->queued_len + len); - } - if (ep_ix == 0U) - { - // Control endpoint: clear the interrupt flag to send the data - USB_REG->DEVEPTICR[0] = DEVEPTICR_TXINIC; - } - else - { - // Other endpoint types: clear the FIFO control flag to send the data - USB_REG->DEVEPTIDR[ep_ix] = DEVEPTIDR_FIFOCONC; - } - USB_REG->DEVEPTIER[ep_ix] = DEVEPTIER_TXINES; -} - -// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) -{ - (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t *xfer = &xfer_status[epnum]; - - xfer->buffer = buffer; - xfer->total_len = total_bytes; - xfer->queued_len = 0; - xfer->fifo = NULL; - - if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) - { - // Force the CPU to flush the buffer. We increase the size by 32 because the call aligns the - // address to 32-byte boundaries. - CleanInValidateCache((uint32_t *)tu_align((uint32_t)buffer, 4), total_bytes + 31); - uint32_t udd_dma_ctrl = total_bytes << DEVDMACONTROL_BUFF_LENGTH_Pos; - if (dir == TUSB_DIR_OUT) - { - udd_dma_ctrl |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN; - } - else - { - udd_dma_ctrl |= DEVDMACONTROL_END_B_EN; - } - USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)buffer; - udd_dma_ctrl |= DEVDMACONTROL_END_BUFFIT | DEVDMACONTROL_CHANN_ENB; - // Disable IRQs to have a short sequence - // between read of EOT_STA and DMA enable - uint32_t irq_state = __get_PRIMASK(); - __disable_irq(); - if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST)) - { - USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl; - USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1); - __set_PRIMASK(irq_state); - return true; - } - __set_PRIMASK(irq_state); - - // Here a ZLP has been recieved - // and the DMA transfer must be not started. - // It is the end of transfer - return false; - } - else - { - if (dir == TUSB_DIR_OUT) - { - USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES; - } - else - { - dcd_transmit_packet(xfer, epnum); - } - } - return true; -} - -// The number of bytes has to be given explicitly to allow more flexible control of how many -// bytes should be written and second to keep the return value free to give back a boolean -// success message. If total_bytes is too big, the FIFO will copy only what is available -// into the USB buffer! -bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) -{ - (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t *xfer = &xfer_status[epnum]; - if (epnum == 0x80) - xfer = &xfer_status[EP_MAX]; - - xfer->buffer = NULL; - xfer->total_len = total_bytes; - xfer->queued_len = 0; - xfer->fifo = ff; - - if (EP_DMA_SUPPORT(epnum) && total_bytes != 0) - { - tu_fifo_buffer_info_t info; - uint32_t udd_dma_ctrl_lin = DEVDMACONTROL_CHANN_ENB; - uint32_t udd_dma_ctrl_wrap = DEVDMACONTROL_CHANN_ENB | DEVDMACONTROL_END_BUFFIT; - if (dir == TUSB_DIR_OUT) - { - tu_fifo_get_write_info(ff, &info); - udd_dma_ctrl_lin |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN; - udd_dma_ctrl_wrap |= DEVDMACONTROL_END_TR_IT | DEVDMACONTROL_END_TR_EN; - } - else - { - tu_fifo_get_read_info(ff, &info); - if (info.len_wrap == 0) - { - udd_dma_ctrl_lin |= DEVDMACONTROL_END_B_EN; - } - udd_dma_ctrl_wrap |= DEVDMACONTROL_END_B_EN; - } - - // Clean invalidate cache of linear part - CleanInValidateCache((uint32_t *)tu_align((uint32_t)info.ptr_lin, 4), info.len_lin + 31); - - USB_REG->DEVDMA[epnum - 1].DEVDMAADDRESS = (uint32_t)info.ptr_lin; - if (info.len_wrap) - { - // Clean invalidate cache of wrapped part - CleanInValidateCache((uint32_t *)tu_align((uint32_t)info.ptr_wrap, 4), info.len_wrap + 31); - - dma_desc[epnum - 1].next_desc = 0; - dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap; - dma_desc[epnum - 1].chnl_ctrl = - udd_dma_ctrl_wrap | (info.len_wrap << DEVDMACONTROL_BUFF_LENGTH_Pos); - // Clean cache of wrapped DMA descriptor - CleanInValidateCache((uint32_t *)&dma_desc[epnum - 1], sizeof(dma_desc_t)); - - udd_dma_ctrl_lin |= DEVDMASTATUS_DESC_LDST; - USB_REG->DEVDMA[epnum - 1].DEVDMANXTDSC = (uint32_t)&dma_desc[epnum - 1]; - } - else - { - udd_dma_ctrl_lin |= DEVDMACONTROL_END_BUFFIT; - } - udd_dma_ctrl_lin |= (info.len_lin << DEVDMACONTROL_BUFF_LENGTH_Pos); - // Disable IRQs to have a short sequence - // between read of EOT_STA and DMA enable - uint32_t irq_state = __get_PRIMASK(); - __disable_irq(); - if (!(USB_REG->DEVDMA[epnum - 1].DEVDMASTATUS & DEVDMASTATUS_END_TR_ST)) - { - USB_REG->DEVDMA[epnum - 1].DEVDMACONTROL = udd_dma_ctrl_lin; - USB_REG->DEVIER = DEVIER_DMA_1 << (epnum - 1); - __set_PRIMASK(irq_state); - return true; - } - __set_PRIMASK(irq_state); - - // Here a ZLP has been recieved - // and the DMA transfer must be not started. - // It is the end of transfer - return false; - } - else - { - if (dir == TUSB_DIR_OUT) - { - USB_REG->DEVEPTIER[epnum] = DEVEPTIER_RXOUTES; - } - else - { - dcd_transmit_packet(xfer, epnum); - } - } - return true; -} - -// Stall endpoint -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - USB_REG->DEVEPTIER[epnum] = DEVEPTIER_CTRL_STALLRQS; - // Re-enable SETUP interrupt - if (epnum == 0) - { - USB_REG->DEVEPTIER[0] = DEVEPTIER_CTRL_RXSTPES; - } -} - -// clear stall, data toggle is also reset to DATA0 -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - USB_REG->DEVEPTIDR[epnum] = DEVEPTIDR_CTRL_STALLRQC; - USB_REG->DEVEPTIER[epnum] = HSTPIPIER_RSTDTS; -} - -#endif diff --git a/uCNC/src/tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/uCNC/src/tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.c new file mode 100644 index 000000000..3d5027ead --- /dev/null +++ b/uCNC/src/tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -0,0 +1,599 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "../../../tusb_option.h" + +#if TUSB_OPT_DEVICE_ENABLED && \ + (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX) + +#include "../../../device/dcd.h" +#include "dcd_lpc17_40.h" +#include "LPC17xx.h" + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF +//--------------------------------------------------------------------+ +#define DCD_ENDPOINT_MAX 32 + +typedef struct TU_ATTR_ALIGNED(4) +{ + //------------- Word 0 -------------// + uint32_t next; + + //------------- Word 1 -------------// + uint16_t atle_mode : 2; // 00: normal, 01: ATLE (auto length extraction) + uint16_t next_valid : 1; + uint16_t : 1; ///< reserved + uint16_t isochronous : 1; // is an iso endpoint + uint16_t max_packet_size : 11; + + volatile uint16_t buflen; // bytes for non-iso, number of packets for iso endpoint + + //------------- Word 2 -------------// + volatile uint32_t buffer; + + //------------- Word 3 -------------// + volatile uint16_t retired : 1; // initialized to zero + volatile uint16_t status : 4; + volatile uint16_t iso_last_packet_valid : 1; + volatile uint16_t atle_lsb_extracted : 1; // used in ATLE mode + volatile uint16_t atle_msb_extracted : 1; // used in ATLE mode + volatile uint16_t atle_mess_len_position : 6; // used in ATLE mode + uint16_t : 2; + + volatile uint16_t present_count; // For non-iso : The number of bytes transferred by the DMA engine + // For iso : number of packets + + //------------- Word 4 -------------// + // uint32_t iso_packet_size_addr; // iso only, can be omitted for non-iso +} dma_desc_t; + +TU_VERIFY_STATIC(sizeof(dma_desc_t) == 16, "size is not correct"); // TODO not support ISO for now + +typedef struct +{ + // must be 128 byte aligned + volatile dma_desc_t *udca[DCD_ENDPOINT_MAX]; + + // TODO DMA does not support control transfer (0-1 are not used, offset to reduce memory) + dma_desc_t dd[DCD_ENDPOINT_MAX]; + + struct + { + uint8_t *out_buffer; + uint8_t out_bytes; + volatile bool out_received; // indicate if data is already received in endpoint + + uint8_t in_bytes; + } control; + +} dcd_data_t; + +CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(128) static dcd_data_t _dcd; + +//--------------------------------------------------------------------+ +// SIE Command +//--------------------------------------------------------------------+ +static void sie_cmd_code(sie_cmdphase_t phase, uint8_t code_data) +{ + LPC_USB->USBDevIntClr = (DEV_INT_COMMAND_CODE_EMPTY_MASK | DEV_INT_COMMAND_DATA_FULL_MASK); + LPC_USB->USBCmdCode = (phase << 8) | (code_data << 16); + + uint32_t const wait_flag = (phase == SIE_CMDPHASE_READ) ? DEV_INT_COMMAND_DATA_FULL_MASK : DEV_INT_COMMAND_CODE_EMPTY_MASK; + while ((LPC_USB->USBDevIntSt & wait_flag) == 0) + { + } + + LPC_USB->USBDevIntClr = wait_flag; +} + +static void sie_write(uint8_t cmd_code, uint8_t data_len, uint8_t data) +{ + sie_cmd_code(SIE_CMDPHASE_COMMAND, cmd_code); + + if (data_len) + { + sie_cmd_code(SIE_CMDPHASE_WRITE, data); + } +} + +static uint8_t sie_read(uint8_t cmd_code) +{ + sie_cmd_code(SIE_CMDPHASE_COMMAND, cmd_code); + sie_cmd_code(SIE_CMDPHASE_READ, cmd_code); + return (uint8_t)LPC_USB->USBCmdData; +} + +//--------------------------------------------------------------------+ +// PIPE HELPER +//--------------------------------------------------------------------+ +static inline uint8_t ep_addr2idx(uint8_t ep_addr) +{ + return 2 * (ep_addr & 0x0F) + ((ep_addr & TUSB_DIR_IN_MASK) ? 1 : 0); +} + +static void set_ep_size(uint8_t ep_id, uint16_t max_packet_size) +{ + // follows example in 11.10.4.2 + LPC_USB->USBReEp |= TU_BIT(ep_id); + LPC_USB->USBEpInd = ep_id; // select index before setting packet size + LPC_USB->USBMaxPSize = max_packet_size; + + while ((LPC_USB->USBDevIntSt & DEV_INT_ENDPOINT_REALIZED_MASK) == 0) + { + } + LPC_USB->USBDevIntClr = DEV_INT_ENDPOINT_REALIZED_MASK; +} + +//--------------------------------------------------------------------+ +// CONTROLLER API +//--------------------------------------------------------------------+ +static void bus_reset(void) +{ + // step 7 : slave mode set up + LPC_USB->USBEpIntClr = 0xFFFFFFFF; // clear all pending interrupt + LPC_USB->USBDevIntClr = 0xFFFFFFFF; // clear all pending interrupt + LPC_USB->USBEpIntEn = 0x03UL; // control endpoint cannot use DMA, non-control all use DMA + LPC_USB->USBEpIntPri = 0x03UL; // fast for control endpoint + + // step 8 : DMA set up + LPC_USB->USBEpDMADis = 0xFFFFFFFF; // firstly disable all dma + LPC_USB->USBDMARClr = 0xFFFFFFFF; // clear all pending interrupt + LPC_USB->USBEoTIntClr = 0xFFFFFFFF; + LPC_USB->USBNDDRIntClr = 0xFFFFFFFF; + LPC_USB->USBSysErrIntClr = 0xFFFFFFFF; + + tu_memclr(&_dcd, sizeof(dcd_data_t)); +} + +void dcd_init(uint8_t rhport) +{ + (void)rhport; + + //------------- user manual 11.13 usb device controller initialization -------------// + // step 6 : set up control endpoint + set_ep_size(0, CFG_TUD_ENDPOINT0_SIZE); + set_ep_size(1, CFG_TUD_ENDPOINT0_SIZE); + + bus_reset(); + + LPC_USB->USBDevIntEn = (DEV_INT_DEVICE_STATUS_MASK | DEV_INT_ENDPOINT_FAST_MASK | DEV_INT_ENDPOINT_SLOW_MASK | DEV_INT_ERROR_MASK); + LPC_USB->USBUDCAH = (uint32_t)_dcd.udca; + LPC_USB->USBDMAIntEn = (DMA_INT_END_OF_XFER_MASK /*| DMA_INT_NEW_DD_REQUEST_MASK*/ | DMA_INT_ERROR_MASK); + + dcd_connect(rhport); + + // Clear pending IRQ + NVIC_ClearPendingIRQ(USB_IRQn); +} + +void dcd_int_enable(uint8_t rhport) +{ + (void)rhport; + NVIC_EnableIRQ(USB_IRQn); +} + +void dcd_int_disable(uint8_t rhport) +{ + (void)rhport; + NVIC_DisableIRQ(USB_IRQn); +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + // Response with status first before changing device address + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); + + sie_write(SIE_CMDCODE_SET_ADDRESS, 1, 0x80 | dev_addr); // 7th bit is : device_enable + + // Also Set Configure Device to enable non-control endpoint response + sie_write(SIE_CMDCODE_CONFIGURE_DEVICE, 1, 1); +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void)rhport; +} + +void dcd_connect(uint8_t rhport) +{ + (void)rhport; + sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, SIE_DEV_STATUS_CONNECT_STATUS_MASK); +} + +void dcd_disconnect(uint8_t rhport) +{ + (void)rhport; + sie_write(SIE_CMDCODE_DEVICE_STATUS, 1, 0); +} + +//--------------------------------------------------------------------+ +// CONTROL HELPER +//--------------------------------------------------------------------+ +static inline uint8_t byte2dword(uint8_t bytes) +{ + return (bytes + 3) / 4; // length in dwords +} + +static void control_ep_write(void const *buffer, uint8_t len) +{ + uint32_t const *buf32 = (uint32_t const *)buffer; + + LPC_USB->USBCtrl = USBCTRL_WRITE_ENABLE_MASK; // logical endpoint = 0 + LPC_USB->USBTxPLen = (uint32_t)len; + + for (uint8_t count = 0; count < byte2dword(len); count++) + { + LPC_USB->USBTxData = *buf32; // NOTE: cortex M3 have no problem with alignment + buf32++; + } + + LPC_USB->USBCtrl = 0; + + // select control IN & validate the endpoint + sie_write(SIE_CMDCODE_ENDPOINT_SELECT + 1, 0, 0); + sie_write(SIE_CMDCODE_BUFFER_VALIDATE, 0, 0); +} + +static uint8_t control_ep_read(void *buffer, uint8_t len) +{ + LPC_USB->USBCtrl = USBCTRL_READ_ENABLE_MASK; // logical endpoint = 0 + while ((LPC_USB->USBRxPLen & USBRXPLEN_PACKET_READY_MASK) == 0) + { + } // TODO blocking, should have timeout + + len = tu_min8(len, (uint8_t)(LPC_USB->USBRxPLen & USBRXPLEN_PACKET_LENGTH_MASK)); + uint32_t *buf32 = (uint32_t *)buffer; + + for (uint8_t count = 0; count < byte2dword(len); count++) + { + *buf32 = LPC_USB->USBRxData; + buf32++; + } + + LPC_USB->USBCtrl = 0; + + // select control OUT & clear the endpoint + sie_write(SIE_CMDCODE_ENDPOINT_SELECT + 0, 0, 0); + sie_write(SIE_CMDCODE_BUFFER_CLEAR, 0, 0); + + return len; +} + +//--------------------------------------------------------------------+ +// DCD Endpoint Port +//--------------------------------------------------------------------+ + +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc) +{ + (void)rhport; + + uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); + uint8_t const ep_id = ep_addr2idx(p_endpoint_desc->bEndpointAddress); + + // Endpoint type is fixed to endpoint number + // 1: interrupt, 2: Bulk, 3: Iso and so on + switch (p_endpoint_desc->bmAttributes.xfer) + { + case TUSB_XFER_INTERRUPT: + TU_ASSERT((epnum % 3) == 1); + break; + + case TUSB_XFER_BULK: + TU_ASSERT((epnum % 3) == 2 || (epnum == 15)); + break; + + case TUSB_XFER_ISOCHRONOUS: + TU_ASSERT((epnum % 3) == 0 && (epnum != 0) && (epnum != 15)); + break; + + default: + break; + } + + //------------- Realize Endpoint with Max Packet Size -------------// + const uint16_t ep_size = tu_edpt_packet_size(p_endpoint_desc); + set_ep_size(ep_id, ep_size); + + //------------- first DD prepare -------------// + dma_desc_t *const dd = &_dcd.dd[ep_id]; + tu_memclr(dd, sizeof(dma_desc_t)); + + dd->isochronous = (p_endpoint_desc->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) ? 1 : 0; + dd->max_packet_size = ep_size; + dd->retired = 1; // invalid at first + + sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + ep_id, 1, 0); // clear all endpoint status + + return true; +} + +void dcd_edpt_close_all(uint8_t rhport) +{ + (void)rhport; + // TODO implement dcd_edpt_close_all() +} + +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + + if (tu_edpt_number(ep_addr) == 0) + { + sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + 0, 1, SIE_SET_ENDPOINT_STALLED_MASK | SIE_SET_ENDPOINT_CONDITION_STALLED_MASK); + } + else + { + uint8_t ep_id = ep_addr2idx(ep_addr); + sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + ep_id, 1, SIE_SET_ENDPOINT_STALLED_MASK); + } +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + uint8_t ep_id = ep_addr2idx(ep_addr); + + sie_write(SIE_CMDCODE_ENDPOINT_SET_STATUS + ep_id, 1, 0); +} + +static bool control_xact(uint8_t rhport, uint8_t dir, uint8_t *buffer, uint8_t len) +{ + (void)rhport; + + if (dir) + { + _dcd.control.in_bytes = len; + control_ep_write(buffer, len); + } + else + { + if (_dcd.control.out_received) + { + // Already received the DATA OUT packet + _dcd.control.out_received = false; + _dcd.control.out_buffer = NULL; + _dcd.control.out_bytes = 0; + + uint8_t received = control_ep_read(buffer, len); + dcd_event_xfer_complete(0, 0, received, XFER_RESULT_SUCCESS, true); + } + else + { + _dcd.control.out_buffer = buffer; + _dcd.control.out_bytes = len; + } + } + + return true; +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + // Control transfer is not DMA support, and must be done in slave mode + if (tu_edpt_number(ep_addr) == 0) + { + return control_xact(rhport, tu_edpt_dir(ep_addr), buffer, (uint8_t)total_bytes); + } + else + { + uint8_t ep_id = ep_addr2idx(ep_addr); + dma_desc_t *dd = &_dcd.dd[ep_id]; + + // Prepare DMA descriptor + // Isochronous & max packet size must be preserved, Other fields of dd should be clear + uint16_t const ep_size = dd->max_packet_size; + uint8_t is_iso = dd->isochronous; + + tu_memclr(dd, sizeof(dma_desc_t)); + dd->isochronous = is_iso; + dd->max_packet_size = ep_size; + dd->buffer = (uint32_t)buffer; + dd->buflen = total_bytes; + + _dcd.udca[ep_id] = dd; + + if (ep_id % 2) + { + // Clear EP interrupt before Enable DMA + LPC_USB->USBEpIntEn &= ~TU_BIT(ep_id); + LPC_USB->USBEpDMAEn = TU_BIT(ep_id); + + // endpoint IN need to actively raise DMA request + LPC_USB->USBDMARSet = TU_BIT(ep_id); + } + else + { + // Enable DMA + LPC_USB->USBEpDMAEn = TU_BIT(ep_id); + } + + return true; + } +} + +//--------------------------------------------------------------------+ +// ISR +//--------------------------------------------------------------------+ + +// handle control xfer (slave mode) +static void control_xfer_isr(uint8_t rhport, uint32_t ep_int_status) +{ + // Control out complete + if (ep_int_status & TU_BIT(0)) + { + bool is_setup = sie_read(SIE_CMDCODE_ENDPOINT_SELECT + 0) & SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK; + + LPC_USB->USBEpIntClr = TU_BIT(0); + + if (is_setup) + { + uint8_t setup_packet[8]; + control_ep_read(setup_packet, 8); // TODO read before clear setup above + + dcd_event_setup_received(rhport, setup_packet, true); + } + else if (_dcd.control.out_buffer) + { + // software queued transfer previously + uint8_t received = control_ep_read(_dcd.control.out_buffer, _dcd.control.out_bytes); + + _dcd.control.out_buffer = NULL; + _dcd.control.out_bytes = 0; + + dcd_event_xfer_complete(rhport, 0, received, XFER_RESULT_SUCCESS, true); + } + else + { + // hardware auto ack packet -> mark as received + _dcd.control.out_received = true; + } + } + + // Control In complete + if (ep_int_status & TU_BIT(1)) + { + LPC_USB->USBEpIntClr = TU_BIT(1); + dcd_event_xfer_complete(rhport, TUSB_DIR_IN_MASK, _dcd.control.in_bytes, XFER_RESULT_SUCCESS, true); + } +} + +// handle bus event signal +static void bus_event_isr(uint8_t rhport) +{ + uint8_t const dev_status = sie_read(SIE_CMDCODE_DEVICE_STATUS); + if (dev_status & SIE_DEV_STATUS_RESET_MASK) + { + bus_reset(); + dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); + } + + if (dev_status & SIE_DEV_STATUS_CONNECT_CHANGE_MASK) + { + // device is disconnected, require using VBUS (P1_30) + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + + if (dev_status & SIE_DEV_STATUS_SUSPEND_CHANGE_MASK) + { + if (dev_status & SIE_DEV_STATUS_SUSPEND_MASK) + { + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + else + { + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + } +} + +// Helper to complete a DMA descriptor for non-control transfer +static void dd_complete_isr(uint8_t rhport, uint8_t ep_id) +{ + dma_desc_t *const dd = &_dcd.dd[ep_id]; + uint8_t result = (dd->status == DD_STATUS_NORMAL || dd->status == DD_STATUS_DATA_UNDERUN) ? XFER_RESULT_SUCCESS : XFER_RESULT_FAILED; + uint8_t const ep_addr = (ep_id / 2) | ((ep_id & 0x01) ? TUSB_DIR_IN_MASK : 0); + + dcd_event_xfer_complete(rhport, ep_addr, dd->present_count, result, true); +} + +// main USB IRQ handler +void dcd_int_handler(uint8_t rhport) +{ + uint32_t const dev_int_status = LPC_USB->USBDevIntSt & LPC_USB->USBDevIntEn; + LPC_USB->USBDevIntClr = dev_int_status; // Acknowledge handled interrupt + + // Bus event + if (dev_int_status & DEV_INT_DEVICE_STATUS_MASK) + { + bus_event_isr(rhport); + } + + // Endpoint interrupt + uint32_t const ep_int_status = LPC_USB->USBEpIntSt & LPC_USB->USBEpIntEn; + + // Control Endpoint are fast + if (dev_int_status & DEV_INT_ENDPOINT_FAST_MASK) + { + // Note clear USBEpIntClr will also clear the setup received bit --> clear after handle setup packet + // Only clear USBEpIntClr 1 endpoint each, and should wait for CDFULL bit set + control_xfer_isr(rhport, ep_int_status); + } + + // non-control IN are slow + if (dev_int_status & DEV_INT_ENDPOINT_SLOW_MASK) + { + for (uint8_t ep_id = 3; ep_id < DCD_ENDPOINT_MAX; ep_id += 2) + { + if (tu_bit_test(ep_int_status, ep_id)) + { + LPC_USB->USBEpIntClr = TU_BIT(ep_id); + + // Clear Ep interrupt for next DMA + LPC_USB->USBEpIntEn &= ~TU_BIT(ep_id); + + dd_complete_isr(rhport, ep_id); + } + } + } + + // DMA transfer complete (RAM <-> EP) for Non-Control + // OUT: USB transfer is fully complete + // IN : UBS transfer is still on-going -> enable EpIntEn to know when it is complete + uint32_t const dma_int_status = LPC_USB->USBDMAIntSt & LPC_USB->USBDMAIntEn; + if (dma_int_status & DMA_INT_END_OF_XFER_MASK) + { + uint32_t const eot = LPC_USB->USBEoTIntSt; + LPC_USB->USBEoTIntClr = eot; // acknowledge interrupt source + + for (uint8_t ep_id = 2; ep_id < DCD_ENDPOINT_MAX; ep_id++) + { + if (tu_bit_test(eot, ep_id)) + { + if (ep_id & 0x01) + { + // IN enable EpInt for end of usb transfer + LPC_USB->USBEpIntEn |= TU_BIT(ep_id); + } + else + { + // OUT + dd_complete_isr(rhport, ep_id); + } + } + } + } + + // Errors + if ((dev_int_status & DEV_INT_ERROR_MASK) || (dma_int_status & DMA_INT_ERROR_MASK)) + { + uint32_t error_status = sie_read(SIE_CMDCODE_READ_ERROR_STATUS); + (void)error_status; + TU_BREAKPOINT(); + } +} + +#endif diff --git a/uCNC/src/tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.h b/uCNC/src/tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.h new file mode 100644 index 000000000..136420513 --- /dev/null +++ b/uCNC/src/tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.h @@ -0,0 +1,161 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_DCD_LPC17_40_H_ +#define _TUSB_DCD_LPC17_40_H_ + +#include "../../../common/tusb_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + //--------------------------------------------------------------------+ + // Register Interface + //--------------------------------------------------------------------+ + + //------------- USB Interrupt USBIntSt -------------// + // enum { + // DCD_USB_REQ_LOW_PRIO_MASK = TU_BIT(0), + // DCD_USB_REQ_HIGH_PRIO_MASK = TU_BIT(1), + // DCD_USB_REQ_DMA_MASK = TU_BIT(2), + // DCD_USB_REQ_NEED_CLOCK_MASK = TU_BIT(8), + // DCD_USB_REQ_ENABLE_MASK = TU_BIT(31) + //}; + + //------------- Device Interrupt USBDevInt -------------// + enum + { + DEV_INT_FRAME_MASK = TU_BIT(0), + DEV_INT_ENDPOINT_FAST_MASK = TU_BIT(1), + DEV_INT_ENDPOINT_SLOW_MASK = TU_BIT(2), + DEV_INT_DEVICE_STATUS_MASK = TU_BIT(3), + DEV_INT_COMMAND_CODE_EMPTY_MASK = TU_BIT(4), + DEV_INT_COMMAND_DATA_FULL_MASK = TU_BIT(5), + DEV_INT_RX_ENDPOINT_PACKET_MASK = TU_BIT(6), + DEV_INT_TX_ENDPOINT_PACKET_MASK = TU_BIT(7), + DEV_INT_ENDPOINT_REALIZED_MASK = TU_BIT(8), + DEV_INT_ERROR_MASK = TU_BIT(9) + }; + + //------------- DMA Interrupt USBDMAInt-------------// + enum + { + DMA_INT_END_OF_XFER_MASK = TU_BIT(0), + DMA_INT_NEW_DD_REQUEST_MASK = TU_BIT(1), + DMA_INT_ERROR_MASK = TU_BIT(2) + }; + + //------------- USBCtrl -------------// + enum + { + USBCTRL_READ_ENABLE_MASK = TU_BIT(0), + USBCTRL_WRITE_ENABLE_MASK = TU_BIT(1), + }; + + //------------- USBRxPLen -------------// + enum + { + USBRXPLEN_PACKET_LENGTH_MASK = (TU_BIT(10) - 1), + USBRXPLEN_DATA_VALID_MASK = TU_BIT(10), + USBRXPLEN_PACKET_READY_MASK = TU_BIT(11), + }; + + //------------- SIE Command Code -------------// + typedef enum + { + SIE_CMDPHASE_WRITE = 1, + SIE_CMDPHASE_READ = 2, + SIE_CMDPHASE_COMMAND = 5 + } sie_cmdphase_t; + + enum + { + // device commands + SIE_CMDCODE_SET_ADDRESS = 0xd0, + SIE_CMDCODE_CONFIGURE_DEVICE = 0xd8, + SIE_CMDCODE_SET_MODE = 0xf3, + SIE_CMDCODE_READ_FRAME_NUMBER = 0xf5, + SIE_CMDCODE_READ_TEST_REGISTER = 0xfd, + SIE_CMDCODE_DEVICE_STATUS = 0xfe, + SIE_CMDCODE_GET_ERROR = 0xff, + SIE_CMDCODE_READ_ERROR_STATUS = 0xfb, + + // endpoint commands + SIE_CMDCODE_ENDPOINT_SELECT = 0x00, // + endpoint index + SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT = 0x40, // + endpoint index, should use USBEpIntClr instead + SIE_CMDCODE_ENDPOINT_SET_STATUS = 0x40, // + endpoint index + SIE_CMDCODE_BUFFER_CLEAR = 0xf2, + SIE_CMDCODE_BUFFER_VALIDATE = 0xfa + }; + + //------------- SIE Device Status (get/set from SIE_CMDCODE_DEVICE_STATUS) -------------// + enum + { + SIE_DEV_STATUS_CONNECT_STATUS_MASK = TU_BIT(0), + SIE_DEV_STATUS_CONNECT_CHANGE_MASK = TU_BIT(1), + SIE_DEV_STATUS_SUSPEND_MASK = TU_BIT(2), + SIE_DEV_STATUS_SUSPEND_CHANGE_MASK = TU_BIT(3), + SIE_DEV_STATUS_RESET_MASK = TU_BIT(4) + }; + + //------------- SIE Select Endpoint Command -------------// + enum + { + SIE_SELECT_ENDPOINT_FULL_EMPTY_MASK = TU_BIT(0), // 0: empty, 1 full. IN endpoint checks empty, OUT endpoint check full + SIE_SELECT_ENDPOINT_STALL_MASK = TU_BIT(1), + SIE_SELECT_ENDPOINT_SETUP_RECEIVED_MASK = TU_BIT(2), // clear by SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT + SIE_SELECT_ENDPOINT_PACKET_OVERWRITTEN_MASK = TU_BIT(3), // previous packet is overwritten by a SETUP packet + SIE_SELECT_ENDPOINT_NAK_MASK = TU_BIT(4), // last packet response is NAK (auto clear by an ACK) + SIE_SELECT_ENDPOINT_BUFFER1_FULL_MASK = TU_BIT(5), + SIE_SELECT_ENDPOINT_BUFFER2_FULL_MASK = TU_BIT(6) + }; + + typedef enum + { + SIE_SET_ENDPOINT_STALLED_MASK = TU_BIT(0), + SIE_SET_ENDPOINT_DISABLED_MASK = TU_BIT(5), + SIE_SET_ENDPOINT_RATE_FEEDBACK_MASK = TU_BIT(6), + SIE_SET_ENDPOINT_CONDITION_STALLED_MASK = TU_BIT(7), + } sie_endpoint_set_status_mask_t; + + //------------- DMA Descriptor Status -------------// + enum + { + DD_STATUS_NOT_SERVICED = 0, + DD_STATUS_BEING_SERVICED, + DD_STATUS_NORMAL, + DD_STATUS_DATA_UNDERUN, // short packet + DD_STATUS_DATA_OVERRUN, + DD_STATUS_SYSTEM_ERROR + }; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/uCNC/src/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/uCNC/src/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index c2db3e75e..37a996236 100644 --- a/uCNC/src/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/uCNC/src/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -104,14 +104,14 @@ #include "../../../tusb_option.h" #if defined(STM32F102x6) || defined(STM32F102xB) || \ - defined(STM32F103x6) || defined(STM32F103xB) || \ - defined(STM32F103xE) || defined(STM32F103xG) + defined(STM32F103x6) || defined(STM32F103xB) || \ + defined(STM32F103xE) || defined(STM32F103xG) #define STM32F1_FSDEV #endif #if TUSB_OPT_DEVICE_ENABLED && \ - (TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4) || \ - (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV))) + (TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F3, OPT_MCU_STM32L0, OPT_MCU_STM32L1, OPT_MCU_STM32G4) || \ + (TU_CHECK_MCU(OPT_MCU_STM32F1) && defined(STM32F1_FSDEV))) // In order to reduce the dependance on HAL, we undefine this. // Some definitions are copied to our private include file. @@ -153,27 +153,27 @@ TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware"); TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH)) <= (PMA_LENGTH), - "BTABLE does not fit in PMA RAM"); + "BTABLE does not fit in PMA RAM"); TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes"); // One of these for every EP IN & OUT, uses a bit of RAM.... typedef struct { - uint8_t *buffer; - // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API - uint16_t total_len; - uint16_t queued_len; - uint16_t pma_ptr; - uint8_t max_packet_size; - uint8_t pma_alloc_size; + uint8_t *buffer; + // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API + uint16_t total_len; + uint16_t queued_len; + uint16_t pma_ptr; + uint8_t max_packet_size; + uint8_t pma_alloc_size; } xfer_ctl_t; static xfer_ctl_t xfer_status[MAX_EP_COUNT][2]; static inline xfer_ctl_t *xfer_ctl_ptr(uint32_t epnum, uint32_t dir) { - return &xfer_status[epnum][dir]; + return &xfer_status[epnum][dir]; } static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6]; @@ -201,58 +201,58 @@ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN // This seems better than having to do type casts everywhere else static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) { - *reg = (uint16_t)(*reg & ~mask); + *reg = (uint16_t)(*reg & ~mask); } // Bits in ISTR are cleared upon writing 0 static inline void clear_istr_bits(uint16_t mask) { - USB->ISTR = ~mask; + USB->ISTR = ~mask; } void dcd_init(uint8_t rhport) { - /* Clocks should already be enabled */ - /* Use __HAL_RCC_USB_CLK_ENABLE(); to enable the clocks before calling this function */ - - /* The RM mentions to use a special ordering of PDWN and FRES, but this isn't done in HAL. - * Here, the RM is followed. */ - - for (uint32_t i = 0; i < 200; i++) // should be a few us - { - asm("NOP"); - } - // Perform USB peripheral reset - USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN; - for (uint32_t i = 0; i < 200; i++) // should be a few us - { - asm("NOP"); - } - reg16_clear_bits(&USB->CNTR, USB_CNTR_PDWN); // Remove powerdown - // Wait startup time, for F042 and F070, this is <= 1 us. - for (uint32_t i = 0; i < 200; i++) // should be a few us - { - asm("NOP"); - } - USB->CNTR = 0; // Enable USB - - USB->BTABLE = DCD_STM32_BTABLE_BASE; - - USB->ISTR = 0; // Clear pending interrupts - - // Reset endpoints to disabled - for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) - { - // This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED. - pcd_set_endpoint(USB, i, 0u); - } - - USB->CNTR |= USB_CNTR_RESETM | (USE_SOF ? USB_CNTR_SOFM : 0) | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM; - dcd_handle_bus_reset(); - - // Enable pull-up if supported - if (dcd_connect) - dcd_connect(rhport); + /* Clocks should already be enabled */ + /* Use __HAL_RCC_USB_CLK_ENABLE(); to enable the clocks before calling this function */ + + /* The RM mentions to use a special ordering of PDWN and FRES, but this isn't done in HAL. + * Here, the RM is followed. */ + + for (uint32_t i = 0; i < 200; i++) // should be a few us + { + asm("NOP"); + } + // Perform USB peripheral reset + USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN; + for (uint32_t i = 0; i < 200; i++) // should be a few us + { + asm("NOP"); + } + reg16_clear_bits(&USB->CNTR, USB_CNTR_PDWN); // Remove powerdown + // Wait startup time, for F042 and F070, this is <= 1 us. + for (uint32_t i = 0; i < 200; i++) // should be a few us + { + asm("NOP"); + } + USB->CNTR = 0; // Enable USB + + USB->BTABLE = DCD_STM32_BTABLE_BASE; + + USB->ISTR = 0; // Clear pending interrupts + + // Reset endpoints to disabled + for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) + { + // This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED. + pcd_set_endpoint(USB, i, 0u); + } + + USB->CNTR |= USB_CNTR_RESETM | (USE_SOF ? USB_CNTR_SOFM : 0) | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM; + dcd_handle_bus_reset(); + + // Enable pull-up if supported + if (dcd_connect) + dcd_connect(rhport); } // Define only on MCU with internal pull-up. BSP can define on MCU without internal PU. @@ -261,73 +261,73 @@ void dcd_init(uint8_t rhport) // Disable internal D+ PU void dcd_disconnect(uint8_t rhport) { - (void)rhport; - USB->BCDR &= ~(USB_BCDR_DPPU); + (void)rhport; + USB->BCDR &= ~(USB_BCDR_DPPU); } // Enable internal D+ PU void dcd_connect(uint8_t rhport) { - (void)rhport; - USB->BCDR |= USB_BCDR_DPPU; + (void)rhport; + USB->BCDR |= USB_BCDR_DPPU; } #elif defined(SYSCFG_PMC_USB_PU) // works e.g. on STM32L151 // Disable internal D+ PU void dcd_disconnect(uint8_t rhport) { - (void)rhport; - SYSCFG->PMC &= ~(SYSCFG_PMC_USB_PU); + (void)rhport; + SYSCFG->PMC &= ~(SYSCFG_PMC_USB_PU); } // Enable internal D+ PU void dcd_connect(uint8_t rhport) { - (void)rhport; - SYSCFG->PMC |= SYSCFG_PMC_USB_PU; + (void)rhport; + SYSCFG->PMC |= SYSCFG_PMC_USB_PU; } #endif // Enable device interrupt void dcd_int_enable(uint8_t rhport) { - (void)rhport; - // Member here forces write to RAM before allowing ISR to execute - __DSB(); - __ISB(); + (void)rhport; + // Member here forces write to RAM before allowing ISR to execute + __DSB(); + __ISB(); #if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 - NVIC_EnableIRQ(USB_IRQn); + NVIC_EnableIRQ(USB_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32L1 - NVIC_EnableIRQ(USB_LP_IRQn); + NVIC_EnableIRQ(USB_LP_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32F3 // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from // shared USB/CAN IRQs to separate CAN and USB IRQs. // This dynamically checks if this remap is active to enable the right IRQs. #ifdef SYSCFG_CFGR1_USB_IT_RMP - if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) - { - NVIC_EnableIRQ(USB_HP_IRQn); - NVIC_EnableIRQ(USB_LP_IRQn); - NVIC_EnableIRQ(USBWakeUp_RMP_IRQn); - } - else + if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) + { + NVIC_EnableIRQ(USB_HP_IRQn); + NVIC_EnableIRQ(USB_LP_IRQn); + NVIC_EnableIRQ(USBWakeUp_RMP_IRQn); + } + else #endif - { - NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn); - NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); - NVIC_EnableIRQ(USBWakeUp_IRQn); - } + { + NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn); + NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); + NVIC_EnableIRQ(USBWakeUp_IRQn); + } #elif CFG_TUSB_MCU == OPT_MCU_STM32F1 - NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn); - NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn); - NVIC_EnableIRQ(USBWakeUp_IRQn); + NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn); + NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn); + NVIC_EnableIRQ(USBWakeUp_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32G4 - NVIC_EnableIRQ(USB_HP_IRQn); - NVIC_EnableIRQ(USB_LP_IRQn); - NVIC_EnableIRQ(USBWakeUp_IRQn); + NVIC_EnableIRQ(USB_HP_IRQn); + NVIC_EnableIRQ(USB_LP_IRQn); + NVIC_EnableIRQ(USBWakeUp_IRQn); #else #error Unknown arch in USB driver @@ -337,104 +337,104 @@ void dcd_int_enable(uint8_t rhport) // Disable device interrupt void dcd_int_disable(uint8_t rhport) { - (void)rhport; + (void)rhport; #if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0 - NVIC_DisableIRQ(USB_IRQn); + NVIC_DisableIRQ(USB_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32L1 - NVIC_DisableIRQ(USB_LP_IRQn); + NVIC_DisableIRQ(USB_LP_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32F3 // Some STM32F302/F303 devices allow to remap the USB interrupt vectors from // shared USB/CAN IRQs to separate CAN and USB IRQs. // This dynamically checks if this remap is active to disable the right IRQs. #ifdef SYSCFG_CFGR1_USB_IT_RMP - if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) - { - NVIC_DisableIRQ(USB_HP_IRQn); - NVIC_DisableIRQ(USB_LP_IRQn); - NVIC_DisableIRQ(USBWakeUp_RMP_IRQn); - } - else + if (SYSCFG->CFGR1 & SYSCFG_CFGR1_USB_IT_RMP) + { + NVIC_DisableIRQ(USB_HP_IRQn); + NVIC_DisableIRQ(USB_LP_IRQn); + NVIC_DisableIRQ(USBWakeUp_RMP_IRQn); + } + else #endif - { - NVIC_DisableIRQ(USB_HP_CAN_TX_IRQn); - NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn); - NVIC_DisableIRQ(USBWakeUp_IRQn); - } + { + NVIC_DisableIRQ(USB_HP_CAN_TX_IRQn); + NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn); + NVIC_DisableIRQ(USBWakeUp_IRQn); + } #elif CFG_TUSB_MCU == OPT_MCU_STM32F1 - NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn); - NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn); - NVIC_DisableIRQ(USBWakeUp_IRQn); + NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn); + NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn); + NVIC_DisableIRQ(USBWakeUp_IRQn); #elif CFG_TUSB_MCU == OPT_MCU_STM32G4 - NVIC_DisableIRQ(USB_HP_IRQn); - NVIC_DisableIRQ(USB_LP_IRQn); - NVIC_DisableIRQ(USBWakeUp_IRQn); + NVIC_DisableIRQ(USB_HP_IRQn); + NVIC_DisableIRQ(USB_LP_IRQn); + NVIC_DisableIRQ(USBWakeUp_IRQn); #else #error Unknown arch in USB driver #endif - // CMSIS has a membar after disabling interrupts + // CMSIS has a membar after disabling interrupts } // Receive Set Address request, mcu port must also include status IN response void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void)rhport; - (void)dev_addr; + (void)rhport; + (void)dev_addr; - // Respond with status - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); + // Respond with status + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); - // DCD can only set address after status for this request is complete. - // do it at dcd_edpt0_status_complete() + // DCD can only set address after status for this request is complete. + // do it at dcd_edpt0_status_complete() } void dcd_remote_wakeup(uint8_t rhport) { - (void)rhport; + (void)rhport; - USB->CNTR |= (uint16_t)USB_CNTR_RESUME; - remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms. + USB->CNTR |= (uint16_t)USB_CNTR_RESUME; + remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms. } static const tusb_desc_endpoint_t ep0OUT_desc = - { - .bLength = sizeof(tusb_desc_endpoint_t), - .bDescriptorType = TUSB_DESC_ENDPOINT, + { + .bLength = sizeof(tusb_desc_endpoint_t), + .bDescriptorType = TUSB_DESC_ENDPOINT, - .bEndpointAddress = 0x00, - .bmAttributes = {.xfer = TUSB_XFER_CONTROL}, - .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, - .bInterval = 0}; + .bEndpointAddress = 0x00, + .bmAttributes = {.xfer = TUSB_XFER_CONTROL}, + .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, + .bInterval = 0}; static const tusb_desc_endpoint_t ep0IN_desc = - { - .bLength = sizeof(tusb_desc_endpoint_t), - .bDescriptorType = TUSB_DESC_ENDPOINT, + { + .bLength = sizeof(tusb_desc_endpoint_t), + .bDescriptorType = TUSB_DESC_ENDPOINT, - .bEndpointAddress = 0x80, - .bmAttributes = {.xfer = TUSB_XFER_CONTROL}, - .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, - .bInterval = 0}; + .bEndpointAddress = 0x80, + .bmAttributes = {.xfer = TUSB_XFER_CONTROL}, + .wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE, + .bInterval = 0}; static void dcd_handle_bus_reset(void) { - //__IO uint16_t * const epreg = &(EPREG(0)); - USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag + //__IO uint16_t * const epreg = &(EPREG(0)); + USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag - // Clear all EPREG (or maybe this is automatic? I'm not sure) - for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) - { - pcd_set_endpoint(USB, i, 0u); - } + // Clear all EPREG (or maybe this is automatic? I'm not sure) + for (uint32_t i = 0; i < STFSDEV_EP_COUNT; i++) + { + pcd_set_endpoint(USB, i, 0u); + } - dcd_pma_alloc_reset(); - dcd_edpt_open(0, &ep0OUT_desc); - dcd_edpt_open(0, &ep0IN_desc); + dcd_pma_alloc_reset(); + dcd_edpt_open(0, &ep0OUT_desc); + dcd_edpt_open(0, &ep0IN_desc); - USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero. + USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero. } // Handle CTR interrupt for the TX/IN direction @@ -442,28 +442,28 @@ static void dcd_handle_bus_reset(void) // Upon call, (wIstr & USB_ISTR_DIR) == 0U static void dcd_ep_ctr_tx_handler(uint32_t wIstr) { - uint32_t EPindex = wIstr & USB_ISTR_EP_ID; - uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex); - - // Verify the CTR_TX bit is set. This was in the ST Micro code, - // but I'm not sure it's actually necessary? - if ((wEPRegVal & USB_EP_CTR_TX) == 0U) - { - return; - } - - /* clear int flag */ - pcd_clear_tx_ep_ctr(USB, EPindex); - - xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex, TUSB_DIR_IN); - if ((xfer->total_len != xfer->queued_len)) /* TX not complete */ - { - dcd_transmit_packet(xfer, EPindex); - } - else /* TX Complete */ - { - dcd_event_xfer_complete(0, (uint8_t)(0x80 + EPindex), xfer->total_len, XFER_RESULT_SUCCESS, true); - } + uint32_t EPindex = wIstr & USB_ISTR_EP_ID; + uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex); + + // Verify the CTR_TX bit is set. This was in the ST Micro code, + // but I'm not sure it's actually necessary? + if ((wEPRegVal & USB_EP_CTR_TX) == 0U) + { + return; + } + + /* clear int flag */ + pcd_clear_tx_ep_ctr(USB, EPindex); + + xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex, TUSB_DIR_IN); + if ((xfer->total_len != xfer->queued_len)) /* TX not complete */ + { + dcd_transmit_packet(xfer, EPindex); + } + else /* TX Complete */ + { + dcd_event_xfer_complete(0, (uint8_t)(0x80 + EPindex), xfer->total_len, XFER_RESULT_SUCCESS, true); + } } // Handle CTR interrupt for the RX/OUT direction @@ -471,44 +471,44 @@ static void dcd_ep_ctr_tx_handler(uint32_t wIstr) // Upon call, (wIstr & USB_ISTR_DIR) == 0U static void dcd_ep_ctr_rx_handler(uint32_t wIstr) { - uint32_t EPindex = wIstr & USB_ISTR_EP_ID; - uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex); - uint32_t count = pcd_get_ep_rx_cnt(USB, EPindex); - - xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex, TUSB_DIR_OUT); - - // Verify the CTR_RX bit is set. This was in the ST Micro code, - // but I'm not sure it's actually necessary? - if ((wEPRegVal & USB_EP_CTR_RX) == 0U) - { - return; - } - - if ((EPindex == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */ - { - // The setup_received function uses memcpy, so this must first copy the setup data into - // user memory, to allow for the 32-bit access that memcpy performs. - uint8_t userMemBuf[8]; - /* Get SETUP Packet*/ - if (count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again. - { - // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here) - pcd_set_ep_rx_status(USB, 0u, USB_EP_RX_NAK); - pcd_set_ep_tx_status(USB, 0u, USB_EP_TX_NAK); - dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB, EPindex), 8); - dcd_event_setup_received(0, (uint8_t *)userMemBuf, true); - } - } - else - { - // Clear RX CTR interrupt flag - if (EPindex != 0u) - { - pcd_clear_rx_ep_ctr(USB, EPindex); - } - - if (count != 0U) - { + uint32_t EPindex = wIstr & USB_ISTR_EP_ID; + uint32_t wEPRegVal = pcd_get_endpoint(USB, EPindex); + uint32_t count = pcd_get_ep_rx_cnt(USB, EPindex); + + xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex, TUSB_DIR_OUT); + + // Verify the CTR_RX bit is set. This was in the ST Micro code, + // but I'm not sure it's actually necessary? + if ((wEPRegVal & USB_EP_CTR_RX) == 0U) + { + return; + } + + if ((EPindex == 0U) && ((wEPRegVal & USB_EP_SETUP) != 0U)) /* Setup packet */ + { + // The setup_received function uses memcpy, so this must first copy the setup data into + // user memory, to allow for the 32-bit access that memcpy performs. + uint8_t userMemBuf[8]; + /* Get SETUP Packet*/ + if (count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again. + { + // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here) + pcd_set_ep_rx_status(USB, 0u, USB_EP_RX_NAK); + pcd_set_ep_tx_status(USB, 0u, USB_EP_TX_NAK); + dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB, EPindex), 8); + dcd_event_setup_received(0, (uint8_t *)userMemBuf, true); + } + } + else + { + // Clear RX CTR interrupt flag + if (EPindex != 0u) + { + pcd_clear_rx_ep_ctr(USB, EPindex); + } + + if (count != 0U) + { #if 0 // TODO support dcd_edpt_xfer_fifo API if (xfer->ff) { @@ -516,137 +516,137 @@ static void dcd_ep_ctr_rx_handler(uint32_t wIstr) } else #endif - { - dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), *pcd_ep_rx_address_ptr(USB, EPindex), count); - } - - xfer->queued_len = (uint16_t)(xfer->queued_len + count); - } - - if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) - { - /* RX COMPLETE */ - dcd_event_xfer_complete(0, EPindex, xfer->queued_len, XFER_RESULT_SUCCESS, true); - // Though the host could still send, we don't know. - // Does the bulk pipe need to be reset to valid to allow for a ZLP? - } - else - { - uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len; - if (remaining >= xfer->max_packet_size) - { - pcd_set_ep_rx_cnt(USB, EPindex, xfer->max_packet_size); - } - else - { - pcd_set_ep_rx_cnt(USB, EPindex, remaining); - } - pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID); - } - } - - // For EP0, prepare to receive another SETUP packet. - // Clear CTR last so that a new packet does not overwrite the packing being read. - // (Based on the docs, it seems SETUP will always be accepted after CTR is cleared) - if (EPindex == 0u) - { - // Always be prepared for a status packet... - pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE); - pcd_clear_rx_ep_ctr(USB, EPindex); - } + { + dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]), *pcd_ep_rx_address_ptr(USB, EPindex), count); + } + + xfer->queued_len = (uint16_t)(xfer->queued_len + count); + } + + if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len)) + { + /* RX COMPLETE */ + dcd_event_xfer_complete(0, EPindex, xfer->queued_len, XFER_RESULT_SUCCESS, true); + // Though the host could still send, we don't know. + // Does the bulk pipe need to be reset to valid to allow for a ZLP? + } + else + { + uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len; + if (remaining >= xfer->max_packet_size) + { + pcd_set_ep_rx_cnt(USB, EPindex, xfer->max_packet_size); + } + else + { + pcd_set_ep_rx_cnt(USB, EPindex, remaining); + } + pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID); + } + } + + // For EP0, prepare to receive another SETUP packet. + // Clear CTR last so that a new packet does not overwrite the packing being read. + // (Based on the docs, it seems SETUP will always be accepted after CTR is cleared) + if (EPindex == 0u) + { + // Always be prepared for a status packet... + pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE); + pcd_clear_rx_ep_ctr(USB, EPindex); + } } static void dcd_ep_ctr_handler(void) { - uint32_t wIstr; - - /* stay in loop while pending interrupts */ - while (((wIstr = USB->ISTR) & USB_ISTR_CTR) != 0U) - { - - if ((wIstr & USB_ISTR_DIR) == 0U) /* TX/IN */ - { - dcd_ep_ctr_tx_handler(wIstr); - } - else /* RX/OUT*/ - { - dcd_ep_ctr_rx_handler(wIstr); - } - } + uint32_t wIstr; + + /* stay in loop while pending interrupts */ + while (((wIstr = USB->ISTR) & USB_ISTR_CTR) != 0U) + { + + if ((wIstr & USB_ISTR_DIR) == 0U) /* TX/IN */ + { + dcd_ep_ctr_tx_handler(wIstr); + } + else /* RX/OUT*/ + { + dcd_ep_ctr_rx_handler(wIstr); + } + } } void dcd_int_handler(uint8_t rhport) { - (void)rhport; - - uint32_t int_status = USB->ISTR; - // const uint32_t handled_ints = USB_ISTR_CTR | USB_ISTR_RESET | USB_ISTR_WKUP - // | USB_ISTR_SUSP | USB_ISTR_SOF | USB_ISTR_ESOF; - // unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_L1REQ ) - - // The ST driver loops here on the CTR bit, but that loop has been moved into the - // dcd_ep_ctr_handler(), so less need to loop here. The other interrupts shouldn't - // be triggered repeatedly. - - if (int_status & USB_ISTR_RESET) - { - // USBRST is start of reset. - clear_istr_bits(USB_ISTR_RESET); - dcd_handle_bus_reset(); - dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); - return; // Don't do the rest of the things here; perhaps they've been cleared? - } - - if (int_status & USB_ISTR_CTR) - { - /* servicing of the endpoint correct transfer interrupt */ - /* clear of the CTR flag into the sub */ - dcd_ep_ctr_handler(); - } - - if (int_status & USB_ISTR_WKUP) - { - reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE); - reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP); - clear_istr_bits(USB_ISTR_WKUP); - dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); - } - - if (int_status & USB_ISTR_SUSP) - { - /* Suspend is asserted for both suspend and unplug events. without Vbus monitoring, - * these events cannot be differentiated, so we only trigger suspend. */ - - /* Force low-power mode in the macrocell */ - USB->CNTR |= USB_CNTR_FSUSP; - USB->CNTR |= USB_CNTR_LPMODE; - - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - clear_istr_bits(USB_ISTR_SUSP); - dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); - } + (void)rhport; + + uint32_t int_status = USB->ISTR; + // const uint32_t handled_ints = USB_ISTR_CTR | USB_ISTR_RESET | USB_ISTR_WKUP + // | USB_ISTR_SUSP | USB_ISTR_SOF | USB_ISTR_ESOF; + // unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_L1REQ ) + + // The ST driver loops here on the CTR bit, but that loop has been moved into the + // dcd_ep_ctr_handler(), so less need to loop here. The other interrupts shouldn't + // be triggered repeatedly. + + if (int_status & USB_ISTR_RESET) + { + // USBRST is start of reset. + clear_istr_bits(USB_ISTR_RESET); + dcd_handle_bus_reset(); + dcd_event_bus_reset(0, TUSB_SPEED_FULL, true); + return; // Don't do the rest of the things here; perhaps they've been cleared? + } + + if (int_status & USB_ISTR_CTR) + { + /* servicing of the endpoint correct transfer interrupt */ + /* clear of the CTR flag into the sub */ + dcd_ep_ctr_handler(); + } + + if (int_status & USB_ISTR_WKUP) + { + reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE); + reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP); + clear_istr_bits(USB_ISTR_WKUP); + dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); + } + + if (int_status & USB_ISTR_SUSP) + { + /* Suspend is asserted for both suspend and unplug events. without Vbus monitoring, + * these events cannot be differentiated, so we only trigger suspend. */ + + /* Force low-power mode in the macrocell */ + USB->CNTR |= USB_CNTR_FSUSP; + USB->CNTR |= USB_CNTR_LPMODE; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + clear_istr_bits(USB_ISTR_SUSP); + dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true); + } #if USE_SOF - if (int_status & USB_ISTR_SOF) - { - clear_istr_bits(USB_ISTR_SOF); - dcd_event_bus_signal(0, DCD_EVENT_SOF, true); - } + if (int_status & USB_ISTR_SOF) + { + clear_istr_bits(USB_ISTR_SOF); + dcd_event_bus_signal(0, DCD_EVENT_SOF, true); + } #endif - if (int_status & USB_ISTR_ESOF) - { - if (remoteWakeCountdown == 1u) - { - USB->CNTR &= (uint16_t)(~USB_CNTR_RESUME); - } - if (remoteWakeCountdown > 0u) - { - remoteWakeCountdown--; - } - clear_istr_bits(USB_ISTR_ESOF); - } + if (int_status & USB_ISTR_ESOF) + { + if (remoteWakeCountdown == 1u) + { + USB->CNTR &= (uint16_t)(~USB_CNTR_RESUME); + } + if (remoteWakeCountdown > 0u) + { + remoteWakeCountdown--; + } + clear_istr_bits(USB_ISTR_ESOF); + } } //--------------------------------------------------------------------+ @@ -657,31 +657,31 @@ void dcd_int_handler(uint8_t rhport) // May help DCD to prepare for next control transfer, this API is optional. void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { - (void)rhport; - - if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && - request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && - request->bRequest == TUSB_REQ_SET_ADDRESS) - { - uint8_t const dev_addr = (uint8_t)request->wValue; - - // Setting new address after the whole request is complete - reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD); - USB->DADDR = (uint16_t)(USB->DADDR | dev_addr); // leave the enable bit set - } + (void)rhport; + + if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && + request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && + request->bRequest == TUSB_REQ_SET_ADDRESS) + { + uint8_t const dev_addr = (uint8_t)request->wValue; + + // Setting new address after the whole request is complete + reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD); + USB->DADDR = (uint16_t)(USB->DADDR | dev_addr); // leave the enable bit set + } } static void dcd_pma_alloc_reset(void) { - ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8 * MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each) - // TU_LOG2("dcd_pma_alloc_reset()\r\n"); - for (uint32_t i = 0; i < MAX_EP_COUNT; i++) - { - xfer_ctl_ptr(i, TUSB_DIR_OUT)->pma_alloc_size = 0U; - xfer_ctl_ptr(i, TUSB_DIR_IN)->pma_alloc_size = 0U; - xfer_ctl_ptr(i, TUSB_DIR_OUT)->pma_ptr = 0U; - xfer_ctl_ptr(i, TUSB_DIR_IN)->pma_ptr = 0U; - } + ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8 * MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each) + // TU_LOG2("dcd_pma_alloc_reset()\r\n"); + for (uint32_t i = 0; i < MAX_EP_COUNT; i++) + { + xfer_ctl_ptr(i, TUSB_DIR_OUT)->pma_alloc_size = 0U; + xfer_ctl_ptr(i, TUSB_DIR_IN)->pma_alloc_size = 0U; + xfer_ctl_ptr(i, TUSB_DIR_OUT)->pma_ptr = 0U; + xfer_ctl_ptr(i, TUSB_DIR_IN)->pma_ptr = 0U; + } } /*** @@ -695,29 +695,29 @@ static void dcd_pma_alloc_reset(void) */ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) { - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t *epXferCtl = xfer_ctl_ptr(epnum, dir); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + xfer_ctl_t *epXferCtl = xfer_ctl_ptr(epnum, dir); - if (epXferCtl->pma_alloc_size != 0U) - { - // TU_LOG2("dcd_pma_alloc(%x,%x)=%x (cached)\r\n",ep_addr,length,epXferCtl->pma_ptr); - // Previously allocated - TU_ASSERT(length <= epXferCtl->pma_alloc_size, 0xFFFF); // Verify no larger than previous alloc - return epXferCtl->pma_ptr; - } + if (epXferCtl->pma_alloc_size != 0U) + { + // TU_LOG2("dcd_pma_alloc(%x,%x)=%x (cached)\r\n",ep_addr,length,epXferCtl->pma_ptr); + // Previously allocated + TU_ASSERT(length <= epXferCtl->pma_alloc_size, 0xFFFF); // Verify no larger than previous alloc + return epXferCtl->pma_ptr; + } - uint16_t addr = ep_buf_ptr; - ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer + uint16_t addr = ep_buf_ptr; + ep_buf_ptr = (uint16_t)(ep_buf_ptr + length); // increment buffer pointer - // Verify no overflow - TU_ASSERT(ep_buf_ptr <= PMA_LENGTH, 0xFFFF); + // Verify no overflow + TU_ASSERT(ep_buf_ptr <= PMA_LENGTH, 0xFFFF); - epXferCtl->pma_ptr = addr; - epXferCtl->pma_alloc_size = length; - // TU_LOG2("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr); + epXferCtl->pma_ptr = addr; + epXferCtl->pma_alloc_size = length; + // TU_LOG2("dcd_pma_alloc(%x,%x)=%x\r\n",ep_addr,length,addr); - return addr; + return addr; } /*** @@ -725,29 +725,29 @@ static uint16_t dcd_pma_alloc(uint8_t ep_addr, size_t length) */ static void dcd_pma_free(uint8_t ep_addr) { - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - // Presently, this should never be called for EP0 IN/OUT - TU_ASSERT(open_ep_count > 2, /**/); - TU_ASSERT(xfer_ctl_ptr(epnum, dir)->max_packet_size != 0, /**/); - open_ep_count--; - - // If count is 2, only EP0 should be open, so allocations can be mostly reset. - - if (open_ep_count == 2) - { - ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8 * MAX_EP_COUNT + 2 * CFG_TUD_ENDPOINT0_SIZE; // 8 bytes per endpoint (two TX and two RX words, each), and EP0 - - // Skip EP0 - for (uint32_t i = 1; i < MAX_EP_COUNT; i++) - { - xfer_ctl_ptr(i, TUSB_DIR_OUT)->pma_alloc_size = 0U; - xfer_ctl_ptr(i, TUSB_DIR_IN)->pma_alloc_size = 0U; - xfer_ctl_ptr(i, TUSB_DIR_OUT)->pma_ptr = 0U; - xfer_ctl_ptr(i, TUSB_DIR_IN)->pma_ptr = 0U; - } - } + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + // Presently, this should never be called for EP0 IN/OUT + TU_ASSERT(open_ep_count > 2, /**/); + TU_ASSERT(xfer_ctl_ptr(epnum, dir)->max_packet_size != 0, /**/); + open_ep_count--; + + // If count is 2, only EP0 should be open, so allocations can be mostly reset. + + if (open_ep_count == 2) + { + ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8 * MAX_EP_COUNT + 2 * CFG_TUD_ENDPOINT0_SIZE; // 8 bytes per endpoint (two TX and two RX words, each), and EP0 + + // Skip EP0 + for (uint32_t i = 1; i < MAX_EP_COUNT; i++) + { + xfer_ctl_ptr(i, TUSB_DIR_OUT)->pma_alloc_size = 0U; + xfer_ctl_ptr(i, TUSB_DIR_IN)->pma_alloc_size = 0U; + xfer_ctl_ptr(i, TUSB_DIR_OUT)->pma_ptr = 0U; + xfer_ctl_ptr(i, TUSB_DIR_IN)->pma_ptr = 0U; + } + } } // The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers, @@ -755,73 +755,73 @@ static void dcd_pma_free(uint8_t ep_addr) bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *p_endpoint_desc) { - (void)rhport; - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); - const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc); - uint16_t pma_addr; - uint32_t wType; - - // Isochronous not supported (yet), and some other driver assumptions. - TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); - TU_ASSERT(epnum < MAX_EP_COUNT); - - // Set type - switch (p_endpoint_desc->bmAttributes.xfer) - { - case TUSB_XFER_CONTROL: - wType = USB_EP_CONTROL; - break; + (void)rhport; + uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + const uint16_t epMaxPktSize = tu_edpt_packet_size(p_endpoint_desc); + uint16_t pma_addr; + uint32_t wType; + + // Isochronous not supported (yet), and some other driver assumptions. + TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); + TU_ASSERT(epnum < MAX_EP_COUNT); + + // Set type + switch (p_endpoint_desc->bmAttributes.xfer) + { + case TUSB_XFER_CONTROL: + wType = USB_EP_CONTROL; + break; #if (0) - case TUSB_XFER_ISOCHRONOUS: // FIXME: Not yet supported - wType = USB_EP_ISOCHRONOUS; - break; + case TUSB_XFER_ISOCHRONOUS: // FIXME: Not yet supported + wType = USB_EP_ISOCHRONOUS; + break; #endif - case TUSB_XFER_BULK: - wType = USB_EP_CONTROL; - break; - - case TUSB_XFER_INTERRUPT: - wType = USB_EP_INTERRUPT; - break; - - default: - TU_ASSERT(false); - } - - pcd_set_eptype(USB, epnum, wType); - pcd_set_ep_address(USB, epnum, epnum); - // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) - // or being double-buffered (bulk endpoints) - pcd_clear_ep_kind(USB, 0); - - pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, epMaxPktSize); - - if (dir == TUSB_DIR_IN) - { - *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; - pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize); - pcd_clear_tx_dtog(USB, epnum); - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK); - } - else - { - *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; - pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize); - pcd_clear_rx_dtog(USB, epnum); - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); - } - - xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize; - - return true; + case TUSB_XFER_BULK: + wType = USB_EP_CONTROL; + break; + + case TUSB_XFER_INTERRUPT: + wType = USB_EP_INTERRUPT; + break; + + default: + TU_ASSERT(false); + } + + pcd_set_eptype(USB, epnum, wType); + pcd_set_ep_address(USB, epnum, epnum); + // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint) + // or being double-buffered (bulk endpoints) + pcd_clear_ep_kind(USB, 0); + + pma_addr = dcd_pma_alloc(p_endpoint_desc->bEndpointAddress, epMaxPktSize); + + if (dir == TUSB_DIR_IN) + { + *pcd_ep_tx_address_ptr(USB, epnum) = pma_addr; + pcd_set_ep_tx_cnt(USB, epnum, epMaxPktSize); + pcd_clear_tx_dtog(USB, epnum); + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_NAK); + } + else + { + *pcd_ep_rx_address_ptr(USB, epnum) = pma_addr; + pcd_set_ep_rx_cnt(USB, epnum, epMaxPktSize); + pcd_clear_rx_dtog(USB, epnum); + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK); + } + + xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize; + + return true; } void dcd_edpt_close_all(uint8_t rhport) { - (void)rhport; - // TODO implement dcd_edpt_close_all() + (void)rhport; + // TODO implement dcd_edpt_close_all() } /** @@ -833,33 +833,33 @@ void dcd_edpt_close_all(uint8_t rhport) */ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - uint32_t const epnum = tu_edpt_number(ep_addr); - uint32_t const dir = tu_edpt_dir(ep_addr); - - if (dir == TUSB_DIR_IN) - { - pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); - } - else - { - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); - } - - dcd_pma_free(ep_addr); + (void)rhport; + uint32_t const epnum = tu_edpt_number(ep_addr); + uint32_t const dir = tu_edpt_dir(ep_addr); + + if (dir == TUSB_DIR_IN) + { + pcd_set_ep_tx_status(USB, epnum, USB_EP_TX_DIS); + } + else + { + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_DIS); + } + + dcd_pma_free(ep_addr); } // Currently, single-buffered, and only 64 bytes at a time (max) static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) { - uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len); + uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len); - if (len > xfer->max_packet_size) // max packet size for FS transfer - { - len = xfer->max_packet_size; - } - uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB, ep_ix); + if (len > xfer->max_packet_size) // max packet size for FS transfer + { + len = xfer->max_packet_size; + } + uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB, ep_ix); #if 0 // TODO support dcd_edpt_xfer_fifo API if (xfer->ff) @@ -868,52 +868,52 @@ static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) } else #endif - { - dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len); - } - xfer->queued_len = (uint16_t)(xfer->queued_len + len); + { + dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len); + } + xfer->queued_len = (uint16_t)(xfer->queued_len + len); - pcd_set_ep_tx_cnt(USB, ep_ix, len); - pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID); + pcd_set_ep_tx_cnt(USB, ep_ix, len); + pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID); } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t *xfer = xfer_ctl_ptr(epnum, dir); - - xfer->buffer = buffer; - // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API - xfer->total_len = total_bytes; - xfer->queued_len = 0; - - if (dir == TUSB_DIR_OUT) - { - // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid - // buffer for the control endpoint. - if (epnum == 0 && buffer == NULL) - { - xfer->buffer = (uint8_t *)_setup_packet; - } - if (total_bytes > xfer->max_packet_size) - { - pcd_set_ep_rx_cnt(USB, epnum, xfer->max_packet_size); - } - else - { - pcd_set_ep_rx_cnt(USB, epnum, total_bytes); - } - pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID); - } - else // IN - { - dcd_transmit_packet(xfer, epnum); - } - return true; + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t *xfer = xfer_ctl_ptr(epnum, dir); + + xfer->buffer = buffer; + // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API + xfer->total_len = total_bytes; + xfer->queued_len = 0; + + if (dir == TUSB_DIR_OUT) + { + // A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid + // buffer for the control endpoint. + if (epnum == 0 && buffer == NULL) + { + xfer->buffer = (uint8_t *)_setup_packet; + } + if (total_bytes > xfer->max_packet_size) + { + pcd_set_ep_rx_cnt(USB, epnum, xfer->max_packet_size); + } + else + { + pcd_set_ep_rx_cnt(USB, epnum, total_bytes); + } + pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID); + } + else // IN + { + dcd_transmit_packet(xfer, epnum); + } + return true; } #if 0 // TODO support dcd_edpt_xfer_fifo API @@ -951,38 +951,38 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - if (ep_addr & 0x80) - { // IN - pcd_set_ep_tx_status(USB, ep_addr & 0x7F, USB_EP_TX_STALL); - } - else - { // OUT - pcd_set_ep_rx_status(USB, ep_addr, USB_EP_RX_STALL); - } + (void)rhport; + + if (ep_addr & 0x80) + { // IN + pcd_set_ep_tx_status(USB, ep_addr & 0x7F, USB_EP_TX_STALL); + } + else + { // OUT + pcd_set_ep_rx_status(USB, ep_addr, USB_EP_RX_STALL); + } } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; + (void)rhport; - if (ep_addr & 0x80) - { // IN - ep_addr &= 0x7F; + if (ep_addr & 0x80) + { // IN + ep_addr &= 0x7F; - pcd_set_ep_tx_status(USB, ep_addr, USB_EP_TX_NAK); + pcd_set_ep_tx_status(USB, ep_addr, USB_EP_TX_NAK); - /* Reset to DATA0 if clearing stall condition. */ - pcd_clear_tx_dtog(USB, ep_addr); - } - else - { // OUT - /* Reset to DATA0 if clearing stall condition. */ - pcd_clear_rx_dtog(USB, ep_addr); + /* Reset to DATA0 if clearing stall condition. */ + pcd_clear_tx_dtog(USB, ep_addr); + } + else + { // OUT + /* Reset to DATA0 if clearing stall condition. */ + pcd_clear_rx_dtog(USB, ep_addr); - pcd_set_ep_rx_status(USB, ep_addr, USB_EP_RX_NAK); - } + pcd_set_ep_rx_status(USB, ep_addr, USB_EP_RX_NAK); + } } // Packet buffer access can only be 8- or 16-bit. @@ -998,28 +998,28 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) */ static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes) { - uint32_t n = ((uint32_t)wNBytes + 1U) >> 1U; - uint32_t i; - uint16_t temp1, temp2; - const uint8_t *srcVal; - - // The GCC optimizer will combine access to 32-bit sizes if we let it. Force - // it volatile so that it won't do that. - __IO uint16_t *pdwVal; - - srcVal = src; - pdwVal = &pma[PMA_STRIDE * (dst >> 1)]; - - for (i = n; i != 0; i--) - { - temp1 = (uint16_t)*srcVal; - srcVal++; - temp2 = temp1 | ((uint16_t)((uint16_t)((*srcVal) << 8U))); - *pdwVal = temp2; - pdwVal += PMA_STRIDE; - srcVal++; - } - return true; + uint32_t n = ((uint32_t)wNBytes + 1U) >> 1U; + uint32_t i; + uint16_t temp1, temp2; + const uint8_t *srcVal; + + // The GCC optimizer will combine access to 32-bit sizes if we let it. Force + // it volatile so that it won't do that. + __IO uint16_t *pdwVal; + + srcVal = src; + pdwVal = &pma[PMA_STRIDE * (dst >> 1)]; + + for (i = n; i != 0; i--) + { + temp1 = (uint16_t)*srcVal; + srcVal++; + temp2 = temp1 | ((uint16_t)((uint16_t)((*srcVal) << 8U))); + *pdwVal = temp2; + pdwVal += PMA_STRIDE; + srcVal++; + } + return true; } #if 0 // TODO support dcd_edpt_xfer_fifo API @@ -1077,31 +1077,31 @@ static bool dcd_write_packet_memory_ff(tu_fifo_t * ff, uint16_t dst, uint16_t wN */ static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes) { - uint32_t n = (uint32_t)wNBytes >> 1U; - uint32_t i; - // The GCC optimizer will combine access to 32-bit sizes if we let it. Force - // it volatile so that it won't do that. - __IO const uint16_t *pdwVal; - uint32_t temp; - - pdwVal = &pma[PMA_STRIDE * (src >> 1)]; - uint8_t *dstVal = (uint8_t *)dst; - - for (i = n; i != 0U; i--) - { - temp = *pdwVal; - pdwVal += PMA_STRIDE; - *dstVal++ = ((temp >> 0) & 0xFF); - *dstVal++ = ((temp >> 8) & 0xFF); - } - - if (wNBytes % 2) - { - temp = *pdwVal; - pdwVal += PMA_STRIDE; - *dstVal++ = ((temp >> 0) & 0xFF); - } - return true; + uint32_t n = (uint32_t)wNBytes >> 1U; + uint32_t i; + // The GCC optimizer will combine access to 32-bit sizes if we let it. Force + // it volatile so that it won't do that. + __IO const uint16_t *pdwVal; + uint32_t temp; + + pdwVal = &pma[PMA_STRIDE * (src >> 1)]; + uint8_t *dstVal = (uint8_t *)dst; + + for (i = n; i != 0U; i--) + { + temp = *pdwVal; + pdwVal += PMA_STRIDE; + *dstVal++ = ((temp >> 0) & 0xFF); + *dstVal++ = ((temp >> 8) & 0xFF); + } + + if (wNBytes % 2) + { + temp = *pdwVal; + pdwVal += PMA_STRIDE; + *dstVal++ = ((temp >> 0) & 0xFF); + } + return true; } #if 0 // TODO support dcd_edpt_xfer_fifo API diff --git a/uCNC/src/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h b/uCNC/src/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h index 933cbb520..596f7be6c 100644 --- a/uCNC/src/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h +++ b/uCNC/src/tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h @@ -1,36 +1,36 @@ /** - ****************************************************************************** - * @file dcd_stm32f0_pvt_st.h - * @brief DCD utilities from ST code - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- *

© parts COPYRIGHT(c) N Conrad

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **********/ + ****************************************************************************** + * @file dcd_stm32f0_pvt_st.h + * @brief DCD utilities from ST code + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© parts COPYRIGHT(c) N Conrad

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + **********/ // This file contains source copied from ST's HAL, and thus should have their copyright statement. @@ -41,361 +41,362 @@ #ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ #define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ -#if defined(STM32F042x6) || \ - defined(STM32F070x6) || defined(STM32F070xB) || \ - defined(STM32F072xB) || \ - defined(STM32F078xx) -#include "stm32f0xx.h" -#define PMA_LENGTH (1024u) -// F0x2 models are crystal-less -// All have internal D+ pull-up -// 070RB: 2 x 16 bits/word memory LPM Support, BCD Support -// PMA dedicated to USB (no sharing with CAN) +#if defined(STM32F042x6) || \ + defined(STM32F070x6) || defined(STM32F070xB) || \ + defined(STM32F072xB) || \ + defined(STM32F078xx) + #include "stm32f0xx.h" + #define PMA_LENGTH (1024u) + // F0x2 models are crystal-less + // All have internal D+ pull-up + // 070RB: 2 x 16 bits/word memory LPM Support, BCD Support + // PMA dedicated to USB (no sharing with CAN) #elif defined(STM32F1_FSDEV) -#include "stm32f1xx.h" -#define PMA_LENGTH (512u) -// NO internal Pull-ups -// *B, and *C: 2 x 16 bits/word + #include "stm32f1xx.h" + #define PMA_LENGTH (512u) + // NO internal Pull-ups + // *B, and *C: 2 x 16 bits/word -// F1 names this differently from the rest -#define USB_CNTR_LPMODE USB_CNTR_LP_MODE + // F1 names this differently from the rest + #define USB_CNTR_LPMODE USB_CNTR_LP_MODE #elif defined(STM32F302xB) || defined(STM32F302xC) || \ - defined(STM32F303xB) || defined(STM32F303xC) || \ - defined(STM32F373xC) -#include "stm32f3xx.h" -#define PMA_LENGTH (512u) -// NO internal Pull-ups -// *B, and *C: 1 x 16 bits/word -// PMA dedicated to USB (no sharing with CAN) + defined(STM32F303xB) || defined(STM32F303xC) || \ + defined(STM32F373xC) + #include "stm32f3xx.h" + #define PMA_LENGTH (512u) + // NO internal Pull-ups + // *B, and *C: 1 x 16 bits/word + // PMA dedicated to USB (no sharing with CAN) #elif defined(STM32F302x6) || defined(STM32F302x8) || \ - defined(STM32F302xD) || defined(STM32F302xE) || \ - defined(STM32F303xD) || defined(STM32F303xE) -#include "stm32f3xx.h" -#define PMA_LENGTH (1024u) -// NO internal Pull-ups -// *6, *8, *D, and *E: 2 x 16 bits/word LPM Support -// When CAN clock is enabled, USB can use first 768 bytes ONLY. + defined(STM32F302xD) || defined(STM32F302xE) || \ + defined(STM32F303xD) || defined(STM32F303xE) + #include "stm32f3xx.h" + #define PMA_LENGTH (1024u) + // NO internal Pull-ups + // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support + // When CAN clock is enabled, USB can use first 768 bytes ONLY. #elif CFG_TUSB_MCU == OPT_MCU_STM32L0 -#include "stm32l0xx.h" -#define PMA_LENGTH (1024u) + #include "stm32l0xx.h" + #define PMA_LENGTH (1024u) #elif CFG_TUSB_MCU == OPT_MCU_STM32L1 -#include "stm32l1xx.h" -#define PMA_LENGTH (512u) + #include "stm32l1xx.h" + #define PMA_LENGTH (512u) #elif CFG_TUSB_MCU == OPT_MCU_STM32G4 -#include "stm32g4xx.h" -#define PMA_LENGTH (1024u) + #include "stm32g4xx.h" + #define PMA_LENGTH (1024u) #else -#error You are using an untested or unimplemented STM32 variant. Please update the driver. -// This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4 + #error You are using an untested or unimplemented STM32 variant. Please update the driver. + // This includes L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4 #endif // For purposes of accessing the packet #if ((PMA_LENGTH) == 512u) -#define PMA_STRIDE (2u) + #define PMA_STRIDE (2u) #elif ((PMA_LENGTH) == 1024u) -#define PMA_STRIDE (1u) + #define PMA_STRIDE (1u) #endif // And for type-safety create a new macro for the volatile address of PMAADDR // The compiler should warn us if we cast it to a non-volatile type? // Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden) -static __IO uint16_t *const pma = (__IO uint16_t *)USB_PMAADDR; +static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR; // prototypes -static inline __IO uint16_t *pcd_ep_rx_cnt_ptr(USB_TypeDef *USBx, uint32_t bEpNum); -static inline __IO uint16_t *pcd_ep_tx_cnt_ptr(USB_TypeDef *USBx, uint32_t bEpNum); -static inline void pcd_set_endpoint(USB_TypeDef *USBx, uint32_t bEpNum, uint32_t wRegValue); +static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); +static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum); +static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue); + /* SetENDPOINT */ -static inline void pcd_set_endpoint(USB_TypeDef *USBx, uint32_t bEpNum, uint32_t wRegValue) +static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wRegValue) { - __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpNum * 2u); - *reg = (uint16_t)wRegValue; + __O uint16_t *reg = (__O uint16_t *)((&USBx->EP0R) + bEpNum*2u); + *reg = (uint16_t)wRegValue; } /* GetENDPOINT */ -static inline uint16_t pcd_get_endpoint(USB_TypeDef *USBx, uint32_t bEpNum) -{ - __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpNum * 2u); - return *reg; +static inline uint16_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t bEpNum) { + __I uint16_t *reg = (__I uint16_t *)((&USBx->EP0R) + bEpNum*2u); + return *reg; } -static inline void pcd_set_eptype(USB_TypeDef *USBx, uint32_t bEpNum, uint32_t wType) +static inline void pcd_set_eptype(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wType) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= (uint32_t)USB_EP_T_MASK; - regVal |= wType; - regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= (uint32_t)USB_EP_T_MASK; + regVal |= wType; + regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; // These clear on write0, so must set high + pcd_set_endpoint(USBx, bEpNum, regVal); } -static inline uint32_t pcd_get_eptype(USB_TypeDef *USBx, uint32_t bEpNum) +static inline uint32_t pcd_get_eptype(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= USB_EP_T_FIELD; - return regVal; + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= USB_EP_T_FIELD; + return regVal; } /** - * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -static inline void pcd_clear_rx_ep_ctr(USB_TypeDef *USBx, uint32_t bEpNum) + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +static inline void pcd_clear_rx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= USB_EPREG_MASK; - regVal &= ~USB_EP_CTR_RX; - regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0) - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= USB_EPREG_MASK; + regVal &= ~USB_EP_CTR_RX; + regVal |= USB_EP_CTR_TX; // preserve CTR_TX (clears on writing 0) + pcd_set_endpoint(USBx, bEpNum, regVal); } -static inline void pcd_clear_tx_ep_ctr(USB_TypeDef *USBx, uint32_t bEpNum) +static inline void pcd_clear_tx_ep_ctr(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= USB_EPREG_MASK; - regVal &= ~USB_EP_CTR_TX; - regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0) - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= USB_EPREG_MASK; + regVal &= ~USB_EP_CTR_TX; + regVal |= USB_EP_CTR_RX; // preserve CTR_RX (clears on writing 0) + pcd_set_endpoint(USBx, bEpNum,regVal); } /** - * @brief gets counter of the tx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval Counter value - */ -static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef *USBx, uint32_t bEpNum) + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +static inline uint32_t pcd_get_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) { - __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpNum); - return *regPtr & 0x3ffU; + __I uint16_t *regPtr = pcd_ep_tx_cnt_ptr(USBx, bEpNum); + return *regPtr & 0x3ffU; } -static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef *USBx, uint32_t bEpNum) +static inline uint32_t pcd_get_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum) { - __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpNum); - return *regPtr & 0x3ffU; + __I uint16_t *regPtr = pcd_ep_rx_cnt_ptr(USBx, bEpNum); + return *regPtr & 0x3ffU; } /** - * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg Register - * @param wCount Counter. - * @param wNBlocks no. of Blocks. - * @retval None - */ - -static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t *pdwReg, size_t wCount) -{ - uint32_t wNBlocks; - if (wCount > 62u) - { - wNBlocks = wCount >> 5u; - if ((wCount & 0x1fU) == 0u) - { - wNBlocks--; - } - wNBlocks = wNBlocks << 10u; - wNBlocks |= 0x8000u; // Mark block size as 32byte - *pdwReg = (uint16_t)wNBlocks; - } - else - { - wNBlocks = wCount >> 1u; - if ((wCount & 0x1U) != 0u) - { - wNBlocks++; - } - *pdwReg = (uint16_t)((wNBlocks) << 10u); - } + * @brief Sets counter of rx buffer with no. of blocks. + * @param dwReg Register + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ + +static inline void pcd_set_ep_cnt_rx_reg(__O uint16_t * pdwReg, size_t wCount) { + uint32_t wNBlocks; + if(wCount > 62u) + { + wNBlocks = wCount >> 5u; + if((wCount & 0x1fU) == 0u) + { + wNBlocks--; + } + wNBlocks = wNBlocks << 10u; + wNBlocks |= 0x8000u; // Mark block size as 32byte + *pdwReg = (uint16_t)wNBlocks; + } + else + { + wNBlocks = wCount >> 1u; + if((wCount & 0x1U) != 0u) + { + wNBlocks++; + } + *pdwReg = (uint16_t)((wNBlocks) << 10u); + } } + /** - * @brief Sets address in an endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param bAddr Address. - * @retval None - */ -static inline void pcd_set_ep_address(USB_TypeDef *USBx, uint32_t bEpNum, uint32_t bAddr) + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +static inline void pcd_set_ep_address(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t bAddr) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= USB_EPREG_MASK; - regVal |= bAddr; - regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= USB_EPREG_MASK; + regVal |= bAddr; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpNum,regVal); } -static inline __IO uint16_t *pcd_btable_word_ptr(USB_TypeDef *USBx, size_t x) +static inline __IO uint16_t * pcd_btable_word_ptr(USB_TypeDef * USBx, size_t x) { - size_t total_word_offset = (((USBx)->BTABLE) >> 1) + x; - total_word_offset *= PMA_STRIDE; - return &(pma[total_word_offset]); + size_t total_word_offset = (((USBx)->BTABLE)>>1) + x; + total_word_offset *= PMA_STRIDE; + return &(pma[total_word_offset]); } // Pointers to the PMA table entries (using the ARM address space) -static inline __IO uint16_t *pcd_ep_tx_address_ptr(USB_TypeDef *USBx, uint32_t bEpNum) +static inline __IO uint16_t* pcd_ep_tx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum) { - return pcd_btable_word_ptr(USBx, (bEpNum)*4u + 0u); + return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 0u); } -static inline __IO uint16_t *pcd_ep_tx_cnt_ptr(USB_TypeDef *USBx, uint32_t bEpNum) +static inline __IO uint16_t* pcd_ep_tx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum) { - return pcd_btable_word_ptr(USBx, (bEpNum)*4u + 1u); + return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 1u); } -static inline __IO uint16_t *pcd_ep_rx_address_ptr(USB_TypeDef *USBx, uint32_t bEpNum) +static inline __IO uint16_t* pcd_ep_rx_address_ptr(USB_TypeDef * USBx, uint32_t bEpNum) { - return pcd_btable_word_ptr(USBx, (bEpNum)*4u + 2u); + return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 2u); } -static inline __IO uint16_t *pcd_ep_rx_cnt_ptr(USB_TypeDef *USBx, uint32_t bEpNum) +static inline __IO uint16_t* pcd_ep_rx_cnt_ptr(USB_TypeDef * USBx, uint32_t bEpNum) { - return pcd_btable_word_ptr(USBx, (bEpNum)*4u + 3u); + return pcd_btable_word_ptr(USBx,(bEpNum)*4u + 3u); } -static inline void pcd_set_ep_tx_cnt(USB_TypeDef *USBx, uint32_t bEpNum, uint32_t wCount) +static inline void pcd_set_ep_tx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) { - *pcd_ep_tx_cnt_ptr(USBx, bEpNum) = (uint16_t)wCount; + *pcd_ep_tx_cnt_ptr(USBx, bEpNum) = (uint16_t)wCount; } -static inline void pcd_set_ep_rx_cnt(USB_TypeDef *USBx, uint32_t bEpNum, uint32_t wCount) +static inline void pcd_set_ep_rx_cnt(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wCount) { - __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx), (bEpNum)); - pcd_set_ep_cnt_rx_reg(pdwReg, wCount); + __IO uint16_t *pdwReg = pcd_ep_rx_cnt_ptr((USBx),(bEpNum)); + pcd_set_ep_cnt_rx_reg(pdwReg, wCount); } /** - * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wState new state - * @retval None - */ -static inline void pcd_set_ep_tx_status(USB_TypeDef *USBx, uint32_t bEpNum, uint32_t wState) + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +static inline void pcd_set_ep_tx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= USB_EPTX_DTOGMASK; - - /* toggle first bit ? */ - if ((USB_EPTX_DTOG1 & (wState)) != 0U) - { - regVal ^= USB_EPTX_DTOG1; - } - /* toggle second bit ? */ - if ((USB_EPTX_DTOG2 & ((uint32_t)(wState))) != 0U) - { - regVal ^= USB_EPTX_DTOG2; - } - regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= USB_EPTX_DTOGMASK; + + /* toggle first bit ? */ + if((USB_EPTX_DTOG1 & (wState))!= 0U) + { + regVal ^= USB_EPTX_DTOG1; + } + /* toggle second bit ? */ + if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) + { + regVal ^= USB_EPTX_DTOG2; + } + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpNum, regVal); } /* pcd_set_ep_tx_status */ /** - * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wState new state - * @retval None - */ - -static inline void pcd_set_ep_rx_status(USB_TypeDef *USBx, uint32_t bEpNum, uint32_t wState) + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ + +static inline void pcd_set_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum, uint32_t wState) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= USB_EPRX_DTOGMASK; - - /* toggle first bit ? */ - if ((USB_EPRX_DTOG1 & wState) != 0U) - { - regVal ^= USB_EPRX_DTOG1; - } - /* toggle second bit ? */ - if ((USB_EPRX_DTOG2 & wState) != 0U) - { - regVal ^= USB_EPRX_DTOG2; - } - regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= USB_EPRX_DTOGMASK; + + /* toggle first bit ? */ + if((USB_EPRX_DTOG1 & wState)!= 0U) + { + regVal ^= USB_EPRX_DTOG1; + } + /* toggle second bit ? */ + if((USB_EPRX_DTOG2 & wState)!= 0U) + { + regVal ^= USB_EPRX_DTOG2; + } + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpNum, regVal); } /* pcd_set_ep_rx_status */ -static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef *USBx, uint32_t bEpNum) +static inline uint32_t pcd_get_ep_rx_status(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - return (regVal & USB_EPRX_STAT) >> (12u); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + return (regVal & USB_EPRX_STAT) >> (12u); } /* pcd_get_ep_rx_status */ + /** - * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -static inline void pcd_rx_dtog(USB_TypeDef *USBx, uint32_t bEpNum) + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +static inline void pcd_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= USB_EPREG_MASK; - regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX; - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= USB_EPREG_MASK; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX; + pcd_set_endpoint(USBx, bEpNum, regVal); } -static inline void pcd_tx_dtog(USB_TypeDef *USBx, uint32_t bEpNum) +static inline void pcd_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= USB_EPREG_MASK; - regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= USB_EPREG_MASK; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX; + pcd_set_endpoint(USBx, bEpNum, regVal); } /** - * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ -static inline void pcd_clear_rx_dtog(USB_TypeDef *USBx, uint32_t bEpNum) +static inline void pcd_clear_rx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - if ((regVal & USB_EP_DTOG_RX) != 0) - { - pcd_rx_dtog(USBx, bEpNum); - } + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + if((regVal & USB_EP_DTOG_RX) != 0) + { + pcd_rx_dtog(USBx,bEpNum); + } } -static inline void pcd_clear_tx_dtog(USB_TypeDef *USBx, uint32_t bEpNum) +static inline void pcd_clear_tx_dtog(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - if ((regVal & USB_EP_DTOG_TX) != 0) - { - pcd_tx_dtog(USBx, bEpNum); - } + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + if((regVal & USB_EP_DTOG_TX) != 0) + { + pcd_tx_dtog(USBx,bEpNum); + } } /** - * @brief set & clear EP_KIND bit. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ + * @brief set & clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ -static inline void pcd_set_ep_kind(USB_TypeDef *USBx, uint32_t bEpNum) +static inline void pcd_set_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal |= USB_EP_KIND; - regVal &= USB_EPREG_MASK; - regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal |= USB_EP_KIND; + regVal &= USB_EPREG_MASK; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpNum, regVal); } -static inline void pcd_clear_ep_kind(USB_TypeDef *USBx, uint32_t bEpNum) +static inline void pcd_clear_ep_kind(USB_TypeDef * USBx, uint32_t bEpNum) { - uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); - regVal &= USB_EPKIND_MASK; - regVal |= USB_EP_CTR_RX | USB_EP_CTR_TX; - pcd_set_endpoint(USBx, bEpNum, regVal); + uint32_t regVal = pcd_get_endpoint(USBx, bEpNum); + regVal &= USB_EPKIND_MASK; + regVal |= USB_EP_CTR_RX|USB_EP_CTR_TX; + pcd_set_endpoint(USBx, bEpNum, regVal); } // This checks if the device has "LPM" @@ -406,7 +407,7 @@ static inline void pcd_clear_ep_kind(USB_TypeDef *USBx, uint32_t bEpNum) #endif #define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \ - USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED) + USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED ) // Number of endpoints in hardware #define STFSDEV_EP_COUNT (8u) diff --git a/uCNC/src/tinyusb/src/portable/st/synopsys/dcd_synopsys.c b/uCNC/src/tinyusb/src/portable/st/synopsys/dcd_synopsys.c index 1feffe405..0d5e5f71a 100644 --- a/uCNC/src/tinyusb/src/portable/st/synopsys/dcd_synopsys.c +++ b/uCNC/src/tinyusb/src/portable/st/synopsys/dcd_synopsys.c @@ -34,25 +34,25 @@ #define USE_SOF 0 #if defined(STM32F105x8) || defined(STM32F105xB) || defined(STM32F105xC) || \ - defined(STM32F107xB) || defined(STM32F107xC) + defined(STM32F107xB) || defined(STM32F107xC) #define STM32F1_SYNOPSYS #endif #if defined(STM32L475xx) || defined(STM32L476xx) || \ - defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || \ - defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) + defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || \ + defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || \ + defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) #define STM32L4_SYNOPSYS #endif #if TUSB_OPT_DEVICE_ENABLED && \ - ((CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \ - CFG_TUSB_MCU == OPT_MCU_STM32F2 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F4 || \ - CFG_TUSB_MCU == OPT_MCU_STM32F7 || \ - CFG_TUSB_MCU == OPT_MCU_STM32H7 || \ - (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS) || \ - CFG_TUSB_MCU == OPT_MCU_GD32VF103)) + ((CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_SYNOPSYS)) || \ + CFG_TUSB_MCU == OPT_MCU_STM32F2 || \ + CFG_TUSB_MCU == OPT_MCU_STM32F4 || \ + CFG_TUSB_MCU == OPT_MCU_STM32F7 || \ + CFG_TUSB_MCU == OPT_MCU_STM32H7 || \ + (CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS) || \ + CFG_TUSB_MCU == OPT_MCU_GD32VF103)) // EP_MAX : Max number of bi-directional endpoints including EP0 // EP_FIFO_SIZE : Size of dedicated USB SRAM @@ -113,12 +113,12 @@ static inline void __eclic_enable_interrupt(uint32_t irq) { - *(volatile uint8_t *)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1; + *(volatile uint8_t *)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 1; } static inline void __eclic_disable_interrupt(uint32_t irq) { - *(volatile uint8_t *)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0; + *(volatile uint8_t *)(ECLIC_INTERRUPT_ENABLE_BASE + (irq * 4)) = 0; } #else @@ -154,20 +154,20 @@ static inline void __eclic_disable_interrupt(uint32_t irq) enum { - DCD_HIGH_SPEED = 0, // Highspeed mode - DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY) - DCD_FULL_SPEED = 3, // Full speed with internal PHY + DCD_HIGH_SPEED = 0, // Highspeed mode + DCD_FULL_SPEED_USE_HS = 1, // Full speed in Highspeed port (probably with internal PHY) + DCD_FULL_SPEED = 3, // Full speed with internal PHY }; static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; typedef struct { - uint8_t *buffer; - tu_fifo_t *ff; - uint16_t total_len; - uint16_t max_size; - uint8_t interval; + uint8_t *buffer; + tu_fifo_t *ff; + uint16_t total_len; + uint16_t max_size; + uint8_t interval; } xfer_ctl_t; typedef volatile uint32_t *usb_fifo_t; @@ -180,302 +180,302 @@ static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type // TX FIFO RAM allocation so far in words - RX FIFO size is readily available from usb_otg->GRXFSIZ static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) -static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) +static bool _out_ep_closed; // Flag to check if RX FIFO size needs an update (reduce its size) // Calculate the RX FIFO size according to recommendations from reference manual static inline uint16_t calc_rx_ff_size(uint16_t ep_size) { - return 15 + 2 * (ep_size / 4) + 2 * EP_MAX; + return 15 + 2 * (ep_size / 4) + 2 * EP_MAX; } static void update_grxfsiz(uint8_t rhport) { - (void)rhport; + (void)rhport; - USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); + USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); - // Determine largest EP size for RX FIFO - uint16_t max_epsize = 0; - for (uint8_t epnum = 0; epnum < EP_MAX; epnum++) - { - max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size); - } + // Determine largest EP size for RX FIFO + uint16_t max_epsize = 0; + for (uint8_t epnum = 0; epnum < EP_MAX; epnum++) + { + max_epsize = tu_max16(max_epsize, xfer_status[epnum][TUSB_DIR_OUT].max_size); + } - // Update size of RX FIFO - usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize); + // Update size of RX FIFO + usb_otg->GRXFSIZ = calc_rx_ff_size(max_epsize); } // Setup the control endpoint 0. static void bus_reset(uint8_t rhport) { - (void)rhport; - - USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); - - tu_memclr(xfer_status, sizeof(xfer_status)); - _out_ep_closed = false; - - // clear device address - dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk; - - // 1. NAK for all OUT endpoints - for (uint8_t n = 0; n < EP_MAX; n++) - { - out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK; - } - - // 2. Un-mask interrupt bits - dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); - dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM; - dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM; - - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start. - // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located - // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard - // configuration done below. - // - // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed. - // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a - // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually - // opened when the host sends an additional command: setInterface. At this point in time - // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size - // an additional memory - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): - // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN - // - // - All EP OUT shared a unique OUT FIFO which uses - // - 13 for setup packets + control words (up to 3 setup packets). - // - 1 for global NAK (not required/used here). - // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" - // - 2 for each used OUT endpoint - // - // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum - // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x EP_MAX = 47 + 2 x EP_MAX - // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX - // - // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge - // of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX - // - // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO - // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to - // overwrite this. - - usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); - - _allocated_fifo_words_tx = 16; - - // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE / 4 - _allocated_fifo_words_tx); - - // Fixed control EP0 size to 64 bytes - in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos); - xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64; - - out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); - - usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT; + (void)rhport; + + USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); + + tu_memclr(xfer_status, sizeof(xfer_status)); + _out_ep_closed = false; + + // clear device address + dev->DCFG &= ~USB_OTG_DCFG_DAD_Msk; + + // 1. NAK for all OUT endpoints + for (uint8_t n = 0; n < EP_MAX; n++) + { + out_ep[n].DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + + // 2. Un-mask interrupt bits + dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); + dev->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM; + dev->DIEPMSK = USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM; + + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start. + // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located + // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard + // configuration done below. + // + // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed. + // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a + // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually + // opened when the host sends an additional command: setInterface. At this point in time + // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size + // an additional memory + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO 0 | + // --------------- (320 or 1024) - 16 + // | IN FIFO 1 | + // --------------- (320 or 1024) - 16 - x + // | . . . . | + // --------------- (320 or 1024) - 16 - x - y - ... - z + // | IN FIFO MAX | + // --------------- + // | FREE | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): + // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN + // + // - All EP OUT shared a unique OUT FIFO which uses + // - 13 for setup packets + control words (up to 3 setup packets). + // - 1 for global NAK (not required/used here). + // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" + // - 2 for each used OUT endpoint + // + // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum + // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x EP_MAX = 47 + 2 x EP_MAX + // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x EP_MAX = 271 + 2 x EP_MAX + // + // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge + // of the overall picture yet. We will use the worst scenario: largest possible + EP_MAX + // + // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO + // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to + // overwrite this. + + usb_otg->GRXFSIZ = calc_rx_ff_size(TUD_OPT_HIGH_SPEED ? 512 : 64); + + _allocated_fifo_words_tx = 16; + + // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) + usb_otg->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (EP_FIFO_SIZE / 4 - _allocated_fifo_words_tx); + + // Fixed control EP0 size to 64 bytes + in_ep[0].DIEPCTL &= ~(0x03 << USB_OTG_DIEPCTL_MPSIZ_Pos); + xfer_status[0][TUSB_DIR_OUT].max_size = xfer_status[0][TUSB_DIR_IN].max_size = 64; + + out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); + + usb_otg->GINTMSK |= USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT; } // Set turn-around timeout according to link speed extern uint32_t SystemCoreClock; static void set_turnaround(USB_OTG_GlobalTypeDef *usb_otg, tusb_speed_t speed) { - usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - - if (speed == TUSB_SPEED_HIGH) - { - // Use fixed 0x09 for Highspeed - usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos); - } - else - { - // Turnaround timeout depends on the MCU clock - uint32_t turnaround; - - if (SystemCoreClock >= 32000000U) - turnaround = 0x6U; - else if (SystemCoreClock >= 27500000U) - turnaround = 0x7U; - else if (SystemCoreClock >= 24000000U) - turnaround = 0x8U; - else if (SystemCoreClock >= 21800000U) - turnaround = 0x9U; - else if (SystemCoreClock >= 20000000U) - turnaround = 0xAU; - else if (SystemCoreClock >= 18500000U) - turnaround = 0xBU; - else if (SystemCoreClock >= 17200000U) - turnaround = 0xCU; - else if (SystemCoreClock >= 16000000U) - turnaround = 0xDU; - else if (SystemCoreClock >= 15000000U) - turnaround = 0xEU; - else - turnaround = 0xFU; - - // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz - usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos); - } + usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + + if (speed == TUSB_SPEED_HIGH) + { + // Use fixed 0x09 for Highspeed + usb_otg->GUSBCFG |= (0x09 << USB_OTG_GUSBCFG_TRDT_Pos); + } + else + { + // Turnaround timeout depends on the MCU clock + uint32_t turnaround; + + if (SystemCoreClock >= 32000000U) + turnaround = 0x6U; + else if (SystemCoreClock >= 27500000U) + turnaround = 0x7U; + else if (SystemCoreClock >= 24000000U) + turnaround = 0x8U; + else if (SystemCoreClock >= 21800000U) + turnaround = 0x9U; + else if (SystemCoreClock >= 20000000U) + turnaround = 0xAU; + else if (SystemCoreClock >= 18500000U) + turnaround = 0xBU; + else if (SystemCoreClock >= 17200000U) + turnaround = 0xCU; + else if (SystemCoreClock >= 16000000U) + turnaround = 0xDU; + else if (SystemCoreClock >= 15000000U) + turnaround = 0xEU; + else + turnaround = 0xFU; + + // Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz + usb_otg->GUSBCFG |= (turnaround << USB_OTG_GUSBCFG_TRDT_Pos); + } } static tusb_speed_t get_speed(uint8_t rhport) { - (void)rhport; - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos; - return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; + (void)rhport; + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + uint32_t const enum_spd = (dev->DSTS & USB_OTG_DSTS_ENUMSPD_Msk) >> USB_OTG_DSTS_ENUMSPD_Pos; + return (enum_spd == DCD_HIGH_SPEED) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL; } static void set_speed(uint8_t rhport, tusb_speed_t speed) { - uint32_t bitvalue; - - if (rhport == 1) - { - bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS); - } - else - { - bitvalue = DCD_FULL_SPEED; - } - - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - - // Clear and set speed bits - dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos); - dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos); + uint32_t bitvalue; + + if (rhport == 1) + { + bitvalue = ((TUSB_SPEED_HIGH == speed) ? DCD_HIGH_SPEED : DCD_FULL_SPEED_USE_HS); + } + else + { + bitvalue = DCD_FULL_SPEED; + } + + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + + // Clear and set speed bits + dev->DCFG &= ~(3 << USB_OTG_DCFG_DSPD_Pos); + dev->DCFG |= (bitvalue << USB_OTG_DCFG_DSPD_Pos); } #if defined(USB_HS_PHYC) static bool USB_HS_PHYCInit(void) { - USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef *)USB_HS_PHYC_CONTROLLER_BASE; - - // Enable LDO: Note STM32F72/3xx Reference Manual rev 3 June 2018 incorrectly defined this bit as Disabled !! - usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; - - // Wait until LDO ready - while (0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS)) - { - } - - uint32_t phyc_pll = 0; - - // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS - switch (HSE_VALUE) - { - case 12000000: - phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ; - break; - case 12500000: - phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ; - break; - case 16000000: - phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ; - break; - case 24000000: - phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ; - break; - case 25000000: - phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ; - break; - case 32000000: - phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk; - break; // Value not defined in header - default: - TU_ASSERT(0); - } - usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll; - - // Control the tuning interface of the High Speed PHY - // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver - usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U; - - // Enable PLL internal PHY - usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; - - // Original ST code has 2 ms delay for PLL stabilization. - // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration - - return true; + USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef *)USB_HS_PHYC_CONTROLLER_BASE; + + // Enable LDO: Note STM32F72/3xx Reference Manual rev 3 June 2018 incorrectly defined this bit as Disabled !! + usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + // Wait until LDO ready + while (0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS)) + { + } + + uint32_t phyc_pll = 0; + + // TODO Try to get HSE_VALUE from registers instead of depending CFLAGS + switch (HSE_VALUE) + { + case 12000000: + phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ; + break; + case 12500000: + phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ; + break; + case 16000000: + phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ; + break; + case 24000000: + phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ; + break; + case 25000000: + phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ; + break; + case 32000000: + phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk; + break; // Value not defined in header + default: + TU_ASSERT(0); + } + usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll; + + // Control the tuning interface of the High Speed PHY + // Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver + usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U; + + // Enable PLL internal PHY + usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + // Original ST code has 2 ms delay for PLL stabilization. + // Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration + + return true; } #endif static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes) { - (void)rhport; - - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); - - // EP0 is limited to one packet each xfer - // We use multiple transaction of xfer->max_size length to get a whole transfer done - if (epnum == 0) - { - xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, dir); - total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); - ep0_pending[dir] -= total_bytes; - } - - // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. - if (dir == TUSB_DIR_IN) - { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) | - ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk); - - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK; - // For ISO endpoint set correct odd/even bit for next frame. - if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) - { - // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); - in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk); - } - // Enable fifo empty interrupt only if there are something to put in the fifo. - if (total_bytes != 0) - { - dev->DIEPEMPMSK |= (1 << epnum); - } - } - else - { - // A full OUT transfer (multiple packets, possibly) triggers XFRC. - out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ); - out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) | - ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk); - - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; - if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) - { - // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); - out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk); - } - } + (void)rhport; + + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); + + // EP0 is limited to one packet each xfer + // We use multiple transaction of xfer->max_size length to get a whole transfer done + if (epnum == 0) + { + xfer_ctl_t *const xfer = XFER_CTL_BASE(epnum, dir); + total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); + ep0_pending[dir] -= total_bytes; + } + + // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. + if (dir == TUSB_DIR_IN) + { + // A full IN transfer (multiple packets, possibly) triggers XFRC. + in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) | + ((total_bytes << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) & USB_OTG_DIEPTSIZ_XFRSIZ_Msk); + + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK; + // For ISO endpoint set correct odd/even bit for next frame. + if ((in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPTYP) == USB_OTG_DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + { + // Take odd/even bit from frame counter. + uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); + in_ep[epnum].DIEPCTL |= (odd_frame_now ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DIEPCTL_SODDFRM_Msk); + } + // Enable fifo empty interrupt only if there are something to put in the fifo. + if (total_bytes != 0) + { + dev->DIEPEMPMSK |= (1 << epnum); + } + } + else + { + // A full OUT transfer (multiple packets, possibly) triggers XFRC. + out_ep[epnum].DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT_Msk | USB_OTG_DOEPTSIZ_XFRSIZ); + out_ep[epnum].DOEPTSIZ |= (num_packets << USB_OTG_DOEPTSIZ_PKTCNT_Pos) | + ((total_bytes << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) & USB_OTG_DOEPTSIZ_XFRSIZ_Msk); + + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_CNAK; + if ((out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPTYP) == USB_OTG_DOEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) + { + // Take odd/even bit from frame counter. + uint32_t const odd_frame_now = (dev->DSTS & (1u << USB_OTG_DSTS_FNSOF_Pos)); + out_ep[epnum].DOEPCTL |= (odd_frame_now ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk : USB_OTG_DOEPCTL_SODDFRM_Msk); + } + } } /*------------------------------------------------------------------*/ @@ -483,151 +483,151 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c *------------------------------------------------------------------*/ void dcd_init(uint8_t rhport) { - // Programming model begins in the last section of the chapter on the USB - // peripheral in each Reference Manual. + // Programming model begins in the last section of the chapter on the USB + // peripheral in each Reference Manual. - USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); + USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); - // No HNP/SRP (no OTG support), program timeout later. - if (rhport == 1) - { - // On selected MCUs HS port1 can be used with external PHY via ULPI interface + // No HNP/SRP (no OTG support), program timeout later. + if (rhport == 1) + { + // On selected MCUs HS port1 can be used with external PHY via ULPI interface #if CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED - // deactivate internal PHY - usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN; + // deactivate internal PHY + usb_otg->GCCFG &= ~USB_OTG_GCCFG_PWRDWN; - // Init The UTMI Interface - usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + // Init The UTMI Interface + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); - // Select default internal VBUS Indicator and Drive for ULPI - usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + // Select default internal VBUS Indicator and Drive for ULPI + usb_otg->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); #else - usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; #endif #if defined(USB_HS_PHYC) - // Highspeed with embedded UTMI PHYC + // Highspeed with embedded UTMI PHYC - // Select UTMI Interface - usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; - usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN; + // Select UTMI Interface + usb_otg->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + usb_otg->GCCFG |= USB_OTG_GCCFG_PHYHSEN; - // Enables control of a High Speed USB PHY - USB_HS_PHYCInit(); + // Enables control of a High Speed USB PHY + USB_HS_PHYCInit(); #endif - } - else - { - // Enable internal PHY - usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - } - - // Reset core after selecting PHY - // Wait AHB IDLE, reset then wait until it is cleared - while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) - { - } - usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) - { - } - - // Restart PHY clock - *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0; - - // Clear all interrupts - usb_otg->GINTSTS |= usb_otg->GINTSTS; - - // Required as part of core initialization. - // TODO: How should mode mismatch be handled? It will cause - // the core to stop working/require reset. - usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM; - - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - - // If USB host misbehaves during status portion of control xfer - // (non zero-length packet), send STALL back and discard. - dev->DCFG |= USB_OTG_DCFG_NZLSOHSK; - - set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); - - // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. - if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) - usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN; - - usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | - USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM | - USB_OTG_GINTMSK_RXFLVLM | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0); - - // Enable global interrupt - usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT; - - dcd_connect(rhport); + } + else + { + // Enable internal PHY + usb_otg->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + } + + // Reset core after selecting PHY + // Wait AHB IDLE, reset then wait until it is cleared + while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) + { + } + usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST) + { + } + + // Restart PHY clock + *((volatile uint32_t *)(RHPORT_REGS_BASE + USB_OTG_PCGCCTL_BASE)) = 0; + + // Clear all interrupts + usb_otg->GINTSTS |= usb_otg->GINTSTS; + + // Required as part of core initialization. + // TODO: How should mode mismatch be handled? It will cause + // the core to stop working/require reset. + usb_otg->GINTMSK |= USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_MMISM; + + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + + // If USB host misbehaves during status portion of control xfer + // (non zero-length packet), send STALL back and discard. + dev->DCFG |= USB_OTG_DCFG_NZLSOHSK; + + set_speed(rhport, TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL); + + // Enable internal USB transceiver, unless using HS core (port 1) with external PHY. + if (!(rhport == 1 && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HIGH_SPEED))) + usb_otg->GCCFG |= USB_OTG_GCCFG_PWRDWN; + + usb_otg->GINTMSK |= USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | + USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_WUIM | + USB_OTG_GINTMSK_RXFLVLM | (USE_SOF ? USB_OTG_GINTMSK_SOFM : 0); + + // Enable global interrupt + usb_otg->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + + dcd_connect(rhport); } void dcd_int_enable(uint8_t rhport) { - (void)rhport; - NVIC_EnableIRQ(RHPORT_IRQn); + (void)rhport; + NVIC_EnableIRQ(RHPORT_IRQn); } void dcd_int_disable(uint8_t rhport) { - (void)rhport; - NVIC_DisableIRQ(RHPORT_IRQn); + (void)rhport; + NVIC_DisableIRQ(RHPORT_IRQn); } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos); + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + dev->DCFG = (dev->DCFG & ~USB_OTG_DCFG_DAD_Msk) | (dev_addr << USB_OTG_DCFG_DAD_Pos); - // Response with status after changing device address - dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); + // Response with status after changing device address + dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0); } static void remote_wakeup_delay(void) { - // try to delay for 1 ms - uint32_t count = SystemCoreClock / 1000; - while (count--) - { - __NOP(); - } + // try to delay for 1 ms + uint32_t count = SystemCoreClock / 1000; + while (count--) + { + __NOP(); + } } void dcd_remote_wakeup(uint8_t rhport) { - (void)rhport; + (void)rhport; - USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - // set remote wakeup - dev->DCTL |= USB_OTG_DCTL_RWUSIG; + // set remote wakeup + dev->DCTL |= USB_OTG_DCTL_RWUSIG; - // enable SOF to detect bus resume - usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; - usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM; + // enable SOF to detect bus resume + usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; + usb_otg->GINTMSK |= USB_OTG_GINTMSK_SOFM; - // Per specs: remote wakeup signal bit must be clear within 1-15ms - remote_wakeup_delay(); + // Per specs: remote wakeup signal bit must be clear within 1-15ms + remote_wakeup_delay(); - dev->DCTL &= ~USB_OTG_DCTL_RWUSIG; + dev->DCTL &= ~USB_OTG_DCTL_RWUSIG; } void dcd_connect(uint8_t rhport) { - (void)rhport; - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - dev->DCTL &= ~USB_OTG_DCTL_SDIS; + (void)rhport; + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + dev->DCTL &= ~USB_OTG_DCTL_SDIS; } void dcd_disconnect(uint8_t rhport) { - (void)rhport; - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - dev->DCTL |= USB_OTG_DCTL_SDIS; + (void)rhport; + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + dev->DCTL |= USB_OTG_DCTL_SDIS; } /*------------------------------------------------------------------*/ @@ -636,151 +636,151 @@ void dcd_disconnect(uint8_t rhport) bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { - (void)rhport; - - USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); - - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - - TU_ASSERT(epnum < EP_MAX); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = tu_edpt_packet_size(desc_edpt); - xfer->interval = desc_edpt->bInterval; - - uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word - - if (dir == TUSB_DIR_OUT) - { - // Calculate required size of RX FIFO - uint16_t const sz = calc_rx_ff_size(4 * fifo_size); - - // If size_rx needs to be extended check if possible and if so enlarge it - if (usb_otg->GRXFSIZ < sz) - { - TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE / 4); - - // Enlarge RX FIFO - usb_otg->GRXFSIZ = sz; - } - - out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | - (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos); - - dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum)); - } - else - { - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // In FIFO is allocated by following rules: - // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". - - // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE / 4); - - _allocated_fifo_words_tx += fifo_size; - - TU_LOG(2, " Allocated %u bytes at offset %u", fifo_size * 4, EP_FIFO_SIZE - _allocated_fifo_words_tx * 4); - - // DIEPTXF starts at FIFO #1. - // Both TXFD and TXSA are in unit of 32-bit words. - usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE / 4 - _allocated_fifo_words_tx); - - in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | - (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) | - (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) | - (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos); - - dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum)); - } - - return true; + (void)rhport; + + USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + TU_ASSERT(epnum < EP_MAX); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = tu_edpt_packet_size(desc_edpt); + xfer->interval = desc_edpt->bInterval; + + uint16_t const fifo_size = (xfer->max_size + 3) / 4; // Round up to next full word + + if (dir == TUSB_DIR_OUT) + { + // Calculate required size of RX FIFO + uint16_t const sz = calc_rx_ff_size(4 * fifo_size); + + // If size_rx needs to be extended check if possible and if so enlarge it + if (usb_otg->GRXFSIZ < sz) + { + TU_ASSERT(sz + _allocated_fifo_words_tx <= EP_FIFO_SIZE / 4); + + // Enlarge RX FIFO + usb_otg->GRXFSIZ = sz; + } + + out_ep[epnum].DOEPCTL |= (1 << USB_OTG_DOEPCTL_USBAEP_Pos) | + (desc_edpt->bmAttributes.xfer << USB_OTG_DOEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DOEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << USB_OTG_DOEPCTL_MPSIZ_Pos); + + dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_OEPM_Pos + epnum)); + } + else + { + // "USB Data FIFOs" section in reference manual + // Peripheral FIFO architecture + // + // --------------- 320 or 1024 ( 1280 or 4096 bytes ) + // | IN FIFO 0 | + // --------------- (320 or 1024) - 16 + // | IN FIFO 1 | + // --------------- (320 or 1024) - 16 - x + // | . . . . | + // --------------- (320 or 1024) - 16 - x - y - ... - z + // | IN FIFO MAX | + // --------------- + // | FREE | + // --------------- GRXFSIZ + // | OUT FIFO | + // | ( Shared ) | + // --------------- 0 + // + // In FIFO is allocated by following rules: + // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". + + // Check if free space is available + TU_ASSERT(_allocated_fifo_words_tx + fifo_size + usb_otg->GRXFSIZ <= EP_FIFO_SIZE / 4); + + _allocated_fifo_words_tx += fifo_size; + + TU_LOG(2, " Allocated %u bytes at offset %u", fifo_size * 4, EP_FIFO_SIZE - _allocated_fifo_words_tx * 4); + + // DIEPTXF starts at FIFO #1. + // Both TXFD and TXSA are in unit of 32-bit words. + usb_otg->DIEPTXF[epnum - 1] = (fifo_size << USB_OTG_DIEPTXF_INEPTXFD_Pos) | (EP_FIFO_SIZE / 4 - _allocated_fifo_words_tx); + + in_ep[epnum].DIEPCTL |= (1 << USB_OTG_DIEPCTL_USBAEP_Pos) | + (epnum << USB_OTG_DIEPCTL_TXFNUM_Pos) | + (desc_edpt->bmAttributes.xfer << USB_OTG_DIEPCTL_EPTYP_Pos) | + (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? USB_OTG_DIEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << USB_OTG_DIEPCTL_MPSIZ_Pos); + + dev->DAINTMSK |= (1 << (USB_OTG_DAINTMSK_IEPM_Pos + epnum)); + } + + return true; } // Close all non-control endpoints, cancel all pending transfers if any. void dcd_edpt_close_all(uint8_t rhport) { - (void)rhport; + (void)rhport; - // USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); + // USB_OTG_GlobalTypeDef * usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); - // Disable non-control interrupt - dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); + // Disable non-control interrupt + dev->DAINTMSK = (1 << USB_OTG_DAINTMSK_OEPM_Pos) | (1 << USB_OTG_DAINTMSK_IEPM_Pos); - for (uint8_t n = 1; n < EP_MAX; n++) - { - // disable OUT endpoint - out_ep[n].DOEPCTL = 0; - xfer_status[n][TUSB_DIR_OUT].max_size = 0; + for (uint8_t n = 1; n < EP_MAX; n++) + { + // disable OUT endpoint + out_ep[n].DOEPCTL = 0; + xfer_status[n][TUSB_DIR_OUT].max_size = 0; - // disable IN endpoint - in_ep[n].DIEPCTL = 0; - xfer_status[n][TUSB_DIR_IN].max_size = 0; - } + // disable IN endpoint + in_ep[n].DIEPCTL = 0; + xfer_status[n][TUSB_DIR_IN].max_size = 0; + } - // reset allocated fifo IN - _allocated_fifo_words_tx = 16; + // reset allocated fifo IN + _allocated_fifo_words_tx = 16; } bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - xfer->ff = NULL; - xfer->total_len = total_bytes; - - // EP0 can only handle one packet - if (epnum == 0) - { - ep0_pending[dir] = total_bytes; - // Schedule the first transaction for EP0 transfer - edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); - return true; - } - - uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t const short_packet_size = total_bytes % xfer->max_size; - - // Zero-size packet is special case. - if (short_packet_size > 0 || (total_bytes == 0)) - { - num_packets++; - } - - // Schedule packets to be sent within interrupt - edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); - - return true; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + xfer->ff = NULL; + xfer->total_len = total_bytes; + + // EP0 can only handle one packet + if (epnum == 0) + { + ep0_pending[dir] = total_bytes; + // Schedule the first transaction for EP0 transfer + edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); + return true; + } + + uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t const short_packet_size = total_bytes % xfer->max_size; + + // Zero-size packet is special case. + if (short_packet_size > 0 || (total_bytes == 0)) + { + num_packets++; + } + + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); + + return true; } // The number of bytes has to be given explicitly to allow more flexible control of how many @@ -789,96 +789,96 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to // into the USB buffer! bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) { - // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 - TU_ASSERT(ff->item_size == 1); + // USB buffers always work in bytes so to avoid unnecessary divisions we demand item_size = 1 + TU_ASSERT(ff->item_size == 1); - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = NULL; - xfer->ff = ff; - xfer->total_len = total_bytes; + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = NULL; + xfer->ff = ff; + xfer->total_len = total_bytes; - uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t const short_packet_size = total_bytes % xfer->max_size; + uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t const short_packet_size = total_bytes % xfer->max_size; - // Zero-size packet is special case. - if (short_packet_size > 0 || (total_bytes == 0)) - num_packets++; + // Zero-size packet is special case. + if (short_packet_size > 0 || (total_bytes == 0)) + num_packets++; - // Schedule packets to be sent within interrupt - edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); - return true; + return true; } static void dcd_edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { - (void)rhport; - - USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (dir == TUSB_DIR_IN) - { - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA)) - { - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0); - } - else - { - // Stop transmitting packets and NAK IN xfers. - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK; - while ((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0) - ; - - // Disable the endpoint. - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0); - while ((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0) - ; - in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD; - } - - // Flush the FIFO, and wait until we have confirmed it cleared. - usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos); - usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH; - while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0) - ; - } - else - { - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA)) - { - out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0; - } - else - { - // Asserting GONAK is required to STALL an OUT endpoint. - // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt - // anyway, and it can't be cleared by user code. If this while loop never - // finishes, we have bigger problems than just the stack. - dev->DCTL |= USB_OTG_DCTL_SGONAK; - while ((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0) - ; - - // Ditto here- disable the endpoint. - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0); - while ((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0) - ; - out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD; - - // Allow other OUT endpoints to keep receiving. - dev->DCTL |= USB_OTG_DCTL_CGONAK; - } - } + (void)rhport; + + USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (dir == TUSB_DIR_IN) + { + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(in_ep[epnum].DIEPCTL & USB_OTG_DIEPCTL_EPENA)) + { + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK | (stall ? USB_OTG_DIEPCTL_STALL : 0); + } + else + { + // Stop transmitting packets and NAK IN xfers. + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + while ((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_INEPNE) == 0) + ; + + // Disable the endpoint. + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPDIS | (stall ? USB_OTG_DIEPCTL_STALL : 0); + while ((in_ep[epnum].DIEPINT & USB_OTG_DIEPINT_EPDISD_Msk) == 0) + ; + in_ep[epnum].DIEPINT = USB_OTG_DIEPINT_EPDISD; + } + + // Flush the FIFO, and wait until we have confirmed it cleared. + usb_otg->GRSTCTL |= (epnum << USB_OTG_GRSTCTL_TXFNUM_Pos); + usb_otg->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH; + while ((usb_otg->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0) + ; + } + else + { + // Only disable currently enabled non-control endpoint + if ((epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA)) + { + out_ep[epnum].DOEPCTL |= stall ? USB_OTG_DOEPCTL_STALL : 0; + } + else + { + // Asserting GONAK is required to STALL an OUT endpoint. + // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt + // anyway, and it can't be cleared by user code. If this while loop never + // finishes, we have bigger problems than just the stack. + dev->DCTL |= USB_OTG_DCTL_SGONAK; + while ((usb_otg->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0) + ; + + // Ditto here- disable the endpoint. + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_EPDIS | (stall ? USB_OTG_DOEPCTL_STALL : 0); + while ((out_ep[epnum].DOEPINT & USB_OTG_DOEPINT_EPDISD_Msk) == 0) + ; + out_ep[epnum].DOEPINT = USB_OTG_DOEPINT_EPDISD; + + // Allow other OUT endpoints to keep receiving. + dev->DCTL |= USB_OTG_DCTL_CGONAK; + } + } } /** @@ -886,56 +886,56 @@ static void dcd_edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) */ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - dcd_edpt_disable(rhport, ep_addr, false); - - // Update max_size - xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation - - if (dir == TUSB_DIR_IN) - { - uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos; - uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos; - // For now only the last opened endpoint can be closed without fuss. - TU_ASSERT(fifo_start == EP_FIFO_SIZE / 4 - _allocated_fifo_words_tx, ); - _allocated_fifo_words_tx -= fifo_size; - } - else - { - _out_ep_closed = true; // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty - } + USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + dcd_edpt_disable(rhport, ep_addr, false); + + // Update max_size + xfer_status[epnum][dir].max_size = 0; // max_size = 0 marks a disabled EP - required for changing FIFO allocation + + if (dir == TUSB_DIR_IN) + { + uint16_t const fifo_size = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXFD_Msk) >> USB_OTG_DIEPTXF_INEPTXFD_Pos; + uint16_t const fifo_start = (usb_otg->DIEPTXF[epnum - 1] & USB_OTG_DIEPTXF_INEPTXSA_Msk) >> USB_OTG_DIEPTXF_INEPTXSA_Pos; + // For now only the last opened endpoint can be closed without fuss. + TU_ASSERT(fifo_start == EP_FIFO_SIZE / 4 - _allocated_fifo_words_tx, ); + _allocated_fifo_words_tx -= fifo_size; + } + else + { + _out_ep_closed = true; // Set flag such that RX FIFO gets reduced in size once RX FIFO is empty + } } void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - dcd_edpt_disable(rhport, ep_addr, true); + dcd_edpt_disable(rhport, ep_addr, true); } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - // Clear stall and reset data toggle - if (dir == TUSB_DIR_IN) - { - in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - else - { - out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - } + (void)rhport; + + USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + // Clear stall and reset data toggle + if (dir == TUSB_DIR_IN) + { + in_ep[epnum].DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + else + { + out_ep[epnum].DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + out_ep[epnum].DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } } /*------------------------------------------------------------------*/ @@ -943,363 +943,363 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) // Read a single data packet from receive FIFO static void read_fifo_packet(uint8_t rhport, uint8_t *dst, uint16_t len) { - (void)rhport; - - usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); - - // Reading full available 32 bit words from fifo - uint16_t full_words = len >> 2; - for (uint16_t i = 0; i < full_words; i++) - { - uint32_t tmp = *rx_fifo; - dst[0] = tmp & 0x000000FF; - dst[1] = (tmp & 0x0000FF00) >> 8; - dst[2] = (tmp & 0x00FF0000) >> 16; - dst[3] = (tmp & 0xFF000000) >> 24; - dst += 4; - } - - // Read the remaining 1-3 bytes from fifo - uint8_t bytes_rem = len & 0x03; - if (bytes_rem != 0) - { - uint32_t tmp = *rx_fifo; - dst[0] = tmp & 0x000000FF; - if (bytes_rem > 1) - { - dst[1] = (tmp & 0x0000FF00) >> 8; - } - if (bytes_rem > 2) - { - dst[2] = (tmp & 0x00FF0000) >> 16; - } - } + (void)rhport; + + usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); + + // Reading full available 32 bit words from fifo + uint16_t full_words = len >> 2; + for (uint16_t i = 0; i < full_words; i++) + { + uint32_t tmp = *rx_fifo; + dst[0] = tmp & 0x000000FF; + dst[1] = (tmp & 0x0000FF00) >> 8; + dst[2] = (tmp & 0x00FF0000) >> 16; + dst[3] = (tmp & 0xFF000000) >> 24; + dst += 4; + } + + // Read the remaining 1-3 bytes from fifo + uint8_t bytes_rem = len & 0x03; + if (bytes_rem != 0) + { + uint32_t tmp = *rx_fifo; + dst[0] = tmp & 0x000000FF; + if (bytes_rem > 1) + { + dst[1] = (tmp & 0x0000FF00) >> 8; + } + if (bytes_rem > 2) + { + dst[2] = (tmp & 0x00FF0000) >> 16; + } + } } // Write a single data packet to EPIN FIFO static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t *src, uint16_t len) { - (void)rhport; - - usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num); - - // Pushing full available 32 bit words to fifo - uint16_t full_words = len >> 2; - for (uint16_t i = 0; i < full_words; i++) - { - *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0]; - src += 4; - } - - // Write the remaining 1-3 bytes into fifo - uint8_t bytes_rem = len & 0x03; - if (bytes_rem) - { - uint32_t tmp_word = 0; - tmp_word |= src[0]; - if (bytes_rem > 1) - { - tmp_word |= src[1] << 8; - } - if (bytes_rem > 2) - { - tmp_word |= src[2] << 16; - } - *tx_fifo = tmp_word; - } + (void)rhport; + + usb_fifo_t tx_fifo = FIFO_BASE(rhport, fifo_num); + + // Pushing full available 32 bit words to fifo + uint16_t full_words = len >> 2; + for (uint16_t i = 0; i < full_words; i++) + { + *tx_fifo = (src[3] << 24) | (src[2] << 16) | (src[1] << 8) | src[0]; + src += 4; + } + + // Write the remaining 1-3 bytes into fifo + uint8_t bytes_rem = len & 0x03; + if (bytes_rem) + { + uint32_t tmp_word = 0; + tmp_word |= src[0]; + if (bytes_rem > 1) + { + tmp_word |= src[1] << 8; + } + if (bytes_rem > 2) + { + tmp_word |= src[2] << 16; + } + *tx_fifo = tmp_word; + } } static void handle_rxflvl_ints(uint8_t rhport, USB_OTG_OUTEndpointTypeDef *out_ep) { - USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); - usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); - - // Pop control word off FIFO - uint32_t ctl_word = usb_otg->GRXSTSP; - uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos; - uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos; - uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos; - - switch (pktsts) - { - case 0x01: // Global OUT NAK (Interrupt) - break; - - case 0x02: // Out packet recvd - { - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - - // Read packet off RxFIFO - if (xfer->ff) - { - // Ring buffer - tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t)rx_fifo, bcnt); - } - else - { - // Linear buffer - read_fifo_packet(rhport, xfer->buffer, bcnt); - - // Increment pointer to xfer data - xfer->buffer += bcnt; - } - - // Truncate transfer length in case of short packet - if (bcnt < xfer->max_size) - { - xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos; - if (epnum == 0) - { - xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; - ep0_pending[TUSB_DIR_OUT] = 0; - } - } - } - break; - - case 0x03: // Out packet done (Interrupt) - break; - - case 0x04: // Setup packet done (Interrupt) - out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); - break; - - case 0x06: // Setup packet recvd - // We can receive up to three setup packets in succession, but - // only the last one is valid. - _setup_packet[0] = (*rx_fifo); - _setup_packet[1] = (*rx_fifo); - break; - - default: // Invalid - TU_BREAKPOINT(); - break; - } + USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); + usb_fifo_t rx_fifo = FIFO_BASE(rhport, 0); + + // Pop control word off FIFO + uint32_t ctl_word = usb_otg->GRXSTSP; + uint8_t pktsts = (ctl_word & USB_OTG_GRXSTSP_PKTSTS_Msk) >> USB_OTG_GRXSTSP_PKTSTS_Pos; + uint8_t epnum = (ctl_word & USB_OTG_GRXSTSP_EPNUM_Msk) >> USB_OTG_GRXSTSP_EPNUM_Pos; + uint16_t bcnt = (ctl_word & USB_OTG_GRXSTSP_BCNT_Msk) >> USB_OTG_GRXSTSP_BCNT_Pos; + + switch (pktsts) + { + case 0x01: // Global OUT NAK (Interrupt) + break; + + case 0x02: // Out packet recvd + { + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + + // Read packet off RxFIFO + if (xfer->ff) + { + // Ring buffer + tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void *)(uintptr_t)rx_fifo, bcnt); + } + else + { + // Linear buffer + read_fifo_packet(rhport, xfer->buffer, bcnt); + + // Increment pointer to xfer data + xfer->buffer += bcnt; + } + + // Truncate transfer length in case of short packet + if (bcnt < xfer->max_size) + { + xfer->total_len -= (out_ep[epnum].DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DOEPTSIZ_XFRSIZ_Pos; + if (epnum == 0) + { + xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; + ep0_pending[TUSB_DIR_OUT] = 0; + } + } + } + break; + + case 0x03: // Out packet done (Interrupt) + break; + + case 0x04: // Setup packet done (Interrupt) + out_ep[epnum].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos); + break; + + case 0x06: // Setup packet recvd + // We can receive up to three setup packets in succession, but + // only the last one is valid. + _setup_packet[0] = (*rx_fifo); + _setup_packet[1] = (*rx_fifo); + break; + + default: // Invalid + TU_BREAKPOINT(); + break; + } } static void handle_epout_ints(uint8_t rhport, USB_OTG_DeviceTypeDef *dev, USB_OTG_OUTEndpointTypeDef *out_ep) { - // DAINT for a given EP clears when DOEPINTx is cleared. - // OEPINT will be cleared when DAINT's out bits are cleared. - for (uint8_t n = 0; n < EP_MAX; n++) - { - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - - if (dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) - { - // SETUP packet Setup Phase done. - if (out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) - { - out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP; - dcd_event_setup_received(rhport, (uint8_t *)&_setup_packet[0], true); - } - - // OUT XFER complete - if (out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) - { - out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC; - - // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) - { - // Schedule another packet to be received. - edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); - } - else - { - dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - } - } - } + // DAINT for a given EP clears when DOEPINTx is cleared. + // OEPINT will be cleared when DAINT's out bits are cleared. + for (uint8_t n = 0; n < EP_MAX; n++) + { + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + + if (dev->DAINT & (1 << (USB_OTG_DAINT_OEPINT_Pos + n))) + { + // SETUP packet Setup Phase done. + if (out_ep[n].DOEPINT & USB_OTG_DOEPINT_STUP) + { + out_ep[n].DOEPINT = USB_OTG_DOEPINT_STUP; + dcd_event_setup_received(rhport, (uint8_t *)&_setup_packet[0], true); + } + + // OUT XFER complete + if (out_ep[n].DOEPINT & USB_OTG_DOEPINT_XFRC) + { + out_ep[n].DOEPINT = USB_OTG_DOEPINT_XFRC; + + // EP0 can only handle one packet + if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) + { + // Schedule another packet to be received. + edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + } + else + { + dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + } + } } static void handle_epin_ints(uint8_t rhport, USB_OTG_DeviceTypeDef *dev, USB_OTG_INEndpointTypeDef *in_ep) { - // DAINT for a given EP clears when DIEPINTx is cleared. - // IEPINT will be cleared when DAINT's out bits are cleared. - for (uint8_t n = 0; n < EP_MAX; n++) - { - xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - - if (dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n))) - { - // IN XFER complete (entire xfer). - if (in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC) - { - in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC; - - // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_IN]) - { - // Schedule another packet to be transmitted. - edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); - } - else - { - dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - } - - // XFER FIFO empty - if ((in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n))) - { - // DIEPINT's TXFE bit is read-only, software cannot clear it. - // It will only be cleared by hardware when written bytes is more than - // - 64 bytes or - // - Half of TX FIFO size (configured by DIEPTXF) - - uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos; - - // Process every single packet (only whole packets can be written to fifo) - for (uint16_t i = 0; i < remaining_packets; i++) - { - uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos; - - // Packet can not be larger than ep max size - uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); - - // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current - // EP has to be checked if the buffer can take another WHOLE packet - if (packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) - break; - - // Push packet to Tx-FIFO - if (xfer->ff) - { - usb_fifo_t tx_fifo = FIFO_BASE(rhport, n); - tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t)tx_fifo, packet_size); - } - else - { - write_fifo_packet(rhport, n, xfer->buffer, packet_size); - - // Increment pointer to xfer data - xfer->buffer += packet_size; - } - } - - // Turn off TXFE if all bytes are written. - if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0) - { - dev->DIEPEMPMSK &= ~(1 << n); - } - } - } - } + // DAINT for a given EP clears when DIEPINTx is cleared. + // IEPINT will be cleared when DAINT's out bits are cleared. + for (uint8_t n = 0; n < EP_MAX; n++) + { + xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); + + if (dev->DAINT & (1 << (USB_OTG_DAINT_IEPINT_Pos + n))) + { + // IN XFER complete (entire xfer). + if (in_ep[n].DIEPINT & USB_OTG_DIEPINT_XFRC) + { + in_ep[n].DIEPINT = USB_OTG_DIEPINT_XFRC; + + // EP0 can only handle one packet + if ((n == 0) && ep0_pending[TUSB_DIR_IN]) + { + // Schedule another packet to be transmitted. + edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); + } + else + { + dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + + // XFER FIFO empty + if ((in_ep[n].DIEPINT & USB_OTG_DIEPINT_TXFE) && (dev->DIEPEMPMSK & (1 << n))) + { + // DIEPINT's TXFE bit is read-only, software cannot clear it. + // It will only be cleared by hardware when written bytes is more than + // - 64 bytes or + // - Half of TX FIFO size (configured by DIEPTXF) + + uint16_t remaining_packets = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_PKTCNT_Msk) >> USB_OTG_DIEPTSIZ_PKTCNT_Pos; + + // Process every single packet (only whole packets can be written to fifo) + for (uint16_t i = 0; i < remaining_packets; i++) + { + uint16_t const remaining_bytes = (in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos; + + // Packet can not be larger than ep max size + uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); + + // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current + // EP has to be checked if the buffer can take another WHOLE packet + if (packet_size > ((in_ep[n].DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV_Msk) << 2)) + break; + + // Push packet to Tx-FIFO + if (xfer->ff) + { + usb_fifo_t tx_fifo = FIFO_BASE(rhport, n); + tu_fifo_read_n_const_addr_full_words(xfer->ff, (void *)(uintptr_t)tx_fifo, packet_size); + } + else + { + write_fifo_packet(rhport, n, xfer->buffer, packet_size); + + // Increment pointer to xfer data + xfer->buffer += packet_size; + } + } + + // Turn off TXFE if all bytes are written. + if (((in_ep[n].DIEPTSIZ & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) >> USB_OTG_DIEPTSIZ_XFRSIZ_Pos) == 0) + { + dev->DIEPEMPMSK &= ~(1 << n); + } + } + } + } } void dcd_int_handler(uint8_t rhport) { - USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); - USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); - USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); - USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); - - uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK; - - if (int_status & USB_OTG_GINTSTS_USBRST) - { - // USBRST is start of reset. - usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST; - bus_reset(rhport); - } - - if (int_status & USB_OTG_GINTSTS_ENUMDNE) - { - // ENUMDNE is the end of reset where speed of the link is detected - - usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE; - - tusb_speed_t const speed = get_speed(rhport); - - set_turnaround(usb_otg, speed); - dcd_event_bus_reset(rhport, speed, true); - } - - if (int_status & USB_OTG_GINTSTS_USBSUSP) - { - usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP; - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); - } - - if (int_status & USB_OTG_GINTSTS_WKUINT) - { - usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT; - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); - } - - // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection - // if(int_status & USB_OTG_GINTSTS_DISCINT) - - if (int_status & USB_OTG_GINTSTS_OTGINT) - { - // OTG INT bit is read-only - uint32_t const otg_int = usb_otg->GOTGINT; - - if (otg_int & USB_OTG_GOTGINT_SEDET) - { - dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); - } - - usb_otg->GOTGINT = otg_int; - } - - if (int_status & USB_OTG_GINTSTS_SOF) - { - usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; - - // Disable SOF interrupt since currently only used for remote wakeup detection - usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM; - - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); - } - - // RxFIFO non-empty interrupt handling. - if (int_status & USB_OTG_GINTSTS_RXFLVL) - { - // RXFLVL bit is read-only - - // Mask out RXFLVL while reading data from FIFO - usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM; - - // Loop until all available packets were handled - do - { - handle_rxflvl_ints(rhport, out_ep); - } while (usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL); - - // Manage RX FIFO size - if (_out_ep_closed) - { - update_grxfsiz(rhport); - - // Disable flag - _out_ep_closed = false; - } - - usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - // OUT endpoint interrupt handling. - if (int_status & USB_OTG_GINTSTS_OEPINT) - { - // OEPINT is read-only - handle_epout_ints(rhport, dev, out_ep); - } - - // IN endpoint interrupt handling. - if (int_status & USB_OTG_GINTSTS_IEPINT) - { - // IEPINT bit read-only - handle_epin_ints(rhport, dev, in_ep); - } - - // // Check for Incomplete isochronous IN transfer - // if(int_status & USB_OTG_GINTSTS_IISOIXFR) { - // printf(" IISOIXFR!\r\n"); - //// TU_LOG2(" IISOIXFR!\r\n"); - // } + USB_OTG_GlobalTypeDef *usb_otg = GLOBAL_BASE(rhport); + USB_OTG_DeviceTypeDef *dev = DEVICE_BASE(rhport); + USB_OTG_OUTEndpointTypeDef *out_ep = OUT_EP_BASE(rhport); + USB_OTG_INEndpointTypeDef *in_ep = IN_EP_BASE(rhport); + + uint32_t const int_status = usb_otg->GINTSTS & usb_otg->GINTMSK; + + if (int_status & USB_OTG_GINTSTS_USBRST) + { + // USBRST is start of reset. + usb_otg->GINTSTS = USB_OTG_GINTSTS_USBRST; + bus_reset(rhport); + } + + if (int_status & USB_OTG_GINTSTS_ENUMDNE) + { + // ENUMDNE is the end of reset where speed of the link is detected + + usb_otg->GINTSTS = USB_OTG_GINTSTS_ENUMDNE; + + tusb_speed_t const speed = get_speed(rhport); + + set_turnaround(usb_otg, speed); + dcd_event_bus_reset(rhport, speed, true); + } + + if (int_status & USB_OTG_GINTSTS_USBSUSP) + { + usb_otg->GINTSTS = USB_OTG_GINTSTS_USBSUSP; + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + + if (int_status & USB_OTG_GINTSTS_WKUINT) + { + usb_otg->GINTSTS = USB_OTG_GINTSTS_WKUINT; + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + + // TODO check USB_OTG_GINTSTS_DISCINT for disconnect detection + // if(int_status & USB_OTG_GINTSTS_DISCINT) + + if (int_status & USB_OTG_GINTSTS_OTGINT) + { + // OTG INT bit is read-only + uint32_t const otg_int = usb_otg->GOTGINT; + + if (otg_int & USB_OTG_GOTGINT_SEDET) + { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + + usb_otg->GOTGINT = otg_int; + } + + if (int_status & USB_OTG_GINTSTS_SOF) + { + usb_otg->GINTSTS = USB_OTG_GINTSTS_SOF; + + // Disable SOF interrupt since currently only used for remote wakeup detection + usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_SOFM; + + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } + + // RxFIFO non-empty interrupt handling. + if (int_status & USB_OTG_GINTSTS_RXFLVL) + { + // RXFLVL bit is read-only + + // Mask out RXFLVL while reading data from FIFO + usb_otg->GINTMSK &= ~USB_OTG_GINTMSK_RXFLVLM; + + // Loop until all available packets were handled + do + { + handle_rxflvl_ints(rhport, out_ep); + } while (usb_otg->GINTSTS & USB_OTG_GINTSTS_RXFLVL); + + // Manage RX FIFO size + if (_out_ep_closed) + { + update_grxfsiz(rhport); + + // Disable flag + _out_ep_closed = false; + } + + usb_otg->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + // OUT endpoint interrupt handling. + if (int_status & USB_OTG_GINTSTS_OEPINT) + { + // OEPINT is read-only + handle_epout_ints(rhport, dev, out_ep); + } + + // IN endpoint interrupt handling. + if (int_status & USB_OTG_GINTSTS_IEPINT) + { + // IEPINT bit read-only + handle_epin_ints(rhport, dev, in_ep); + } + + // // Check for Incomplete isochronous IN transfer + // if(int_status & USB_OTG_GINTSTS_IISOIXFR) { + // printf(" IISOIXFR!\r\n"); + //// TU_LOG2(" IISOIXFR!\r\n"); + // } } #endif diff --git a/uCNC/src/tinyusb/src/portable/st/synopsys/synopsys_common.h b/uCNC/src/tinyusb/src/portable/st/synopsys/synopsys_common.h index 4c4a7997e..6f0602fe9 100644 --- a/uCNC/src/tinyusb/src/portable/st/synopsys/synopsys_common.h +++ b/uCNC/src/tinyusb/src/portable/st/synopsys/synopsys_common.h @@ -1,175 +1,175 @@ /** - ****************************************************************************** - * @file synopsys_common.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device USB OTG peripheral Header File. - * This file contains the USB OTG peripheral register's definitions, bits - * definitions and memory mapping for STM32F1xx devices. - * - * This file contains: - * - Data structures and the address mapping for the USB OTG peripheral - * - The Peripheral's registers declarations and bits definition - * - Macros to access the peripheral's registers hardware - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + ****************************************************************************** + * @file synopsys_common.h + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device USB OTG peripheral Header File. + * This file contains the USB OTG peripheral register's definitions, bits + * definitions and memory mapping for STM32F1xx devices. + * + * This file contains: + * - Data structures and the address mapping for the USB OTG peripheral + * - The Peripheral's registers declarations and bits definition + * - Macros to access the peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ #include "stdint.h" #pragma once #ifdef __cplusplus -#define __I volatile + #define __I volatile #else -#define __I volatile const + #define __I volatile const #endif -#define __O volatile -#define __IO volatile -#define __IM volatile const -#define __OM volatile -#define __IOM volatile +#define __O volatile +#define __IO volatile +#define __IM volatile const +#define __OM volatile +#define __IOM volatile -/** - * @brief __USB_OTG_Core_register - */ +/** + * @brief __USB_OTG_Core_register + */ typedef struct { - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ - __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ - uint32_t Reserved30[2]; /*!< Reserved 030h*/ - __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ - __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ - uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ } USB_OTG_GlobalTypeDef; -/** - * @brief __device_Registers - */ +/** + * @brief __device_Registers + */ -typedef struct +typedef struct { - __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/ - __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/ - __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/ - uint32_t Reserved0C; /*!< Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/ - uint32_t Reserved20; /*!< Reserved 820h*/ - uint32_t Reserved9; /*!< Reserved 824h*/ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/ - __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ - uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/ - uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/ + __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/ + __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/ + __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/ + uint32_t Reserved0C; /*!< Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/ + uint32_t Reserved20; /*!< Reserved 820h*/ + uint32_t Reserved9; /*!< Reserved 824h*/ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/ + __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ + uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/ } USB_OTG_DeviceTypeDef; -/** - * @brief __IN_Endpoint-Specific_Register - */ +/** + * @brief __IN_Endpoint-Specific_Register + */ -typedef struct +typedef struct { - __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ } USB_OTG_INEndpointTypeDef; -/** - * @brief __OUT_Endpoint-Specific_Registers - */ +/** + * @brief __OUT_Endpoint-Specific_Registers + */ -typedef struct +typedef struct { - __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ } USB_OTG_OUTEndpointTypeDef; -/** - * @brief __Host_Mode_Register_Structures - */ +/** + * @brief __Host_Mode_Register_Structures + */ -typedef struct +typedef struct { - __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/ - __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /*!< Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /*!< Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/ } USB_OTG_HostTypeDef; -/** - * @brief __Host_Channel_Specific_Registers - */ +/** + * @brief __Host_Channel_Specific_Registers + */ typedef struct { - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; } USB_OTG_HostChannelTypeDef; /*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE 0x50000000UL - -#define USB_OTG_GLOBAL_BASE 0x00000000UL -#define USB_OTG_DEVICE_BASE 0x00000800UL -#define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL -#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL -#define USB_OTG_EP_REG_SIZE 0x00000020UL -#define USB_OTG_HOST_BASE 0x00000400UL -#define USB_OTG_HOST_PORT_BASE 0x00000440UL -#define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL -#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL -#define USB_OTG_PCGCCTL_BASE 0x00000E00UL -#define USB_OTG_FIFO_BASE 0x00001000UL -#define USB_OTG_FIFO_SIZE 0x00001000UL +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_GLOBAL_BASE 0x00000000UL +#define USB_OTG_DEVICE_BASE 0x00000800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL +#define USB_OTG_EP_REG_SIZE 0x00000020UL +#define USB_OTG_HOST_BASE 0x00000400UL +#define USB_OTG_HOST_PORT_BASE 0x00000440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL +#define USB_OTG_PCGCCTL_BASE 0x00000E00UL +#define USB_OTG_FIFO_BASE 0x00001000UL +#define USB_OTG_FIFO_SIZE 0x00001000UL /******************************************************************************/ /* */ @@ -177,1288 +177,1289 @@ typedef struct /* */ /******************************************************************************/ /******************** Bit definition for USB_OTG_GOTGCTL register ***********/ -#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) -#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ -#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ -#define USB_OTG_GOTGCTL_SRQ_Pos (1U) -#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ -#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ -#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) -#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ -#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) -#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ -#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ -#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) -#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ -#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ -#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) -#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ -#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ -#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) -#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ -#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ -#define USB_OTG_GOTGCTL_DBCT_Pos (17U) -#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ -#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ -#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) -#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ -#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ -#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ /******************** Bit definition for USB_OTG_HCFG register ********************/ -#define USB_OTG_HCFG_FSLSPCS_Pos (0U) -#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ -#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ -#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCFG_FSLSS_Pos (2U) -#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ /******************** Bit definition for USB_OTG_DCFG register ********************/ -#define USB_OTG_DCFG_DSPD_Pos (0U) -#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ -#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ -#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ -#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) -#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ -#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ - -#define USB_OTG_DCFG_DAD_Pos (4U) -#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ -#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ -#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ -#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ -#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ -#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ -#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ -#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ -#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ - -#define USB_OTG_DCFG_PFIVL_Pos (11U) -#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ -#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ -#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ -#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ - -#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) -#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ -#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ -#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ -#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ +#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ /******************** Bit definition for USB_OTG_PCGCR register ********************/ -#define USB_OTG_PCGCR_STPPCLK_Pos (0U) -#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ -#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) -#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ -#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) -#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ -#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ /******************** Bit definition for USB_OTG_GOTGINT register ********************/ -#define USB_OTG_GOTGINT_SEDET_Pos (2U) -#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ -#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ -#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) -#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ -#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ -#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) -#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ -#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ -#define USB_OTG_GOTGINT_HNGDET_Pos (17U) -#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ -#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ -#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) -#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ -#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ -#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) -#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ +#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ /******************** Bit definition for USB_OTG_DCTL register ********************/ -#define USB_OTG_DCTL_RWUSIG_Pos (0U) -#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ -#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ -#define USB_OTG_DCTL_SDIS_Pos (1U) -#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ -#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ -#define USB_OTG_DCTL_GINSTS_Pos (2U) -#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ -#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ -#define USB_OTG_DCTL_GONSTS_Pos (3U) -#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ -#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ - -#define USB_OTG_DCTL_TCTL_Pos (4U) -#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ -#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ -#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ -#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ -#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ -#define USB_OTG_DCTL_SGINAK_Pos (7U) -#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ -#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ -#define USB_OTG_DCTL_CGINAK_Pos (8U) -#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ -#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ -#define USB_OTG_DCTL_SGONAK_Pos (9U) -#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ -#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ -#define USB_OTG_DCTL_CGONAK_Pos (10U) -#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ -#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ -#define USB_OTG_DCTL_POPRGDNE_Pos (11U) -#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ -#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ /******************** Bit definition for USB_OTG_HFIR register ********************/ -#define USB_OTG_HFIR_FRIVL_Pos (0U) -#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ -#define USB_OTG_HFNUM_FRNUM_Pos (0U) -#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ -#define USB_OTG_HFNUM_FTREM_Pos (16U) -#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ +#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ /******************** Bit definition for USB_OTG_DSTS register ********************/ -#define USB_OTG_DSTS_SUSPSTS_Pos (0U) -#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ -#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ - -#define USB_OTG_DSTS_ENUMSPD_Pos (1U) -#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ -#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ -#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ -#define USB_OTG_DSTS_EERR_Pos (3U) -#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ -#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ -#define USB_OTG_DSTS_FNSOF_Pos (8U) -#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ -#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ -#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) -#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ -#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ -#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ -#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ -#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ -#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ -#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ -#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) -#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ -#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ -#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) -#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ -#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ -#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) -#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ -#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ +#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ -#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) -#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ -#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ -#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ -#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ -#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ -#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) -#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ -#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ -#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) -#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ -#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ -#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) -#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ -#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ -#define USB_OTG_GUSBCFG_TRDT_Pos (10U) -#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ -#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ -#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ -#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ -#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ -#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ -#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) -#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ -#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ -#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) -#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ -#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ -#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) -#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ -#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) -#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ -#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) -#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ -#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ -#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) -#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ -#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ -#define USB_OTG_GUSBCFG_PCCI_Pos (23U) -#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ -#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ -#define USB_OTG_GUSBCFG_PTCI_Pos (24U) -#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ -#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ -#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) -#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ -#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ -#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) -#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ -#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ -#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) -#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ -#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ -#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) -#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ -#define USB_OTG_GRSTCTL_CSRST_Pos (0U) -#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ -#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ -#define USB_OTG_GRSTCTL_FCRST_Pos (2U) -#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ -#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ -#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) -#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ -#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ -#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) -#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ -#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ - -#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) -#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ -#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ -#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ -#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ -#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ -#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ -#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) -#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ -#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ -#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) -#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ -#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ + + +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ -#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) -#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPMSK_EPDM_Pos (1U) -#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPMSK_TOM_Pos (3U) -#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) -#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) -#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) -#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ -#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) -#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ -#define USB_OTG_DIEPMSK_BIM_Pos (9U) -#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ -#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) -#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ -#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) -#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ -#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ -#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ -#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ - -#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) -#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ -#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ -#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ /******************** Bit definition for USB_OTG_HAINT register ********************/ -#define USB_OTG_HAINT_HAINT_Pos (0U) -#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ +#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ -#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) -#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPMSK_EPDM_Pos (1U) -#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) -#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ -#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ -#define USB_OTG_DOEPMSK_STUPM_Pos (3U) -#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ -#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) -#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ -#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ -#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) -#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ -#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) -#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ -#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ -#define USB_OTG_DOEPMSK_BOIM_Pos (9U) -#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DOEPMSK_BERRM_Pos (12U) -#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ -#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ -#define USB_OTG_DOEPMSK_NAKM_Pos (13U) -#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ -#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ -#define USB_OTG_DOEPMSK_NYETM_Pos (14U) -#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ -#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKM_Pos (13U) +#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETM_Pos (14U) +#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ -#define USB_OTG_GINTSTS_CMOD_Pos (0U) -#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ -#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ -#define USB_OTG_GINTSTS_MMIS_Pos (1U) -#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ -#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ -#define USB_OTG_GINTSTS_OTGINT_Pos (2U) -#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ -#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ -#define USB_OTG_GINTSTS_SOF_Pos (3U) -#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ -#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ -#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) -#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ -#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ -#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) -#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ -#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ -#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) -#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ -#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ -#define USB_OTG_GINTSTS_ESUSP_Pos (10U) -#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ -#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ -#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) -#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ -#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ -#define USB_OTG_GINTSTS_USBRST_Pos (12U) -#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ -#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ -#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) -#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ -#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ -#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) -#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ -#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ -#define USB_OTG_GINTSTS_EOPF_Pos (15U) -#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ -#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ -#define USB_OTG_GINTSTS_IEPINT_Pos (18U) -#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ -#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ -#define USB_OTG_GINTSTS_OEPINT_Pos (19U) -#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ -#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ -#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) -#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ -#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ -#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) -#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ -#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ -#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) -#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ -#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ -#define USB_OTG_GINTSTS_HCINT_Pos (25U) -#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ -#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ -#define USB_OTG_GINTSTS_PTXFE_Pos (26U) -#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ -#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ -#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) -#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ -#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ -#define USB_OTG_GINTSTS_DISCINT_Pos (29U) -#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ -#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ -#define USB_OTG_GINTSTS_SRQINT_Pos (30U) -#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ -#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ -#define USB_OTG_GINTMSK_MMISM_Pos (1U) -#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ -#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ -#define USB_OTG_GINTMSK_OTGINT_Pos (2U) -#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ -#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ -#define USB_OTG_GINTMSK_SOFM_Pos (3U) -#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ -#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ -#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) -#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ -#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ -#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) -#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ -#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) -#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ -#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ -#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) -#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ -#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) -#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ -#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ -#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) -#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ -#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ -#define USB_OTG_GINTMSK_USBRST_Pos (12U) -#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ -#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ -#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) -#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ -#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ -#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) -#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ -#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ -#define USB_OTG_GINTMSK_EOPFM_Pos (15U) -#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ -#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ -#define USB_OTG_GINTMSK_EPMISM_Pos (17U) -#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ -#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ -#define USB_OTG_GINTMSK_IEPINT_Pos (18U) -#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ -#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ -#define USB_OTG_GINTMSK_OEPINT_Pos (19U) -#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ -#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ -#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) -#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ -#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ -#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) -#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ -#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ -#define USB_OTG_GINTMSK_PRTIM_Pos (24U) -#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ -#define USB_OTG_GINTMSK_HCIM_Pos (25U) -#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ -#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ -#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) -#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ -#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ -#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) -#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ -#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ -#define USB_OTG_GINTMSK_DISCINT_Pos (29U) -#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ -#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ -#define USB_OTG_GINTMSK_SRQIM_Pos (30U) -#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ -#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ -#define USB_OTG_GINTMSK_WUIM_Pos (31U) -#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ +#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ /******************** Bit definition for USB_OTG_DAINT register ********************/ -#define USB_OTG_DAINT_IEPINT_Pos (0U) -#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ -#define USB_OTG_DAINT_OEPINT_Pos (16U) -#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ +#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ -#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) -#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_BCNT_Pos (4U) -#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_DPID_Pos (15U) -#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ -#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) -#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ -#define USB_OTG_DAINTMSK_IEPM_Pos (0U) -#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ -#define USB_OTG_DAINTMSK_OEPM_Pos (16U) -#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ -#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) -#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ -#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) -#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ /******************** Bit definition for OTG register ********************/ -#define USB_OTG_NPTXFSA_Pos (0U) -#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ -#define USB_OTG_NPTXFD_Pos (16U) -#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ -#define USB_OTG_TX0FSA_Pos (0U) -#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ -#define USB_OTG_TX0FD_Pos (16U) -#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ +#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ -#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) -#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ -#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ -#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) -#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ - -#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) -#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ -#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ - -#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) -#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ -#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ /******************** Bit definition for USB_OTG_DTHRCTL register ********************/ -#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) -#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ -#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ -#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) -#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ -#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ - -#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) -#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ -#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ -#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ -#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ -#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) -#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ -#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ - -#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) -#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ -#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) -#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ -#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ -#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) -#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ /******************** Bit definition for USB_OTG_DEACHINT register ********************/ -#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) -#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ -#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ -#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) -#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ -#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ /******************** Bit definition for USB_OTG_GCCFG register ********************/ -#define USB_OTG_GCCFG_PWRDWN_Pos (16U) -#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ -#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ -#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) -#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ -#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) -#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ -#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ -#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) -#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ -#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ +#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) +#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) +#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) +#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ -#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) -#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ -#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) -#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ -#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ /******************** Bit definition for USB_OTG_CID register ********************/ -#define USB_OTG_CID_PRODUCT_ID_Pos (0U) -#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ -#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ -#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) -#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) -#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) -#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) -#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) -#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) -#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ -#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) -#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) -#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPRT register ********************/ -#define USB_OTG_HPRT_PCSTS_Pos (0U) -#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ -#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ -#define USB_OTG_HPRT_PCDET_Pos (1U) -#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ -#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ -#define USB_OTG_HPRT_PENA_Pos (2U) -#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ -#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ -#define USB_OTG_HPRT_PENCHNG_Pos (3U) -#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ -#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ -#define USB_OTG_HPRT_POCA_Pos (4U) -#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ -#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ -#define USB_OTG_HPRT_POCCHNG_Pos (5U) -#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ -#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ -#define USB_OTG_HPRT_PRES_Pos (6U) -#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ -#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ -#define USB_OTG_HPRT_PSUSP_Pos (7U) -#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ -#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ -#define USB_OTG_HPRT_PRST_Pos (8U) -#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ -#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - -#define USB_OTG_HPRT_PLSTS_Pos (10U) -#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ -#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ -#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ -#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ -#define USB_OTG_HPRT_PPWR_Pos (12U) -#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ -#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - -#define USB_OTG_HPRT_PTCTL_Pos (13U) -#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ -#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ -#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ -#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ -#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ -#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - -#define USB_OTG_HPRT_PSPD_Pos (17U) -#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ -#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ -#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ -#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ +#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ + +#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ -#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) -#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) -#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ -#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) -#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ -#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ -#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) -#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ -#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ -#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) -#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ -#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ -#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) -#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ -#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) -#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ -#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) -#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ -#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) -#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ -#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ -#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) -#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ -#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ -#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) -#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ -#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) -#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ -#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) -#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ -#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ -#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) -#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ -#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ -#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) -#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ - -#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) -#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ -#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ -#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ -#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ -#define USB_OTG_DIEPCTL_STALL_Pos (21U) -#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ -#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ - -#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) -#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ -#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ -#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ -#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ -#define USB_OTG_DIEPCTL_CNAK_Pos (26U) -#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ -#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ -#define USB_OTG_DIEPCTL_SNAK_Pos (27U) -#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ -#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ -#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) -#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ -#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ -#define USB_OTG_DIEPCTL_EPENA_Pos (31U) -#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ -#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ /******************** Bit definition for USB_OTG_HCCHAR register ********************/ -#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) -#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ -#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - -#define USB_OTG_HCCHAR_EPNUM_Pos (11U) -#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ -#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ -#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ -#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ -#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ -#define USB_OTG_HCCHAR_EPDIR_Pos (15U) -#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ -#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ -#define USB_OTG_HCCHAR_LSDEV_Pos (17U) -#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ -#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - -#define USB_OTG_HCCHAR_EPTYP_Pos (18U) -#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ -#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ -#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ -#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - -#define USB_OTG_HCCHAR_DAD_Pos (22U) -#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ -#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ -#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ -#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ -#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ -#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ -#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ -#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ -#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ -#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) -#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ -#define USB_OTG_HCCHAR_CHDIS_Pos (30U) -#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ -#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ -#define USB_OTG_HCCHAR_CHENA_Pos (31U) -#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ + +#define USB_OTG_HCCHAR_MC_Pos (20U) +#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ + +#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ /******************** Bit definition for USB_OTG_HCSPLT register ********************/ -#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) -#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ -#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ -#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ -#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ -#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ -#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ - -#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) -#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ -#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ -#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ -#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ -#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ -#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ -#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ -#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ -#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ - -#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) -#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ -#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ -#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ -#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ -#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) -#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ -#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ -#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) -#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ + +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ + +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ /******************** Bit definition for USB_OTG_HCINT register ********************/ -#define USB_OTG_HCINT_XFRC_Pos (0U) -#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ -#define USB_OTG_HCINT_CHH_Pos (1U) -#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ -#define USB_OTG_HCINT_AHBERR_Pos (2U) -#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ -#define USB_OTG_HCINT_STALL_Pos (3U) -#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ -#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ -#define USB_OTG_HCINT_NAK_Pos (4U) -#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ -#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ -#define USB_OTG_HCINT_ACK_Pos (5U) -#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ -#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ -#define USB_OTG_HCINT_NYET_Pos (6U) -#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ -#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ -#define USB_OTG_HCINT_TXERR_Pos (7U) -#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ -#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ -#define USB_OTG_HCINT_BBERR_Pos (8U) -#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ -#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ -#define USB_OTG_HCINT_FRMOR_Pos (9U) -#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ -#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ -#define USB_OTG_HCINT_DTERR_Pos (10U) -#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ -#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ +#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ /******************** Bit definition for USB_OTG_DIEPINT register ********************/ -#define USB_OTG_DIEPINT_XFRC_Pos (0U) -#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ -#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ -#define USB_OTG_DIEPINT_EPDISD_Pos (1U) -#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ -#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ -#define USB_OTG_DIEPINT_AHBERR_Pos (2U) -#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ -#define USB_OTG_DIEPINT_TOC_Pos (3U) -#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ -#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ -#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) -#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ -#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ -#define USB_OTG_DIEPINT_INEPNM_Pos (5U) -#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ -#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ -#define USB_OTG_DIEPINT_INEPNE_Pos (6U) -#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ -#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ -#define USB_OTG_DIEPINT_TXFE_Pos (7U) -#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ -#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ -#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) -#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ -#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ -#define USB_OTG_DIEPINT_BNA_Pos (9U) -#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ -#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ -#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) -#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ -#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ -#define USB_OTG_DIEPINT_BERR_Pos (12U) -#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ -#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ -#define USB_OTG_DIEPINT_NAK_Pos (13U) -#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ -#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ +#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_AHBERR_Pos (2U) +#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ /******************** Bit definition for USB_OTG_HCINTMSK register ********************/ -#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) -#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ -#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ -#define USB_OTG_HCINTMSK_CHHM_Pos (1U) -#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ -#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ -#define USB_OTG_HCINTMSK_STALLM_Pos (3U) -#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ -#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ -#define USB_OTG_HCINTMSK_NAKM_Pos (4U) -#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ -#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ -#define USB_OTG_HCINTMSK_ACKM_Pos (5U) -#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ -#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ -#define USB_OTG_HCINTMSK_NYET_Pos (6U) -#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ -#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ -#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) -#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ -#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ -#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) -#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ -#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ -#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) -#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ -#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ -#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) -#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ -#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ -#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) -#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ -#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) -#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ -#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) -#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ -#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ -#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) -#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ -#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ -#define USB_OTG_HCTSIZ_DPID_Pos (29U) -#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ -#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ -#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ -#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ -#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) -#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ /******************** Bit definition for USB_OTG_HCDMA register ********************/ -#define USB_OTG_HCDMA_DMAADDR_Pos (0U) -#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ -#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ -#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) -#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ -#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) -#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ -#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ -#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) -#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ -#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) -#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ -#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!bEndpointAddress, max_packet_size); - - switch (desc_ep->bmAttributes.xfer) - { - case TUSB_XFER_ISOCHRONOUS: - { - uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 1023); - TU_ASSERT(max_packet_size <= spec_size); - } - break; - - case TUSB_XFER_BULK: - if (speed == TUSB_SPEED_HIGH) - { - // Bulk highspeed must be EXACTLY 512 - TU_ASSERT(max_packet_size == 512); - } - else - { - // TODO Bulk fullspeed can only be 8, 16, 32, 64 - TU_ASSERT(max_packet_size <= 64); - } - break; - - case TUSB_XFER_INTERRUPT: - { - uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64); - TU_ASSERT(max_packet_size <= spec_size); - } - break; - - default: - return false; - } - - return true; + uint16_t const max_packet_size = tu_edpt_packet_size(desc_ep); + TU_LOG2(" Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size); + + switch (desc_ep->bmAttributes.xfer) + { + case TUSB_XFER_ISOCHRONOUS: + { + uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 1023); + TU_ASSERT(max_packet_size <= spec_size); + } + break; + + case TUSB_XFER_BULK: + if (speed == TUSB_SPEED_HIGH) + { + // Bulk highspeed must be EXACTLY 512 + TU_ASSERT(max_packet_size == 512); + }else + { + // TODO Bulk fullspeed can only be 8, 16, 32, 64 + TU_ASSERT(max_packet_size <= 64); + } + break; + + case TUSB_XFER_INTERRUPT: + { + uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64); + TU_ASSERT(max_packet_size <= spec_size); + } + break; + + default: return false; + } + + return true; } -void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const *desc_itf, uint16_t desc_len, uint8_t driver_id) +void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id) { - uint8_t const *p_desc = (uint8_t const *)desc_itf; - uint8_t const *desc_end = p_desc + desc_len; + uint8_t const* p_desc = (uint8_t const*) desc_itf; + uint8_t const* desc_end = p_desc + desc_len; - while (p_desc < desc_end) - { - if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) - { - uint8_t const ep_addr = ((tusb_desc_endpoint_t const *)p_desc)->bEndpointAddress; + while( p_desc < desc_end ) + { + if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) ) + { + uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress; - TU_LOG(2, " Bind EP %02x to driver id %u\r\n", ep_addr, driver_id); - ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id; - } + TU_LOG(2, " Bind EP %02x to driver id %u\r\n", ep_addr, driver_id); + ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id; + } - p_desc = tu_desc_next(p_desc); - } + p_desc = tu_desc_next(p_desc); + } } -uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const *desc_itf, uint8_t itf_count, uint16_t max_len) +uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) { - uint8_t const *p_desc = (uint8_t const *)desc_itf; - uint16_t len = 0; - - while (itf_count--) - { - // Next on interface desc - len += tu_desc_len(desc_itf); - p_desc = tu_desc_next(p_desc); - - while (len < max_len) - { - // return on IAD regardless of itf count - if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) - return len; - - if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && - ((tusb_desc_interface_t const *)p_desc)->bAlternateSetting == 0) - { - break; - } - - len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); - } - } - - return len; + uint8_t const* p_desc = (uint8_t const*) desc_itf; + uint16_t len = 0; + + while (itf_count--) + { + // Next on interface desc + len += tu_desc_len(desc_itf); + p_desc = tu_desc_next(p_desc); + + while (len < max_len) + { + // return on IAD regardless of itf count + if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len; + + if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && + ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 ) + { + break; + } + + len += tu_desc_len(p_desc); + p_desc = tu_desc_next(p_desc); + } + } + + return len; } /*------------------------------------------------------------------*/ @@ -164,20 +161,20 @@ uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const *desc_itf, #if CFG_TUSB_DEBUG #include -char const *const tusb_strerr[TUSB_ERROR_COUNT] = {ERROR_TABLE(ERROR_STRING)}; +char const* const tusb_strerr[TUSB_ERROR_COUNT] = { ERROR_TABLE(ERROR_STRING) }; -static void dump_str_line(uint8_t const *buf, uint16_t count) +static void dump_str_line(uint8_t const* buf, uint16_t count) { - tu_printf(" |"); + tu_printf(" |"); - // each line is 16 bytes - for (uint16_t i = 0; i < count; i++) - { - const char ch = buf[i]; - tu_printf("%c", isprint(ch) ? ch : '.'); - } + // each line is 16 bytes + for(uint16_t i=0; i= 0) +#define TUH_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) ) +#define TUSB_OPT_HOST_ENABLED ( TUH_OPT_RHPORT >= 0 ) // Which roothub port is configured as device -#define TUD_OPT_RHPORT (((CFG_TUSB_RHPORT0_MODE)&OPT_MODE_DEVICE) ? 0 : (((CFG_TUSB_RHPORT1_MODE)&OPT_MODE_DEVICE) ? 1 : -1)) +#define TUD_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE) ? 1 : -1) ) #if TUD_OPT_RHPORT == 0 -#define TUD_OPT_HIGH_SPEED ((CFG_TUSB_RHPORT0_MODE)&OPT_MODE_HIGH_SPEED) +#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HIGH_SPEED ) #else -#define TUD_OPT_HIGH_SPEED ((CFG_TUSB_RHPORT1_MODE)&OPT_MODE_HIGH_SPEED) +#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HIGH_SPEED ) #endif -#define TUSB_OPT_DEVICE_ENABLED (TUD_OPT_RHPORT >= 0) +#define TUSB_OPT_DEVICE_ENABLED ( TUD_OPT_RHPORT >= 0 ) //--------------------------------------------------------------------+ // COMMON OPTIONS @@ -208,26 +210,26 @@ // Debug enable to print out error message #ifndef CFG_TUSB_DEBUG -#define CFG_TUSB_DEBUG 0 + #define CFG_TUSB_DEBUG 0 #endif // place data in accessible RAM for usb controller #ifndef CFG_TUSB_MEM_SECTION -#define CFG_TUSB_MEM_SECTION + #define CFG_TUSB_MEM_SECTION #endif // alignment requirement of buffer used for endpoint transferring #ifndef CFG_TUSB_MEM_ALIGN -#define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) + #define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) #endif // OS selection #ifndef CFG_TUSB_OS -#define CFG_TUSB_OS OPT_OS_NONE + #define CFG_TUSB_OS OPT_OS_NONE #endif #ifndef CFG_TUSB_OS_INC_PATH -#define CFG_TUSB_OS_INC_PATH + #define CFG_TUSB_OS_INC_PATH #endif //-------------------------------------------------------------------- @@ -235,99 +237,99 @@ //-------------------------------------------------------------------- #ifndef CFG_TUD_ENDPOINT0_SIZE -#define CFG_TUD_ENDPOINT0_SIZE 64 + #define CFG_TUD_ENDPOINT0_SIZE 64 #endif #ifndef CFG_TUD_CDC -#define CFG_TUD_CDC 0 + #define CFG_TUD_CDC 0 #endif #ifndef CFG_TUD_MSC -#define CFG_TUD_MSC 0 + #define CFG_TUD_MSC 0 #endif #ifndef CFG_TUD_HID -#define CFG_TUD_HID 0 + #define CFG_TUD_HID 0 #endif #ifndef CFG_TUD_AUDIO -#define CFG_TUD_AUDIO 0 + #define CFG_TUD_AUDIO 0 #endif #ifndef CFG_TUD_VIDEO -#define CFG_TUD_VIDEO 0 + #define CFG_TUD_VIDEO 0 #endif #ifndef CFG_TUD_MIDI -#define CFG_TUD_MIDI 0 + #define CFG_TUD_MIDI 0 #endif #ifndef CFG_TUD_VENDOR -#define CFG_TUD_VENDOR 0 + #define CFG_TUD_VENDOR 0 #endif #ifndef CFG_TUD_USBTMC -#define CFG_TUD_USBTMC 0 + #define CFG_TUD_USBTMC 0 #endif #ifndef CFG_TUD_DFU_RUNTIME -#define CFG_TUD_DFU_RUNTIME 0 + #define CFG_TUD_DFU_RUNTIME 0 #endif #ifndef CFG_TUD_DFU -#define CFG_TUD_DFU 0 + #define CFG_TUD_DFU 0 #endif #ifndef CFG_TUD_BTH -#define CFG_TUD_BTH 0 + #define CFG_TUD_BTH 0 #endif #ifndef CFG_TUD_ECM_RNDIS -#ifdef CFG_TUD_NET -#warning "CFG_TUD_NET is renamed to CFG_TUD_ECM_RNDIS" -#define CFG_TUD_ECM_RNDIS CFG_TUD_NET -#else -#define CFG_TUD_ECM_RNDIS 0 -#endif + #ifdef CFG_TUD_NET + #warning "CFG_TUD_NET is renamed to CFG_TUD_ECM_RNDIS" + #define CFG_TUD_ECM_RNDIS CFG_TUD_NET + #else + #define CFG_TUD_ECM_RNDIS 0 + #endif #endif #ifndef CFG_TUD_NCM -#define CFG_TUD_NCM 0 + #define CFG_TUD_NCM 0 #endif //-------------------------------------------------------------------- // HOST OPTIONS //-------------------------------------------------------------------- #if TUSB_OPT_HOST_ENABLED -#ifndef CFG_TUH_DEVICE_MAX -#define CFG_TUH_DEVICE_MAX 1 -#endif + #ifndef CFG_TUH_DEVICE_MAX + #define CFG_TUH_DEVICE_MAX 1 + #endif -#ifndef CFG_TUH_ENUMERATION_BUFSIZE -#define CFG_TUH_ENUMERATION_BUFSIZE 256 -#endif + #ifndef CFG_TUH_ENUMERATION_BUFSIZE + #define CFG_TUH_ENUMERATION_BUFSIZE 256 + #endif #endif // TUSB_OPT_HOST_ENABLED //------------- CLASS -------------// #ifndef CFG_TUH_HUB -#define CFG_TUH_HUB 0 +#define CFG_TUH_HUB 0 #endif #ifndef CFG_TUH_CDC -#define CFG_TUH_CDC 0 +#define CFG_TUH_CDC 0 #endif #ifndef CFG_TUH_HID -#define CFG_TUH_HID 0 +#define CFG_TUH_HID 0 #endif #ifndef CFG_TUH_MIDI -#define CFG_TUH_MIDI 0 +#define CFG_TUH_MIDI 0 #endif #ifndef CFG_TUH_MSC -#define CFG_TUH_MSC 0 +#define CFG_TUH_MSC 0 #endif #ifndef CFG_TUH_VENDOR @@ -343,9 +345,9 @@ // ARMv7+ (M3-M7, M23-M33) can access unaligned memory #if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7)) -#define TUP_ARCH_STRICT_ALIGN 0 + #define TUP_ARCH_STRICT_ALIGN 0 #else -#define TUP_ARCH_STRICT_ALIGN 1 + #define TUP_ARCH_STRICT_ALIGN 1 #endif // TUP_MCU_STRICT_ALIGN will overwrite TUP_ARCH_STRICT_ALIGN. @@ -353,16 +355,17 @@ // to generate unaligned access code. // LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM #if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX) -#define TUP_MCU_STRICT_ALIGN 1 + #define TUP_MCU_STRICT_ALIGN 1 #else -#define TUP_MCU_STRICT_ALIGN 0 + #define TUP_MCU_STRICT_ALIGN 0 #endif + //------------------------------------------------------------------ // Configuration Validation //------------------------------------------------------------------ #if CFG_TUD_ENDPOINT0_SIZE > 64 -#error Control Endpoint Max Packet Size cannot be larger than 64 + #error Control Endpoint Max Packet Size cannot be larger than 64 #endif #endif /* _TUSB_OPTION_H_ */ diff --git a/uCNC/src/tinyusb/tusb_config.h b/uCNC/src/tinyusb/tusb_config.h index 830700ab3..9d5495bad 100644 --- a/uCNC/src/tinyusb/tusb_config.h +++ b/uCNC/src/tinyusb/tusb_config.h @@ -55,7 +55,7 @@ extern "C" // Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed #ifndef BOARD_DEVICE_RHPORT_SPEED #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ - CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56) + CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56) #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_HIGH_SPEED #else #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED @@ -93,9 +93,9 @@ extern "C" #define CFG_TUSB_MEM_ALIGN __attribute__((aligned(4))) #endif - //-------------------------------------------------------------------- - // DEVICE CONFIGURATION - //-------------------------------------------------------------------- + //-------------------------------------------------------------------- + // DEVICE CONFIGURATION + //-------------------------------------------------------------------- #ifndef CFG_TUD_ENDPOINT0_SIZE #define CFG_TUD_ENDPOINT0_SIZE 64 diff --git a/uCNC/src/tinyusb/tusb_descriptors.c b/uCNC/src/tinyusb/tusb_descriptors.c index 5a7f66e28..3eee46438 100644 --- a/uCNC/src/tinyusb/tusb_descriptors.c +++ b/uCNC/src/tinyusb/tusb_descriptors.c @@ -1,4 +1,4 @@ -/* +/* * The MIT License (MIT) * * Copyright (c) 2019 Ha Thach (tinyusb.org) @@ -33,39 +33,39 @@ */ #define _PID_MAP(itf, n) ((CFG_TUD_##itf) << (n)) #define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ - _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4)) + _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4)) //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ tusb_desc_device_t const desc_device = - { - .bLength = sizeof(tusb_desc_device_t), - .bDescriptorType = TUSB_DESC_DEVICE, - .bcdUSB = 0x0200, + { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0200, - // Use Interface Association Descriptor (IAD) for CDC - // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) - .bDeviceClass = TUSB_CLASS_MISC, - .bDeviceSubClass = MISC_SUBCLASS_COMMON, - .bDeviceProtocol = MISC_PROTOCOL_IAD, - .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + // Use Interface Association Descriptor (IAD) for CDC + // As required by USB Specs IAD's subclass must be common class (2) and protocol must be IAD (1) + .bDeviceClass = TUSB_CLASS_MISC, + .bDeviceSubClass = MISC_SUBCLASS_COMMON, + .bDeviceProtocol = MISC_PROTOCOL_IAD, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, - .idVendor = 0xCafe, - .idProduct = USB_PID, - .bcdDevice = 0x0100, + .idVendor = 0xCafe, + .idProduct = USB_PID, + .bcdDevice = 0x0100, - .iManufacturer = 0x01, - .iProduct = 0x02, - .iSerialNumber = 0x03, + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, - .bNumConfigurations = 0x01}; + .bNumConfigurations = 0x01}; // Invoked when received GET DEVICE DESCRIPTOR // Application return pointer to descriptor uint8_t const *tud_descriptor_device_cb(void) { - return (uint8_t const *)&desc_device; + return (uint8_t const *)&desc_device; } //--------------------------------------------------------------------+ @@ -73,9 +73,9 @@ uint8_t const *tud_descriptor_device_cb(void) //--------------------------------------------------------------------+ enum { - ITF_NUM_CDC_0 = 0, - ITF_NUM_CDC_0_DATA, - ITF_NUM_TOTAL + ITF_NUM_CDC_0 = 0, + ITF_NUM_CDC_0_DATA, + ITF_NUM_TOTAL }; #define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + CFG_TUD_CDC * TUD_CDC_DESC_LEN) @@ -91,22 +91,22 @@ enum #endif uint8_t const desc_fs_configuration[] = - { - // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), - // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. - TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_DATA, 0x80 | EPNUM_CDC_0_DATA, 64), + // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_DATA, 0x80 | EPNUM_CDC_0_DATA, 64), }; #if TUD_OPT_HIGH_SPEED uint8_t const desc_hs_configuration[] = - { - // Config number, interface count, string index, total length, attribute, power in mA - TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), - // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. - TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_DATA, 0x80 | EPNUM_CDC_0_DATA, 512), + // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 8, EPNUM_CDC_0_DATA, 0x80 | EPNUM_CDC_0_DATA, 512), }; #endif @@ -115,13 +115,13 @@ uint8_t const desc_hs_configuration[] = // Descriptor contents must exist long enough for transfer to complete uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { - (void)index; // for multiple configurations + (void)index; // for multiple configurations #if TUD_OPT_HIGH_SPEED - // Although we are highspeed, host may be fullspeed. - return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration; + // Although we are highspeed, host may be fullspeed. + return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration; #else - return desc_fs_configuration; + return desc_fs_configuration; #endif } @@ -131,12 +131,12 @@ uint8_t const *tud_descriptor_configuration_cb(uint8_t index) // array of pointer to string descriptors char const *string_desc_arr[] = - { - (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409) - "TinyUSB", // 1: Manufacturer - "TinyUSB Device", // 2: Product - "123456", // 3: Serials, should use chip ID - "TinyUSB CDC", // 4: CDC Interface + { + (const char[]){0x09, 0x04}, // 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + "123456", // 3: Serials, should use chip ID + "TinyUSB CDC", // 4: CDC Interface }; static uint16_t _desc_str[32]; @@ -145,39 +145,39 @@ static uint16_t _desc_str[32]; // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { - (void)langid; + (void)langid; - uint8_t chr_count; + uint8_t chr_count; - if (index == 0) - { - memcpy(&_desc_str[1], string_desc_arr[0], 2); - chr_count = 1; - } - else - { - // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. - // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + if (index == 0) + { + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + } + else + { + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors - if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) - return NULL; + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) + return NULL; - const char *str = string_desc_arr[index]; + const char *str = string_desc_arr[index]; - // Cap at max char - chr_count = strlen(str); - if (chr_count > 31) - chr_count = 31; + // Cap at max char + chr_count = strlen(str); + if (chr_count > 31) + chr_count = 31; - // Convert ASCII string into UTF-16 - for (uint8_t i = 0; i < chr_count; i++) - { - _desc_str[1 + i] = str[i]; - } - } + // Convert ASCII string into UTF-16 + for (uint8_t i = 0; i < chr_count; i++) + { + _desc_str[1 + i] = str[i]; + } + } - // first byte is length (including header), second byte is string type - _desc_str[0] = (TUSB_DESC_STRING << 8) | (2 * chr_count + 2); + // first byte is length (including header), second byte is string type + _desc_str[0] = (TUSB_DESC_STRING << 8) | (2 * chr_count + 2); - return _desc_str; + return _desc_str; } diff --git a/uCNC/uCNC.ino b/uCNC/uCNC.ino index 97f63da50..6c036b78e 100644 --- a/uCNC/uCNC.ino +++ b/uCNC/uCNC.ino @@ -1,12 +1,13 @@ #include "src/cnc.h" -int main(void) +void setup() { - // initializes all systems - cnc_init(); + // put your setup code here, to run once: + cnc_init(); +} - for (;;) - { - cnc_run(); - } +void loop() +{ + // put your main code here, to run repeatedly: + cnc_run(); } From dc91f462b3ac2614eb6d356a5511b40c4ce587bc Mon Sep 17 00:00:00 2001 From: Paciente8159 Date: Sat, 9 Jul 2022 23:02:30 +0100 Subject: [PATCH 2/6] fix LPC176x PWM --- uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c | 48 +++++++++++-------------- 1 file changed, 21 insertions(+), 27 deletions(-) diff --git a/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c index 43eb25b35..346c32b11 100644 --- a/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c +++ b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c @@ -67,33 +67,27 @@ volatile bool lpc_global_isr_enabled; LPC_PINCON->__helper__(PINMODE, __indirect__(diopin, PINCON), ) &= ~(3 << (0x1F & (__indirect__(diopin, BIT) << 1))); \ } -/* -// #define mcu_config_pwm(diopin) \ -// { \ -// LPC_PINCON->__helper__(PINSEL, __indirect__(diopin, PINCON), ) &= ~(3 << (0x1F & (__indirect__(diopin, BIT) << 1))); \ -// LPC_PINCON->__helper__(PINSEL, __indirect__(diopin, PINCON), ) |= (__indirect__(diopin, PINSEL) << (0x1F & (__indirect__(diopin, BIT) << 1))); \ -// LPC_PWM1->TCR = (1 << 0) | (1 << 2); \ -// LPC_PWM1->MCR = (1 << 1); \ -// LPC_PWM1->MR0 = 255; \ -// LPC_PWM1->LER = (1 << 0) | PWM_LER; \ -// LPC_PWM1->PCR = PWM_ENA & 0x0FE0; \ -// } -*/ - -#define mcu_config_pwm(diopin) \ - { \ - PINSEL_CFG_Type pwm = {__indirect__(diopin, PORT), __indirect__(diopin, BIT), __indirect__(diopin, FUNC), PINSEL_PINMODE_NORMAL}; \ - PINSEL_ConfigPin(&pwm); \ - PWM_TIMERCFG_Type pwmtmr; \ - PWM_ConfigStructInit(PWM_MODE_TIMER, &pwmtmr); \ - pwmtmr.PrescaleValue = 4; \ - PWM_Init(LPC_PWM1, PWM_MODE_TIMER, &pwmtmr); \ - PWM_MATCHCFG_Type pwmconf = {__indirect__(diopin, CHANNEL), DISABLE, DISABLE, ENABLE}; \ - PWM_ConfigMatch(LPC_PWM1, &pwmconf); \ - PWM_ResetCounter(LPC_PWM1); \ - LPC_PWM1->MR0 = 255; \ - mcu_set_pwm(diopin, 0); \ - PWM_Cmd(LPC_PWM1, ENABLE); \ +#define mcu_config_pwm(diopin) \ + { \ + mcu_config_output(diopin); \ + CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCPWM1, ENABLE); \ + CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_PWM1, CLKPWR_PCLKSEL_CCLK_DIV_4); \ + LPC_PWM1->IR = 0xFF & PWM_IR_BITMASK; \ + LPC_PWM1->TCR = 0; \ + LPC_PWM1->CTCR = 0; \ + LPC_PWM1->MCR = 0; \ + LPC_PWM1->CCR = 0; \ + LPC_PWM1->PCR &= 0xFF00; \ + LPC_PWM1->LER |= (1UL << 0) | (1UL << __indirect__(diopin, CHANNEL)); \ + LPC_PWM1->PCR |= (1UL << (8 + __indirect__(diopin, CHANNEL))); \ + LPC_PWM1->PR = (CLKPWR_GetPCLK(CLKPWR_PCLKSEL_PWM1) / (255 * 1000)) - 1; \ + LPC_PWM1->MCR = (1UL << 1); \ + LPC_PWM1->MR0 = 255; \ + LPC_PWM1->TCR = (1UL << 3) | (1UL << 0); \ + mcu_config_output(diopin); \ + PINSEL_CFG_Type pwm = {__indirect__(diopin, PORT), __indirect__(diopin, BIT), __indirect__(diopin, FUNC), PINSEL_PINMODE_PULLUP, PINSEL_PINMODE_NORMAL}; \ + PINSEL_ConfigPin(&pwm); \ + mcu_set_pwm(diopin, 0); \ } #define CLOCK_SETUP 1 From 3f462326045f62e2f9c11123785175c4a85101ff Mon Sep 17 00:00:00 2001 From: Paciente8159 Date: Sat, 9 Jul 2022 23:17:25 +0100 Subject: [PATCH 3/6] LPC176x servos --- uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c | 131 +++++++++++++++++++++--- 1 file changed, 118 insertions(+), 13 deletions(-) diff --git a/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c index 346c32b11..a45b7e2f1 100644 --- a/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c +++ b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c @@ -90,23 +90,128 @@ volatile bool lpc_global_isr_enabled; mcu_set_pwm(diopin, 0); \ } -#define CLOCK_SETUP 1 -#define SCS_Val 0x00000020 -#define CLKSRCSEL_Val 0x00000001 -#define PLL0_SETUP 1 -#define PLL0CFG_Val 0x00050063 -#define PLL1_SETUP 1 -#define PLL1CFG_Val 0x00000023 -#define CCLKCFG_Val 0x00000003 -#define USBCLKCFG_Val 0x00000000 -#define PCLKSEL0_Val 0x00000000 -#define PCLKSEL1_Val 0x00000000 -#define PCONP_Val 0x042887DE -#define CLKOUTCFG_Val 0x00000000 +// #define CLOCK_SETUP 1 +// #define SCS_Val 0x00000020 +// #define CLKSRCSEL_Val 0x00000001 +// #define PLL0_SETUP 1 +// #define PLL0CFG_Val 0x00050063 +// #define PLL1_SETUP 1 +// #define PLL1CFG_Val 0x00000023 +// #define CCLKCFG_Val 0x00000003 +// #define USBCLKCFG_Val 0x00000000 +// #define PCLKSEL0_Val 0x00000000 +// #define PCLKSEL1_Val 0x00000000 +// #define PCONP_Val 0x042887DE +// #define CLKOUTCFG_Val 0x00000000 + +// define the mcu internal servo variables +#if SERVOS_MASK > 0 + +static uint8_t mcu_servos[6]; + +static FORCEINLINE void mcu_clear_servos() +{ +#if SERVO0 >= 0 + mcu_clear_output(SERVO0); +#endif +#if SERVO1 >= 0 + mcu_clear_output(SERVO1); +#endif +#if SERVO2 >= 0 + mcu_clear_output(SERVO2); +#endif +#if SERVO3 >= 0 + mcu_clear_output(SERVO3); +#endif +#if SERVO4 >= 0 + mcu_clear_output(SERVO4); +#endif +#if SERVO5 >= 0 + mcu_clear_output(SERVO5); +#endif +} + +void servo_start_timeout(uint8_t val) +{ + TIM_Cmd(SERVO_TIMER_REG, DISABLE); + TIM_TIMERCFG_Type tmrconfig; + TIM_ConfigStructInit(TIM_TIMER_MODE, &tmrconfig); + TIM_Init(SERVO_TIMER_REG, TIM_TIMER_MODE, &tmrconfig); + TIM_MATCHCFG_Type tmrmatch; + tmrmatch.MatchChannel = SERVO_TIMER; + tmrmatch.IntOnMatch = ENABLE; + tmrmatch.StopOnMatch = ENABLE; + tmrmatch.ResetOnMatch = ENABLE; + tmrmatch.MatchValue = (val << 1) + 125; + TIM_ConfigMatch(SERVO_TIMER_REG, &tmrmatch); + NVIC_SetPriority(SERVO_TIMER_IRQ, 10); + NVIC_ClearPendingIRQ(SERVO_TIMER_IRQ); + NVIC_EnableIRQ(SERVO_TIMER_IRQ); + + TIM_Cmd(SERVO_TIMER_REG, ENABLE); +} + +void MCU_SERVO_ISR(void) +{ + mcu_enable_global_isr(); + mcu_clear_servos(); + TIM_ClearIntPending(SERVO_TIMER_REG, SERVO_INT_FLAG); +} + +#endif void MCU_RTC_ISR(void) { mcu_disable_global_isr(); +#if SERVOS_MASK > 0 + static uint8_t ms_servo_counter = 0; + uint8_t servo_counter = ms_servo_counter; + + switch (servo_counter) + { +#if SERVO0 >= 0 + case SERVO0_FRAME: + servo_start_timeout(mcu_servos[0]); + mcu_set_output(SERVO0); + break; +#endif +#if SERVO1 >= 0 + case SERVO1_FRAME: + mcu_set_output(SERVO1); + servo_start_timeout(mcu_servos[1]); + break; +#endif +#if SERVO2 >= 0 + case SERVO2_FRAME: + mcu_set_output(SERVO2); + servo_start_timeout(mcu_servos[2]); + break; +#endif +#if SERVO3 >= 0 + case SERVO3_FRAME: + mcu_set_output(SERVO3); + servo_start_timeout(mcu_servos[3]); + break; +#endif +#if SERVO4 >= 0 + case SERVO4_FRAME: + mcu_set_output(SERVO4); + servo_start_timeout(mcu_servos[4]); + break; +#endif +#if SERVO5 >= 0 + case SERVO5_FRAME: + mcu_set_output(SERVO5); + servo_start_timeout(mcu_servos[5]); + break; +#endif + } + + servo_counter++; + ms_servo_counter = (servo_counter != 20) ? servo_counter : 0; + +#endif + uint32_t millis = mcu_runtime_ms; millis++; mcu_runtime_ms = millis; From 940a2fb6acbf560e608ff8c7489ed5b46839417a Mon Sep 17 00:00:00 2001 From: Paciente8159 Date: Sat, 9 Jul 2022 23:56:14 +0100 Subject: [PATCH 4/6] Systick working - Systick working - replaced us delay by pure C function --- platformio.ini | 3 +- uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp | 11 ----- uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c | 55 ++++++++++------------ uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h | 8 ++++ 4 files changed, 34 insertions(+), 43 deletions(-) delete mode 100644 uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp diff --git a/platformio.ini b/platformio.ini index 2fda2c419..d985798c2 100644 --- a/platformio.ini +++ b/platformio.ini @@ -96,8 +96,7 @@ build_flags = -D BOARD=BOARD_BLACKPILL -D INTERFACE=1 -D HAL_TIM_MODULE_DISABLED [env:re_arm] extends = common_Arduino platform = https://github.com/p3p/pio-nxplpc-arduino-lpc176x/archive/0.1.3.zip -platform_packages = p3p/framework-arduino-lpc176x -;Paciente8159/framework-arduino-lpc176x @ https://github.com/Paciente8159/pio-framework-arduino-lpc176x/archive/0.2.10.zip +platform_packages = Paciente8159/framework-arduino-lpc176x @ https://github.com/Paciente8159/pio-framework-arduino-lpc176x/archive/0.2.10.zip board = nxp_lpc1768 lib_ldf_mode = off lib_compat_mode = strict diff --git a/uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp b/uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp deleted file mode 100644 index c271a2dad..000000000 --- a/uCNC/src/hal/mcus/lpc176x/lpc176x_time.cpp +++ /dev/null @@ -1,11 +0,0 @@ -#ifdef ARDUINO_ARCH_LPC176X -#include - -extern "C" -{ - void lpc176x_delay_us(uint32_t delay) - { - LPC176x::delay_us(delay); - } -} -#endif \ No newline at end of file diff --git a/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c index a45b7e2f1..e3c6c2175 100644 --- a/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c +++ b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c @@ -160,7 +160,7 @@ void MCU_SERVO_ISR(void) #endif -void MCU_RTC_ISR(void) +void SysTick_Callback(void) { mcu_disable_global_isr(); #if SERVOS_MASK > 0 @@ -216,7 +216,7 @@ void MCU_RTC_ISR(void) millis++; mcu_runtime_ms = millis; mcu_rtc_cb(millis); - TIM_ClearIntPending(RTC_TIMER_REG, RTC_INT_FLAG); + // TIM_ClearIntPending(RTC_TIMER_REG, RTC_INT_FLAG); mcu_enable_global_isr(); } @@ -362,32 +362,24 @@ void mcu_usart_init(void) void mcu_rtc_init() { - // SysTick->CTRL = 0; - // SysTick->LOAD = ((F_CPU / 1000) - 1); - // SysTick->VAL = 0; - // NVIC_SetPriority(SysTick_IRQn, 10); - // SysTick->CTRL = 3; - - // SYSTICK_InternalInit(1); - // SYSTICK_ClearCounterFlag(); - // NVIC_SetPriority(SysTick_IRQn, 10); - // SYSTICK_IntCmd(ENABLE); - TIM_Cmd(RTC_TIMER_REG, DISABLE); - TIM_TIMERCFG_Type tmrconfig; - TIM_ConfigStructInit(TIM_TIMER_MODE, &tmrconfig); - TIM_Init(RTC_TIMER_REG, TIM_TIMER_MODE, &tmrconfig); - TIM_MATCHCFG_Type tmrmatch; - tmrmatch.MatchChannel = RTC_TIMER; - tmrmatch.IntOnMatch = ENABLE; - tmrmatch.StopOnMatch = DISABLE; - tmrmatch.ResetOnMatch = ENABLE; - tmrmatch.MatchValue = 1000; - TIM_ConfigMatch(RTC_TIMER_REG, &tmrmatch); - NVIC_SetPriority(RTC_TIMER_IRQ, 1); - NVIC_ClearPendingIRQ(RTC_TIMER_IRQ); - NVIC_EnableIRQ(RTC_TIMER_IRQ); - - TIM_Cmd(RTC_TIMER_REG, ENABLE); + // TIM_Cmd(RTC_TIMER_REG, DISABLE); + // TIM_TIMERCFG_Type tmrconfig; + // TIM_ConfigStructInit(TIM_TIMER_MODE, &tmrconfig); + // TIM_Init(RTC_TIMER_REG, TIM_TIMER_MODE, &tmrconfig); + // TIM_MATCHCFG_Type tmrmatch; + // tmrmatch.MatchChannel = RTC_TIMER; + // tmrmatch.IntOnMatch = ENABLE; + // tmrmatch.StopOnMatch = DISABLE; + // tmrmatch.ResetOnMatch = ENABLE; + // tmrmatch.MatchValue = 1000; + // TIM_ConfigMatch(RTC_TIMER_REG, &tmrmatch); + // NVIC_SetPriority(RTC_TIMER_IRQ, 1); + // NVIC_ClearPendingIRQ(RTC_TIMER_IRQ); + // NVIC_EnableIRQ(RTC_TIMER_IRQ); + + // TIM_Cmd(RTC_TIMER_REG, ENABLE); + + // Systick is initialized by the framework } /*IO functions*/ @@ -1318,11 +1310,14 @@ uint32_t mcu_millis() * provides a delay in us (micro seconds) * the maximum allowed delay is 255 us * */ -void lpc176x_delay_us(uint32_t delay); +#define mcu_micros ((mcu_runtime_ms * 1000) + ((SysTick->LOAD - SysTick->VAL) / (SystemCoreClock / 1000000))) #ifndef mcu_delay_us void mcu_delay_us(uint8_t delay) { - lpc176x_delay_us(delay); + // lpc176x_delay_us(delay); + uint32_t target = mcu_micros; + while (target > mcu_micros) + ; } #endif diff --git a/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h b/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h index 2491ada08..bef2c2b34 100644 --- a/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h +++ b/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h @@ -3247,6 +3247,14 @@ extern "C" #define RTC_INT_FLAG __helper__(TIM_MR, RTC_TIMER, _INT) #define RTC_TIMER_IRQ __helper__(TIMER, RTC_TIMER, _IRQn) +#ifndef SERVO_TIMER +#define SERVO_TIMER 2 +#endif +#define SERVO_TIMER_REG __helper__(LPC_TIM, SERVO_TIMER, ) +#define MCU_SERVO_ISR __helper__(TIMER, SERVO_TIMER, _IRQHandler) +#define SERVO_INT_FLAG __helper__(TIM_MR, SERVO_TIMER, _INT) +#define SERVO_TIMER_IRQ __helper__(TIMER, SERVO_TIMER, _IRQn) + // Indirect macro access #define __indirect__ex__(X, Y) DIO##X##_##Y #define __indirect__(X, Y) __indirect__ex__(X, Y) From 338907c5821857d047ba85b6cfbd5cbc881529df Mon Sep 17 00:00:00 2001 From: Paciente8159 Date: Wed, 13 Jul 2022 00:08:40 +0100 Subject: [PATCH 5/6] servos running - LPC servos running - added runtime message to $P command - fixed servos map in re-arm --- uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h | 76 ++++--------------- uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c | 49 +++++------- uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h | 10 +-- uCNC/src/interface/protocol.c | 4 + 4 files changed, 42 insertions(+), 97 deletions(-) diff --git a/uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h b/uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h index 38f691465..dc1601876 100644 --- a/uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h +++ b/uCNC/src/hal/boards/lpc176x/boardmap_re_arm.h @@ -104,8 +104,8 @@ extern "C" // Functionalities are set in config.h file // // blink led -#define DOUT31_BIT 28 -#define DOUT31_PORT 4 +// #define DOUT31_BIT 28 +// #define DOUT31_PORT 4 // Stepper enable pin. For Grbl on Uno board a single pin is used #define STEP0_EN_BIT 10 @@ -120,66 +120,20 @@ extern "C" #define STEP4_EN_PORT 4 // Setup the Step Timer used has the heartbeat for µCNC - // Timer 1 is used by default + // Timer 0 is used by default //#define ITP_TIMER 0 - // Setup the RTC Timer used by µCNC to provide an (mostly) accurate time base for all time dependent functions - // Timer 0 is set by default - //#define RTC_TIMER 1 - - // // TMC0 UART - // #define DOUT23_BIT 1 - // #define DOUT23_PORT G - // #define DIN23_BIT 1 - // #define DIN23_PORT K - // #define DIN23_PULLUP - - // // TMC1 UART - // #define DOUT24_BIT 5 - // #define DOUT24_PORT F - // #define DIN24_BIT 2 - // #define DIN24_PORT K - // #define DIN24_PULLUP - - // // TMC2 UART - // #define DOUT25_BIT 7 - // #define DOUT25_PORT L - // #define DIN25_BIT 3 - // #define DIN25_PORT K - // #define DIN25_PULLUP - - // // TMC3 UART - // #define DOUT26_BIT 5 - // #define DOUT26_PORT L - // #define DIN26_BIT 4 - // #define DIN26_PORT K - // #define DIN26_PULLUP - - // // // TMC4 UART - // // #define DOUT27_BIT 3 - // // #define DOUT27_PORT F - // // #define DIN27_BIT 4 - // // #define DIN27_PORT F - // // #define DIN27_PULLUP - - // #define SERVO0_BIT 5 - // #define SERVO0_PORT G - // #define SERVO1_BIT 3 - // #define SERVO1_PORT E - // #define SERVO2_BIT 3 - // #define SERVO2_PORT H - // #define SERVO3_BIT 5 - // #define SERVO3_PORT B - - // // SERVO3 pin supports ISR and can be used as an encoder/counter - // // #define DIN0_BIT 5 - // // #define DIN0_PORT B - // // #define DIN0_ISR 0 - - // // software I2C - // #define DIN20_BIT 1 - // #define DIN20_PORT D - // #define DIN21_BIT 0 - // #define DIN21_PORT D + // Setup the SERVO Timer used by µCNC + // Timer 1 is set by default + //#define SERVO_TIMER 1 + + #define SERVO3_BIT 18 + #define SERVO3_PORT 1 + #define SERVO2_BIT 19 + #define SERVO2_PORT 1 + #define SERVO1_BIT 21 + #define SERVO1_PORT 1 + #define SERVO0_BIT 20 + #define SERVO0_PORT 1 #ifdef __cplusplus } diff --git a/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c index e3c6c2175..030eec1ed 100644 --- a/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c +++ b/uCNC/src/hal/mcus/lpc176x/mcu_lpc176x.c @@ -90,20 +90,6 @@ volatile bool lpc_global_isr_enabled; mcu_set_pwm(diopin, 0); \ } -// #define CLOCK_SETUP 1 -// #define SCS_Val 0x00000020 -// #define CLKSRCSEL_Val 0x00000001 -// #define PLL0_SETUP 1 -// #define PLL0CFG_Val 0x00050063 -// #define PLL1_SETUP 1 -// #define PLL1CFG_Val 0x00000023 -// #define CCLKCFG_Val 0x00000003 -// #define USBCLKCFG_Val 0x00000000 -// #define PCLKSEL0_Val 0x00000000 -// #define PCLKSEL1_Val 0x00000000 -// #define PCONP_Val 0x042887DE -// #define CLKOUTCFG_Val 0x00000000 - // define the mcu internal servo variables #if SERVOS_MASK > 0 @@ -131,36 +117,44 @@ static FORCEINLINE void mcu_clear_servos() #endif } -void servo_start_timeout(uint8_t val) +void servo_timer_init(void) { - TIM_Cmd(SERVO_TIMER_REG, DISABLE); + TIM_Cmd(SERVO_TIMER_REG, DISABLE); TIM_TIMERCFG_Type tmrconfig; TIM_ConfigStructInit(TIM_TIMER_MODE, &tmrconfig); TIM_Init(SERVO_TIMER_REG, TIM_TIMER_MODE, &tmrconfig); + NVIC_SetPriority(SERVO_TIMER_IRQ, 10); + NVIC_ClearPendingIRQ(SERVO_TIMER_IRQ); + NVIC_EnableIRQ(SERVO_TIMER_IRQ); +} + +void servo_start_timeout(uint8_t val) +{ + TIM_Cmd(SERVO_TIMER_REG, DISABLE); TIM_MATCHCFG_Type tmrmatch; tmrmatch.MatchChannel = SERVO_TIMER; tmrmatch.IntOnMatch = ENABLE; - tmrmatch.StopOnMatch = ENABLE; + tmrmatch.StopOnMatch = DISABLE; tmrmatch.ResetOnMatch = ENABLE; - tmrmatch.MatchValue = (val << 1) + 125; - TIM_ConfigMatch(SERVO_TIMER_REG, &tmrmatch); - NVIC_SetPriority(SERVO_TIMER_IRQ, 10); + tmrmatch.MatchValue = ((uint32_t)((float)val * 7.875f)) + 500; + TIM_ClearIntPending(SERVO_TIMER_REG, SERVO_INT_FLAG); NVIC_ClearPendingIRQ(SERVO_TIMER_IRQ); - NVIC_EnableIRQ(SERVO_TIMER_IRQ); + TIM_ConfigMatch(SERVO_TIMER_REG, &tmrmatch); TIM_Cmd(SERVO_TIMER_REG, ENABLE); } void MCU_SERVO_ISR(void) { - mcu_enable_global_isr(); mcu_clear_servos(); TIM_ClearIntPending(SERVO_TIMER_REG, SERVO_INT_FLAG); + NVIC_ClearPendingIRQ(SERVO_TIMER_IRQ); + TIM_Cmd(SERVO_TIMER_REG, DISABLE); } #endif -void SysTick_Callback(void) +void MCU_RTC_ISR(void) { mcu_disable_global_isr(); #if SERVOS_MASK > 0 @@ -216,7 +210,7 @@ void SysTick_Callback(void) millis++; mcu_runtime_ms = millis; mcu_rtc_cb(millis); - // TIM_ClearIntPending(RTC_TIMER_REG, RTC_INT_FLAG); + //TIM_ClearIntPending(RTC_TIMER_REG, RTC_INT_FLAG); mcu_enable_global_isr(); } @@ -373,10 +367,9 @@ void mcu_rtc_init() // tmrmatch.ResetOnMatch = ENABLE; // tmrmatch.MatchValue = 1000; // TIM_ConfigMatch(RTC_TIMER_REG, &tmrmatch); - // NVIC_SetPriority(RTC_TIMER_IRQ, 1); + // NVIC_SetPriority(RTC_TIMER_IRQ, 10); // NVIC_ClearPendingIRQ(RTC_TIMER_IRQ); // NVIC_EnableIRQ(RTC_TIMER_IRQ); - // TIM_Cmd(RTC_TIMER_REG, ENABLE); // Systick is initialized by the framework @@ -1125,10 +1118,10 @@ uint8_t mcu_get_pwm(uint8_t pwm) * sets the pwm for a servo (50Hz with tON between 1~2ms) * can be defined either as a function or a macro call * */ -#define SERVO0_UCNC_INTERNAL_PIN 40 #ifndef mcu_set_servo void mcu_set_servo(uint8_t servo, uint8_t value) { + mcu_servos[servo - SERVO0_UCNC_INTERNAL_PIN] = value; } #endif @@ -1139,7 +1132,7 @@ void mcu_set_servo(uint8_t servo, uint8_t value) #ifndef mcu_get_servo uint8_t mcu_get_servo(uint8_t servo) { - return 0; + return mcu_servos[servo - SERVO0_UCNC_INTERNAL_PIN]; } #endif diff --git a/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h b/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h index bef2c2b34..ed79019ad 100644 --- a/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h +++ b/uCNC/src/hal/mcus/lpc176x/mcumap_lpc176x.h @@ -3239,16 +3239,10 @@ extern "C" #define ITP_INT_FLAG __helper__(TIM_MR, ITP_TIMER, _INT) #define ITP_TIMER_IRQ __helper__(TIMER, ITP_TIMER, _IRQn) -#ifndef RTC_TIMER -#define RTC_TIMER 1 -#endif -#define RTC_TIMER_REG __helper__(LPC_TIM, RTC_TIMER, ) -#define MCU_RTC_ISR __helper__(TIMER, RTC_TIMER, _IRQHandler) -#define RTC_INT_FLAG __helper__(TIM_MR, RTC_TIMER, _INT) -#define RTC_TIMER_IRQ __helper__(TIMER, RTC_TIMER, _IRQn) +#define MCU_RTC_ISR SysTick_Handler #ifndef SERVO_TIMER -#define SERVO_TIMER 2 +#define SERVO_TIMER 1 #endif #define SERVO_TIMER_REG __helper__(LPC_TIM, SERVO_TIMER, ) #define MCU_SERVO_ISR __helper__(TIMER, SERVO_TIMER, _IRQHandler) diff --git a/uCNC/src/interface/protocol.c b/uCNC/src/interface/protocol.c index 2801901c0..72baf429a 100644 --- a/uCNC/src/interface/protocol.c +++ b/uCNC/src/interface/protocol.c @@ -725,6 +725,10 @@ void protocol_send_pins_states(void) mod_send_pins_states_hook(); #endif + serial_print_str(__romstr__("[RUNTIME:")); + serial_print_int(mcu_millis()); + serial_print_str(MSG_END); + #ifdef ECHO_CMD protocol_busy = false; #endif From b4edad0c11c83faf1987e71e6eb01591871e6555 Mon Sep 17 00:00:00 2001 From: Paciente8159 Date: Fri, 29 Jul 2022 22:20:10 +0100 Subject: [PATCH 6/6] lpc176x PIO ini --- platformio.ini | 2 +- uCNC/src/hal/boards/esp8266/esp8266.ini | 6 +++--- uCNC/src/hal/boards/lpc176x/lpc176x.ini | 15 +++++++++++++++ uCNC/src/hal/boards/stm32/stm32.ini | 3 --- 4 files changed, 19 insertions(+), 7 deletions(-) create mode 100644 uCNC/src/hal/boards/lpc176x/lpc176x.ini diff --git a/platformio.ini b/platformio.ini index 4eb5968ec..b3d106032 100644 --- a/platformio.ini +++ b/platformio.ini @@ -17,7 +17,7 @@ extra_configs = uCNC/src/hal/boards/samd21/samd21.ini uCNC/src/hal/boards/stm32/stm32.ini uCNC/src/hal/boards/esp8266/esp8266.ini - uCNC/src/hal/boards/esp8266/lpc176x.ini + uCNC/src/hal/boards/lpc176x/lpc176x.ini ; uCNC/src/hal/mcus/virtual/virtual.ini [common] diff --git a/uCNC/src/hal/boards/esp8266/esp8266.ini b/uCNC/src/hal/boards/esp8266/esp8266.ini index f35790575..4ee78fcae 100644 --- a/uCNC/src/hal/boards/esp8266/esp8266.ini +++ b/uCNC/src/hal/boards/esp8266/esp8266.ini @@ -1,6 +1,6 @@ -################ -# STM32 Boards # -################ +################## +# ESP8266 Boards # +################## [env:d1] platform = espressif8266 diff --git a/uCNC/src/hal/boards/lpc176x/lpc176x.ini b/uCNC/src/hal/boards/lpc176x/lpc176x.ini new file mode 100644 index 000000000..2d3cfb5d8 --- /dev/null +++ b/uCNC/src/hal/boards/lpc176x/lpc176x.ini @@ -0,0 +1,15 @@ +################## +# LPC176X Boards # +################## + +[common_lpc176x] +platform = https://github.com/p3p/pio-nxplpc-arduino-lpc176x/archive/0.1.3.zip +platform_packages = Paciente8159/framework-arduino-lpc176x @ https://github.com/Paciente8159/pio-framework-arduino-lpc176x/archive/0.2.10.zip +lib_ldf_mode = off +lib_compat_mode = strict +build_flags = ${common.build_flags} -D NXP_LPC17xx + +[env:re_arm] +extends = common_lpc176x +board = nxp_lpc1768 +build_flags = ${common_lpc176x.build_flags} -D BOARD=BOARD_RE_ARM -D INTERFACE=1 diff --git a/uCNC/src/hal/boards/stm32/stm32.ini b/uCNC/src/hal/boards/stm32/stm32.ini index 0bb1b46cb..08d4b3d15 100644 --- a/uCNC/src/hal/boards/stm32/stm32.ini +++ b/uCNC/src/hal/boards/stm32/stm32.ini @@ -21,13 +21,11 @@ build_flags = ${common.build_flags} -D HAL_TIM_MODULE_DISABLED -D HAL_EXTI_MODUL [env:bluepill_f103c8] extends = common_stm32 -platform = ststm32 board = bluepill_f103c8 build_flags = ${common_stm32.build_flags} -D BOARD=BOARD_BLUEPILL -D INTERFACE=1 [env:bluepill_f103c8_clone] extends = common_stm32 -platform = ststm32 board = bluepill_f103c8 build_flags = ${common_stm32.build_flags} -D BOARD=BOARD_BLUEPILL -D INTERFACE=1 ; uncomment if it's a bluepill clone @@ -35,7 +33,6 @@ upload_flags = -c set CPUTAPID 0x2ba01477 [env:blackpill_f401cc] extends = common_stm32 -platform = ststm32 board = blackpill_f401cc build_flags = ${common_stm32.build_flags} -D BOARD=BOARD_BLACKPILL -D INTERFACE=1