From b4b466f4bf123bd0dea28f4d88f25d2274981393 Mon Sep 17 00:00:00 2001 From: OutisLi Date: Wed, 6 Mar 2024 23:45:39 +0800 Subject: [PATCH] deploy --- 404.html | 20 + ...1.07-Verilog\350\257\255\346\263\225.html" | 94 ++++ ...\347\241\200\350\257\255\346\263\225.html" | 107 +++++ ...\346\224\257\350\257\255\345\217\245.html" | 153 ++++++ ...\345\200\274\350\241\250\347\244\272.html" | 117 +++++ .../2023.11.15-Vivado.html" | 116 +++++ ...\345\241\236\350\265\213\345\200\274.html" | 102 ++++ ...\346\215\256\347\261\273\345\236\213.html" | 176 +++++++ ...\350\241\250\350\276\276\345\274\217.html" | 206 +++++++++ Chip/Chip/2024.02.21-Chisel.html | 98 ++++ .../2024.02.21-1 Introduction to Scala.html | 238 ++++++++++ .../2024.02.23-2.1 First Chisel Module.html | 209 +++++++++ .../2024.02.24-2.2 Combinational Logic.html | 266 +++++++++++ .../2024.02.25-2.3 Control Flow.html | 229 +++++++++ .../2024.02.26-2.4 Sequential Logic.html | 241 ++++++++++ .../2024.02.28-2.5 FIR Filter.html | 135 ++++++ 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b/404.html @@ -0,0 +1,20 @@ + + + + + + Hello World --from OutisLi + + + + + + + + +

404

There's nothing here.
+ Take me home. +
+ + + diff --git "a/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225.html" "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225.html" new file mode 100644 index 0000000..c7ab94d --- /dev/null +++ "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225.html" @@ -0,0 +1,94 @@ + + + + + + 2023.11.07-Verilog语法 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2023.11.07-Verilog语法

1. Verilog 基础语法

2. Verilog 数值表示

3. Verilog 数据类型

4. Verilog 表达式

10. Verilog 多路分支语句

2023.11.15-Vivado 2023.11.16-阻塞与非阻塞赋值

+ 2024.02.21-Chisel + + → +

+ + + diff --git "a/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/1.Verilog \345\237\272\347\241\200\350\257\255\346\263\225.html" "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/1.Verilog \345\237\272\347\241\200\350\257\255\346\263\225.html" new file mode 100644 index 0000000..d34276a --- /dev/null +++ "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/1.Verilog \345\237\272\347\241\200\350\257\255\346\263\225.html" @@ -0,0 +1,107 @@ + + + + + + 1. Verilog 基础语法 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 1. Verilog 基础语法

# 格式

Verilog 是区分大小写的。

格式自由，可以在一行内编写，也可跨多行编写。

每个语句必须以分号为结束符。空白符（换行、制表、空格）都没有实际的意义，在编译阶段可忽略。例如下面两中编程方式都是等效的。

# 不换行（不推荐）

**wire** [1:0]  results ;**assign** results = (a == 1'b0) ? 2'b01 ： (b==1'b0) ? 2'b10 ： 2'b11 ;
+

# 换行（推荐）

**wire** [1:0]  results ;
+**assign**      results = (a == 1'b0) ? 2'b01 ：(b==1'b0) ? 2'b10 ：2'b11 ;
+

# 注释

Verilog 中有 2 种注释方式:

用 // 进行单行注释：

reg [3:0] counter ;  // A definition of counter register
+

用**/* */**进行跨行注释:

wire [11:0]  addr ;
+/*
+Next are notes with multiple lines.
+Codes here cannot be compiled.
+*/
+assign   addr = 12'b0 ;
+

# 标识符与关键字

标识符（identifier）可以是任意一组字母、数字、$ 符号和 _(下划线)符号的合，但标识符的第一个字符必须是字母或者下划线，不能以数字或者美元符开始。

另外，标识符是区分大小写的。

关键字是 Verilog 中预留的用于定义语言结构的特殊标识符。

Verilog 中关键字全部为小写。

# 实例

**reg** [3:0] counter ; *//reg 为关键字， counter 为标识符*
+**input** clk; *//input 为关键字，clk 为标识符*
+**input** CLK; *//CLK 与 clk是 2 个不同的标识符*
+

+ 10. Verilog 多路分支语句 + + → +

+ + + diff --git "a/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/10.Verilog \345\244\232\350\267\257\345\210\206\346\224\257\350\257\255\345\217\245.html" "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/10.Verilog \345\244\232\350\267\257\345\210\206\346\224\257\350\257\255\345\217\245.html" new file mode 100644 index 0000000..9db0c5c --- /dev/null +++ "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/10.Verilog \345\244\232\350\267\257\345\210\206\346\224\257\350\257\255\345\217\245.html" @@ -0,0 +1,153 @@ + + + + + + 10. Verilog 多路分支语句 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 10. Verilog 多路分支语句

# 关键词：case，选择器

case 语句是一种多路条件分支的形式，可以解决 if 语句中有多个条件选项时使用不方便的问题。

# case 语句

case 语句格式如下：

case(case_expr)
+    condition1     :             true_statement1 ;
+    condition2     :             true_statement2 ;
+    ……
+    default        :             default_statement ;
+endcase
+

case 语句执行时，如果 condition1 为真，则执行 true_statement1 ; 如果 condition1 为假，condition2 为真，则执行 true_statement2；依次类推。如果各个 condition 都不为真，则执行 default_statement 语句。

default 语句是可选的，且在一个 case 语句中不能有多个 default 语句。

条件选项可以有多个，不仅限于 condition1、condition2 等，而且这些条件选项不要求互斥。虽然这些条件选项是并发比较的，但执行效果是谁在前且条件为真谁被执行。

ture_statement1 等执行语句可以是一条语句，也可以是多条。如果是多条执行语句，则需要用 begin 与 end 关键字进行说明。

# case 语句支持嵌套使用。

下面用 case 语句代替 if 语句实现了一个 4 路选择器的功能。仿真结果与 testbench 可参考条件语句 (opens new window)一章，两者完全一致。

# 实例

**module** mux4to1(
+    **input** [1:0]     sel ,
+    **input** [1:0]     p0 ,
+    **input** [1:0]     p1 ,
+    **input** [1:0]     p2 ,
+    **input** [1:0]     p3 ,
+    **output** [1:0]    sout);
+ 
+    **reg** [1:0]     sout_t ;
+    **always** @(*)
+        **case**(sel)
+            2'b00:   **begin**      
+                    sout_t = p0 ;
+                **end**
+            2'b01:       sout_t = p1 ;
+            2'b10:       sout_t = p2 ;
+            **default**:     sout_t = p3 ;
+        **endcase**
+    **assign** sout = sout_t ;
+ **endmodule**
+

case 语句中的条件选项表单式不必都是常量，也可以是 x 值或 z 值。

当多个条件选项下需要执行相同的语句时，多个条件选项可以用逗号分开，放在同一个语句块的候选项中。

# 例如，对 4 路选择器的 case 语句进行扩展，举例如下：

**case**(sel)
+    2'b00:   sout_t = p0 ;
+    2'b01:   sout_t = p1 ;
+    2'b10:   sout_t = p2 ;
+    2'b11:     sout_t = p3 ;
+    2'bx0, 2'bx1, 2'bxz, 2'bxx, 2'b0x, 2'b1x, 2'bzx :
+        sout_t = 2'bxx ;
+    2'bz0, 2'bz1, 2'bzz, 2'b0z, 2'b1z :
+        sout_t = 2'bzz ;
+    **default**:  $display("Unexpected input control!!!");**endcase**
+

# casex/casez 语句

casex、 casez 语句是 case 语句的变形，用来表示条件选项中的无关项。

casex 用 "x" 来表示无关值，casez 用问号 "?" 来表示无关值。

两者的实现的功能是完全一致的，语法与 case 语句也完全一致。

  1. 在case语句中，敏感表达式中与各项值之间的比较是一种全等比较，每一位都相同才认为匹配。
  2. 在casez语句中，如果分支表达式某些位的值为高阻z，那么对这些位的比较就会忽略，不予考虑，而只关注其他位的比较结果。
  3. 在casex语句中，则把这种处理方式进一步扩展到对x的处理，即如果比较双方有一方的某些位的值是z或x，那么这些位的比较就不予考虑。

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# 例如用 casez 语句来实现一个 4bit 控制端的 4 路选择选择器。

**module** mux4to1(
+    **input** [3:0]     sel ,
+    **input** [1:0]     p0 ,
+    **input** [1:0]     p1 ,
+    **input** [1:0]     p2 ,
+    **input** [1:0]     p3 ,
+    **output** [1:0]    sout);
+ 
+    **reg** [1:0]     sout_t ;
+    **always** @(*)
+        **casez**(sel)
+            4'b???1:     sout_t = p0 ;
+            4'b??1?:     sout_t = p1 ;
+            4'b?1??:     sout_t = p2 ;
+            4'b1???:     sout_t = p3 ;  
+        **default**:         sout_t = 2'b0 ;
+    **endcase**
+    **assign**      sout = sout_t ;
+ **endmodule**
+

+ ← + + 2. Verilog 数值表示 + + → +

+ + + diff --git "a/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/2.Verilog \346\225\260\345\200\274\350\241\250\347\244\272.html" "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/2.Verilog \346\225\260\345\200\274\350\241\250\347\244\272.html" new file mode 100644 index 0000000..de265af --- /dev/null +++ "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/2.Verilog \346\225\260\345\200\274\350\241\250\347\244\272.html" @@ -0,0 +1,117 @@ + + + + + + 2. Verilog 数值表示 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2. Verilog 数值表示

# 数值种类

Verilog HDL 有下列四种基本的值来表示硬件电路中的电平逻辑：

  • 0：逻辑 0 或 "假"
  • 1：逻辑 1 或 "真"
  • x 或 X：未知
  • z 或 Z：高阻

x 意味着信号数值的不确定，即在实际电路里，信号可能为 1，也可能为 0。

z 意味着信号处于高阻状态，常见于信号（input, reg）没有驱动时的逻辑结果。例如一个 pad 的 input 呈现高阻状态时，其逻辑值和上下拉的状态有关系。上拉则逻辑值为 1，下拉则为 0 。

# 整数数值表示方法

数字声明时，合法的基数格式有 4 中，包括：十进制('d 或 'D)，十六进制('h 或 'H)，二进制（'b 或 'B），八进制（'o 或 'O）。数值可指明位宽，也可不指明位宽。

# 指明位宽：

4'b1011         *// 4bit 数值*
+32'h3022_c0de   *// 32bit 的数值    一个16进制的数需要4bit来表示*
+

其中，下划线 _ 是为了增强代码的可读性。

# 不指明位宽:

一般直接写数字时，默认为十进制表示，例如下面的 3 种写法是等效的：

counter = 'd100; *//一般会根据编译器自动分频位宽，常见的为32bit*
+counter = 100;
+counter = 32'h64;
+

# 负数表示

通常在表示位宽的数字前面加一个减号来表示负数。例如：

-6'd15
+-15
+
  • 15 在 5 位二进制中的形式为 5'b10001, 在 6 位二进制中的形式为 6'b11_0001。

需要注意的是，减号放在基数和数字之间是非法的，例如下面的表示方法是错误的：

4'd-2 //非法说明
+

# 实数表示方法

实数表示方法主要有两种方式：

# 十进制：

30.123
+6.0
+3.0
+0.001
+

# 科学计数法：

1.2e4         //大小为12000
+1_0001e4      //大小为100010000
+1E-3          //大小为0.001
+

# 字符串表示方法

字符串是由双引号包起来的字符队列。字符串不能多行书写，即字符串中不能包含回车符。Verilog 将字符串当做一系列的单字节 ASCII 字符队列。例如，为存储字符串 "www.runoob.com", 需要 14*8bit 的存储单元。例如：

**reg** [0: 14*8-1]   str ;
+**initial** **begin**    
+			str = "www.runoob.com";
+**end**
+

+ ← + + 2023.11.15-Vivado + + → +

+ + + diff --git "a/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/2023.11.15-Vivado.html" "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/2023.11.15-Vivado.html" new file mode 100644 index 0000000..1193a75 --- /dev/null +++ "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/2023.11.15-Vivado.html" @@ -0,0 +1,116 @@ + + + + + + 2023.11.15-Vivado | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2023.11.15-Vivado

# 1. RTL Schematic & Synthesis Schematic

在 Vivado 或类似的 FPGA 开发环境中，您会遇到 RTL (Register Transfer Level) 分析中的 Schematic 和 Synthesis 过程中的 Schematic。它们虽然看起来相似，但代表了不同阶段的电路设计和功能。

  1. RTL Analysis Schematic:

    • 这个 Schematic 是您用硬件描述语言（如 Verilog）编写的代码的直接可视化表示。
    • 它展示了代码中定义的模块、它们的互联以及信号流。
    • RTL Schematic 重点在于逻辑功能的实现，而不是实际硬件如何实现这些功能。它更多地表示逻辑结构而非物理结构。
    • 这是设计验证的早期阶段，您可以在这里检查逻辑错误或结构问题。

    Untitled

  2. Synthesis Schematic:

    • 经过综合后的 Schematic 是将 RTL 设计转换为实际 FPGA 内部资源（如查找表（LUTs）、寄存器和逻辑单元）的表示。
    • 这个过程涉及优化、逻辑最小化、资源分配和时序分析。
    • Synthesis Schematic 展示了设计如何映射到 FPGA 的实际硬件上，包括使用的具体资源和连接。
    • 这是设计流程的后期阶段，您可以在这里优化性能、资源使用和满足时序要求。

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总结来说，RTL Schematic 关注于逻辑设计的表示，而 Synthesis Schematic 则关注于该设计在 FPGA 上的物理实现。理解两者的区别对于 FPGA 开发至关重要，因为这影响着您如何优化设计以及解决可能出现的问题。

# 2. Project汇总中的LUT，FF，IO，BUFG

在 Vivado 或类似的 FPGA 设计项目中，您会遇到几个关键的资源指标，如 LUT、FF、IO 和 BUFG。这些指标是 FPGA 设计和资源利用的重要部分。下面是每个术语的简要解释：

  1. LUT (Look-Up Table): +
    • LUT 是 FPGA 中实现逻辑功能的基本单元。
    • 它本质上是一个可编程的真值表，可以配置为执行各种逻辑操作（如 AND、OR、NOT、XOR 等）。
    • LUT 的大小和数量是 FPGA 性能和复杂性的关键决定因素。在设计中，LUT 的使用量通常是衡量设计复杂度的一个重要指标。
  2. FF (Flip-Flop): +
    • FF 是用于存储数据的基本存储元件，通常用于实现寄存器、计数器等。
    • 在 FPGA 中，FF 通常与 LUT 配对使用，以实现存储和逻辑功能的组合。
    • FF 的数量通常表明了设计中的数据存储需求和时序复杂度。
  3. IO (Input/Output Ports): +
    • 这些是 FPGA 与外界通信的端口，包括输入端口和输出端口。
    • IO 的数量和类型（如单端或差分）取决于 FPGA 的物理特性和您的设计需求。
    • 在设计中，您需要确保 FPGA 有足够的 IO 端口来满足您的外部连接需求。
  4. BUFG (Buffered Global Clock): +
    • BUFG 是一种专用的时钟缓冲器，用于分配全局时钟信号。
    • 在复杂的 FPGA 设计中，确保时钟信号的稳定和同步是非常重要的。BUFG 能够在整个芯片上稳定地分配时钟信号。
    • BUFG 的使用和配置对于实现有效的时钟管理和避免时钟偏移非常关键。

理解这些资源对于 FPGA 设计至关重要，因为它们直接影响您的设计能否在特定的 FPGA 上实现，以及该设计的性能和效率。在 Vivado 的项目汇总中，这些参数帮助您评估设计对 FPGA 资源的利用情况。

# 3. FPGA的组成构造

FPGA (Field-Programmable Gate Array) 是一种高度灵活的可编程硬件，它由多个不同的元件构成，共同实现复杂的数字逻辑功能。以下是 FPGA 内部主要组成部分的概述：

  1. 查找表 (LUTs): +
    • 如您所述，LUTs 是 FPGA 的核心，用于实现基本的逻辑功能。它们通过存储预定义的输出值来模拟逻辑门的行为。
    • LUTs 可以通过编程来实现简单的逻辑操作（如 AND、OR、NOT）或更复杂的组合逻辑。
  2. 多路选择器 (MUXes): +
    • 虽然在传统的逻辑电路中，MUXes 是通过逻辑门实现的，但在 FPGA 中，它们通常与 LUTs 结合或独立实现。
    • MUXes 在 FPGA 设计中用于根据控制信号选择不同的输入路径，这对于创建复杂的数据路径和逻辑结构至关重要。
  3. 触发器 (Flip-Flops): +
    • Flip-Flops 用于存储信息，是实现时序逻辑的关键元件。它们通常与 LUTs 配对，以构成可存储状态的逻辑单元。
  4. 编程互联资源 (Programmable Interconnects): +
    • 这些是连接 FPGA 内部不同部件的路径。它们可以被编程以形成任何所需的逻辑网络，从而将 LUTs、Flip-Flops 和其他资源连接起来。
  5. 输入/输出块 (I/O Blocks): +
    • 这些块连接 FPGA 和外部世界，提供数据输入和输出功能。它们可以配置为不同类型的接口（如单端或差分）。
  6. 专用硬件资源: +
    • 许多 FPGA 还包含专用的硬件资源，如 DSP (数字信号处理) 块、内存控制器、时钟管理模块（如 PLLs 和 BUFGs），以及其他特定功能块。
  7. 存储资源: +
    • 包括 RAM 块 (Block RAM) 或更小的存储单元，用于数据存储和缓冲。

FPGA 的关键优势在于其高度可编程性和灵活性。设计师可以通过编程定义 LUTs、MUXes、Flip-Flops 以及互连的配置和组合方式，从而在没有物理改动硬件的情况下实现几乎任何数字逻辑设计。这种灵活性使得 FPGA 在快速原型制作、定制硬件加速和可重配置系统中非常有价值。

FPGA (Field-Programmable Gate Array) 是一种高度灵活的可编程硬件，它由多个不同的元件构成，共同实现复杂的数字逻辑功能。以下是 FPGA 内部主要组成部分的概述：

  1. 查找表 (LUTs): +
    • 如您所述，LUTs 是 FPGA 的核心，用于实现基本的逻辑功能。它们通过存储预定义的输出值来模拟逻辑门的行为。
    • LUTs 可以通过编程来实现简单的逻辑操作（如 AND、OR、NOT）或更复杂的组合逻辑。
  2. 多路选择器 (MUXes): +
    • 虽然在传统的逻辑电路中，MUXes 是通过逻辑门实现的，但在 FPGA 中，它们通常与 LUTs 结合或独立实现。
    • MUXes 在 FPGA 设计中用于根据控制信号选择不同的输入路径，这对于创建复杂的数据路径和逻辑结构至关重要。
  3. 触发器 (Flip-Flops): +
    • Flip-Flops 用于存储信息，是实现时序逻辑的关键元件。它们通常与 LUTs 配对，以构成可存储状态的逻辑单元。
  4. 编程互联资源 (Programmable Interconnects): +
    • 这些是连接 FPGA 内部不同部件的路径。它们可以被编程以形成任何所需的逻辑网络，从而将 LUTs、Flip-Flops 和其他资源连接起来。
  5. 输入/输出块 (I/O Blocks): +
    • 这些块连接 FPGA 和外部世界，提供数据输入和输出功能。它们可以配置为不同类型的接口（如单端或差分）。
  6. 专用硬件资源: +
    • 许多 FPGA 还包含专用的硬件资源，如 DSP (数字信号处理) 块、内存控制器、时钟管理模块（如 PLLs 和 BUFGs），以及其他特定功能块。
  7. 存储资源: +
    • 包括 RAM 块 (Block RAM) 或更小的存储单元，用于数据存储和缓冲。

FPGA 的关键优势在于其高度可编程性和灵活性。设计师可以通过编程定义 LUTs、MUXes、Flip-Flops 以及互连的配置和组合方式，从而在没有物理改动硬件的情况下实现几乎任何数字逻辑设计。这种灵活性使得 FPGA 在快速原型制作、定制硬件加速和可重配置系统中非常有价值。

+ ← + + 2023.11.16-阻塞与非阻塞赋值 + + → +

+ + + diff --git "a/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/2023.11.16-\351\230\273\345\241\236\344\270\216\351\235\236\351\230\273\345\241\236\350\265\213\345\200\274.html" "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/2023.11.16-\351\230\273\345\241\236\344\270\216\351\235\236\351\230\273\345\241\236\350\265\213\345\200\274.html" new file mode 100644 index 0000000..f1bc0fb --- /dev/null +++ "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/2023.11.16-\351\230\273\345\241\236\344\270\216\351\235\236\351\230\273\345\241\236\350\265\213\345\200\274.html" @@ -0,0 +1,102 @@ + + + + + + 2023.11.16-阻塞与非阻塞赋值 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2023.11.16-阻塞与非阻塞赋值

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组合逻辑电路使用阻塞赋值

时序逻辑电路使用非阻塞赋值

在 Verilog 中，阻塞赋值（Blocking Assignment）和非阻塞赋值（Non-Blocking Assignment）是两种不同的信号赋值方法，它们在时序逻辑的模拟和硬件描述语言（HDL）代码的编写中有着重要的区别。

# 阻塞赋值（Blocking Assignment）

  • 使用符号 = 进行赋值。
  • 阻塞赋值在执行时会“阻塞”代码的进一步执行，直到赋值完成。
  • 在执行下一条语句之前，当前语句必须完成其操作。
  • 在组合逻辑设计中常用，但在时序逻辑中使用可能会导致问题，因为它们可能会引起模拟时序和硬件时序的不一致。

举例：

a = b;
+c = a;
+

在这个例子中，c = a; 会等待 a = b; 完成后才执行。

# 非阻塞赋值（Non-Blocking Assignment）

  • 使用符号 <= 进行赋值。
  • 非阻塞赋值允许代码的后续部分在赋值完成之前继续执行。
  • 这意味着所有非阻塞赋值都是并行发生的（或看起来如此），这更接近于硬件的实际行为。
  • 在时序逻辑，特别是在描述触发器（如寄存器）的行为时非常重要和常用。

举例：

a <= b;
+c <= a;
+

在这个例子中，c <= a; 不会等待 a <= b; 的完成。a 和 c 的赋值看似同时发生。

在一个always块中，不同地方对同一个变量的赋值会被同时执行，最终结果是变量变成最后一次赋值的结果（前面的操作被覆盖）

+ ← + + 3. Verilog 数据类型 + + → +

+ + + diff --git "a/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/3.Verilog \346\225\260\346\215\256\347\261\273\345\236\213.html" "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/3.Verilog \346\225\260\346\215\256\347\261\273\345\236\213.html" new file mode 100644 index 0000000..f14055f --- /dev/null +++ "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/3.Verilog \346\225\260\346\215\256\347\261\273\345\236\213.html" @@ -0,0 +1,176 @@ + + + + + + 3. Verilog 数据类型 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 3. Verilog 数据类型

Verilog 最常用的 2 种数据类型就是线网（wire）与寄存器（reg），其余类型可以理解为这两种数据类型的扩展或辅助。

# 线网（wire）

wire 类型表示硬件单元之间的物理连线，由其连接的器件输出端连续驱动。如果没有驱动元件连接到 wire 型变量，缺省值一般为 "Z"。举例如下：

**wire**   interrupt;
+**wire**   flag1, flag2;
+**wire**   gnd = 1'b0;
+

线网型还有其他数据类型，包括 wand，wor，wri，triand，trior，trireg 等。这些数据类型用的频率不是很高，这里不做介绍。

# 寄存器（reg）

寄存器（reg）用来表示存储单元，它会保持数据原有的值，直到被改写。声明举例如下：

**reg**    clk_temp;
+**reg**    flag1, flag2;
+

例如在 always 块中，寄存器可能被综合成边沿触发器，在组合逻辑中可能被综合成 wire 型变量。寄存器不需要驱动源，也不一定需要时钟信号。在仿真时，寄存器的值可在任意时刻通过赋值操作进行改写。例如：

**reg** rstn ;
+**initial** **begin**    
+		rstn = 1'b0;
+    #100;
+    rstn = 1'b1;
+**end**
+

# 向量

当位宽大于 1 时，wire 或 reg 即可声明为向量的形式。例如：

**reg** [3:0]      counter ;    *//声明4bit位宽的寄存器counter*
+**wire** [32-1:0]  gpio_data;   *//声明32bit位宽的线型变量gpio_data*
+**wire** [8:2]     addr ;       *//声明7bit位宽的线型变量addr，位宽范围为8:2*
+**reg** [0:31]     data ;       *//声明32bit位宽的寄存器变量data, 最高有效位为0*
+

对于上面的向量，我们可以指定某一位或若干相邻位，作为其他逻辑使用。例如：

**wire** [9:0]     data_low = data[0:9] ;addr_temp[3:2] = addr[8:7] + 1'b1 ;
+

Verilog 支持可变的向量域选择，例如：

**reg** [31:0]     data1 ;
+**reg** [7:0]      byte1 [3:0];
+**integer** j ;
+**always**@* **begin**
+    **for** (j=0; j<=3;j=j+1) **begin**
+        byte1[j] = data1[(j+1)*8-1 : j*8];
+        *//把data1[7:0]…data1[31:24]依次赋值给byte1[0][7:0]…byte[3][7:0]*
+    **end
+end**
+

Verilog 还支持指定 bit 位后固定位宽的向量域选择访问。

  • [bit+: width] : 从起始 bit 位开始递增，位宽为 width。
  • [bit-: width] : 从起始 bit 位开始递减，位宽为 width。
*//下面 2 种赋值是等效的*
+A = data1[31-: 8] ;
+A = data1[31:24] ;
+*//下面 2 种赋值是等效的*
+B = data1[0+ : 8] ;
+B = data1[0:7] ;
+

对信号重新进行组合成新的向量时，需要借助大括号。例如：

**wire** [31:0]    temp1, temp2 ;
+**assign** temp1 = {byte1[0][7:0], data1[31:8]};  *//数据拼接*
+**assign** temp2 = {32{1'b0}};  *//赋值32位的数值0*
+

# 整数，实数，时间寄存器变量

整数，实数，时间等数据类型实际也属于寄存器类型。

# 整数（integer）

整数类型用关键字 integer 来声明。声明时不用指明位宽，位宽和编译器有关，一般为32 bit。reg 型变量为无符号数，而 integer 型变量为有符号数。例如：

**reg** [31:0]      data1 ;
+**reg** [3:0]       byte1 [7:0]; *//数组变量，后续介绍*
+**integer** j ;  *//整型变量，用来辅助生成数字电路*
+**always**@* **begin**
+    **for** (j=0; j<=3;j=j+1) **begin**
+        byte1[j] = data1[(j+1)*8-1 : j*8];
+        *//把data1[7:0]…data1[31:24]依次赋值给byte1[0][7:0]…byte[3][7:0]*
+        **end
+end**
+

此例中，integer 信号 j 作为辅助信号，将 data1 的数据依次赋值给数组 byte1。综合后实际电路里并没有 j 这个信号，j 只是辅助生成相应的硬件电路。

# 实数（real）

实数用关键字 real 来声明，可用十进制或科学计数法来表示。实数声明不能带有范围，默认值为 0。如果将一个实数赋值给一个整数，则只有实数的整数部分会赋值给整数。例如：

**real**        data1 ;
+**integer**     temp ;
+**initial** **begin**
+    data1 = 2e3 ;
+    data1 = 3.75 ;
+**end**
+
+**initial** **begin**
+    temp = data1 ; *//temp 值的大小为3*
+**end**
+

# 时间（time）

Verilog 使用特殊的时间寄存器 time 型变量，对仿真时间进行保存。其宽度一般为 64 bit，通过调用系统函数 $time 获取当前仿真时间。例如：

**time**       current_time ;
+**initial** **begin**
+       #100 ;
+       current_time = $time ; *//current_time 的大小为 100*
+**end**
+

# 数组

在 Verilog 中允许声明 reg, wire, integer, time, real 及其向量类型的数组。

数组维数没有限制。线网数组也可以用于连接实例模块的端口。数组中的每个元素都可以作为一个标量或者向量，以同样的方式来使用，形如：数组名[下标]。对于多维数组来讲，用户需要说明其每一维的索引。例如：

**integer**          flag [7:0] ; *//8个整数组成的数组*
+**reg**  [3:0]       counter [3:0] ; *//由4个4bit计数器组成的数组*
+**wire** [7:0]       addr_bus [3:0] ; *//由4个8bit wire型变量组成的数组*
+**wire**             data_bit[7:0][5:0] ; *//声明1bit wire型变量的二维数组*
+**reg** [31:0]       data_4d[11:0][3:0][3:0][255:0] ; *//声明4维的32bit数据变量数组*
+

下面显示了对数组元素的赋值操作：

flag [1]   = 32'd0 ; *//将flag数组中第二个元素赋值为32bit的0值*
+counter[3] = 4'hF ;  *//将数组counter中第4个元素的值赋值为4bit 十六进制数F，等效于counter[3][3:0] = 4'hF，即可省略宽度;*
+**assign** addr_bus[0]        = 8'b0 ; *//将数组addr_bus中第一个元素的值赋值为0*
+**assign** data_bit[0][1]     = 1'b1;  *//将数组data_bit的第1行第2列的元素赋值为1，这里不能省略第二个访问标号，即 assign data_bit[0] = 1'b1; 是非法的。*
+data_4d[0][0][0][0][15:0] = 15'd3 ;  *//将数组data_4d中标号为[0][0][0][0]的寄存器单元的15~0bit赋值为3*
+

虽然数组与向量的访问方式在一定程度上类似，但不要将向量和数组混淆。向量是一个单独的元件，位宽为 n；数组由多个元件组成，其中每个元件的位宽为 n 或 1。它们在结构的定义上就有所区别。

# 存储器

存储器变量就是一种寄存器数组，可用来描述 RAM 或 ROM 的行为。例如：

**reg**               membit[0:255] ;  *//256bit的1bit存储器*
+**reg**  [7:0]        mem[0:1023] ;    *//1Kbyte存储器，位宽8bit*
+mem[511] = 8'b0 ;                  *//令第512个8bit的存储单元值为0*
+

# 参数

参数用来表示常量，用关键字 parameter 声明，只能赋值一次。例如：

**parameter**      data_width = 10'd32 ;
+**parameter**      i=1, j=2, k=3 ;
+**parameter**      mem_size = data_width * 10 ;
+

但是，通过实例化的方式，可以更改参数在模块中的值。此部分以后会介绍。

局部参数用 localparam 来声明，其作用和用法与 parameter 相同，区别在于它的值不能被改变。所以当参数只在本模块中调用时，可用 localparam 来说明。

# 字符串

字符串保存在 reg 类型的变量中，每个字符占用一个字节（8bit）。因此寄存器变量的宽度应该足够大，以保证不会溢出。

字符串不能多行书写，即字符串中不能包含回车符。如果寄存器变量的宽度大于字符串的大小，则使用 0 来填充左边的空余位；如果寄存器变量的宽度小于字符串大小，则会截去字符串左边多余的数据。例如，为存储字符串 "run.runoob.com", 需要 14*8bit 的存储单元：

**reg** [0: 14*8-1]       str ;
+**initial** **begin**
+    str = "run.runoob.com";
+**end**
+

有一些特殊字符在显示字符串中有特殊意义，例如换行符，制表符等。如果需要在字符串中显示这些特殊的字符，则需要在前面加前缀转义字符 ** 。例如下表所示：

转义字符 显示字符
\n 换行
\t 制表符
%% %
\ \
" "
\ooo 1到3个8进制数字字符

其实，在 SystemVerilog（主要用于 Verilog 仿真的编程语言）语言中，已经可以直接用关键字 string 来表示字符串变量类型，这为 Verilog 的仿真带来了极大的便利。有兴趣的学者可以简单学习下 SystemVerilog。

+ ← + + 4. Verilog 表达式 + + → +

+ + + diff --git "a/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/4.Verilog \350\241\250\350\276\276\345\274\217.html" "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/4.Verilog \350\241\250\350\276\276\345\274\217.html" new file mode 100644 index 0000000..05c6708 --- /dev/null +++ "b/Chip/Chip/2023.11.07-Verilog\350\257\255\346\263\225/4.Verilog \350\241\250\350\276\276\345\274\217.html" @@ -0,0 +1,206 @@ + + + + + + 4. Verilog 表达式 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 4. Verilog 表达式

# 表达式

表达式由操作符和操作数构成，其目的是根据操作符的意义得到一个计算结果。表达式可以在出现数值的任何地方使用。例如：

# 实例

a^b ;          *//a与b进行异或操作*
+address[9:0] + 10'b1 ;  *//地址累加*
+flag1 && flag2 ;  *//逻辑与操作*
+

# 操作数

操作数可以是任意的数据类型，只是某些特定的语法结构要求使用特定类型的操作数。

操作数可以为常数，整数，实数，线网，寄存器，时间，位选，域选，存储器及函数调用等。

# 实例

**module** test;
+*//实数*
+**real** a, b, c;
+c = a + b ;
+*//寄存器*
+**reg**  [3:0]       cprmu_1, cprmu_2 ;
+**always** @(**posedge** clk) **begin**
+        cprmu_2 = cprmu_1 ^ cprmu_2 ;
+**end**
+         
+*//函数*
+**reg**  flag1 ;
+flag = calculate_result(A, B);
+ *//非法操作数*
+**reg** [3:0]         res;
+**wire** [3:0]        temp;
+**always**@ （*）**begin**
+    res    = cprmu_2 – cprmu_1 ;
+    *//temp = cprmu_2 – cprmu_1 ; //不合法，always块里赋值对象不能是wire型*
+**end
+endmodule**
+

# 操作符

Verilog 中提供了大约 9 种操作符，分别是算术、关系、等价、逻辑、按位、归约、移位、拼接、条件操作符。

大部分操作符与 C 语言中类似。同类型操作符之间，除条件操作符从右往左关联，其余操作符都是自左向右关联。圆括号内表达式优先执行。例如下面每组的 2 种写法都是等价的。

//自右向左关联，两种写法等价
+A+B-C ;
+(A+B）-C ;
+
+//自右向左关联，两种写法等价，结果为 B、D 或 F
+A ? B : C ? D : F ;
+A ? B : (C ? D : F) ;
+
+//自右向左关联，两种写法不等价
+(A ? B : C) ? D : F ;  //结果 D 或 F
+A ? B : C ? D : F ; //结果为 B、D 或 F
+

不同操作符之间，优先级是不同的。下表列出了操作符优先级从高至低的排列顺序。当没有圆括号时，Verilog 会根据操作符优先级对表达式进行计算。为了避免由操作符优先级导致的计算混乱，在不确定优先级时，建议用圆括号将表达式区分开来。

操作符 操作符号 优先级
单目运算 + - ! ~ 最高
乘、除、取模 * / %
加减 + -
移位 <<  >>
关系 <  <=  >  >=
等价 ==  !=  ===  !===
归约 & ~&
^ ~^
~
逻辑 &&
条件 ?: 最低

# 算术操作符

算术操作符包括单目操作符和双目操作符。

双目操作符对 2 个操作数进行算术运算，包括乘（*）、除（/）、加（+）、减（-）、求幂（**）、取模（%）。

# 实例

**reg** [3:0]  a, b;**reg** [4:0]  c ;
+a = 4'b0010 ;
+b = 4'b1001 ;
+c = a+b;        *//结果为c=b'b1011*
+c = a/b;          *//结果为c=4，取整*
+

如果操作数某一位为 X，则计算结果也会全部出现 X。例如：

# 实例

b = 4'b100x ;
+c = a+b ;       *//结果为c=4'bxxxx*
+

对变量进行声明时，要根据变量的操作符对变量的位宽进行合理声明，不要让结果溢出。上述例子中，相加的 2 个变量位宽为 4bit，那么结果寄存器变量位宽最少为 5bit。否则，高位将被截断，导致结果高位丢失。无符号数乘法时，结果变量位宽应该为 2 个操作数位宽之和。

# 实例

**reg** [3:0]        mula ;**reg** [1:0]        mulb;**reg** [5:0]        res ;
+mula = 4'he   ;
+mulb = 2'h3   ;
+res  = mula * mulb ; *//结果为res=6'h2a, 数据结果没有丢失位数*
+
  • 和 - 也可以作为单目操作符来使用，表示操作数的正负性。此类操作符优先级最高。
-4  //表示负4
++3  //表示正3
+

负数表示时，可以直接在十进制数字前面增加一个减号 -，也可以指定位宽。因为负数使用二进制补码来表示，不指定位宽来表示负数，编译器在转换时，会自动分配位宽，从而导致意想不到的结果。例如：

# 实例

mula = -4'd4 ;
+mulb = 2 ;
+res = mula * mulb ;      *//计算结果为res=-6'd8, 即res=6'h38，正常*
+res = mula * (-'d4) ;    *//(4的32次幂-4) * 2, 结果异常*
+

# 关系操作符

关系操作符有大于（>），小于（<），大于等于（>=），小于等于（<=）。

关系操作符的正常结果有 2 种，真（1）或假（0）。

如果操作数中有一位为 x 或 z，则关系表达式的结果为 x。

# 实例

A = 4 ;
+B = 3 ;
+X = 3'b1xx ;
+   
+A > B     *//为真*
+A <= B    *//为假*
+A >= Z    *//为X，不确定*
+

# 等价操作符

等价操作符包括逻辑相等（==），逻辑不等（!=），全等（===），非全等（!==）。

等价操作符的正常结果有 2 种：为真（1）或假（0）。

逻辑相等/不等操作符不能比较 x 或 z，当操作数包含一个 x 或 z，则结果为不确定值。

全等比较时，如果按位比较有相同的 x 或 z，返回结果也可以为 1，即全等比较可比较 x 或 z。所以，全等比较的结果一定不包含 x。举例如下：

# 实例

A = 4 ;
+B = 8'h04 ;
+C = 4'bxxxx ;
+D = 4'hx ;
+A == B        *//为真*
+A == (B + 1)  *//为假*
+A == C        *//为X，不确定*
+A === C       *//为假，返回值为0*
+C === D       *//为真，返回值为1*
+

# 逻辑操作符

逻辑操作符主要有 3 个：&&（逻辑与）, ||（逻辑或），!（逻辑非）。

逻辑操作符的计算结果是一个 1 bit 的值，0 表示假，1 表示真，x 表示不确定。

如果一个操作数不为 0，它等价于逻辑 1；如果一个操作数等于 0，它等价于逻辑 0。如果它任意一位为 x 或 z，它等价于 x。

如果任意一个操作数包含 x，逻辑操作符运算结果不一定为 x。

逻辑操作符的操作数可以为变量，也可以为表达式。例如：

# 实例

A = 3;
+B = 0;
+C = 2'b1x ;
+   
+A && B    *//     为假*
+A || B    *//     为真*! A       *//     为假*! B       *//     为真*
+A && C    *//     为X，不确定*
+A || C    *//     为真，因为A为真*(A==2) && (! B)  *//为真，此时第一个操作数为表达式*
+

# 按位操作符

按位操作符包括：取反（~），与（&），或（|），异或（^），同或（~^）。

按位操作符对 2 个操作数的每 1 bit 数据进行按位操作。

如果 2 个操作数位宽不相等，则用 0 向左扩展补充较短的操作数。

取反操作符只有一个操作数，它对操作数的每 1 bit 数据进行取反操作。

下图给出了按位操作符的逻辑规则。

| &(与） | 0 | 1 | x | | |(或) | 0 | 1 | x | +| --- | --- | --- | --- | --- | --- | --- | --- | --- | +| 0 | 0 | 0 | 0 | | 0 | 0 | 1 | x | +| 1 | 0 | 1 | x | | 1 | 1 | 1 | 1 | +| x | 0 | x | x | | x | x | 1 | x |

^(异或) 0 1 x ~^(同或) 0 1 x
0 0 1 x 0 1 0 x
1 1 0 x 1 0 1 x
x x x x x x x x

# 实例

A = 4'b0101 ;
+B = 4'b1001 ;
+C = 4'bx010 ;
+~A        *//4'b1010*
+A & B     *//4'b0001*
+A | B     *//4'b1101*
+A^B       *//4'b1100*
+A ~^ B    *//4'b0011*
+B | C     *//4'b1011*
+B&C       *//4'bx000*
+

# 归约操作符

归约操作符包括：归约与（&），归约与非（~&），归约或（|），归约或非（~|），归约异或（^），归约同或（~^）。

归约操作符只有一个操作数，它对这个向量操作数逐位进行操作，最终产生一个 1bit 结果。

逻辑操作符、按位操作符和归约操作符都使用相同的符号表示，因此有时候容易混淆。区分这些操作符的关键是分清操作数的数目，和计算结果的规则。

A = 4'b1010 ;
+&A ;      //结果为 1 & 0 & 1 & 0 = 1'b0，可用来判断变量A是否全1
+~|A ;     //结果为 ~(1 | 0 | 1 | 0) = 1'b0, 可用来判断变量A是否为全0
+^A ;      //结果为 1 ^ 0 ^ 1 ^ 0 = 1'b0
+

# 移位操作符

移位操作符包括左移（<<），右移（>>），算术左移（<<<），算术右移（>>>）。

移位操作符是双目操作符，两个操作数分别表示要进行移位的向量信号（操作符左侧）与移动的位数（操作符右侧）。

算术左移和逻辑左移时，右边低位会补 0。

逻辑右移时，左边高位会补 0；而算术右移时，左边高位会补充符号位，以保证数据缩小后值的正确性。

# 实例

A = 4'b1100 ;
+B = 4'b0010 ;
+A = A >> 2 ;        *//结果为 4'b0011*
+A = A << 1;         *//结果为 4'b1000*
+A = A <<< 1 ;       *//结果为 4'b1000*
+C = B + (A>>>2);    *//结果为 2 + (-4/4) = 1, 4'b0001*
+

# 拼接操作符

拼接操作符用大括号 {，} 来表示，用于将多个操作数（向量）拼接成新的操作数（向量），信号间用逗号隔开。

拼接符操作数必须指定位宽，常数的话也需要指定位宽。例如：

# 实例

A = 4'b1010 ;
+B = 1'b1 ;
+Y1 = {B, A[3:2], A[0], 4'h3 };  *//结果为Y1='b1100_0011*
+Y2 = {4{B}, 3'd4};  *//结果为 Y2=7'b111_1100*
+Y3 = {32{1'b0}};  *//结果为 Y3=32h0，常用作寄存器初始化时匹配位宽的赋初值*
+

# 条件操作符

条件表达式有 3 个操作符，结构描述如下：

condition_expression ? true_expression : false_expression
+

计算时，如果 condition_expression 为真（逻辑值为 1），则运算结果为 true_expression；如果 condition_expression 为假（逻辑值为 0），则计算结果为 false_expression。

assign hsel    = (addr[9:8] == 2'b0) ? hsel_p1 : hsel_p2 ;
+//当信号 addr 高 2bit 为 0 时，hsel 赋值为 hsel_p1; 否则，将 hsel_p2 赋值给 hsel。
+

其实，条件表达式类似于 2 路（或多路）选择器，其描述方式完全可以用 if-else 语句代替。

当然条件操作符也能进行嵌套，完成一个多次选择的逻辑。例如：

# 实例

**assign**   hsel = (addr[9:8] == 2'b00) ? hsel_p1 :
+                (addr[9:8] == 2'b01) ? hsel_p2 :
+                (addr[9:8] == 2'b10) ? hsel_p3 :
+                (addr[9:8] == 2'b11) ? hsel_p4 ;
+

+ ← +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel.html b/Chip/Chip/2024.02.21-Chisel.html new file mode 100644 index 0000000..47a71bb --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel.html @@ -0,0 +1,98 @@ + + + + + + 2024.02.21-Chisel | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.02.21-Chisel

2024.02.21-1. Introduction to Scala

2024.02.23-2.1 First Chisel Module

2024.02.24-2.2 Combinational Logic

2024.02.25-2.3 Control Flow

2024.02.26-2.4 Sequential Logic

2024.02.28-2.5 FIR Filter

2024.02.29-2.6 More on ChiselTest

2024.03.01-3.1 Generators: Parameters

2024.03.03-3.2 Generators: Collections

2024.03.04-3.3 Interlude: Chisel Standard Library

2024.03.05-3.4 Higher-Order Functions

+ ← + + 一生一芯计划 + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.02.21-1 Introduction to Scala.html b/Chip/Chip/2024.02.21-Chisel/2024.02.21-1 Introduction to Scala.html new file mode 100644 index 0000000..7bda03b --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.02.21-1 Introduction to Scala.html @@ -0,0 +1,238 @@ + + + + + + 2024.02.21-1. Introduction to Scala | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.02.21-1. Introduction to Scala

# Variables and Constants - var and val

var numberOfKittens = 6
+val kittensPerHouse = 101
+val alphabet = "abcdefghijklmnopqrstuvwxyz"
+var done = false
+
+/*
+numberOfKittens: Int = 6
+kittensPerHouse: Int = 101
+alphabet: String = "abcdefghijklmnopqrstuvwxyz"
+done: Boolean = false
+*/
+

变量使用var声明，常量则使用val

# Conditionals

if (done) {
+    println("we are done")
+}
+else if (numberOfKittens < kittensPerHouse) {
+    println("more kittens!")
+    numberOfKittens += 1
+}
+else {
+    done = true
+}
+

类似于C++，如果只有一行，可以省略大括号

val likelyCharactersSet = if (alphabet.length == 26)
+    "english"
+else 
+    "not english"
+
+println(likelyCharactersSet)
+// likelyCharactersSet: String = "english"
+

if这一串的返回值又所选择的分支的最后一行确定

# Methods (Functions)

// Simple scaling function with an input argument, e.g., times2(3) returns 6
+// Curly braces can be omitted for short one-line functions.
+def times2(x: Int): Int = 2 * x
+
+// More complicated function
+def distance(x: Int, y: Int, returnPositive: Boolean): Int = {
+    val xy = x * y
+    if (returnPositive) xy.abs else -xy.abs
+}
+

# Overloading Functions

// Overloaded function
+def times2(x: Int): Int = 2 * x
+def times2(x: String): Int = 2 * x.toInt
+
+times2(5)   // 10
+times2("7")   // 14
+

# Recursive and Nested Functions

def asciiTriangle(rows: Int) {
+    
+    // This is cute: multiplying "X" makes a string with many copies of "X"
+    // Unit means no return value
+    def printRow(columns: Int): Unit = println("X" * columns)
+    
+    if(rows > 0) {
+        printRow(rows)
+        asciiTriangle(rows - 1) // Here is the recursive call
+    }
+}
+
+// printRow(1) // This would not work, since we're calling printRow outside its scope
+asciiTriangle(6)
+
+// Output:
+XXXXXX
+XXXXX
+XXXX
+XXX
+XX
+X
+

# Named Parameters and Parameter Defaults

Consider the following method definition.

def myMethod(count: Int, wrap: Boolean, wrapValue: Int= 24): Unit= { ... }
+

When calling the method, you will often see the parameter names along with the passed-in values.

myMethod(count= 10, wrap= false, wrapValue= 23)
+

Using named parameters, you can even call the function with a different ordering.

myMethod(wrapValue= 23, wrap= false, count= 10)
+

For frequently called methods, the parameter ordering may be obvious. But for less common methods and, in particular, boolean arguments, including the names with calls can make your code a lot more readable. If methods have a long list of arguments of the same type, using names also decreases the chance of error. Parameters to class definitions also use this named argument scheme (they are actually just the parameters to the constructor method for the class).

When certain parameters have default values (that don't need to be overridden), callers only have to pass (by name) specific arguments that do not use defaults. Notice that the parameter  wrapValue has a default value of 24. Therefore, this will work as if 24 had been passed in.

myMethod(wrap= false, count= 10)
+

# Lists

val x = 7
+val y = 14
+val list1 = List(1, 2, 3)
+val list2 = x :: y :: y :: Nil       // An alternate notation for assembling a list
+                                     // Nil就是一个空的List[Nothing]，即一个可以封装任何类型元素但又没有元素的容器
+
+val list3 = list1 ++ list2           // Appends the second list to the first list
+val m = list2.length
+val s = list2.size
+
+val headOfList = list1.head          // Gets the first element of the list
+val restOfList = list1.tail          // Get a new list with first element removed
+
+val third = list1(2)                 // Gets the third element of a list (0-indexed)
+
+// Output:
+x: Int = 7
+y: Int = 14
+list1: List[Int] = List(1, 2, 3)
+list2: List[Int] = List(7, 14, 14)
+list3: List[Int] = List(1, 2, 3, 7, 14, 14)
+m: Int = 3
+s: Int = 3
+headOfList: Int = 1
+restOfList: List[Int] = List(2, 3)
+third: Int = 3
+

# for Statement

for (i <- 0 to 7) { print(i + " ") } // include 7
+println()
+
+i <- 0 until 7 // exclude 7
+i <- 0 to 10 by 2
+

print 用于连续输出不换行，而 println 用于输出后换行。

<- 是用在for循环构造中的一个操作符，表示从一个集合中逐一取出元素

# Packages and Imports

  • package 用于定义一个命名空间，它可以包含类、对象和特质（traits），以及其他包。包主要用于组织和管理代码，防止命名冲突，并提供访问控制。
  • class 是定义数据结构及其行为的蓝图。它可以包含数据成员（属性）和方法。类用于实例化对象，每个对象都可以拥有不同的属性值。

**import语句可以用来引入包、类、对象，甚至是特定的方法或属性。这意味着你可以使用import**来引用几乎任何你需要的代码实体。以下是一些例子：

  • 引入一个包中的所有成员：import scala.collection.mutable._，这里的**_相当于Java中的``，表示引入mutable**包下的所有成员。
  • 引入一个特定的类：import scala.collection.mutable.ListBuffer，这表示只引入**ListBuffer**类。
  • 引入一个包中的多个类：import scala.collection.mutable.{ArrayBuffer, LinkedList}，这表示同时引入**ArrayBuffer和LinkedList**两个类。
  • 引入一个对象中的特定成员：import java.lang.System.{out => stdout}，这里还演示了将**System.out重命名为stdout**，以便在代码中使用简化的名称。
// 从chisel3.iotesters包中引入特定的几个类：ChiselFlatSpec、Driver、和PeekPokeTester
+import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester}
+

# Class

// WrapCounter counts up to a max value based on a bit size
+class WrapCounter(counterBits: Int) {
+
+  val max: Long = (1 << counterBits) - 1
+  var counter = 0L
+    
+  def inc(): Long = {
+    counter = counter + 1
+    if (counter > max) {
+        counter = 0
+    }
+    counter
+  }
+  println(s"counter created with max value $max")
+}
+

  • class WrapCounter -- This is the definition of WrapCounter.

  • (counterBits: Int) -- Creating a WrapCounter requires an integer parameter, nicely named to suggest it is the bit width of the counter.

  • Braces ({}) delimit a block of code. Most classes use a code block to define variables, constants, and methods (functions).

  • val max: Long = -- the class contains a member variable max, declared as type Long and initialized as the class is created.

  • (1 << counterBits) - 1 computes the maximum value that can be contained in counterBits bits. Since max was created with val it cannot be changed.

  • A variable counter is created and initialized to 0L. The L says that 0 is a long value; thus, counter is inferred to be Long.

  • max and counter are commonly called member variables of the class.

  • A class method inc is defined which takes no arguments and returns a Long value.

  • The body of the method inc is a code block that has:

    • counter = counter + 1 increments counter.
    • if (counter > max) { counter = 0 } tests if the counter is greater than the max value and sets it back to zero if it is.
    • counter -- The last line of the code block is important. +
      • Any value expressed as the last line of a code block is considered to be the return value of that code block. The return value can be used or ignored by the calling statement.
      • This applies quite generally; for example, since an if then else statement defines its true and false clauses with code blocks, it can return a value i.e., val result = if (10 * 10 > 90) "greater" else "lesser" would create a val with the value "greater".
    • So in this case the function inc returns the value of counter.

  • println(s"counter created with max value $max") prints a string to standard output. Because the println is directly in the defining code block, it is part of the class initialization code and is run, i.e. prints out the string, every time an instance of this class is created.

  • The string printed in this case is an interpolated string.

    • The leading s in front of the first double quote identifies this as an interpolated string.
    • An interpolated string is processed at run time.
    • The $max is replaced with the value of max.
    • If the $ is followed by a code block, arbitrary Scala can be in that code block. +
      • For example, println(s"doubled max is ${max + max}").
      • The return value of this code block will be inserted in place of ${...}.
      • If the return value is not a string, it will be converted to one; virtually every class or type in scala has an implicit conversion to a string defined).
    • You should generally avoid printing something every time an instance of a class is created to avoid flooding standard output, unless you're debugging.

    # Creating an Instance of a Class

    val x = new WrapCounter(2)
+x.inc() // Increments the counter
+
+// Member variables of the instance x are visible to the outside, unless they are declared private
+if(x.counter == x.max) {              
+    println("counter is about to wrap")
+}
+
+x inc() // Scala allows the dots to be omitted; this can be useful for making embedded DSL's look more natural
+

    有时候实例化类时不需要使用**new关键字，这通常是因为该类定义了一个或多个apply方法。apply方法可以在类的伴生对象（companion object）中定义，允许你直接通过类名加括号的方式创建类的实例，而不需要显式地使用new关键字。这种方式提供了一种更简洁的语法来创建对象，同时也可以在apply**方法内部执行初始化操作或参数处理，为对象创建提供更多的灵活性和控制。

    例如，假设有一个名为**Person的类及其伴生对象，伴生对象中定义了apply**方法：

    class Person(val name: String)
+
+object Person {
+  def apply(name: String): Person = new Person(name)
+}
+

    在这个例子中，可以通过调用**Person伴生对象的apply方法来创建Person类的实例，而不需要使用new**关键字：

    val person = Person("Alice")  // 相当于调用 Person.apply("Alice")
+

    这里，**Person("Alice")实际上调用的是伴生对象中的apply方法，该方法内部使用new关键字创建了Person**类的实例。这种方式使得代码看起来更简洁，同时保留了通过构造函数创建对象的灵活性。

# Code Blocks

Code blocks are delimited by braces. A block can contain zero or more lines of Scala code. The last line of Scala code becomes the return value (which may be ignored) of the code block. A code block with no lines would return a special null-like object called Unit. Code blocks are used throughout Scala: they are the bodies of class definitions, they form function and method definitions, they are the clauses of if statements, and they are the bodies of for and many other Scala operators.

# Parameterized Code Blocks

Code blocks can take parameters. In the case of class and method definitions, these parameters look like those in most conventional programming languages. In the example below, c and s are parameters of the code blocks.

// A one-line code block doesn't need to be enclosed in {}
+def add1(c: Int): Int = c + 1
+
+class RepeatString(s: String) {
+    val repeatedString = s + s
+}
+

IMPORTANT: There is another way in which code blocks may be parameterized. Here is an example.

val intList = List(1, 2, 3)
+val stringList = intList.map { i =>
+    i.toString
+}
+

使用**map方法对intList中的每个元素应用一个函数，该函数将整数转换为其对应的字符串表示。具体来说，map方法遍历intList中的每个元素（用i表示），并对每个元素执行i.toString**操作，将其转换为字符串。This type of code block is called an anonymous function, and more details on anonymous functions are provided in a later module.

+ 2024.02.23-2.1 First Chisel Module + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.02.23-2.1 First Chisel Module.html b/Chip/Chip/2024.02.21-Chisel/2024.02.23-2.1 First Chisel Module.html new file mode 100644 index 0000000..4847a29 --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.02.23-2.1 First Chisel Module.html @@ -0,0 +1,209 @@ + + + + + + 2024.02.23-2.1 First Chisel Module | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.02.23-2.1 First Chisel Module

# Setup

val path = System.getProperty("user.dir") + "/source/load-ivy.sc"
+interp.load.module(ammonite.ops.Path(java.nio.file.FileSystems.getDefault().getPath(path)))
+import chisel3._
+import chisel3.util._
+import chisel3.tester._
+import chisel3.tester.RawTester.test
+import dotvisualizer._
+

这两句代码在使用Chisel（一种硬件描述语言）时，涉及到Ammonite脚本的动态加载。第一句定义了一个**path变量，它通过获取系统属性"user.dir"（当前用户目录）并附加上"/source/load-ivy.sc"路径，用于指定一个Scala脚本文件的位置。第二句使用Ammonite的interp.load.module**方法动态加载这个指定路径下的Scala脚本文件。

动态加载脚本在使用Chisel编写代码时可以有多个用途，如：

  1. 引入依赖：动态加载**load-ivy.sc**脚本可以用来引入或更新Ammonite会话中的Ivy依赖，确保代码运行时有必要的库支持。
  2. 执行初始化代码：可以在脚本中执行必要的初始化操作，为后续的Chisel硬件设计代码执行设置适当的环境或参数。
  3. 灵活性和模块化：通过动态加载脚本，可以根据需要灵活地加载和卸载模块，使代码结构更加模块化，便于管理和维护。
  • import chisel3._：基础的Chisel功能，包括定义硬件组件的基本构建块。
  • import chisel3.util._：提供了一些实用工具和额外的硬件构建块，比如计数器、移位寄存器等。
  • import chisel3.tester._：提供了测试Chisel硬件设计的工具和框架。
  • import chisel3.tester.RawTester.test：是**chisel3.tester**中的一个具体的测试功能，用于执行硬件测试。

# Example Module

class Passthrough extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(4.W))
+    val out = Output(UInt(4.W))
+  })
+  io.out := io.in
+}
+
+// with parameter
+class PassthroughGenerator(width: Int) extends Module { 
+  val io = IO(new Bundle {
+    val in = Input(UInt(width.W))
+    val out = Output(UInt(width.W))
+  })
+  io.out := io.in
+}
+
class Passthrough extends Module {
+

我们声明一个叫做Passthrough的新模块。Module是Chisel内置的一个类，所有硬件模块都必须扩展它

val io = IO(...)
+

我们在一个特殊的**io变量中声明所有的输入和输出端口。它必须被命名为io，并且是一个IO对象或实例，这需要形如IO(_instantiated_bundle_)**的东西

在Chisel中，io、in和out被声明为val（不可变引用）而不是**var（可变引用），因为它们代表硬件模块的接口。在硬件设计中，接口的结构（例如信号的数量、类型和方向）在编译时确定且不会改变。虽然信号的值在模拟过程中会变化，但信号的定义（即接口）是固定的。使用val**声明这些接口强调了它们是不变的结构，而信号值的变化则通过信号之间的连接和赋值来体现，这与软件编程中变量的概念有所不同。

new Bundle {
+    val in = Input(...)
+    val out = Output(...)
+}
+

我们声明了一个新的硬件结构类型（Bundle），它包含了一些命名的信号**in和out**，分别具有输入和输出的方向。

在Chisel中，Bundle是一种用于定义一组相关信号的类，类似于Verilog中的module内部信号或VHDL中的record。它允许开发者将多个信号组合成一个单一的复合类型，这样可以更方便地管理和传递数据结构。每个**Bundle内的信号可以有不同的类型和方向（如输入Input、输出Output**），使其成为定义模块接口和内部数据结构的强大工具。

UInt(4.W)
+

我们声明了信号的硬件类型。在这个案例中，它是宽度为4的无符号整数。

io.out := io.in
+

我们将我们的输入端口连接到我们的输出端口，这样**io.in驱动io.out。注意，:=操作符是一个*Chisel***操作符，它表示右手边的信号驱动左手边的信号。它是一个有方向的操作符。

硬件构建语言（HCLs）的一个整洁之处在于我们可以使用底层的编程语言作为脚本语言。例如，在声明我们的Chisel模块之后，我们接着使用Scala调用Chisel编译器将Chisel的**Passthrough翻译成Verilog的Passthrough。这个过程被称为*精炼***。

# Generate Verilog

println(getVerilog(new Passthrough))
+
module Passthrough(
+  input        clock,
+  input        reset,
+  input  [3:0] io_in,
+  output [3:0] io_out
+);
+  assign io_out = io_in; // @[cmd2.sc 6:10]
+endmodule
+

# Generate Firrtl

println(getFirrtl(new Passthrough))
+
circuit Passthrough :
+  module Passthrough :
+    input clock : Clock
+    input reset : UInt<1>
+    output io : { flip in : UInt<4>, out : UInt<4>}
+
+    io.out <= io.in @[cmd2.sc 6:10]
+

# Example Tester

// Scala Code: `test` runs the unit test. 
+// test takes a user Module and has a code block that applies pokes and expects to the 
+// circuit under test (c)
+test(new Passthrough()) { c =>
+    c.io.in.poke(0.U)     // Set our input to value 0
+    c.io.out.expect(0.U)  // Assert that the output correctly has 0
+    c.io.in.poke(1.U)     // Set our input to value 1
+    c.io.out.expect(1.U)  // Assert that the output correctly has 1
+    c.io.in.poke(2.U)     // Set our input to value 2
+    c.io.out.expect(2.U)  // Assert that the output correctly has 2
+}
+println("SUCCESS!!") // Scala Code: if we get here, our tests passed!
+
+// Test with width 10
+test(new PassthroughGenerator(10)) { c =>
+    c.io.in.poke(0.U(10.W))     // Set our input to value 0
+    c.io.out.expect(0.U(10.W))  // Assert that the output correctly has 0
+    c.io.in.poke(1.U(10.W))     // Set our input to value 1
+    c.io.out.expect(1.U(10.W))  // Assert that the output correctly has 1
+    c.io.in.poke(2.U(10.W))     // Set our input to value 2
+		c.io.out.expect(2.U(10.W))  // Assert that the output correctly has 2
+}
+
  • c.io.in.poke(0.U)：设置模块的输入**in**为0。
  • c.io.out.expect(0.U)：检查模块的输出**out**是否为0，确保电路按预期工作。
  • 接下来，代码以相同的方式测试输入值1和2，分别使用**poke方法设置输入值，并用expect**方法验证输出值。

在Scala中，可以直接在函数调用后跟一个代码块，这是因为Scala支持高阶函数，即可以接受函数作为参数的函数。在这个例子中，**test函数接受两个参数：一个是Passthrough模块的实例，另一个是一个匿名函数（或称为代码块），这个匿名函数以c作为参数进行操作。这种语法使得代码更加简洁易读，允许直接在调用函数时定义行为逻辑，非常适合进行单元测试等场景。当一个函数的最后一个参数是函数类型时，可以使用特殊的语法糖允许将这个函数参数写在方法调用的外部。这种语法不仅使得代码更加清晰，而且在使用匿名函数或代码块作为参数时尤其有用，因为它允许代码块在视觉上更为突出，从而提高了代码的可读性。这就是为什么test(new Passthrough())**后面可以直接跟一个代码块的原因。

c =>是一个函数字面量（匿名函数）的语法，用于定义一个函数。这里，c是函数的参数，=>后面跟着的是函数体。在这个上下文中，c代表传递给测试代码块的模块实例（如Passthrough模块实例），然后在代码块内部，你可以使用c来访问和操作这个实例的输入和输出端口。在Scala的函数字面量中，参数类型通常是通过上下文推断出来的，不需要显式声明。在test(new Passthrough()) { c => ... }这段代码中，c是由test函数根据其参数类型推断出的Passthrough模块实例。也就是说，当你写c =>时，c的类型（在这个例子中是Passthrough模块实例）是由test函数的定义确定的，根据这个函数期望的参数类型。这就是为什么可以直接使用c来访问Passthrough实例的成员，如c.io.in和c.io.out，而不需要额外的类型声明。

Note that the `poke` and `expect` use chisel hardware literal notation. Both operations expect literals of the correct type.
+If `poke`ing a `UInt()` you must supply a `UInt` literal (example: `c.io.in.poke(10.U)`, likewise if the input is a `Bool()` the `poke` would expect either `true.B` or `false.B`.
+

# Appendix: A Note on "printf" Debugging

class PrintingModule extends Module {
+    val io = IO(new Bundle {
+        val in = Input(UInt(4.W))
+        val out = Output(UInt(4.W))
+    })
+    io.out := io.in
+
+    printf("Print during simulation: Input is %d\n", io.in)
+    // chisel printf has its own string interpolator too
+    printf(p"Print during simulation: IO is $io\n")
+
+    println(s"Print during generation: Input is ${io.in}")
+// s用于一般的Scala字符串插值，而p专门为Chisel设计，用于更方便地在仿真中打印硬件信号和对象
+}
+
+test(new PrintingModule ) { c =>
+    c.io.in.poke(3.U)
+    c.io.out.expect(3.U)
+    c.clock.step(5) // circuit will print
+    
+    println(s"Print during testing: Input is ${c.io.in.peek()}")
+}
+
Elaborating design...
+Print during generation: Input is UInt<4>(IO in unelaborated PrintingModule)
+Done elaborating.
+Print during simulation: Input is   3
+Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
+Print during simulation: Input is   3
+Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
+Print during simulation: Input is   3
+Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
+Print during simulation: Input is   3
+Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
+Print during simulation: Input is   3
+Print during simulation: IO is AnonymousBundle(in ->   3, out ->   3)
+Print during testing: Input is UInt<4>(3)
+Print during simulation: Input is   0
+Print during simulation: IO is AnonymousBundle(in ->   0, out ->   0)
+test PrintingModule Success: 0 tests passed in 7 cycles in 0.003471 seconds 2016.88 Hz
+

这段代码定义了一个**PrintingModule类，它扩展了Chisel的Module**，用于演示在不同阶段打印信息：

  1. 模块定义中的printf语句：这些在仿真时每个时钟周期都会打印。**printf("Print during simulation: Input is %d\n", io.in)会打印输入信号的值，而printf(p"Print during simulation: IO is $io\n")会打印io**对象的信息。这些仅在仿真（运行时）生效。
  2. 模块定义中的println语句：这句话在模块的生成阶段打印，即代码编译时，打印到终端或控制台。它不会在仿真时打印，因为它是Scala的打印语句，不是Chisel的。
  3. 测试块中的println语句：这在Scala测试环境中执行，用于打印测试时的信息。如**println(s"Print during testing: Input is ${c.io.in.peek()}")**将在测试过程中打印输入信号的当前值。
  • **c.io.in.poke(3.U)**设置输入为3。
  • **c.io.out.expect(3.U)**期望输出为3，这个测试会通过，因为输出应该与输入相同。
  • **c.clock.step(5)推进仿真时钟5个周期，这期间printf**语句会打印信息。
  1. 最后的Print during simulation: Input is 0 是因为被重置回到默认状态
  2. 7 周期则是因为测试中执行了**c.clock.step(5)**，推进了5个时钟周期，加上测试开始前后的各1个周期

综上，**println用于代码生成阶段和测试代码中，打印到Scala的执行环境；printf**用于仿真阶段，打印到仿真的输出中。

+ ← + + 2024.02.24-2.2 Combinational Logic + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.02.24-2.2 Combinational Logic.html b/Chip/Chip/2024.02.21-Chisel/2024.02.24-2.2 Combinational Logic.html new file mode 100644 index 0000000..c70f81a --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.02.24-2.2 Combinational Logic.html @@ -0,0 +1,266 @@ + + + + + + 2024.02.24-2.2 Combinational Logic | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.02.24-2.2 Combinational Logic

# Common Operators

class MyModule extends Module {
+  val io = IO(new Bundle {
+    val in  = Input(UInt(4.W))
+    val out = Output(UInt(4.W))
+  })
+	
+	// Scala expression
+  val two  = 1 + 1
+  println(two)
+	// Chisel expression
+  val utwo = 1.U + 1.U
+  println(utwo)
+	// incorrect
+	val twotwo = 1.U + 1
+  
+  io.out := io.in
+}
+
class MyOperators extends Module {
+  val io = IO(new Bundle {
+    val in      = Input(UInt(4.W))
+    val out_add = Output(UInt(4.W))
+    val out_sub = Output(UInt(4.W))
+    val out_mul = Output(UInt(4.W))
+  })
+
+  io.out_add := 1.U + 4.U
+  io.out_sub := 2.U - 1.U
+  io.out_mul := 4.U * 2.U
+}
+
+// 没有参数时可以省略小括号
+test(new MyOperators) {c =>
+  c.io.out_add.expect(5.U)
+  c.io.out_sub.expect(1.U)
+  c.io.out_mul.expect(8.U)
+}
+

# Mux and Concatenation

class MyOperatorsTwo extends Module {
+  val io = IO(new Bundle {
+    val in      = Input(UInt(4.W))
+    val out_mux = Output(UInt(4.W))
+    val out_cat = Output(UInt(4.W))
+  })
+
+  val s = true.B
+  io.out_mux := Mux(s, 3.U, 0.U) // should return 3.U, since s is true
+  io.out_cat := Cat(2.U, 1.U)    // concatenates 2 (b10) with 1 (b1) to give 5 (101)
+}
+
+println(getVerilog(new MyOperatorsTwo))
+
+test(new MyOperatorsTwo) { c =>
+  c.io.out_mux.expect(3.U)
+  c.io.out_cat.expect(5.U)
+}
+

The Mux operates like a traditional ternary operator, with the order (select, value if true, value if false)

The Cat ordering is MSB then LSB (where B refers to bit or bits), and only takes two arguments.

# MAC: multiply accumulate function

class MAC extends Module {
+  val io = IO(new Bundle {
+    val in_a = Input(UInt(4.W))
+    val in_b = Input(UInt(4.W))
+    val in_c = Input(UInt(4.W))
+    val out  = Output(UInt(8.W))
+  })
+
+  io.out := (io.in_a * io.in_b) + io.in_c
+}
+
+test(new MAC) { c =>
+  val cycles = 100
+  import scala.util.Random
+  for (i <- 0 until cycles) {
+    val in_a = Random.nextInt(16)
+    val in_b = Random.nextInt(16)
+    val in_c = Random.nextInt(16)
+    c.io.in_a.poke(in_a.U)
+    c.io.in_b.poke(in_b.U)
+    c.io.in_c.poke(in_c.U)
+    c.io.out.expect((in_a * in_b + in_c).U)
+  }
+}
+

# Arbiter

The following circuit arbitrates data coming from a FIFO into two parallel processing units. The FIFO and processing elements (PEs) communicate with ready-valid interfaces. Construct the arbiter to send data to whichever PE is ready to receive data, prioritizing PE0 if both are ready to receive data. Remember that the arbiter should tell the FIFO that it's ready to receive data when at least one of the PEs can receive data. Also, wait for a PE to assert that it's ready before asserting that the data are valid. You will likely need binary operators to complete this exercise.

Untitled

class Arbiter extends Module {
+  val io = IO(new Bundle {
+    // FIFO
+    val fifo_valid = Input(Bool())
+    val fifo_ready = Output(Bool())
+    val fifo_data  = Input(UInt(16.W))
+    
+    // PE0
+    val pe0_valid  = Output(Bool())
+    val pe0_ready  = Input(Bool())
+    val pe0_data   = Output(UInt(16.W))
+    
+    // PE1
+    val pe1_valid  = Output(Bool())
+    val pe1_ready  = Input(Bool())
+    val pe1_data   = Output(UInt(16.W))
+  })
+
+  io.fifo_ready := io.pe0_ready || io.pe1_ready
+  io.pe0_valid  := io.fifo_valid && io.pe0_ready
+  io.pe1_valid  := io.fifo_valid && !io.pe0_ready && io.pe1_ready
+  io.pe0_data   := io.fifo_data
+  io.pe1_data   := io.fifo_data
+}
+
+test(new Arbiter) { c =>
+  import scala.util.Random
+  val data = Random.nextInt(65536)
+  c.io.fifo_data.poke(data.U)
+  
+  for (i <- 0 until 8) {
+    c.io.fifo_valid.poke((((i >> 0) % 2) != 0).B)
+    c.io.pe0_ready.poke((((i >> 1) % 2) != 0).B)
+    c.io.pe1_ready.poke((((i >> 2) % 2) != 0).B)
+
+    c.io.fifo_ready.expect((i > 1).B)
+    c.io.pe0_valid.expect((i == 3 || i == 7).B)
+    c.io.pe1_valid.expect((i == 5).B)
+    
+    if (i == 3 || i ==7) {
+      c.io.pe0_data.expect((data).U)
+    } else if (i == 5) {
+      c.io.pe1_data.expect((data).U)
+    }
+  }
+}
+println("SUCCESS!!")
+

数据线（如**io.pe0_data** 和 io.pe1_data）通常会持续地带有它们可能需要使用的数据信号（本例中为**io.fifo_data）。但是，这些数据是否被“接收”或“采用”通常由valid**信号来控制。

测试代码设计用来验证**Arbiter模块的行为。测试通过随机生成一个数据，然后使用不同的组合的fifo_valid，pe0_ready和pe1_ready**信号来模拟不同的工作情况。

  • **c.io.fifo_data.poke(data.U)**模拟从FIFO发送的数据。
  • 循环**for (i <- 0 until 8)**遍历8种不同的信号组合状态。
  • c.io.fifo_valid.poke，**c.io.pe0_ready.poke和c.io.pe1_ready.poke根据i**的不同值模拟不同的信号状态，使用位操作来确定每个信号是否应该被激活。
  • c.io.fifo_ready.expect，**c.io.pe0_valid.expect和c.io.pe1_valid.expect**是对仲裁器预期行为的断言检查。
  • 如果**i的值表示PE0或PE1应该接收数据（如i == 3 || i == 7是PE0，i == 5是PE1），则使用expect断言来检查io.pe0_data或io.pe1_data**与FIFO的数据相同。

# Parameterized Adder

class ParameterizedAdder(saturate: Boolean) extends Module {
+  val io = IO(new Bundle {
+    val in_a = Input(UInt(4.W))
+    val in_b = Input(UInt(4.W))
+    val out  = Output(UInt(4.W))
+  })
+  val sum = io.in_a +& io.in_b
+  if(saturate){
+    io.out := Mux(sum>15.U,15.U,sum)
+  }else{
+    io.out := sum
+  }
+}
+
+for (saturate <- Seq(true, false)) {
+  test(new ParameterizedAdder(saturate)) { c =>
+    // 100 random tests
+    val cycles = 100
+    import scala.util.Random
+    import scala.math.min
+    for (i <- 0 until cycles) {
+      val in_a = Random.nextInt(16)
+      val in_b = Random.nextInt(16)
+      c.io.in_a.poke(in_a.U)
+      c.io.in_b.poke(in_b.U)
+      if (saturate) {
+        c.io.out.expect(min(in_a + in_b, 15).U)
+      } else {
+        c.io.out.expect(((in_a + in_b) % 16).U)
+      }
+    }
+    
+    // ensure we test saturation vs. truncation
+    c.io.in_a.poke(15.U)
+    c.io.in_b.poke(15.U)
+    if (saturate) {
+      c.io.out.expect(15.U)
+    } else {
+      c.io.out.expect(14.U)
+    }
+  }
+}
+println("SUCCESS!!")
+

在Chisel中，+&是一个用于加法的运算符，它会考虑输入的进位，得到一个比最大输入位宽更宽的结果。如果输入是4位UInt，标准加法结果**io.in_a + io.in_b会是4位，可能会截断超出的位。而+&加法会产生一个5位的结果，这可以用于在必要时实现饱和加法逻辑。连接一个4位的UInt线到一个5位的UInt**线（一个4.W的量等于5.W的量），默认会截断最高位（MSB）。这样，你可以用这个方法来轻松实现非饱和加法器，只保留5位和的低4位。

+ ← + + 2024.02.25-2.3 Control Flow + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.02.25-2.3 Control Flow.html b/Chip/Chip/2024.02.21-Chisel/2024.02.25-2.3 Control Flow.html new file mode 100644 index 0000000..53eafb1 --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.02.25-2.3 Control Flow.html @@ -0,0 +1,229 @@ + + + + + + 2024.02.25-2.3 Control Flow | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.02.25-2.3 Control Flow

# Last Connect Semantics

class LastConnect extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(4.W))
+    val out = Output(UInt(4.W))
+  })
+  io.out := 1.U
+  io.out := 2.U
+  io.out := 3.U
+  io.out := 4.U
+}
+
+//  Test LastConnect
+test(new LastConnect) { c => c.io.out.expect(4.U) }
+

当有多个值被赋值给一个量时，最后的那个生效

# when, elsewhen, and otherwise

when(someBooleanCondition) {
+  // things to do when true
+}.elsewhen(someOtherBooleanCondition) {
+  // things to do on this condition
+}.otherwise {
+  // things to do if none of th boolean conditions are true
+}
+

when是一种特殊的构造，它用于硬件生成。它类似于软件编程中的if语句，但是在硬件描述中，when会生成实际的硬件逻辑，如多路复用器。而标准的if语句通常用于生成时（编译时）的控制流，并不直接生成硬件。if语句在Scala（因此在Chisel的生成时）可以有返回值，可以用于赋值或者作为表达式的一部分。相比之下，when是一种专门为硬件设计提供的控制结构，用于生成条件硬件逻辑，如多路复用器或条件赋值，但它不返回值。因此，当你需要根据输入信号在运行时动态地选择硬件行为时，你会使用when。而当你在编译时根据某些条件生成不同的硬件模块时，你会使用**if**。

在Scala中，**==用于基本类型和对象的相等性比较，而在Chisel中（一个建立在Scala之上的硬件构建语言），===用于硬件信号之间的相等性比较。这是因为Chisel需要区分硬件操作和Scala的软件操作，===在Chisel中被定义为生成硬件电路中的等于比较逻辑。而在Scala的if语句中，==**仍然用于比较两个值是否相等。这种区分确保了代码的清晰性，以及硬件设计中逻辑正确性的维护。因此，在when中使用===来生成判断相等的硬件电路

# The Wire Construct

Wire是一种基本的硬件构造类型，用于创建一个可以在模块内部读取和写入的信号。它主要用于表示组合逻辑或暂存数据，允许在硬件描述中定义中间变量或内部连接。使用Wire时，需要指定信号的数据类型，如UInt或SInt等。Wire类型的变量在定义时不持有初始值，需要在逻辑中显式赋值。在使用过程中，可以根据需要多次对其赋值，但在每个时钟周期结束时，Wire仅保留最后一次赋值的结果。val myWire = Wire(UInt(32.W))

List(1, 2, 3, 4).permutations.foreach { case i0 :: i1 :: i2 :: i3 :: Nil =>
+    println(s"Sorting $i0 $i1 $i2 $i3")}
+List(1, 2, 3, 4).permutations.foreach { case i0 :: i1 :: i2 :: _ :: Nil =>
+  println(s"Sorting $i0 $i1 $i2")}
+

使用Scala的集合和模式匹配功能来遍历**List(1, 2, 3, 4)的所有排列组合。List(1, 2, 3, 4).permutations生成一个包含所有可能排列的列表的迭代器。foreach**循环遍历这些排列。

在**foreach的代码块中，case i0 :: i1 :: i2 :: i3 :: Nil =>是一个模式匹配表达式，用于解构每个排列列表。这个表达式匹配一个包含四个元素的列表，将这四个元素分别绑定到变量i0、i1、i2、i3。Nil**在这里表示列表的末尾，确保列表只有这四个元素。这种方式允许直接访问每个排列中的元素，然后可以将它们打印出来或用于其他逻辑操作。

# Exercise: Polynomial

class Polynomial extends Module {
+  val io = IO(new Bundle {
+    val select = Input(UInt(2.W))
+    val x = Input(SInt(32.W))
+    val fOfX = Output(SInt(32.W))
+  })
+    
+  val result = Wire(SInt(32.W))  
+  val square = Wire(SInt(32.W))  
+  
+  square := io.x * io.x
+  when(io.select === 0.U){
+    result := square - 2.S * io.x + 1.S
+  }.elsewhen(io.select === 1.U) {
+    result := 2.S * square + 6.S * io.x + 3.S
+  }.otherwise {
+    result := 4.S * square - 10.S * io.x - 5.S
+  }
+
+  io.fOfX := result  
+}
+
+// Test Polynomial
+test(new Polynomial) { c =>
+  for(x <- 0 to 20) {
+    for(select <- 0 to 2) {
+      c.io.select.poke(select.U)
+      c.io.x.poke(x.S)
+      c.io.fOfX.expect(poly(select, x).S)
+    }
+  }
+}
+

# Exercise: Finite State Machine

Grad students pass through four states in their career: Idle, Coding, Writing, and Graduating. These states transition based off three inputs: Coffee, Ideas they come up with, and Pressure from their advisor to make progress. Once they Graduate, they return to the Idle state. The FSM diagram below shows these states and transitions. Any unlabelled transition (i.e. when there are no inputs) returns a grad student to the Idle state instead of staying in the current state. The input precedence is coffee > idea > pressure, so when in the Idle state and receiving both coffee and pressure, a graduate student will move to the Coding state.

Untitled

检查逻辑：

// state map
+def states = Map("idle" -> 0, "coding" -> 1, "writing" -> 2, "grad" -> 3)
+
+// life is full of question marks
+def gradLife (state: Int, coffee: Boolean, idea: Boolean, pressure: Boolean): Int = {
+  var nextState = states("idle")
+  if(state == states("idle")){
+    if(coffee) nextState = states("coding")
+    else if(idea) nextState = states("idle")
+    else if(pressure) nextState = states("writing")
+    else nextState = states("idle")
+  }else if(state == states("coding")){
+    if(coffee) nextState = states("coding")
+    else if(idea) nextState = states("writing")
+    else if(pressure) nextState = states("writing")
+    else nextState = states("idle")
+  }else if(state == states("writing")){
+    if(coffee) nextState = states("writing")
+    else if(idea) nextState = states("writing")
+    else if(pressure) nextState = states("grad")
+    else nextState = states("idle")
+  }
+  nextState
+}
+
+// some sanity checks
+(0 until states.size).foreach{ state => assert(gradLife(state, false, false, false) == states("idle")) }
+assert(gradLife(states("writing"), true, false, true) == states("writing"))
+assert(gradLife(states("idle"), true, true, true) == states("coding"))
+assert(gradLife(states("idle"), false, true, true) == states("idle"))
+assert(gradLife(states("grad"), false, false, false) == states("idle"))
+

Chisel:

class GradLife extends Module {
+  val io = IO(new Bundle {
+    val state = Input(UInt(2.W))
+    val coffee = Input(Bool())
+    val idea = Input(Bool())
+    val pressure = Input(Bool())
+    val nextState = Output(UInt(2.W))
+  })
+    
+  val idle :: coding :: writing :: grad :: Nil = Enum(4)
+  
+  when(io.state === idle){
+    when(io.coffee) {io.nextState := coding}
+    .elsewhen(io.idea) {io.nextState := idle}
+    .elsewhen(io.pressure) {io.nextState := writing}
+    .otherwise {io.nextState := idle}
+  } .elsewhen (io.state === coding) {
+    when      (io.coffee) { io.nextState := coding } 
+    .elsewhen (io.idea || io.pressure) { io.nextState := writing }
+    .otherwise {io.nextState := idle}
+  } .elsewhen (io.state === writing) {
+    when      (io.coffee || io.idea) { io.nextState := writing }
+    .elsewhen (io.pressure) { io.nextState := grad }
+    .otherwise {io.nextState := idle}
+  }.otherwise {io.nextState := idle}
+}
+
+// Test
+test(new GradLife) { c =>
+  // verify that the hardware matches the golden model
+  for (state <- 0 to 3) {
+    for (coffee <- List(true, false)) {
+      for (idea <- List(true, false)) {
+        for (pressure <- List(true, false)) {
+          c.io.state.poke(state.U)
+          c.io.coffee.poke(coffee.B)
+          c.io.idea.poke(idea.B)
+          c.io.pressure.poke(pressure.B)
+          c.io.nextState.expect(gradLife(state, coffee, idea, pressure).U)
+        }
+      }
+    }
+  }
+}
+

+ ← + + 2024.02.26-2.4 Sequential Logic + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.02.26-2.4 Sequential Logic.html b/Chip/Chip/2024.02.21-Chisel/2024.02.26-2.4 Sequential Logic.html new file mode 100644 index 0000000..ed2701c --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.02.26-2.4 Sequential Logic.html @@ -0,0 +1,241 @@ + + + + + + 2024.02.26-2.4 Sequential Logic | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.02.26-2.4 Sequential Logic

# Registers

A Reg holds its output value until the rising edge of its clock, at which time it takes on the value of its input.

class RegisterModule extends Module {
+  val io = IO(new Bundle {
+    val in  = Input(UInt(12.W))
+    val out = Output(UInt(12.W))
+  })
+  
+	// val register : UInt = Reg(UInt(12.W))
+  val register = Reg(UInt(12.W))
+  register := io.in + 1.U
+  io.out := register
+}
+
+test(new RegisterModule) { c =>
+  for (i <- 0 until 100) {
+    c.io.in.poke(i.U)
+    c.clock.step(1)
+    c.io.out.expect((i + 1).U)
+  }
+}
+println("SUCCESS!!")
+

Notice: One important note is that Chisel distinguishes between types (like UInt) and hardware nodes (like the literal 2.U, or the output of myReg).

// legal because a Reg needs a data type as a model
+val myReg = Reg(UInt(2.W))
+// error because `2.U` is already a hardware node and can't be used as a model
+val myReg = Reg(2.U)
+

# RegInit

The register in RegisterModule was initialized to random data for simulation. Unless otherwised specified, registers do not have a reset value (or a reset). The way to create a register that resets to a given value is with RegInit.

// The first argument is a type node that specified the datatype and its width.
+// The second argument is a hardware node that specified the reset value, in this case 0.
+val myReg = RegInit(UInt(12.W), 0.U)
+
+// It is a hardware node that specifies the reset value, but normally `0.U`.
+val myReg = RegInit(0.U(12.W))
+

RegInit 不仅初始化，也创建了这个reg，因此不需要先创建再init

class RegInitModule extends Module {
+  val io = IO(new Bundle {
+    val in  = Input(UInt(12.W))
+    val out = Output(UInt(12.W))
+  })
+  
+  val register = RegInit(0.U(12.W))
+  register := io.in + 1.U
+  io.out := register
+}
+

# RegNext

RegNext 在 Chisel 中是一个用于创建寄存器并在下一个时钟周期将输入信号的值传递给该寄存器的便捷方法。它简化了寄存器的声明和初始化，使得您可以轻松地创建一个将当前输入信号的值保存到下一个时钟周期的寄存器。使用**RegNext**时，可以指定一个初始值，如果不指定，则寄存器在复位时的值是未定义的

在 Chisel 中使用 RegNext 的基本语法如下：

val myReg = RegNext(inputSignal, initValue)
+
  • inputSignal 是你希望在下一个时钟周期传递给寄存器的信号。
  • initValue 是可选参数，用于指定寄存器在复位时的初始值。如果不提供初始值，寄存器在复位时的值是未定义的。

# Shift Register

Untitled

class MyShiftRegister(val init: Int = 1) extends Module {
+  val io = IO(new Bundle {
+    val in  = Input(Bool())
+    val out = Output(UInt(4.W))
+  })
+
+  val state = RegInit(UInt(4.W), init.U)
+  val stateTemp = (state << 1.U) + io.in.asUInt
+  state := stateTemp
+  io.out := state
+}
+
+test(new MyShiftRegister()) { c =>
+  var state = c.init
+  for (i <- 0 until 10) {
+    // poke in LSB of i (i % 2)
+    c.io.in.poke(((i % 2) != 0).B)
+    // update expected state
+    state = ((state * 2) + (i % 2)) & 0xf
+    c.clock.step(1)
+    c.io.out.expect(state.U)
+  }
+}
+println("SUCCESS!!")
+

# Parameterized Shift Register

// n is the output width (number of delays - 1)
+// init state to init
+class MyOptionalShiftRegister(val n: Int, val init: BigInt = 1) extends Module {
+  val io = IO(new Bundle {
+    val en  = Input(Bool())
+    val in  = Input(Bool())
+    val out = Output(UInt(n.W))
+  })
+
+  val state = RegInit(init.U(n.W))
+
+  when(io.en){
+    state := state << 1 | io.in
+  }
+  io.out := state
+}
+
+// test different depths
+for (i <- Seq(3, 4, 8, 24, 65)) {
+  println(s"Testing n=$i")
+  test(new MyOptionalShiftRegister(n = i)) { c =>
+    val inSeq = Seq(0, 1, 1, 1, 0, 1, 1, 0, 0, 1)
+    var state = c.init
+    var i = 0
+    c.io.en.poke(true.B)
+    while (i < 10 * c.n) {
+      // poke in repeated inSeq
+      val toPoke = inSeq(i % inSeq.length)
+      c.io.in.poke((toPoke != 0).B)
+      // update expected state
+      state = ((state * 2) + toPoke) & BigInt("1"*c.n, 2)
+      c.clock.step(1)
+      c.io.out.expect(state.U)
+
+      i += 1
+    }
+  }
+}
+println("SUCCESS!!")
+

Notice: Chisel中变量被声明为常量val，因此一个变量只能被赋值一次，因为这表示硬件电路连接，但是会根据输入等的不同而具有不同的值。因此不能多次给一个变量赋值，如果需要，可以把中间值重新命名为一个val来调用

# Appendix: Explicit clock and reset

Chisel模块默认使用隐式的时钟和复位信号，每个内部创建的寄存器都会使用这些默认信号。在某些情况下，你可能需要覆盖这种默认行为，比如使用生成时钟或复位信号的黑盒，或者设计多时钟系统。Chisel提供了**withClock() {}、withReset() {}和withClockAndReset() {}等构造来处理这些情况，允许分别或同时覆盖时钟和复位。需要注意的是，至本教程编写时，复位信号总是同步的并且是Bool类型。时钟在Chisel中有其自身的类型（Clock），并且应该相应声明。Bool类型可以通过调用asClock()转换为Clock类型，但需要确保这样做是合理的。同时，chisel-testers**目前对多时钟设计的支持并不完全。

# Example: Multi-Clock Module

// we need to import multi-clock features
+import chisel3.experimental.{withClock, withReset, withClockAndReset}
+
+class ClockExamples extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(10.W))
+    val alternateReset    = Input(Bool())
+    val alternateClock    = Input(Clock())
+    val outImplicit       = Output(UInt())
+    val outAlternateReset = Output(UInt())
+    val outAlternateClock = Output(UInt())
+    val outAlternateBoth  = Output(UInt())
+  })
+
+  val imp = RegInit(0.U(10.W))
+  imp := io.in
+  io.outImplicit := imp
+
+  withReset(io.alternateReset) {
+    // everything in this scope with have alternateReset as the reset
+    val altRst = RegInit(0.U(10.W))
+    altRst := io.in
+    io.outAlternateReset := altRst
+  }
+
+  withClock(io.alternateClock) {
+    val altClk = RegInit(0.U(10.W))
+    altClk := io.in
+    io.outAlternateClock := altClk
+  }
+
+  withClockAndReset(io.alternateClock, io.alternateReset) {
+    val alt = RegInit(0.U(10.W))
+    alt := io.in
+    io.outAlternateBoth := alt
+  }
+}
+
+println(getVerilog(new ClockExamples))
+

通过**import chisel3.experimental.{withClock, withReset, withClockAndReset}引入了多时钟特性。ClockExamples模块定义了一个10位宽的输入io.in，以及替代的复位和时钟信号io.alternateReset和io.alternateClock**。模块输出了四种不同情况下的寄存器值：使用默认时钟和复位、只替换复位、只替换时钟、同时替换时钟和复位。

  1. withReset(io.alternateReset) {...}块定义了一个新的作用域，其中所有寄存器的复位信号被替换为io.alternateReset。在这个作用域内，**altRst寄存器在被替代复位信号复位时初始化为0，并在每个时钟周期将io.in**的值赋给它。
  2. withClock(io.alternateClock) {...}块定义了另一个作用域，其中所有寄存器的时钟信号被替换为io.alternateClock。在这个作用域内，**altClk寄存器在被替代时钟信号驱动时初始化为0，并在每个时钟周期将io.in**的值赋给它。
  3. withClockAndReset(io.alternateClock, io.alternateReset) {...}块同时替换了寄存器的时钟和复位信号为io.alternateClock和io.alternateReset。在这个作用域内，**alt寄存器同时被替代的时钟和复位信号控制，初始化为0，并在每个时钟周期将io.in**的值赋给它。

+ ← + + 2024.02.28-2.5 FIR Filter + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.02.28-2.5 FIR Filter.html b/Chip/Chip/2024.02.21-Chisel/2024.02.28-2.5 FIR Filter.html new file mode 100644 index 0000000..7beeac8 --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.02.28-2.5 FIR Filter.html @@ -0,0 +1,135 @@ + + + + + + 2024.02.28-2.5 FIR Filter | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.02.28-2.5 FIR Filter

Untitled

class My4ElementFir(b0: Int, b1: Int, b2: Int, b3: Int) extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(8.W))
+    val out = Output(UInt(8.W))
+  })
+
+  val reg_1 = RegInit(0.U(8.W))
+  val reg_2 = RegInit(0.U(8.W))
+  val reg_3 = RegInit(0.U(8.W))
+  
+  reg_1 := io.in
+  reg_2 := reg_1
+  reg_3 := reg_2
+
+	// 或者使用RegNext来一并定义初始化及赋值
+	val reg_1 = RegNext(io.in, 0.U)
+	val reg_2 = RegNext(reg_1, 0.U)
+	val reg_3 = RegNext(reg_2, 0.U)
+  
+  io.out := b0.U(8.W) * io.in + b1.U(8.W) * reg_1 + b2.U(8.W) * reg_2 + b3.U(8.W) * reg_3
+}
+

# FIR Filter Generator

一个有限脉冲响应（FIR）滤波器生成器。生成器的**length参数决定了滤波器的抽头数目，即滤波器的长度。这个生成器有三个输入：in（滤波器的输入信号）、valid（一个布尔值，表示输入是否有效）和consts（一个向量，包含所有抽头的系数）。还有一个输出out**，即滤波器的输出。

  • **taps**是一个序列，包含输入和一系列寄存器，用于实现滤波器的延迟线。
  • 当**valid**信号为真时，序列中的每个元素（除了第一个）被更新为前一个元素的值。
  • 输出**out**是抽头值和对应系数乘积之和。

这个结构允许滤波器动态处理不同长度的输入，通过改变**consts**向量的内容来改变滤波器的特性。

class MyManyDynamicElementVecFir(length: Int) extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(8.W))
+    val valid = Input(Bool())
+    val out = Output(UInt(8.W))
+    val consts = Input(Vec(length, UInt(8.W)))
+  })
+  
+  // Such concision! You'll learn what all this means later.
+  val taps = Seq(io.in) ++ Seq.fill(io.consts.length - 1)(RegInit(0.U(8.W)))
+  taps.zip(taps.tail).foreach { case (a, b) => when (io.valid) { b := a } }
+
+  io.out := taps.zip(io.consts).map { case (a, b) => a * b }.reduce(_ + _)
+}
+
+visualize(() => new MyManyDynamicElementVecFir(4))
+

  1. val io = IO(new Bundle {...})定义了模块的接口，包括8位宽的输入in，一个有效信号**valid，8位宽输出out，和长度为length的系数向量consts**。

  2. **val taps = Seq(io.in) ++ Seq.fill(io.consts.length - 1)(RegInit(0.U(8.W)))这行代码在FIR滤波器实现中创建了一个名为taps的序列，用于存储当前和之前的输入值，从而实现数据的时间序列延迟。首先，它将输入信号io.in作为序列的第一个元素。随后，使用++操作符将io.in与一个新的序列连接起来，后者通过Seq.fill(io.consts.length - 1)(RegInit(0.U(8.W)))创建，其中包含length - 1个初始化为0的8位寄存器。这样，taps序列就包含了一个输入信号和length - 1个延迟寄存器，总共length个元素，每个元素对应滤波器的一个抽头。在Chisel中，虽然io.in不是寄存器，但taps序列可以包含不同类型的元素，因为在Chisel里，所有这些都被视为Data类型的子类，可以被综合为硬件。在这个上下文中，io.in**是直接的输入信号，而后续元素是寄存器类型，但它们共同构成了一个序列，用于表示滤波器的不同时间点上的信号值。这种混合类型的序列是可行的，并可以在Chisel生成的硬件中正确表达相应的逻辑。

  3. **taps.zip(taps.tail).foreach { case (a, b) => when (io.valid) { b := a } }在输入valid为真时，将taps**序列中每个元素的值传递到下一个元素，实现数据在寄存器间的移动。

    zip是一个方法，它将两个集合中对应位置的元素组成一对，生成一个新的集合。在这里，taps.zip(taps.tail)的作用是将taps列表中的每个元素与其后面的元素配对。tail是一个方法，返回除第一个元素外的列表所有元素。例如，如果taps是[in, reg1, reg2, reg3]，那么**taps.tail就是[reg1, reg2, reg3]。taps.zip(taps.tail)的结果将是[(in, reg1), (reg1, reg2), (reg2, reg3)]。这样，foreach就可以遍历这些配对，根据valid**信号更新寄存器的值，实现数据的逐级传递。

    case (a, b) =>是模式匹配的语法，用于解构元组，将zip操作生成的元素对分别赋值给a（当前元素）和**b**（下一个元素）。

  4. io.out := taps.zip(io.consts).map { case (a, b) => a * b }.reduce(_ + _)计算输出out，即将每个延迟元素与其对应的系数相乘，并将所有乘积求和得到最终结果。

    在这段代码中，**map和reduce**是Scala中的集合操作方法：

    • map：对集合中的每个元素应用一个函数。这里**map { case (a, b) => a * b }对每对(a, b)应用乘法操作，a来自taps，b来自io.consts**，分别代表寄存器中的数据和滤波器的系数。
    • reduce：对集合中的元素应用一个二元操作，逐步将集合减少为单一结果。这里的**reduce(_ + _)**将所有乘法结果相加，得到最终的滤波输出。

    不使用**foreach是因为foreach仅用于执行操作而不返回结果，而这里的目的是计算经过滤波器后的输出值，需要通过map和reduce**聚合计算结果。

+ ← + + 2024.02.29-2.6 More on ChiselTest + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.02.29-2.6 More on ChiselTest.html b/Chip/Chip/2024.02.21-Chisel/2024.02.29-2.6 More on ChiselTest.html new file mode 100644 index 0000000..6b439b2 --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.02.29-2.6 More on ChiselTest.html @@ -0,0 +1,132 @@ + + + + + + 2024.02.29-2.6 More on ChiselTest | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.02.29-2.6 More on ChiselTest

iotesters ChiselTest
poke poke(c.io.in1, 6) c.io.in1.poke(6.U)
peek peek(c.io.out1) c.io.out1.peek()
expect expect(c.io.out1, 6) c.io.out1.expect(6.U)
step step(1) c.clock.step(1)
initiate Driver.execute(...) { c => test(...) { c =>

# Modules with Decoupled Interfaces

class QueueModule[T <: Data](ioType: T, entries: Int) extends MultiIOModule {
+  val in = IO(Flipped(Decoupled(ioType)))
+  val out = IO(Decoupled(ioType))
+  out <> Queue(in, entries)
+}
+
  1. class QueueModule[T <: Data](ioType: T, entries: Int) extends MultiIOModule 定义了一个泛型队列模块，其中**T <: Data表示T是Data类型或其子类型。ioType是队列中数据的类型，entries**是队列的大小。
  2. Decoupled(ioType)是一个Chisel提供的高级接口，自动包含了valid、**bits和ready信号。valid和bits组合用于传输有效数据，而ready信号用于流量控制。当你声明一个Decoupled**接口时，这些信号都会被自动创建。
  3. IO(Flipped(Decoupled(ioType))) 创建了一个输入端口，**Flipped意味着通常的输入输出方向被反转（即原本是输出的valid和bits成为输入，原本是输入的ready成为输出），Decoupled**表示它是一个可以被反压的接口。
  4. out <> Queue(in, entries) 将输出端口**out连接到一个新建的Queue实例，Queue(in, entries)创建了一个队列，其中in是输入端口，entries是队列大小。<>是连接操作符，表示双向连接。确保了数据可以从in流向队列，经过处理后，再从队列流向out**。

# EnqueueNow and expectDequeueNow

**EnqueueNow和expectDequeueNow是用于测试队列行为的方法。EnqueueNow用于立即将数据入队，而不需要等待队列准备好。expectDequeueNow**用于立即从队列中出队数据，并验证其值是否符合预期。这两个方法都是在基于队列的测试中非常有用，使得测试代码可以直接控制和验证队列中数据的流动。这样，测试者可以确保队列正确地处理了入队和出队操作，并且数据的传输符合设计的预期。

test(new QueueModule(UInt(9.W), entries = 200)) { c =>
+    // Example testsequence showing the use and behavior of Queue
+    c.in.initSource()
+    c.in.setSourceClock(c.clock)
+    c.out.initSink()
+    c.out.setSinkClock(c.clock)
+    
+    val testVector = Seq.tabulate(200){ i => i.U }
+
+    testVector.zip(testVector).foreach { case (in, out) =>
+      c.in.enqueueNow(in)
+      c.out.expectDequeueNow(out)
+    }
+}
+

There is some required boiler plate initSource, setSourceClock, etc that is necessary to ensure that the ready and valid fields are all initialized correctly at the beginning of the test.

# EnqueueSeq and DequeueSeq

EnqueueSeq 允许你一次性将一个序列的元素批量入队，这对于测试需要连续多个数据处理的场景特别有用。DequeueSeq, 相应地，用于一次性从队列中出队多个元素，并验证这些元素是否符合预期的序列。enqueueSeq must finish before the expectDequeueSeq can begin. This example would fail if the testVector's size is made larger than the queue depth, because the queue would fill up and not be able to complete the enqueueSeq.

# Fork and Join

**fork和join用于创建并发测试，允许同时执行多个操作或测试场景。使用fork可以启动一个并发的测试过程，这个过程可以与主测试流程同时运行。可以在fork后使用多个测试命令定义并发执行的操作。随后，join**用于等待所有并发启动的测试过程完成。这样，你可以在一个测试中执行多个并行操作，例如同时对多个模块输入不同的信号，或者同时观察多个输出。这在需要模拟复杂交互或并行处理时特别有用。

test(new QueueModule(UInt(9.W), entries = 200)) { c =>
+    // Example testsequence showing the use and behavior of Queue
+    c.in.initSource()
+    c.in.setSourceClock(c.clock)
+    c.out.initSink()
+    c.out.setSinkClock(c.clock)
+    
+    val testVector = Seq.tabulate(300){ i => i.U }
+
+    fork {
+        c.in.enqueueSeq(testVector)
+    }.fork {
+        c.out.expectDequeueSeq(testVector)
+    }.join()
+}
+

虽然**fork启动了两个并发过程，似乎表明c.in.enqueueSeq(testVector)和c.out.expectDequeueSeq(testVector)应该同时执行，但实际上，它们在逻辑上是有先后顺序的。enqueueSeq首先向队列中填充数据，而expectDequeueSeq则等待这些数据从队列中出现并验证它们。在ChiselTest中，fork创建的并发线程会同时开始执行，但是expectDequeueSeq**自然会在等待有数据可以出队之后才开始验证，确保了数据的正确流向和测试的逻辑顺序。

+ ← + + 2024.03.01-3.1 Generators: Parameters + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.03.01-3.1 Generators Parameters.html b/Chip/Chip/2024.02.21-Chisel/2024.03.01-3.1 Generators Parameters.html new file mode 100644 index 0000000..dbeb3fc --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.03.01-3.1 Generators Parameters.html @@ -0,0 +1,353 @@ + + + + + + 2024.03.01-3.1 Generators: Parameters | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.03.01-3.1 Generators: Parameters

# Parameter Passing

# Example: Parameterized Scala Object

class ParameterizedScalaObject(param1: Int, param2: String) {
+  println(s"I have parameters: param1 = $param1 and param2 = $param2")
+}
+val obj1 = new ParameterizedScalaObject(4,     "Hello")
+val obj2 = new ParameterizedScalaObject(4 + 2, "World")
+

# Example: Parameterized Chisel Object

class ParameterizedWidthAdder(in0Width: Int, in1Width: Int, sumWidth: Int) extends Module {
+  require(in0Width >= 0)
+  require(in1Width >= 0)
+  require(sumWidth >= 0)
+  val io = IO(new Bundle {
+    val in0 = Input(UInt(in0Width.W))
+    val in1 = Input(UInt(in1Width.W))
+    val sum = Output(UInt(sumWidth.W))
+  })
+  // a +& b includes the carry, a + b does not
+  io.sum := io.in0 +& io.in1
+}
+
+println(getVerilog(new ParameterizedWidthAdder(1, 4, 6)))
+

The above code block has some require(...) statements. These are pre-elaboration assertions, which are useful when your generator only works with certain parameterizations or when some parameterizations are mutually exclusive or nonsensical. The above code block checks that widths are non-negative.

# Example: Parameterized 4-input Sort

Untitled

/** Sort4 sorts its 4 inputs to its 4 outputs */
+class Sort4(ascending: Boolean) extends Module {
+  val io = IO(new Bundle {
+    val in0 = Input(UInt(16.W))
+    val in1 = Input(UInt(16.W))
+    val in2 = Input(UInt(16.W))
+    val in3 = Input(UInt(16.W))
+    val out0 = Output(UInt(16.W))
+    val out1 = Output(UInt(16.W))
+    val out2 = Output(UInt(16.W))
+    val out3 = Output(UInt(16.W))
+  })
+    
+  // this comparison funtion decides < or > based on the module's parameterization
+  def comp(l: UInt, r: UInt): Bool = {
+      if (ascending) {
+        l < r
+      } else {
+        l > r
+    }
+  }
+
+  val row10 = Wire(UInt(16.W))
+  val row11 = Wire(UInt(16.W))
+  val row12 = Wire(UInt(16.W))
+  val row13 = Wire(UInt(16.W))
+
+  when(comp(io.in0, io.in1)) {
+    row10 := io.in0            // preserve first two elements
+    row11 := io.in1
+  }.otherwise {
+    row10 := io.in1            // swap first two elements
+    row11 := io.in0
+  }
+
+  when(comp(io.in2, io.in3)) {
+    row12 := io.in2            // preserve last two elements
+    row13 := io.in3
+  }.otherwise {
+    row12 := io.in3            // swap last two elements
+    row13 := io.in2
+  }
+
+  val row21 = Wire(UInt(16.W))
+  val row22 = Wire(UInt(16.W))
+
+  when(comp(row11, row12)) {
+    row21 := row11            // preserve middle 2 elements
+    row22 := row12
+  }.otherwise {
+    row21 := row12            // swap middle two elements
+    row22 := row11
+  }
+
+  val row20 = Wire(UInt(16.W))
+  val row23 = Wire(UInt(16.W))
+  when(comp(row10, row13)) {
+    row20 := row10            // preserve the first and the forth elements
+    row23 := row13
+  }.otherwise {
+    row20 := row13            // swap the first and the forth elements
+    row23 := row10
+  }
+
+  when(comp(row20, row21)) {
+    io.out0 := row20            // preserve first two elements
+    io.out1 := row21
+  }.otherwise {
+    io.out0 := row21            // swap first two elements
+    io.out1 := row20
+  }
+
+  when(comp(row22, row23)) {
+    io.out2 := row22            // preserve first two elements
+    io.out3 := row23
+  }.otherwise {
+    io.out2 := row23            // swap first two elements
+    io.out3 := row22
+  }
+}
+

# Option and Defualt Arguments

val map = Map("a" -> 1)
+val a = map.get("a")
+println(a)
+val b = map.get("b")
+println(b)
+

在Scala中，Map.get(key)方法返回一个Option类型：如果键存在，则返回Some(value)；如果键不存在，则返回**None。在您的例子中，map.get("a")返回Some(1)，因为"a"是映射中的一个键，值为1。然而，map.get("b")返回None，因为"b"不是映射中的键。Some和None**用于Scala中以安全且表达性的方式处理值的存在或缺失，避免空指针异常。

val some = Some(1)
+val none = None
+println(some.get)          // Returns 1
+// println(none.get)       // Errors!
+println(some.getOrElse(2)) // Returns 1
+println(none.getOrElse(2)) // Returns 2
+

getOrElse是一个常用于Option类型的方法，它允许你为Option可能不包含值（即为None）的情况提供一个默认值。getOrElse接受一个参数，这个参数是当Option为None时将返回的值。如果Option是Some，则**getOrElse会返回包裹在Some**中的值。

# Options for Parameters with Defaults

class DelayBy1(resetValue: Option[UInt] = None) extends Module {
+    val io = IO(new Bundle {
+        val in  = Input( UInt(16.W))
+        val out = Output(UInt(16.W))
+    })
+    val reg = if (resetValue.isDefined) { // resetValue = Some(number)
+        RegInit(resetValue.get)
+    } else { //resetValue = None
+        Reg(UInt())
+    }
+    reg := io.in
+    io.out := reg
+}
+
+println(getVerilog(new DelayBy1))
+println(getVerilog(new DelayBy1(Some(3.U))))
+

将 resetValue 默认初始化为 Option[UInt] = None，Reg(UInt()) 可以从上下文中自动推断，不过最好还是指定位宽

// 还可以用match来实现ifelse
+class DelayBy1(resetValue: Option[UInt] = None) extends Module {
+  val io = IO(new Bundle {
+    val in  = Input( UInt(16.W))
+    val out = Output(UInt(16.W))
+  })
+  val reg = resetValue match {
+    case Some(r) => RegInit(r)
+    case None    => Reg(UInt())
+  }
+  reg := io.in
+  io.out := reg
+}
+

# Match/Case Statements

Scala中的匹配概念在Chisel中被广泛使用，是每个Chisel程序员必须理解的基础知识。Scala提供的match操作符支持以下功能：

  • 用于检测多种情况的简单测试，类似于C语言中的switch语句。
  • 对值的复杂组合进行测试。
  • 根据变量的类型采取行动，当变量类型未知或未完全指定时，例如： +
    • 从异构列表中取变量，如**val mixedList = List(1, "string", false)**。
    • 变量已知属于一个超类，但不确定是哪个具体的子类。
  • 使用正则表达式提取字符串的子串。

# Example: Value Matching

// y is an integer variable defined somewhere else in the code
+val y = 7
+/// ...
+val x = y match {
+  case 0 => "zero" // One common syntax, preferred if fits in one line
+  case 1 =>        // Another common syntax, preferred if does not fit in one line.
+      "one"        // Note the code block continues until the next case
+  case 2 => {      // Another syntax, but curly braces are not required
+      "two"
+  }
+  case _ => "many" // _ is a wildcard that matches all values
+}
+println("y is " + x) // out: y is many
+

y 为7，不匹配，因此采用默认值

  • 每个跟在**=>操作符后面的代码块都会继续执行，直到它到达match的结束大括号或下一个case**语句。
  • **match会按照case语句的顺序进行搜索，一旦匹配到一个case语句，就不会再对其他case**语句进行检查。
  • 使用下划线**_**作为通配符，来处理任何未找到匹配的值。

# Example: Multiple Value Matching

def animalType(biggerThanBreadBox: Boolean, meanAsCanBe: Boolean): String = {
+  (biggerThanBreadBox, meanAsCanBe) match {
+    case (true, true) => "wolverine"
+    case (true, false) => "elephant"
+    case (false, true) => "shrew"
+    case (false, false) => "puppy"
+  }
+}
+println(animalType(true, true)) // wolverine
+

# Example: Type Matching

val sequence = Seq("a", 1, 0.0)
+sequence.foreach { x =>
+  x match {
+    case s: String => println(s"$x is a String")
+    case s: Int    => println(s"$x is an Int")
+    case s: Double => println(s"$x is a Double")
+    case _ => println(s"$x is an unknown type!")
+  }
+}
+

Seq是Scala集合中的一个接口，它代表序列，而List是Seq的一个具体实现。在这个例子中，可以直接用List("a", 1, 0.0)来代替Seq("a", 1, 0.0)，而不会影响**foreach和match**语句的行为。

# Example: Multiple Type Matching

If you want to match on whether a value has one of many types, use the following syntax. Note that you must use an _ when matching.

val sequence = Seq("a", 1, 0.0)
+sequence.foreach { x =>
+  x match {
+    case _: Int | _: Double => println(s"$x is a number!")
+    case _ => println(s"$x is an unknown type!")
+  }
+}
+

# Example: Type Matching and Erasure

类型匹配在Scala中有一些限制。由于Scala运行在JVM上，而JVM不保持多态类型信息，因此你不能在运行时基于它们进行匹配（因为这些类型信息已被擦除）。注意下面的例子始终匹配第一个case语句，因为**[String]、[Int]、[Double]这些多态类型在运行时被擦除了，case语句实际上只是在匹配Seq**。

val sequence = Seq(Seq("a"), Seq(1), Seq(0.0))
+sequence.foreach { x =>
+  x match {
+    case s: Seq[String] => println(s"$x is a String")
+    case s: Seq[Int]    => println(s"$x is an Int")
+    case s: Seq[Double] => println(s"$x is a Double")
+  }
+}
+

在Scala中，类型擦除指的是JVM在运行时不保留泛型的具体类型信息。因此，当你对**Seq[String]、Seq[Int]或Seq[Double]进行模式匹配时，JVM实际上无法区分这些Seq的元素类型，因为泛型信息[String]、[Int]、[Double]已经被擦除，只留下了基础的Seq类型。所以，这些case语句在运行时都被视为对Seq类型的匹配，而无法区分具体是哪种Seq。因此，匹配总是成功于第一个case，无论其实际参数是什么类型的Seq。这就是为什么在运行时你看到的行为似乎是它总是匹配Seq**的原因。

# IOs with Optional Fields

有时我们希望IO端口能够根据需要选择性地包含或排除。例如，在调试时可能需要查看一些内部状态，但在生成器用于系统时希望将其隐藏。或者，你的生成器可能有一些输入在某些情况下不需要连接，因为存在合理的默认值。

# Example: Optional IO with Option

示例中展示了一个可选地接收进位信号的一位加法器。如果包含进位，**io.carryIn将是Some[UInt]类型并包含在IO束中；如果不包含进位，io.carryIn将是None**类型并从IO束中排除。

class HalfFullAdder(val hasCarry: Boolean) extends Module {
+  val io = IO(new Bundle {
+    val a = Input(UInt(1.W))
+    val b = Input(UInt(1.W))
+    val carryIn = if (hasCarry) Some(Input(UInt(1.W))) else None
+    val s = Output(UInt(1.W))
+    val carryOut = Output(UInt(1.W))
+  })
+  val sum = io.a +& io.b +& io.carryIn.getOrElse(0.U)
+  io.s := sum(0)
+  io.carryOut := sum(1)
+}
+

# Example: Optional IO with Zero-Width Wires

class HalfFullAdder(val hasCarry: Boolean) extends Module {
+  val io = IO(new Bundle {
+    val a = Input(UInt(1.W))
+    val b = Input(UInt(1.W))
+    val carryIn = Input(if (hasCarry) UInt(1.W) else UInt(0.W))
+    val s = Output(UInt(1.W))
+    val carryOut = Output(UInt(1.W))
+  })
+  val sum = io.a +& io.b +& io.carryIn
+  io.s := sum(0)
+  io.carryOut := sum(1)
+}
+

也可以用一个0宽度的wire来代替None。An IO with width zero is pruned from the emitted Verilog, and anything that tries to use the value of a zero-width wire gets a constant zero.

# Implicits

为了减少大量重复的模板代码，Scala引入了*隐式（implicits）*的概念，允许编译器为你自动进行一些语法简化。由于很多操作是在背后进行，隐式使用可能显得很神奇。

# Implicit Arguments

隐式参数的一个常见用途是当你的代码在深层的函数调用中需要访问某个顶层变量时，可以使用隐式参数自动传递这个变量，而不是手动在每个函数调用中传递它。

# Example: Implicit Cats

object CatDog {
+  implicit val numberOfCats: Int = 3
+  //implicit val numberOfDogs: Int = 5
+
+  def tooManyCats(nDogs: Int)(implicit nCats: Int): Boolean = nCats > nDogs
+    
+  val imp = tooManyCats(2)    // Argument passed implicitly!
+  val exp = tooManyCats(2)(1) // Argument passed explicitly!
+}
+CatDog.imp
+CatDog.exp
+

首先，我们定义了一个隐式值**numberOfCats。在给定的作用域中，同一类型的隐式值只能有一个。然后，我们定义了一个函数，它接受两个参数列表；第一个是任何显式参数，第二个是任何隐式参数。当我们调用tooManyCats**时，我们可以省略第二个隐式参数列表（让编译器为我们找到它），或者显式提供一个参数（这个参数可以与隐式值不同）。

隐式参数可能失败的情况包括：

  • 在一个作用域中定义了给定类型的两个或多个隐式值
  • 如果编译器找不到调用函数所需的隐式值

**object定义了一个单例对象，它是一个类的单一实例。与class不同，当你定义一个object时，Scala会自动为你创建这个类的一个实例。你不需要使用new关键字来创建它的实例。在这个例子中，CatDog是一个单例对象，可以直接访问其成员，无需创建实例。这在定义工具方法或当你需要一个全局唯一的实体时非常有用，比如这里的numberOfCats隐式值和tooManyCats**方法。

# Example: Implicit Logging

sealed trait Verbosity
+implicit case object Silent extends Verbosity
+case object Verbose extends Verbosity
+
+class ParameterizedWidthAdder(in0Width: Int, in1Width: Int, sumWidth: Int)(implicit verbosity: Verbosity)
+extends Module {
+  def log(msg: => String): Unit = verbosity match {
+    case Silent =>
+    case Verbose => println(msg)
+  }
+  require(in0Width >= 0)
+  log(s"in0Width of $in0Width OK")
+  require(in1Width >= 0)
+  log(s"in1Width of $in1Width OK")
+  require(sumWidth >= 0)
+  log(s"sumWidth of $sumWidth OK")
+  val io = IO(new Bundle {
+    val in0 = Input(UInt(in0Width.W))
+    val in1 = Input(UInt(in1Width.W))
+    val sum = Output(UInt(sumWidth.W))
+  })
+  log("Made IO")
+	// 对于结果位宽自然容纳进位的情况，直接使用+也是可行的。
+  io.sum := io.in0 + io.in1
+  log("Assigned output")
+}
+
+println(getVerilog(new ParameterizedWidthAdder(1, 4, 5)))
+println(getVerilog(new ParameterizedWidthAdder(1, 4, 5)(Verbose)))
+
  1. 定义了一个名为**Verbosity的密封特质（sealed trait）和两个实现这个特质的对象。sealed trait Verbosity表示Verbosity是一个可以被继承的类型，但所有继承它的类必须定义在同一个文件中，这有助于实现模式匹配的完整性检查。implicit case object Silent extends Verbosity定义了一个隐式的单例对象Silent，它是Verbosity的一个实现，可以在需要Verbosity类型的隐式参数时自动使用。case object Verbose extends Verbosity定义了另一个名为Verbose的单例对象，也是Verbosity的实现。case object**通常用于代表不可变、无状态的值或单例定义.
  2. msg: => String这样的参数定义使用了名为“call-by-name”的参数传递机制。这种机制意味着，只有在函数内部实际使用到msg时，传入的字符串表达式才会被计算。这对于条件日志记录来说非常有用，因为它允许延迟计算日志消息直到确实需要打印消息时。例如，如果verbosity是Silent，则**msg**根本不会被计算，这样就避免了不必要的性能开销。

# Implicit Conversions

隐式函数（也称为隐式转换）用于减少模板代码。更具体地说，它们用于自动将一个Scala对象转换为另一个对象。

# Example: Implicit Conversion

在下面的例子中，我们有两个类，Animal和Human。Animal有一个species字段，但Human没有。然而，通过实现一个隐式转换，我们可以在Human上调用species方法。这意味着即使Human类原本不包含species字段，通过隐式转换，我们也可以像访问自己的属性一样访问species，就好像这个属性是**Human**类的一部分一样。

class Animal(val name: String, val species: String)
+class Human(val name: String)
+implicit def human2animal(h: Human): Animal = new Animal(h.name, "Homo sapiens")
+val me = new Human("Adam")
+println(me.species)
+

+ ← + + 2024.03.03-3.2 Generators: Collections + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.03.03-3.2 Generators Collections.html b/Chip/Chip/2024.02.21-Chisel/2024.03.03-3.2 Generators Collections.html new file mode 100644 index 0000000..e246810 --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.03.03-3.2 Generators Collections.html @@ -0,0 +1,237 @@ + + + + + + 2024.03.03-3.2 Generators: Collections | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.03.03-3.2 Generators: Collections

# Generators and Collections

# FIR Golden Model

/**
+  * A naive implementation of an FIR filter with an arbitrary number of taps.
+  */
+class ScalaFirFilter(taps: Seq[Int]) {
+  var pseudoRegisters = List.fill(taps.length)(0)
+
+  def poke(value: Int): Int = {
+    pseudoRegisters = value :: pseudoRegisters.take(taps.length - 1)
+    var accumulator = 0
+    for(i <- taps.indices) {
+      accumulator += taps(i) * pseudoRegisters(i)
+    }
+    accumulator
+  }
+}
+

# Seq

当**taps变为Seq[Int]时，意味着类的用户可以在构造类时传递任意长度的Int**序列。

# 寄存器

使用**var pseudoRegisters = List.fill(taps.length)(0)创建了一个List，用于存储前几个周期的值。选择List**是因为其添加元素到头部和移除最后一个元素的语法非常简单。理论上可以使用Scala集合家族中的任何成员。这个列表被初始化为全零。

# Poke

我们的类添加了一个poke函数/方法，模拟将新输入放入过滤器并循环时钟。

# 更新寄存器

**pseudoRegisters = value :: pseudoRegisters.take(taps.length - 1)首先使用列表的take方法保留除最后一个元素外的所有元素，然后使用::列表连接操作符将value**添加到缩减版列表的头部。

# 计算输出

一个简单的for循环和累加器用于求和列表中每个元素与其对应抽头系数的乘积。仅含**accumulator**的行将该值作为函数结果返回。

# Test circuit using the golden model

为了避免使用繁杂的手动验证，这里使用Golden Model来生成期望的值，并与Chisel的结果对比

val goldenModel = new ScalaFirFilter(Seq(1, 1, 1, 1))
+
+test(new My4ElementFir(1, 1, 1, 1)) { c =>
+    for(i <- 0 until 100) {
+        val input = scala.util.Random.nextInt(8)
+
+        val goldenModelResult = goldenModel.poke(input)
+
+        c.io.in.poke(input.U)
+
+        c.io.out.expect(goldenModelResult.U, s"i $i, input $input, gm $goldenModelResult, ${c.io.out.peek().litValue}")
+
+        c.clock.step(1)
+    }
+
+}
+

注意：这里软件上的Golden Model没有考虑位宽，而硬件则与位宽有很大关系。这里只考虑了8以内，即3bit的数，因此不存在这个问题

# Example: Parameterized FIR Generator

class MyManyElementFir(consts: Seq[Int], bitWidth: Int) extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(bitWidth.W))
+    val out = Output(UInt(bitWidth.W))
+  })
+
+  val regs = mutable.ArrayBuffer[UInt]()
+  for(i <- 0 until consts.length) {
+      if(i == 0) regs += io.in
+      else       regs += RegNext(regs(i - 1), 0.U)
+  }
+  
+  val muls = mutable.ArrayBuffer[UInt]()
+  for(i <- 0 until consts.length) {
+      muls += regs(i) * consts(i).U
+  }
+
+  val scan = mutable.ArrayBuffer[UInt]()
+  for(i <- 0 until consts.length) {
+      if(i == 0) scan += muls(i)
+      else scan += muls(i) + scan(i - 1)
+  }
+
+  io.out := scan.last
+}
+
  1. val regs = mutable.ArrayBuffer[UInt]()声明了一个名为regs的不可变变量，它被初始化为一个可变的ArrayBuffer，其中包含**UInt类型的元素。ArrayBuffer是一个可变的序列，允许在序列两端高效地添加或删除元素，适用于需要动态修改元素的场景。在这里，regs可以被用来存储和更新UInt类型的数据，但由于使用了val，regs本身的引用是不可变的，尽管它指向的ArrayBuffer**内容是可变的。
  2. **regs += io.in这行代码的意思是将io.in这个UInt信号添加到regs这个ArrayBuffer中。这里没有直接的数值相加操作，而是将io.in这个元素添加（追加）到regs这个列表的末尾。regs是一个容器，可以逐个添加元素，即使一开始regs是空的。这行代码的作用是初始化regs列表的第一个元素，后续元素则在循环中通过RegNext**添加。
  3. regs作为一个ArrayBuffer，可以包含不同类型的**UInt元素。在这种情况下，io.in是一个Input(UInt)类型，而RegNext(regs(i - 1), 0.U)生成的是一个Reg(UInt)类型。尽管io.in和通过RegNext创建的寄存器在硬件层面扮演不同的角色（一个是输入信号，另一个是寄存器），但它们都是UInt类型，可以存储在同一个ArrayBuffer**中。在Chisel生成的硬件逻辑中，这将创建一个信号和寄存器链，其中信号和寄存器可以互相连接。
  4. 使用**scan数组缓存逐步累加的结果而不是直接对muls求和，是为了展示在每一步如何逐渐累积计算的中间值。这种方法在某些复杂的FIR滤波器设计中可以提供更多的灵活性，比如在需要逐个访问累加过程中的中间结果时。尽管在这个特定例子中，只需要最终的累加结果，直接对muls求和看似更直接，但展开累加过程可以帮助理解和调试滤波器的行为，尤其是在更复杂或参数化的设计中。然而，如果目标只是获取最终的累加和，直接使用muls.reduce(_ + _)**确实会更简洁高效。

# Test a bunch of different sized FIR filters

def r(): Int = {
+  scala.util.Random.nextInt(1024)
+}
+
+/**
+  * run a test comparing software and hardware filters
+  * run for at least twice as many samples as taps
+  */
+def runOneTest(taps: Seq[Int]) {
+    val goldenModel = new ScalaFirFilter(taps)
+
+    test(new MyManyElementFir(taps, 32)) { c =>
+        for(i <- 0 until 2 * taps.length) {
+            val input = r()
+
+            val goldenModelResult = goldenModel.poke(input)
+
+            c.io.in.poke(input.U)
+
+            c.io.out.expect(goldenModelResult.U, s"i $i, input $input, gm $goldenModelResult, ${c.io.out.peek().litValue}")
+
+            c.clock.step(1)
+        }
+    }
+}
+
+for(tapSize <- 2 until 100 by 10) {
+    val taps = Seq.fill(tapSize)(r())  // create a sequence of random coefficients
+
+    runOneTest(taps)
+}
+
  1. 在Chisel测试中，c.clock.step(1)通常放在对输出进行期望检查（expect）之后，因为我们希望在提供输入后推进仿真一个时钟周期，然后在下一个时钟边沿检查输出。这样可以确保寄存器已经更新到了因输入变化而触发的新状态。
  2. 字符串**s"i $i, input $input, gm $goldenModelResult, ${c.io.out.peek().litValue}"是Scala的字符串插值，用于构造包含变量值的字符串。这里它构建了一个描述当前测试状态的字符串，包括迭代次数i，当前输入input，金标准模型goldenModel的结果goldenModelResult，以及从待测试模块的输出c.io.out**中提取的值。这对于调试和理解测试失败的上下文非常有用。

# Hardware Collections

# Example: Add run-time configurable taps to our FIR

在FIR生成器的IO中添加了一个额外的**consts向量，允许在电路生成后从外部改变系数。这是通过Chisel集合类型Vec实现的。Vec支持许多Scala集合方法，但只能包含Chisel硬件元素。仅在普通Scala集合无法满足需求的情况下使用Vec**，主要是以下两种情况：1. 在Bundle中需要元素集合，通常是作为IO使用的Bundle。2. 需要通过硬件部分的索引访问集合（如寄存器文件）。

原因在于**Vec能够创建一组硬件元素的集合，而这些硬件元素可以在生成的硬件电路中被索引和操作。相反，普通的Scala集合，如List或Seq，仅仅在Scala软件环境中存在，它们不能直接映射到硬件电路中。因此，当定义硬件模块的IO接口或需要在硬件级别按索引访问元素时，应该使用Vec**。

class MyManyDynamicElementVecFir(length: Int) extends Module {
+  val io = IO(new Bundle {
+    val in = Input(UInt(8.W))
+    val out = Output(UInt(8.W))
+    val consts = Input(Vec(length, UInt(8.W)))
+  })
+
+  // Reference solution
+  val regs = RegInit(VecInit(Seq.fill(length)(0.U(8.W))))
+  for(i <- 0 until length) {
+      if(i == 0) regs(i) := io.in
+      else       regs(i) := regs(i - 1)
+  }
+  
+  val muls = Wire(Vec(length, UInt(8.W)))
+  for(i <- 0 until length) {
+      if(i == 0) muls(i) := io.in * io.consts(i)
+      else       muls(i) := regs(i - 1) * io.consts(i)
+  }
+
+  val scan = Wire(Vec(length, UInt(8.W)))
+  for(i <- 0 until length) {
+      if(i == 0) scan(i) := muls(i)
+      else scan(i) := muls(i) + scan(i - 1)
+  }
+
+  io.out := scan(length - 1)
+}
+

  1. VecInit用于创建一个Vec，这是Chisel中的一种集合类型，专门用于存储硬件元素。Seq.fill(length - 1)(0.U(8.W))生成一个长度为length - 1，每个元素初始化为8位宽的0的序列。VecInit将这个序列转换成一个Vec，以便在硬件设计中使用。**RegInit则将这个Vec**初始化为寄存器，使得其值在复位时为指定的初始值。这种方式常用于定义具有多个初始相同值的寄存器数组。

  2. Wire(Vec(length, UInt(8.W))) 用于创建一个具有 length 元素的向量，每个元素是 8 位无符号整数。这是在硬件描述语言中创建信号数组的标准方法，允许这些信号在生成的硬件电路中被实例化。

    相比之下，mutable.ArrayBuffer[UInt]() 是 Scala 的一个集合类型，主要用于软件程序中的数据存储和处理。在 Chisel 的上下文中，你不能直接将 ArrayBuffer 用作硬件信号的容器，因为 ArrayBuffer 是一个可变的、仅在 Scala 软件执行环境中存在的数据结构，它不会被合成到硬件中。

    简单来说：

    • Wire(Vec(length, UInt(8.W))) 在 Chisel 中创建一个硬件向量，这个向量可以在生成的硬件电路中存在并携带信号。
    • mutable.ArrayBuffer[UInt]() 创建一个仅在 Scala 软件执行时存在的内存数组，它不能直接用于硬件设计。

    所以，在你的代码中使用 Wire(Vec(length, UInt(8.W))) 是为了定义一个可以在硬件层面操作和传递信号的向量，这对于硬件设计至关重要。

    # Example: 32-bit RISC-V Processor

    Register file: An array of registers that can be read from or written to via a number of read or write ports. Each port consists of an address and data field.

    class RegisterFile(readPorts: Int) extends Module {
+    require(readPorts >= 0)
+    val io = IO(new Bundle {
+        val wen   = Input(Bool())
+        val waddr = Input(UInt(5.W))
+        val wdata = Input(UInt(32.W))
+        val raddr = Input(Vec(readPorts, UInt(5.W)))
+        val rdata = Output(Vec(readPorts, UInt(32.W)))
+    })
+    
+    // A Register of a vector of UInts
+    val reg = RegInit(VecInit(Seq.fill(32)(0.U(32.W))))
+
+    when(io.wen){
+        reg(io.waddr) := io.wdata
+    }
+    for(i <- 0 until readPorts){
+        when(io.raddr(i) === 0.U){
+            io.rdata(i) := 0.U
+        }.otherwise{
+            io.rdata(i) := reg(io.raddr(i))
+        }
+    }
+}
+

    readPorts 表示寄存器文件的读端口数量。这个数量决定了在任何给定的时钟周期内，可以同时读取多少个独立寄存器的数据。每个读端口由其自己的读取地址（raddr）和读取数据（rdata）组成。在这种设置中，你可以在一个时钟周期内并行读取多个寄存器的值，而不是一次只能读取一个，这对于增加处理器的数据吞吐量非常有用。

    具体到代码：

    • readPorts：定义了有多少个并行的读端口可用于同时读取寄存器文件中的数据。
    • io.raddr：一个向量，包含了每个读端口对应的读取地址。每个读端口都可以独立地从寄存器文件中选择一个寄存器进行读取。
    • io.rdata：一个向量，用于输出每个读端口读取到的寄存器值。每个端口根据对应的**raddr读取寄存器文件中的数据，并将其放置在rdata**的相应位置。

+ ← + + 2024.03.04-3.3 Interlude: Chisel Standard Library + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.03.04-3.3 Interlude Chisel Standard Library.html b/Chip/Chip/2024.02.21-Chisel/2024.03.04-3.3 Interlude Chisel Standard Library.html new file mode 100644 index 0000000..dff36d8 --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.03.04-3.3 Interlude Chisel Standard Library.html @@ -0,0 +1,434 @@ + + + + + + 2024.03.04-3.3 Interlude: Chisel Standard Library | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.03.04-3.3 Interlude: Chisel Standard Library

# Decoupled: A Standard Ready-Valid Interface

在 Chisel 中，DecoupledIO 是一种标准的准备就绪（ready-valid）接口，广泛用于不同模块间的数据传输，提供了一种带有流控制的通信机制。使用 DecoupledIO 可以有效地处理数据传输的同步问题，特别是在生产者（source）和消费者（sink）速率不匹配时，确保数据的正确传输与接收。

# 组件

DecoupledIO 接口由以下三个主要部分组成：

  1. valid（有效） - 这是一个输出信号（从数据源角度看），用于表明当前的数据是有效的，可以被读取。当数据源有数据准备好发送时，它会将 valid 信号置为高电平。
  2. ready（准备就绪） - 这是一个输入信号（从数据源角度看），用于表明目标模块（接收端）准备好接收数据。当接收端可以接收新的数据时，它会将 ready 信号置为高电平。
  3. bits（数据位） - 这个信号承载了要传输的实际数据。数据的宽度和类型可以是任意的，从简单的 UInt 或 Bool 到复杂的用户定义 Bundle。

# 数据传输

在 DecoupledIO 接口中，数据传输在以下条件下发生：

  • 数据源设置 valid 为高电平，表示其有数据要发送。
  • 接收端设置 ready 为高电平，表示其准备好接收数据。

当且仅当同一时钟周期内 valid 和 ready 同时为高电平时，数据才会被传输。这允许在接收端或发送端任一端控制数据流，实现背压（backpressure）机制：

  • 如果接收端未准备好接收（ready 为低），即使发送端有数据发送（valid 为高），数据也不会被传输。
  • 如果发送端没有数据要发送（valid 为低），即使接收端准备好了（ready 为高），也不会有数据传输。

# 使用场景

DecoupledIO 非常适用于生产者和消费者速率不一致的情况，如：

  • 在 FIFO 队列的实现中，确保数据不会在缓冲区满时被写入，或在缓冲区空时被读出。
  • 在处理器设计中，用于不同执行单元间的数据传输，确保在数据未准备好或处理单元未准备好时不发生数据传输。

# 代码示例

以下是如何在 Chisel 中创建一个 DecoupledIO 接口的简单示例：

val data = UInt(8.W) // 定义数据宽度
+val decoupledData = Decoupled(data) // 创建 DecoupledIO 接口
+

这里，decoupledData 将是一个拥有 valid、ready 和 bits 字段的 DecoupledIO Bundle，可用于模块间的数据传输。

# Queue

test(new Module {
+    // Example circuit using a Queue
+    val io = IO(new Bundle {
+      val in = Flipped(Decoupled(UInt(8.W)))
+      val out = Decoupled(UInt(8.W))
+    })
+    val queue = Queue(io.in, 2)  // 2-element queue
+    io.out <> queue
+  }) { c =>
+    c.io.out.ready.poke(false.B)
+    c.io.in.valid.poke(true.B)  // Enqueue an element
+    c.io.in.bits.poke(42.U)
+    println(s"Starting:")
+    println(s"\tio.in: ready=${c.io.in.ready.peek().litValue}")
+    println(s"\tio.out: valid=${c.io.out.valid.peek().litValue}, bits=${c.io.out.bits.peek().litValue}")
+    c.clock.step(1)
+
+    c.io.in.valid.poke(true.B)  // Enqueue another element
+    c.io.in.bits.poke(43.U)
+    // What do you think io.out.valid and io.out.bits will be?
+    println(s"After first enqueue:")
+    println(s"\tio.in: ready=${c.io.in.ready.peek().litValue}")
+    println(s"\tio.out: valid=${c.io.out.valid.peek().litValue}, bits=${c.io.out.bits.peek().litValue}")
+    c.clock.step(1)
+
+    c.io.in.valid.poke(true.B)  // Read a element, attempt to enqueue
+    c.io.in.bits.poke(44.U)
+    c.io.out.ready.poke(true.B)
+    // What do you think io.in.ready will be, and will this enqueue succeed, and what will be read?
+    println(s"On first read:")
+    println(s"\tio.in: ready=${c.io.in.ready.peek().litValue}")
+    println(s"\tio.out: valid=${c.io.out.valid.peek().litValue}, bits=${c.io.out.bits.peek().litValue}")
+    c.clock.step(1)
+
+    c.io.in.valid.poke(false.B)  // Read elements out
+    c.io.out.ready.poke(true.B)
+    // What do you think will be read here?
+    println(s"On second read:")
+    println(s"\tio.in: ready=${c.io.in.ready.peek().litValue}")
+    println(s"\tio.out: valid=${c.io.out.valid.peek().litValue}, bits=${c.io.out.bits.peek().litValue}")
+    c.clock.step(1)
+
+    // Will a third read produce anything?
+    println(s"On third read:")
+    println(s"\tio.in: ready=${c.io.in.ready.peek().litValue}")
+    println(s"\tio.out: valid=${c.io.out.valid.peek().litValue}, bits=${c.io.out.bits.peek().litValue}")
+    c.clock.step(1)
+}
+
Starting:
+	io.in: ready=1
+	io.out: valid=0, bits=0
+After first enqueue:
+	io.in: ready=1
+	io.out: valid=1, bits=42
+On first read:
+	io.in: ready=0
+	io.out: valid=1, bits=42
+On second read:
+	io.in: ready=1
+	io.out: valid=1, bits=43
+On third read:
+	io.in: ready=1
+	io.out: valid=0, bits=42
+

  1. **val in = Flipped(Decoupled(UInt(8.W)))** 这里的**Flipped**表示是**Input**，因为**Decoupled**默认是**Output**

  2. **val queue = Queue(io.in, 2)** 连接 io.in 到队列的输入端： 这意味着 io.in 上发生的任何事情（比如信号变化）都会直接影响到队列。具体来说，当您在测试代码中设置 io.in.valid 和 io.in.bits，您实际上是在向队列的入队端提供数据。

  3. io.out <> queue 时，你实际上是在将模块的输出接口 io.out 和队列 queue 的出队接口双向连接。

    具体来说，对于 DecoupledIO 接口：

    • io.out.valid 会连接到 queue.io.deq.valid。
    • io.out.bits 会连接到 queue.io.deq.bits。
    • queue.io.deq.ready 会连接到 io.out.ready。

    这种连接方式确保了数据可以从 queue 的出队端传输到模块的输出 io.out，同时允许 io.out 控制背压（通过 ready 信号）以及 queue 报告其状态（通过 valid 信号）。

  • 开始时：

    • 首先，输出端 io.out.ready 被设为 false，表示消费者还没准备好接收数据。
    • 输入端 io.in.valid 被设为 true，并通过 io.in.bits 提供了值 42，尝试将其入队。
    • 打印的输出显示，初始时，io.in.ready 应该为 true（队列未满，可以接收数据），而 io.out.valid 应该为 false（数据尚未出队到输出端）。

  • 首次入队后：

    • 程序尝试将另一个值 43 入队，并再次检查状态。
    • 由于队列不满，第二个值应该成功入队。io.in.ready 仍然为 true，表明还可以接收更多数据。
    • io.out.valid 被设置为 true 并且 io.out.bits 被更新为 42，因为队列内部确实有一个元素（42）准备好了并且尝试发送。即使 io.out.ready 是 false，io.out.valid 和 io.out.bits 仍然会反映队列出口处的数据状态。
    • 尽管 io.out.valid 为 true 并且 io.out.bits 显示了数据（42），但由于 io.out.ready 为 false，这次数据传输并不会真正完成。换句话说，42 在逻辑上是"准备发送"的，但由于缺乏接收准备就绪的确认（即 io.out.ready 为 false），它实际上并没有"被接收"。

  • 首次读取尝试：

    • 程序尝试同时进行读取（将 io.out.ready 设为 true）和入队（值 44）。
    • 由于此时输出准备好接收数据，第一个入队的值（42）应该会被传递到 io.out，io.out.valid 应变为 true，io.out.bits 应显示 42。
    • io.in.ready 为 0。这是因为队列（queue）此时已经满了。

  • 第二次读取：

    • 这时不再有新数据入队，但 io.out 准备好读取数据。
    • 应该能读取到之前入队的第二个值 43，io.out.valid 应为 true，io.out.bits 应显示 43。

  • 第三次读取尝试：

    • 在这一步，尽管 io.out 依然准备好接收数据，但队列应该已经空了。
    • 因此，io.out.valid 应该变回 false，表示没有更多数据可读。
    • 不过为什么是42？

    注：

    1. peek() 函数用于查看信号的当前值，而 .litValue 用于获取这个值作为一个 Scala 的字面量（literal）。因此，c.io.in.ready.peek().litValue 表示查看 c.io.in.ready 信号的当前值，并获取其字面量值。
    2. 必须要**c.clock.step(1)**以后才会有输出

# Arbiter

一个 Arbiter 是用于解决多个请求源争用单一资源的组件。它的基本功能是在多个输入信号中选择一个进行输出，基于某种特定的优先级或策略。在处理多个并发请求访问同一资源（例如，总线或共享内存）时，仲裁器确保每个时刻只有一个选定的请求被服务，同时遵循公平性或优先级规则，避免资源冲突或死锁。

  1. Arbiter：这是一个静态优先级仲裁器，它总是优先选择索引较低的生产者。如果有多个请求同时到达，Arbiter 会根据请求信号的索引顺序来决定优先权，索引较小的请求者会获得优先服务。这意味着如果较低索引的请求者持续有请求，它将持续获得资源，而更高索引的请求者则需要等待。

    示例代码如下：

    test(new Module {
+    // Example circuit using a priority arbiter
+    val io = IO(new Bundle {
+      val in = Flipped(Vec(2, Decoupled(UInt(8.W))))
+      val out = Decoupled(UInt(8.W))
+    })
+    // Arbiter doesn't have a convenience constructor, so it's built like any Module
+    val arbiter = Module(new Arbiter(UInt(8.W), 2))  // 2 to 1 Priority Arbiter
+    arbiter.io.in <> io.in
+    io.out <> arbiter.io.out
+  }) { c =>
+    c.io.in(0).valid.poke(false.B)
+    c.io.in(1).valid.poke(false.B)
+    c.io.out.ready.poke(false.B)
+    println(s"Start:")
+    println(s"\tin(0).ready=${c.io.in(0).ready.peek().litValue}, in(1).ready=${c.io.in(1).ready.peek().litValue}")
+    println(s"\tout.valid=${c.io.out.valid.peek().litValue}, out.bits=${c.io.out.bits.peek().litValue}")
+    c.io.in(1).valid.poke(true.B)  // Valid input 1
+    c.io.in(1).bits.poke(42.U)
+    c.io.out.ready.poke(true.B)
+    // What do you think the output will be?
+    println(s"valid input 1:")
+    println(s"\tin(0).ready=${c.io.in(0).ready.peek().litValue}, in(1).ready=${c.io.in(1).ready.peek().litValue}")
+    println(s"\tout.valid=${c.io.out.valid.peek().litValue}, out.bits=${c.io.out.bits.peek().litValue}")
+    c.io.in(0).valid.poke(true.B)  // Valid inputs 0 and 1
+    c.io.in(0).bits.poke(43.U)
+    // What do you think the output will be? Which inputs will be ready?
+    println(s"valid inputs 0 and 1:")
+    println(s"\tin(0).ready=${c.io.in(0).ready.peek().litValue}, in(1).ready=${c.io.in(1).ready.peek().litValue}")
+    println(s"\tout.valid=${c.io.out.valid.peek().litValue}, out.bits=${c.io.out.bits.peek().litValue}")
+    c.io.in(1).valid.poke(false.B)  // Valid input 0
+    // What do you think the output will be?
+    println(s"valid input 0:")
+    println(s"\tin(0).ready=${c.io.in(0).ready.peek().litValue}, in(1).ready=${c.io.in(1).ready.peek().litValue}")
+    println(s"\tout.valid=${c.io.out.valid.peek().litValue}, out.bits=${c.io.out.bits.peek().litValue}")
+}
+
    Start:
+  in(0).ready=0, in(1).ready=0
+  out.valid=0, out.bits=0
+valid input 1:
+  in(0).ready=1, in(1).ready=1
+  out.valid=1, out.bits=42
+valid inputs 0 and 1:
+  in(0).ready=1, in(1).ready=0
+  out.valid=1, out.bits=43
+valid input 0:
+  in(0).ready=1, in(1).ready=0
+  out.valid=1, out.bits=43
+

    1. 初始状态检查:

      • 首先，测试确认在没有任何有效输入 (io.in(0).valid 和 io.in(1).valid 都为 false) 时，输出 (io.out.valid) 也应为 false，表示没有数据通过仲裁器。

    2. 激活第二个输入:

      • 然后，测试激活 io.in(1)（即索引为 1 的输入），同时保持 io.out.ready 为 true，这模拟了接收端准备好接收数据的情况。预期 io.in(1) 的数据应该通过到 io.out。

      • 两个输入的 ready 信号都是 1。这是因为 Arbiter 的行为是基于它可以传递数据的能力。让我们分解这个情况：

        当只有 io.in(1) 有效时：

        • in(0).ready=1：这意味着 Arbiter 仲裁器准备好从 io.in(0) 接收数据，尽管此时 io.in(0) 没有数据（不是有效的）。ready 信号为 1 表示如果 io.in(0) 有数据，Arbiter 准备好接收它。
        • in(1).ready=1：同时，Arbiter 也表示准备好接收 io.in(1) 的数据，因为它是有效的。在这种情况下，由于 io.out.ready 被设置为 true，Arbiter 知道输出端已经准备好接收数据，所以它将 io.in(1) 的 ready 也置为 1。

      这里的关键是 ready 信号表示的是接收能力而非当前的数据有效性。即使 io.in(0) 当前没有标记为有效，Arbiter 也表明它准备好从该输入接收数据，这就是为什么在 io.in(1) 有效时，io.in(0).ready 也会是 1。

    3. 同时激活两个输入:

      • 接下来，测试同时激活两个输入，即 io.in(0) 和 io.in(1) 都设置为有效。由于 Arbiter 的静态优先级策略，预期 io.in(0) 的数据（即优先级更高的输入）会被传递到 io.out。
      • 当两个输入 io.in(0) 和 io.in(1) 都被设置为有效时，Arbiter 会根据其内部逻辑来选择一个输入。对于普通的 Arbiter，它将优先选择索引较低的输入，即 io.in(0)。
      • 由于 io.in(0) 被选中，io.in(1) 的 ready 信号将会被置为 false，而 io.in(0).ready 会是 true，表示 Arbiter 准备接受 io.in(0) 的数据。
      • 在此情况下，即使您设置了 io.in(1).bits，这个数据也不会被 Arbiter 选择，因为 io.in(0) 有更高的优先级。

    4. 只激活第一个输入:

      • 最后，测试只激活 io.in(0)。即使之前 io.in(1) 被激活过，在这一步中只有 io.in(0) 有效，所以只有它的数据应该被传递到 io.out。

  2. RRArbiter：这是一个循环（round-robin）仲裁器，它按照循环的顺序为请求者提供服务，确保了长期的公平性。当一个请求被服务后，RRArbiter 会记住最后被服务的请求，并在下一个服务周期中优先考虑下一个请求者。这样可以确保即使在高负载下，所有请求者也能获得均等的服务机会。

    示例代码如下：

    val rrArbiter = Module(new RRArbiter(UInt(8.W), 2))
+rrArbiter.io.in(0) <> producer0
+rrArbiter.io.in(1) <> producer1
+consumer <> rrArbiter.io.out
+

注：Ariter 是组合电路，不需要step(1)

# Misc Function Blocks

# Bitwise Utilities

# PopCount

PopCount returns the number of high (1) bits in the input as a **UInt**.

test(new Module {
+    // Example circuit using PopCount
+    val io = IO(new Bundle {
+      val in = Input(UInt(8.W))
+      val out = Output(UInt(8.W))
+    })
+    io.out := PopCount(io.in)
+  }) { c =>
+    // Integer.parseInt is used create an Integer from a binary specification
+    c.io.in.poke(**Integer.parseInt**("00000000", 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=${c.io.out.peek().litValue}")
+
+    c.io.in.poke(Integer.parseInt("00001111", 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=${c.io.out.peek().litValue}")
+
+    c.io.in.poke(Integer.parseInt("11001010", 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=${c.io.out.peek().litValue}")
+
+    c.io.in.poke(Integer.parseInt("11111111", 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=${c.io.out.peek().litValue}")
+
+}
+
in=0b0, out=0
+in=0b1111, out=4
+in=0b11001010, out=4
+in=0b11111111, out=8
+

# Reverse

Reverse returns the bit-reversed input

test(new Module {
+    // Example circuit using Reverse
+    val io = IO(new Bundle {
+      val in = Input(UInt(8.W))
+      val out = Output(UInt(8.W))
+    })
+    io.out := Reverse(io.in)
+  }) { c =>
+    // Integer.parseInt is used create an Integer from a binary specification
+    c.io.in.poke(Integer.parseInt("01010101", 2).U)
+    println(s"in=0b${**c.io.in.peek().litValue.toInt.toBinaryString**}, out=0b${c.io.out.peek().litValue.toInt.toBinaryString}")
+
+    c.io.in.poke(Integer.parseInt("00001111", 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=0b${c.io.out.peek().litValue.toInt.toBinaryString}")
+
+    c.io.in.poke(Integer.parseInt("11110000", 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=0b${c.io.out.peek().litValue.toInt.toBinaryString}")
+
+    c.io.in.poke(Integer.parseInt("11001010", 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=0b${c.io.out.peek().litValue.toInt.toBinaryString}")
+}
+
in=0b1010101, out=0b10101010
+in=0b1111, out=0b11110000
+in=0b11110000, out=0b1111
+in=0b11001010, out=0b1010011
+

# OneHot encoding utilities

# UIntToOH

UInt to OneHot

test(new Module {
+    // Example circuit using UIntToOH
+    val io = IO(new Bundle {
+      val in = Input(UInt(4.W))
+      val out = Output(UInt(16.W))
+    })
+    io.out := UIntToOH(io.in)
+  }) { c =>
+    c.io.in.poke(0.U)
+    println(s"in=${c.io.in.peek().litValue}, out=0b${c.io.out.peek().litValue.toInt.toBinaryString}")
+
+    c.io.in.poke(1.U)
+    println(s"in=${c.io.in.peek().litValue}, out=0b${c.io.out.peek().litValue.toInt.toBinaryString}")
+
+    c.io.in.poke(8.U)
+    println(s"in=${c.io.in.peek().litValue}, out=0b${c.io.out.peek().litValue.toInt.toBinaryString}")
+
+    c.io.in.poke(15.U)
+    println(s"in=${c.io.in.peek().litValue}, out=0b${c.io.out.peek().litValue.toInt.toBinaryString}")
+}
+
+in=0, out=0b1
+in=1, out=0b10
+in=8, out=0b100000000
+in=15, out=0b1000000000000000
+

# OHToUInt

OneHot to UInt

test(new Module {
+    // Example circuit using OHToUInt
+    val io = IO(new Bundle {
+      val in = Input(UInt(16.W))
+      val out = Output(UInt(4.W))
+    })
+    io.out := OHToUInt(io.in)
+}) { c =>
+    c.io.in.poke(Integer.parseInt("0000 0000 0000 0001".replace(" ", ""), 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=${c.io.out.peek().litValue}")
+
+    c.io.in.poke(Integer.parseInt("0000 0000 1000 0000".replace(" ", ""), 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=${c.io.out.peek().litValue}")
+
+    c.io.in.poke(Integer.parseInt("1000 0000 0000 0001".replace(" ", ""), 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=${c.io.out.peek().litValue}")
+
+    // Some invalid inputs:
+    // None high
+    c.io.in.poke(Integer.parseInt("0000 0000 0000 0000".replace(" ", ""), 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=${c.io.out.peek().litValue}")
+
+    // Multiple high
+    c.io.in.poke(Integer.parseInt("0001 0100 0010 0000".replace(" ", ""), 2).U)
+    println(s"in=0b${c.io.in.peek().litValue.toInt.toBinaryString}, out=${c.io.out.peek().litValue}")
+}
+
+in=0b1, out=0
+in=0b10000000, out=7
+in=0b1000000000000001, out=15
+in=0b0, out=0
+in=0b1010000100000, out=15
+

# MUX

# **PriorityMux**

Outputs the value associated with the lowest-index asserted select signal.

test(new Module {
+    // Example circuit using PriorityMux
+    val io = IO(new Bundle {
+      val in_sels = Input(Vec(2, Bool()))
+      val in_bits = Input(Vec(2, UInt(8.W)))
+      val out = Output(UInt(8.W))
+    })
+    io.out := PriorityMux(io.in_sels, io.in_bits)
+  }) { c =>
+    c.io.in_bits(0).poke(10.U)
+    c.io.in_bits(1).poke(20.U)
+
+    // Select higher index only
+    c.io.in_sels(0).poke(false.B)
+    c.io.in_sels(1).poke(true.B)
+    println(s"in_sels=${c.io.in_sels(0).peek().litValue}, out=${c.io.out.peek().litValue}")
+
+    // Select both - arbitration needed
+    c.io.in_sels(0).poke(true.B)
+    c.io.in_sels(1).poke(true.B)
+    println(s"in_sels=${c.io.in_sels(0).peek().litValue}, out=${c.io.out.peek().litValue}")
+
+    // Select lower index only
+    c.io.in_sels(0).poke(true.B)
+    c.io.in_sels(1).poke(false.B)
+    println(s"in_sels=${c.io.in_sels(0).peek().litValue}, out=${c.io.out.peek().litValue}")
+}
+
+in_sels=0, out=20
+in_sels=1, out=10
+in_sels=1, out=10
+

PriorityMux 会根据 in_sels 中的布尔值，从左到右（即从索引 0 开始）检查哪个输入是选中的，并输出第一个选中输入对应的 in_bits 值。因此，同时使 in_sels(0) 和 in_sels(1) 为 true 时，由于 in_sels(0) 的优先级更高，io.out 应该输出 in_bits(0) 的值，即 10.U。

# OneHot Mux: **Mux1H**

An **Mux1H** provides an efficient implementation when it is guaranteed that exactly one of the select signals will be high. Behavior is undefined if the assumption is not true.

test(new Module {
+    // Example circuit using Mux1H
+    val io = IO(new Bundle {
+      val in_sels = Input(Vec(2, Bool()))
+      val in_bits = Input(Vec(2, UInt(8.W)))
+      val out = Output(UInt(8.W))
+    })
+    io.out := Mux1H(io.in_sels, io.in_bits)
+  }) { c =>
+    c.io.in_bits(0).poke(10.U)
+    c.io.in_bits(1).poke(20.U)
+
+    // Select index 1
+    c.io.in_sels(0).poke(false.B)
+    c.io.in_sels(1).poke(true.B)
+    println(s"in_sels=${c.io.in_sels(0).peek().litValue}, out=${c.io.out.peek().litValue}")
+
+    // Select index 0
+    c.io.in_sels(0).poke(true.B)
+    c.io.in_sels(1).poke(false.B)
+    println(s"in_sels=${c.io.in_sels(0).peek().litValue}, out=${c.io.out.peek().litValue}")
+
+    // Select none (invalid)
+    c.io.in_sels(0).poke(false.B)
+    c.io.in_sels(1).poke(false.B)
+    println(s"in_sels=${c.io.in_sels(0).peek().litValue}, out=${c.io.out.peek().litValue}")
+
+    // Select both (invalid)
+    c.io.in_sels(0).poke(true.B)
+    c.io.in_sels(1).poke(true.B)
+    println(s"in_sels=${c.io.in_sels(0).peek().litValue}, out=${c.io.out.peek().litValue}")
+}
+
+in_sels=0, out=20
+in_sels=1, out=10
+in_sels=0, out=0
+in_sels=1, out=30
+

# **Counter**

A counter that can be incremented once every cycle, up to some specified limit, at which point it overflows. Note that it is not a Module, and its value is accessible.

test(new Module {
+  // Example circuit with two counters
+  val io = IO(new Bundle {
+    val count = Input(Bool())
+    val out = Output(UInt(2.W))
+    val totalCycles = Output(UInt(32.W))  // Assuming 32-bit is enough for cycle count
+  })
+
+  // Counter for controlled increments
+  val controlledCounter = Counter(3)  // 3-count Counter (outputs range [0...2])
+  when(io.count) {
+    controlledCounter.inc()
+  }
+  io.out := controlledCounter.value
+
+  // Counter for total cycles, counting up to (2^32)-1
+  val totalCycleCounter = Counter(math.pow(2, 32).toInt)
+  totalCycleCounter.inc()  // Increment every cycle
+  io.totalCycles := totalCycleCounter.value
+}) { c =>
+  c.io.count.poke(true.B)
+  println(s"start: controlled counter value=${c.io.out.peek().litValue}, total cycles=${c.io.totalCycles.peek().litValue}")
+
+  c.clock.step(1)
+  println(s"step 1: controlled counter value=${c.io.out.peek().litValue}, total cycles=${c.io.totalCycles.peek().litValue}")
+
+  c.clock.step(1)
+  println(s"step 2: controlled counter value=${c.io.out.peek().litValue}, total cycles=${c.io.totalCycles.peek().litValue}")
+
+  c.io.count.poke(false.B)
+  c.clock.step(1)
+  println(s"step without increment: controlled counter value=${c.io.out.peek().litValue}, total cycles=${c.io.totalCycles.peek().litValue}")
+
+  c.io.count.poke(true.B)
+  c.clock.step(1)
+  println(s"step again: controlled counter value=${c.io.out.peek().litValue}, total cycles=${c.io.totalCycles.peek().litValue}")
+}
+
+start: controlled counter value=0, total cycles=0
+step 1: controlled counter value=1, total cycles=1
+step 2: controlled counter value=2, total cycles=2
+step without increment: controlled counter value=2, total cycles=3
+step again: controlled counter value=0, total cycles=4
+

在 Chisel 中创建一个计数器时，如果您传递的参数是 n，那么计数器能够表示的计数范围是从0到 n-1。所以，当您使用 Counter(n) 时，计数器的实际最大计数值是 n-1。

+ ← + + 2024.03.05-3.4 Higher-Order Functions + + → +

+ + + diff --git a/Chip/Chip/2024.02.21-Chisel/2024.03.05-3.4 Higher-Order Functions.html b/Chip/Chip/2024.02.21-Chisel/2024.03.05-3.4 Higher-Order Functions.html new file mode 100644 index 0000000..6862efc --- /dev/null +++ b/Chip/Chip/2024.02.21-Chisel/2024.03.05-3.4 Higher-Order Functions.html @@ -0,0 +1,161 @@ + + + + + + 2024.03.05-3.4 Higher-Order Functions | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.03.05-3.4 Higher-Order Functions

# A Tale of Two FIRs

From the last module, we had the convolution part of the FIR filter written like this:

val muls = Wire(Vec(length, UInt(8.W)))
+for(i <- 0 until length) {
+  if(i == 0) muls(i) := io.in * io.consts(i)
+  else       muls(i) := regs(i - 1) * io.consts(i)
+}
+
+val scan = Wire(Vec(length, UInt(8.W)))
+for(i <- 0 until length) {
+  if(i == 0) scan(i) := muls(i)
+  else scan(i) := muls(i) + scan(i - 1)
+}
+
+io.out := scan(length - 1)
+

As a recap, the idea is to multiply each element of **io.in** with the corresponding element of **io.consts**, and store it in **muls**. Then, the elements in **muls** are accumulated into **scan**, with **scan(0) = muls(0)**, **scan(1) = scan(0) + muls(1) = muls(0) + muls(1)**, and in general **scan(n) = scan(n-1) + muls(n) = muls(0) + ... + muls(n-1) + muls(n)**. The last element in **scan** (equal to the sum of all **muls**) is assigned to **io.out**.

However, it's very verbose for what might be considered quite a simple operation. In fact, all that could be written in one line:

io.out := (taps zip io.consts).map { case (a, b) => a * b }.reduce(_ + _)
+
  • 假设 taps 是所有样本的列表，其中 taps(0) = io.in，taps(1) = regs(0) 等等。
  • (taps zip io.consts) 将两个列表 taps 和 io.consts 合并成一个列表，其中每个元素是一个元组，这个元组包含了在相应位置的输入元素。具体来说，它的值将是 [(taps(0), io.consts(0)), (taps(1), io.consts(1)), ..., (taps(n), io.consts(n))]。记住，在 Scala 中点号是可选的，所以这等同于 (taps.zip(io.consts))。
  • .map { case (a, b) => a * b } 对列表中的元素应用一个匿名函数（接收两个元素的元组并返回它们的乘积），并返回结果。在这个情况下，结果等价于在冗长示例中的 muls，其值为 [taps(0) * io.consts(0), taps(1) * io.consts(1), ..., taps(n) * io.consts(n)]。
  • 最后，.reduce(_ + _) 同样应用一个函数（元素的加法）到列表的元素上。然而，它接收两个参数：第一个是当前的累加值，第二个是列表元素（在第一次迭代中，它只是将前两个元素相加）。这些由括号中的两个下划线表示。那么结果，假设是从左到右的遍历，将会是 (((muls(0) + muls(1)) + muls(2)) + ...) + muls(n)，更深层次括号内的结果先被计算。这就是卷积的输出结果。

# Functions as Arguments

Formally, functions like **map** and **reduce** are called higher-order functions : they are functions that take functions as arguments. As it turns out (and hopefully, as you can see from the above example), these are very powerful constructs that encapsulate a general computational pattern, allowing you to concentrate on the application logic instead of flow control, and resulting in very concise code.

  • 对于每个参数只引用一次的函数，您可以使用下划线（_）来引用每个参数。在上面的例子中，reduce 函数接受两个参数，可以被指定为 _ + _。虽然这很方便，但它受制于一组额外的复杂规则，所以如果不起作用，您可以尝试：
  • 明确指定输入参数列表。reduce 可以被明确写成 (a, b) => a + b，通用形式是把参数列表放在括号里，后面跟着 =>，然后是引用这些参数的函数体。
  • 当需要解包元组时，使用 case 语句，如 case (a, b) => a * b。这接收一个参数，一个两个元素的元组，并将其解包到变量 a 和 b 中，然后可以在函数体中使用它们。

# Practice in Scala

Scala 集合 API 中的主要类，如**List**。这些高阶函数是这些 API 的一部分。实际上，上面的示例使用了**List**上的**map**和**reduce** API。在这一节中，我们将通过示例和练习熟悉这些方法。在这些示例中，我们将对 Scala 数字（**Int**）操作，以简化和明确表示，但因为 Chisel 运算符的行为类似，所以这些概念应该是通用的。

# Example: map

List[A].map 有类型签名 map[B](f: (A) ⇒ B): List[B]。现在，将类型 A 和 B 视为 Int 或 UInt，意味着它们可以是软件或硬件类型。它接受一个类型为 (f: (A) ⇒ B) 的参数，或者一个接受类型为 A（与输入列表的元素类型相同）的一个参数并返回类型为 B 的值的函数。map 然后返回一个新的类型为 B（参数函数的返回类型）的列表。

println(List(1, 2, 3, 4).map(x => x + 1))  // explicit argument list in function
+println(List(1, 2, 3, 4).map(_ + 1))  // equivalent to the above, but implicit arguments
+println(List(1, 2, 3, 4).map(_.toString + "a"))  // the output element type can be different from the input element type
+
+println(List((1, 5), (2, 6), (3, 7), (4, 8)).map { case (x, y) => x*y })  // this unpacks a tuple, note use of curly braces
+
+// Related: Scala has a syntax for constructing lists of sequential numbers
+println(0 to 10)  // to is inclusive , the end point is part of the result
+println(0 until 10)  // until is exclusive at the end, the end point is not part of the result
+
+// Those largely behave like lists, and can be useful for generating indices:
+val myList = List("a", "b", "c", "d")
+println((0 until 4).map(myList(_)))
+
+// output:
+List(2, 3, 4, 5)
+List(2, 3, 4, 5)
+List(1a, 2a, 3a, 4a)
+List(5, 12, 21, 32)
+Range 0 to 10
+Range 0 until 10
+Vector(a, b, c, d)
+

# Example: **zipWithIndex**

**List.zipWithIndex** has type signature **zipWithIndex: List[(A, Int)]**. It takes no arguments, but returns a list where each element is a tuple of the original elements, and the index (with the first one being zero). So **List("a", "b", "c", "d").zipWithIndex** would return **List(("a", 0), ("b", 1), ("c", 2), ("d", 3))**

println(List(1, 2, 3, 4).zipWithIndex)  // note indices start at zero
+println(List("a", "b", "c", "d").zipWithIndex)
+println(List(("a", "b"), ("c", "d"), ("e", "f"), ("g", "h")).zipWithIndex)  // tuples nest
+
+// output:
+List((1,0), (2,1), (3,2), (4,3))
+List((a,0), (b,1), (c,2), (d,3))
+List(((a,b),0), ((c,d),1), ((e,f),2), ((g,h),3))
+

# Example: **reduce**

List[A].map has type signature similar to reduce(op: (A, A) ⇒ A): A. (it's actually more lenient, A only has to be a supertype of the List type, but we're not going to deal with that syntax here)

println(List(1, 2, 3, 4).reduce((a, b) => a + b))  // returns the sum of all the elements
+println(List(1, 2, 3, 4).reduce(_ * _))  // returns the product of all the elements
+println(List(1, 2, 3, 4).map(_ + 1).reduce(_ + _))  // you can chain reduce onto the result of a map
+println(List(1, 2, 3, 4).map(_*2).reduce(_*_))  // returns the product of the double of the elements of the input list.
+
+// output:
+10
+24
+14
+384
+
+// Important note: reduce will fail with an empty list
+println(List[Int]().reduce(_ * _))
+

# Example: **fold**

**List[A].fold** is very similar to reduce, except that you can specify the initial accumulation value. It has type signature similar to **fold(z: A)(op: (A, A) ⇒ A): A**. (like **reduce**, the type of **A** is also more lenient). Notably, it takes two argument lists, the first (**z**) is the initial value, and the second is the accumulation function. Unlike **reduce**, it will not fail with an empty list, instead returning the initial value directly.

println(List(1, 2, 3, 4).fold(0)(_ + _))  // equivalent to the sum using reduce
+println(List(1, 2, 3, 4).fold(1)(_ + _))  // like above, but accumulation starts at 1
+println(List().fold(1)(_ + _))  // unlike reduce, does not fail on an empty input
+println(List(1, 2, 3, 4).fold(2)(_*_))  // returns the double the product of the elements of the input list
+
+// output:
+10
+11
+1
+48
+

+ ← +

+ + + diff --git "a/Chip/Chip/\344\270\200\347\224\237\344\270\200\350\212\257\350\256\241\345\210\222.html" "b/Chip/Chip/\344\270\200\347\224\237\344\270\200\350\212\257\350\256\241\345\210\222.html" new file mode 100644 index 0000000..547aaf9 --- /dev/null +++ "b/Chip/Chip/\344\270\200\347\224\237\344\270\200\350\212\257\350\256\241\345\210\222.html" @@ -0,0 +1,94 @@ + + + + + + 一生一芯计划 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 一生一芯计划

预学习阶段

+ ← +

+ + + diff --git "a/Chip/Chip/\344\270\200\347\224\237\344\270\200\350\212\257\350\256\241\345\210\222/\351\242\204\345\255\246\344\271\240\351\230\266\346\256\265.html" "b/Chip/Chip/\344\270\200\347\224\237\344\270\200\350\212\257\350\256\241\345\210\222/\351\242\204\345\255\246\344\271\240\351\230\266\346\256\265.html" new file mode 100644 index 0000000..898643a --- /dev/null +++ "b/Chip/Chip/\344\270\200\347\224\237\344\270\200\350\212\257\350\256\241\345\210\222/\351\242\204\345\255\246\344\271\240\351\230\266\346\256\265.html" @@ -0,0 +1,90 @@ + + + + + + 预学习阶段 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 预学习阶段

+ + + diff --git a/Chip/index.html b/Chip/index.html new file mode 100644 index 0000000..a97665f --- /dev/null +++ b/Chip/index.html @@ -0,0 +1,90 @@ + + + + + + SoC Design | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# SoC Design

# 一生一芯计划

# 2023.11.07-Verilog语法

# 2024.02.21-Chisel

+ + + diff --git "a/LeetCode/LeetCode/2024 02 22-752 \346\211\223\345\274\200\350\275\254\347\233\230\351\224\201\357\274\210BFS\357\274\211 abab666d7cbf48d2b1656f11166d33f2.html" "b/LeetCode/LeetCode/2024 02 22-752 \346\211\223\345\274\200\350\275\254\347\233\230\351\224\201\357\274\210BFS\357\274\211 abab666d7cbf48d2b1656f11166d33f2.html" new file mode 100644 index 0000000..64d7ded --- /dev/null +++ "b/LeetCode/LeetCode/2024 02 22-752 \346\211\223\345\274\200\350\275\254\347\233\230\351\224\201\357\274\210BFS\357\274\211 abab666d7cbf48d2b1656f11166d33f2.html" @@ -0,0 +1,270 @@ + + + + + + 2024.02.22-752.打开转盘锁（BFS） | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.02.22-752.打开转盘锁（BFS）

/*
+ * @lc app=leetcode.cn id=752 lang=cpp
+ *
+ * [752] 打开转盘锁
+ *
+ * https://leetcode.cn/problems/open-the-lock/description/
+ *
+ * algorithms
+ * Medium (52.77%)
+ * Likes:    653
+ * Dislikes: 0
+ * Total Accepted:    128.3K
+ * Total Submissions: 243.1K
+ * Testcase Example:  '["0201","0101","0102","1212","2002"]\n"0202"'
+ *
+ * 你有一个带有四个圆形拨轮的转盘锁。每个拨轮都有10个数字： '0', '1', '2', '3', '4', '5', '6', '7', '8',
+ * '9' 。每个拨轮可以自由旋转：例如把 '9' 变为 '0'，'0' 变为 '9' 。每次旋转都只能旋转一个拨轮的一位数字。
+ *
+ * 锁的初始数字为 '0000' ，一个代表四个拨轮的数字的字符串。
+ *
+ * 列表 deadends 包含了一组死亡数字，一旦拨轮的数字和列表里的任何一个元素相同，这个锁将会被永久锁定，无法再被旋转。
+ *
+ * 字符串 target 代表可以解锁的数字，你需要给出解锁需要的最小旋转次数，如果无论如何不能解锁，返回 -1 。
+ *
+ *
+ *
+ * 示例 1:
+ *
+ *
+ * 输入：deadends = ["0201","0101","0102","1212","2002"], target = "0202"
+ * 输出：6
+ * 解释：
+ * 可能的移动序列为 "0000" -> "1000" -> "1100" -> "1200" -> "1201" -> "1202" -> "0202"。
+ * 注意 "0000" -> "0001" -> "0002" -> "0102" -> "0202" 这样的序列是不能解锁的，
+ * 因为当拨动到 "0102" 时这个锁就会被锁定。
+ *
+ *
+ * 示例 2:
+ *
+ *
+ * 输入: deadends = ["8888"], target = "0009"
+ * 输出：1
+ * 解释：把最后一位反向旋转一次即可 "0000" -> "0009"。
+ *
+ *
+ * 示例 3:
+ *
+ *
+ * 输入: deadends = ["8887","8889","8878","8898","8788","8988","7888","9888"],
+ * target = "8888"
+ * 输出：-1
+ * 解释：无法旋转到目标数字且不被锁定。
+ *
+ *
+ *
+ *
+ * 提示：
+ *
+ *
+ * 1 <= deadends.length <= 500
+ * deadends[i].length == 4
+ * target.length == 4
+ * target 不在 deadends 之中
+ * target 和 deadends[i] 仅由若干位数字组成
+ *
+ *
+ */
+
class Solution
+{
+public:
+    int openLock(vector<string> &deadends, string target)
+    {
+        int num = 0;
+        queue<string> q;
+        set<string> visited(deadends.begin(), deadends.end());
+        if (visited.find("0000") != visited.end())
+            return -1;
+        q.push("0000");
+        visited.insert("0000");
+        while (!q.empty())
+        {
+            int ssize = q.size();
+            for (int i = 0; i < ssize; i++)
+            {
+                string str = q.front();
+                q.pop();
+                // if (visited.find(str) != visited.end())
+                //     continue;
+                if (str == target)
+                    return num;
+                for (int j = 0; j < 4; j++)
+                {
+                    string up = turnUp(str, j);
+                    string down = turnDown(str, j);
+                    if (visited.find(up) == visited.end())
+                    {
+                        q.push(up);
+                        visited.insert(up);
+                    }
+                    if (visited.find(down) == visited.end())
+                    {
+                        q.push(down);
+                        visited.insert(down);
+                    }
+                }
+            }
+            num++;
+        }
+        return -1;
+    }
+    string turnUp(string str, int index)
+    {
+        char old = str[index];
+        char nnew = (old != '9') ? (old + 1) : '0';
+        string newString = str;
+        newString[index] = nnew;
+        return newString;
+    }
+    string turnDown(string str, int index)
+    {
+        char old = str[index];
+        char nnew = (old != '0') ? (old - 1) : '9';
+        string newString = str;
+        newString[index] = nnew;
+        return newString;
+    }
+};
+

# Hint:

  1. 修改string的某一个字符直接使用[]索引修改即可
  2. 字符’0‘到’1‘直接加一
  3. **deadends**中的字符串以及已经访问过的字符串应该在尝试加入队列之前就被过滤掉，以防止它们被进一步处理。而不是从队列中拿出来的时候检查是不是在visited中
  4. 起始的“0000”也要检查
  5. 使用双向BFS可以加快速度，但是queue修改为set，如下：
int openLock(vector<string> &deadends, string target)
+    {
+        unordered_set<string> dead(deadends.begin(), deadends.end());
+        unordered_set<string> begin, end, *set1, *set2;
+
+        if (dead.find("0000") != dead.end() || dead.find(target) != dead.end())
+            return -1;
+
+        int step = 0;
+        begin.insert("0000");
+        end.insert(target);
+
+        while (!begin.empty() && !end.empty())
+        {
+            // 优化搜索，总是从较小的集合开始扩展
+            if (begin.size() > end.size())
+            {
+                set1 = &end;
+                set2 = &begin;
+            }
+            else
+            {
+                set1 = &begin;
+                set2 = &end;
+            }
+            unordered_set<string> temp;
+            for (auto it = set1->begin(); it != set1->end(); ++it)
+            {
+                string str = *it;
+                if (set2->find(str) != set2->end())
+                    return step;
+                if (dead.find(str) != dead.end())
+                    continue;
+                dead.insert(str); // 标记为已访问
+                for (int j = 0; j < 4; ++j)
+                {
+                    string up = turnUp(str, j);
+                    string down = turnDown(str, j);
+                    if (dead.find(up) == dead.end())
+                        temp.insert(up);
+                    if (dead.find(down) == dead.end())
+                        temp.insert(down);
+                }
+            }
+            step++;
+            *set1 = temp; // 更新当前正在扩展的集合
+        }
+        return -1; // 如果没有找到有效路径
+    }
+
  1. 创建一个临时集合（temp）的原因是在每一轮搜索中，我们需要更新当前层次的节点。由于在遍历当前层次的节点时不能直接修改正在遍历的集合（这会影响迭代器的有效性），因此我们先将新发现的节点存储在一个临时集合中。在当前层次的所有节点都遍历完毕后，我们再用这个临时集合来更新主集合，为下一轮搜索做准备。

+ 2024.03.05-二叉树 + + → +

+ + + diff --git "a/LeetCode/LeetCode/2024 03 05-\344\272\214\345\217\211\346\240\221 6b922d49986f4faf85bc9106cd12c5ab.html" "b/LeetCode/LeetCode/2024 03 05-\344\272\214\345\217\211\346\240\221 6b922d49986f4faf85bc9106cd12c5ab.html" new file mode 100644 index 0000000..dd32ed9 --- /dev/null +++ "b/LeetCode/LeetCode/2024 03 05-\344\272\214\345\217\211\346\240\221 6b922d49986f4faf85bc9106cd12c5ab.html" @@ -0,0 +1,94 @@ + + + + + + 2024.03.05-二叉树 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.03.05-二叉树

2024.03.05-104.二叉树的最大深度

2024.03.05-543.二叉树的直径

+ ← +

+ + + diff --git "a/LeetCode/LeetCode/2024 03 05-\344\272\214\345\217\211\346\240\221 6b922d49986f4faf85bc9106cd12c5ab/2024 03 05-104 \344\272\214\345\217\211\346\240\221\347\232\204\346\234\200\345\244\247\346\267\261\345\272\246 c6649929175d46038db921b552f2a235.html" "b/LeetCode/LeetCode/2024 03 05-\344\272\214\345\217\211\346\240\221 6b922d49986f4faf85bc9106cd12c5ab/2024 03 05-104 \344\272\214\345\217\211\346\240\221\347\232\204\346\234\200\345\244\247\346\267\261\345\272\246 c6649929175d46038db921b552f2a235.html" new file mode 100644 index 0000000..a744ddb --- /dev/null +++ "b/LeetCode/LeetCode/2024 03 05-\344\272\214\345\217\211\346\240\221 6b922d49986f4faf85bc9106cd12c5ab/2024 03 05-104 \344\272\214\345\217\211\346\240\221\347\232\204\346\234\200\345\244\247\346\267\261\345\272\246 c6649929175d46038db921b552f2a235.html" @@ -0,0 +1,189 @@ + + + + + + 2024.03.05-104.二叉树的最大深度 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.03.05-104.二叉树的最大深度

/*
+ * @lc app=leetcode.cn id=104 lang=cpp
+ *
+ * [104] 二叉树的最大深度
+ *
+ * https://leetcode.cn/problems/maximum-depth-of-binary-tree/description/
+ *
+ * algorithms
+ * Easy (77.10%)
+ * Likes:    1786
+ * Dislikes: 0
+ * Total Accepted:    1.2M
+ * Total Submissions: 1.6M
+ * Testcase Example:  '[3,9,20,null,null,15,7]'
+ *
+ * 给定一个二叉树 root ，返回其最大深度。
+ *
+ * 二叉树的 最大深度 是指从根节点到最远叶子节点的最长路径上的节点数。
+ *
+ *
+ *
+ * 示例 1：
+ *
+ *
+ *
+ *
+ *
+ *
+ * 输入：root = [3,9,20,null,null,15,7]
+ * 输出：3
+ *
+ *
+ * 示例 2：
+ *
+ *
+ * 输入：root = [1,null,2]
+ * 输出：2
+ *
+ *
+ *
+ *
+ * 提示：
+ *
+ *
+ * 树中节点的数量在 [0, 10^4] 区间内。
+ * -100 <= Node.val <= 100
+ *
+ *
+ */
+
+// @lc code=start
+/**
+ * Definition for a binary tree node.
+ * struct TreeNode {
+ *     int val;
+ *     TreeNode *left;
+ *     TreeNode *right;
+ *     TreeNode() : val(0), left(nullptr), right(nullptr) {}
+ *     TreeNode(int x) : val(x), left(nullptr), right(nullptr) {}
+ *     TreeNode(int x, TreeNode *left, TreeNode *right) : val(x), left(left), right(right) {}
+ * };
+ */
+// @lc code=end
+
  1. 递归：分解成左右子树
class Solution
+{
+public:
+    int res;
+    int maxDepth(TreeNode *root)
+    {
+        if (root == nullptr)
+            return 0;
+        int tempLeft = maxDepth(root->left);
+        int tempRight = maxDepth(root->right);
+        return res = max(tempLeft, tempRight) + 1;
+    }
+};
+
  1. 遍历：进入节点（前序）加深度，离开节点（后序）减深度，叶子结点处更新结果
class Solution {
+public:
+    int res, temp;
+    int maxDepth(TreeNode* root) {
+        traverse(root);
+        return res;
+    }
+private:
+    void traverse(TreeNode* node){
+        if(node == nullptr){
+            res = max(res,temp);
+            return;
+        }
+        temp++;
+        traverse(node->left);
+        traverse(node->right);
+        temp--;
+    }
+};
+

+ 2024.03.05-543.二叉树的直径 + + → +

+ + + diff --git "a/LeetCode/LeetCode/2024 03 05-\344\272\214\345\217\211\346\240\221 6b922d49986f4faf85bc9106cd12c5ab/2024 03 05-543 \344\272\214\345\217\211\346\240\221\347\232\204\347\233\264\345\276\204 9db6d046b0954b45b96ca749922a2ece.html" "b/LeetCode/LeetCode/2024 03 05-\344\272\214\345\217\211\346\240\221 6b922d49986f4faf85bc9106cd12c5ab/2024 03 05-543 \344\272\214\345\217\211\346\240\221\347\232\204\347\233\264\345\276\204 9db6d046b0954b45b96ca749922a2ece.html" new file mode 100644 index 0000000..f02643b --- /dev/null +++ "b/LeetCode/LeetCode/2024 03 05-\344\272\214\345\217\211\346\240\221 6b922d49986f4faf85bc9106cd12c5ab/2024 03 05-543 \344\272\214\345\217\211\346\240\221\347\232\204\347\233\264\345\276\204 9db6d046b0954b45b96ca749922a2ece.html" @@ -0,0 +1,175 @@ + + + + + + 2024.03.05-543.二叉树的直径 | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# 2024.03.05-543.二叉树的直径

/*
+ * @lc app=leetcode.cn id=543 lang=cpp
+ *
+ * [543] 二叉树的直径
+ *
+ * https://leetcode.cn/problems/diameter-of-binary-tree/description/
+ *
+ * algorithms
+ * Easy (59.72%)
+ * Likes:    1495
+ * Dislikes: 0
+ * Total Accepted:    387.9K
+ * Total Submissions: 649.5K
+ * Testcase Example:  '[1,2,3,4,5]'
+ *
+ * 给你一棵二叉树的根节点，返回该树的 直径 。
+ * 
+ * 二叉树的 直径 是指树中任意两个节点之间最长路径的 长度 。这条路径可能经过也可能不经过根节点 root 。
+ * 
+ * 两节点之间路径的 长度 由它们之间边数表示。
+ * 
+ * 
+ * 
+ * 示例 1：
+ * 
+ * 
+ * 输入：root = [1,2,3,4,5]
+ * 输出：3
+ * 解释：3 ，取路径 [4,2,1,3] 或 [5,2,1,3] 的长度。
+ * 
+ * 
+ * 示例 2：
+ * 
+ * 
+ * 输入：root = [1,2]
+ * 输出：1
+ * 
+ * 
+ * 
+ * 
+ * 提示：
+ * 
+ * 
+ * 树中节点数目在范围 [1, 10^4] 内
+ * -100 <= Node.val <= 100
+ * 
+ * 
+ */
+
+// @lc code=start
+/**
+ * Definition for a binary tree node.
+ * struct TreeNode {
+ *     int val;
+ *     TreeNode *left;
+ *     TreeNode *right;
+ *     TreeNode() : val(0), left(nullptr), right(nullptr) {}
+ *     TreeNode(int x) : val(x), left(nullptr), right(nullptr) {}
+ *     TreeNode(int x, TreeNode *left, TreeNode *right) : val(x), left(left), right(right) {}
+ * };
+ */
+class Solution {
+public:
+    int res = 0;
+    int diameterOfBinaryTree(TreeNode* root) {
+        traverse(root,res);
+        return res;
+    }
+    // cal the maxDepth
+    int traverse(TreeNode* node,int& res){
+        if(node == nullptr){
+            return 0;
+        }
+        int leftMax = traverse(node->left,res);
+        int rightMax = traverse(node->right,res);
+        int nodeMax = max(leftMax,rightMax)+1;
+        res = max(res,leftMax+rightMax);
+        return nodeMax;
+    }
+};
+// @lc code=end
+

+ ← +

+ + + diff --git a/LeetCode/index.html b/LeetCode/index.html new file mode 100644 index 0000000..02ccaf6 --- /dev/null +++ b/LeetCode/index.html @@ -0,0 +1,90 @@ + + + + + + LeetCode | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# LeetCode

# 2024.02.22-752.打开转盘锁（BFS）

# 2024.03.05-二叉树

+ + + diff --git a/about/index.html b/about/index.html new file mode 100644 index 0000000..748cb53 --- /dev/null +++ b/about/index.html @@ -0,0 +1,90 @@ + + + + + + Helloworld | Hello World --from OutisLi + + + + + + + + +
Hello World --from OutisLi

# Helloworld

+ + + diff --git a/assets/css/0.styles.9501ef99.css b/assets/css/0.styles.9501ef99.css new file mode 100644 index 0000000..db4460f --- /dev/null +++ b/assets/css/0.styles.9501ef99.css @@ -0,0 +1 @@ +code[class*=language-],pre[class*=language-]{color:#ccc;background:none;font-family:Consolas,Monaco,Andale Mono,Ubuntu Mono,monospace;font-size:1em;text-align:left;white-space:pre;word-spacing:normal;word-break:normal;word-wrap:normal;line-height:1.5;-moz-tab-size:4;-o-tab-size:4;tab-size:4;-webkit-hyphens:none;hyphens:none}pre[class*=language-]{padding:1em;margin:.5em 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aw62cyxWnccN20+7s7Ui8MU+81o5lHUNSzJNKnowcDr/FR/kIsIjh/wnS72gGYqSPYiiaQDKXxUUGut/sHi6i4vpAgwvJnASjBHEtI86Au2k7LCdfblCWOG0UCQ788uySFXVBOpqK4z2eIV53tuyDTyczjjMF+6YEYUp2ULhLeK/QN90tXPeWcM3Zib7WkeBR6IfdjoTebcNKbYEs/DmdhuZdGgWy41yBi9fO45rrgrZINJJKvXEestGLp3lbX3NkvQ/ZGAUOIuVQRzbZxEd2ideKN5eJDxCVDizO8Hzq1cHKroYB3REMunkXz0Ex0OYam1a5pnmnoslosDnUgKx522CrvzSJZHqzy4rRmmoyaloIC9YlOxA8HbIj2cEx1ShxhOqEKNPqPpc4dWj83O43Oia7fwiMRk5mo6DdbQVUBduq7SpSR2pJs2pj1fZyhVKvsDYBmrP9T5eL84Vfbz4juN96ZVJoO1sgHJ0S8r+RHcy2dJptDyXiXh/DuoORrmgqEYyHdnv78aTjFpDDa0pRaliHHDoFjd2wAXuT1tpoVKmwMuONYig8PJedxsDdjxstK7NOs8PY/FTz0oZndNsdWV6xeh1eHDpgMBFr5V2uQGwi9WbH+ejrSPaJpw37lHANCLmMlGfCPMsiW61Utcj4tH0ZskyH2pC20+ymGGzkf4VPR3rfcPncUTxjv5Uz0kqn3KTVIovFaXMYDVSL0wwKMAZxq3jZENvmfT/8btflzn8OCrmD/0DuKOfBN/oIFk+KqlQb1GbdGvHh+tnIphCvB+ndWmCKY4fjF70n+G7XPqwcXmfA4SValcEaEG+Gu1eufcLYYsDBHFl9uNDyxSd/UUbhwmThbPD6pN296bHksdCAfyh1oe1ScCQ6FuwKdwcj6FTe25hmPGy7tzvpjbI8wwEHbpLLtsS9eY/BUzQBK52biF26FfItO/RbnDaazKqd2xmCJNsZjMeQz8e5+KA75vJ6uIinxzXEeZgBGGDQacDpSdEk36RZbSy1VGueapxpLGkpMdQY1TodEqWUVEGqjXoDQTgIXFBkVoo5OgXCEhCqGD3d6Xk3enJfZByxLsaFh+WzcWZQUo3GFq1a6SYcAPYm9hEM7ZXidZNX5k3m7L+ce+W9K4sLxWvzFkA1baHFa81i/tNr7jMoLU2OFqfFbQ9i32/3JSKRgMfHhxHj4rysK31sfPREJO0GOMegM2AhpPPu3yQu3iausDXZmii7dl3lxtImtUFja4An4NX98Ek2XbNefDuTtXAvwZtpNaW0aHRqrUODY22jR+nVtG86WvlBNsSEMGh8HPz80PGzPQPpPaFR1u3tdHd2fBc9mniz7x9D7/X3ooAfLx50w1h7oI3N7gELLpJz8Cj/oPJ45o1D3PGcvkvCzR8KH3+YKySvrCn8f7HiFwsKMgEeg4LLy+MwzVDkOrKGWG58qXFe472191bcb9c5LJjP7G67DxMnfrdWxLkie0L9A1/3fNNxKXk+cNI7yXVx4xAGv53/3xCDMveL1xb2cekkDMCIPFnOVoPO1mSZvUucO2v1suYGQo2Zz8HgUSHP4j+KC48ubisd3Dli4mhsTIC76K8n29/HheECF/hItzGbe5tbrErTjh2KtVkpYwh+U9szwk07hNsMY8QYpCDm9Xd0oNOnhV9//laEu1qYKBo0a4v10ymTxx7BcahZeS7z4Yc5GV7Izc1AJlpo5alAFpai6XQ8hlGoPxtqQrSbDBr7m2PbMGjYMJC9YF9WsW59XW1zdfPW6hXNy6vEW5Fivvbl9esNBjOmLtqJmcSZLXJf1i7SiQTy+yK0tJvqIUfNF5UBqtMRdyZwIovgvfWzn8T/9E7qFOvNjhF5bJy1SA8KolmvMmDIarFr7QRBIENeGdvoWpJYnJTz2/D0GbdP6glE+jyRUJ+3I3Sk9WLkYPxgx9m+N3s6A/4gl8BGHKuHnQh0DiOG2/yMfuNPV27H4VT4Z0Y/lfuvJZcKQc0oGT1XyVn9Fr8lRMYhu74uJslHXL3RdJBl/V4UCnivHi3ZOSvoQG62kXanA6+CDRy804evg9CL4IOEsLhDmOc95D/I+vkgE8S3BKkAgdeBxL7jpA1anQaJvxYfFOeKSx5/pKlh6bLsmYN22JawtFvT5pFK4foG4bpmocC2B8DGI6y/+OYmUJkMOouFdpANWvG6OnHGDnFG84pN4m01KhuZDWdIzqv8phCJ24/El4OykwaDrh5qcVGQjMOrHlNgzMTOBhy2mLbWtsHOvZ3HRr7bK+S0f9KBAx/sFyuGRElsQ+vmrq3I38JR/qsv5lif66Nz4weEa4WbhCeErTjGwzbRBeIdKP8nvJZ5Py5UF8hSwqUr6woboU5l0TrttNNRqxXvqRTnrhMfUCzV1+ot2VFaGAWv8hnCiHTRuMjtmFptdq3WWAnNUH1APgpxiHhj0f6+rjcGvkUjgrRHmNYqTONiXIRhgWcojzL1/OCdncuOiHfEyk7NjioYCAHqgy4crJnswRfF0JA9HnQNCw9E3+4T8keE4rbz3vZgP+fCAhgJhD1IdrQt2OsZYGOYHL3eWDzQhzEsRnk0eEAWrMuv2rcoq6tRXY38+VViY9P92hflc5D6SdIn3XxBc6D0xxIhd4dwc7WAnEFHgGaQi2DtRfkXlGczn0/mHJ/KRDH5ZxfDBGYsnsvNy3ZteKW6vGG7aqNVQ2NP4B087Yck0xmORbOyz3vjqUPtI11dqVTA2wM/wd4FIObCdutGY0ntnGcffLIUVWobiC2wHirCtel1e2omMcdHMSr4osKdnwrSH99OBoMBdwD923j+T2xygNFpJJWG+WufXbr50erVLa9alyFsRTp8iTceXvhpWa++B9fZOEx4J2LC3DcEmXDLhPD7yITvGEwgoWDtJfHGonytUDIp/A0nhBum/kNC4Bg2u+5O+2uUpllcsUV87mlxFc4JpA7XNum2eaAXhlpDrW5f52Ti6JvCQ3uEZ2LCfYgNdIP0S3hPPVLRpgw24GJV2FVGefmTj28Vc63NtJ3S2RqMGkwi6BcU4e0cBoUfsFKNXTgbCnR0+oMDY6lx9z7Gw3hwooEQFSaD9iQR1sVKh19s+wMGrh3MDsDXf0wb+d+Lt052nTlzNlOKvT5vKlPyTe6VhZkFhbDSsKFxbfnSVS89V1WvbyCqbLuIGudyGpVjx5Bq7DqL0WghyKzrYmDwYWxOUjFqhBw2n1ZerO2wDllRJ9ntbL+qbwH2/dAXr6cnWQ/DX6UUzkw3OxsNGG9w7HU4zESjxVQDr8KuwMrWFveaJM3QzEdt7x0Qrjn3jXBDQpiHGH921+HbyndX7alMVwU34LZpcpooUdIi5i1dcu/apTWPwjMIHhtafaKhzZRy9MJp+KlzZK/Xy7vx8gRsrBHXpI3SEKhK32ivwctSG2jsqOvRj2O6S7Epd2vkrd3Hx8cPHTrceSZ7dvvHe8WbMFj+VpnNUkL7mRzh2kuZR/5TUEQuBqxSrfjaJnHDE+J6u4HEBEnZPDb/v12Sc0eGfOnTwqK9wsKksAjx3VI8qVDRJ3DRPKhoNQTV2PU3NJfWNdTLd7Zss5M0ZnZajYest6Emk1pDGcDiwpsWpgL2oCmujjSkV3ct96uCqmR1WtVhRzztwmEsCq1snD8efnto73goHItjlfBasQ3jhnSaSKSxGC0mvUahUZaCCnR+bbsuRSSrP24ZM3YaE04XxQOgqdHv/5QUclg/g1UfhvTddYl1g0v42YAW5q0COb3VKOY0PvxC8zP/dzHNxDrw2WRBfOqDb4SVl2umZJmM4craQmyZTFaXnTQNc6yPbtzyikZhktubKCsQVy8La0ee2mRjnyKl85F/rD1XMVwR3M5iewEDDmoms0qx8dWaRwA9A1vaqvYaY/YQncge7LpCiAu4OGnUE496/BzH/huCjVBDVbQ0NcnlmkrYBgqPKtyCRjacqP0Ug9fFjsn9reFQIB775UCY9V2d5R7NUFkvamqtj61v35HUBNUJRdrYgXOCn/Vz/ujEQOdpmIDX9XEdkv3gs7gMWEgImnBaHHqGcpM8xngvrqOuUDx+lWejiAthfvCj9xe1Ls0CdebHc/3qnCvaLF6a8sQSnMHN1BLi0Y07X9UqLI24oM1u8moMZ71cp3egzR/PcivGOEiH+1OeEO+BbwF9A0at1Kq54+elNrlhk3qdcgNJOAkcTa7Chgd8jJfr9vckQx0ovb/9TOQo5+/4vluY0SNc2/Z19tzRg8PGdwxA2jXk3dfe2oF8AU8ke+Jkw+GhHhQalR7lL8Bb+fbZHO3UqSnh2anc9sz5wjAkPYlQ2Bfko5DEhA9KLLFau9pSY6goX7hJzNVsMmxEtkaHHE9lVef2Awas9fTVj5EYLzPi2Rsf7zo7/uEHH36NXG7eBbR2VZ14DTwH9XFtN35VmA3x3cHTXa7uX44WkRn0JG5XCyk1Y8+EJDfh2Zc1tpuPCIu73vW3+TpcSRbDN5Z9r5WzYCKiKtQGlYM017ZsIOR2vbpsofik+FtxybyVzXqjTQUbQL0XjiJIcWlPOjiRODD+bfc7gU5/Z3y/rx8nq4GWWCVshSpzmQqVKOVKjMSEF68qyp+dOffji6cKhO1fCm8flzW2X7mhkPA4fEVe3I5+Z48tpU3VDq9OzgbxNnjcJM40raZttA2ro5Ez+wGx2Y8BmJD7rf1jQyeOnj07cfS9z8//mBDyWDxrCCLZEJwpO/ySy4z30UGpTdqd0Ah6lojCXudALewEK21zWlHjo3eLMnGWWKDRNiqz535BzMV/B+HJOiHvlTeQrLGxvT6yFVB5WZ0aS1fXFcmpHOGFL6+8djw3O2Krh/QK07rFO8XiIlhpf8b8B9tGy2qH0WGiTLgNTZw5AF6G5xNpYY7wrHCbsHFKWIt4N+fOckVom6d+SCxOi/Nd4lxuKdAMyRNe2ucOed/74tC7CBvoU+eEu6M/4d0OYdV5UzNUHbHyZpbIMhkmYrVJVw1VSMcQgaFUfXkRbh+L06JdtXH+07OUtVtXaTUIY2VcahEW1AsLtgmzrZ3aIxSHjQ9LQSOUY3/EiAKslc3GBBrb4s7Fip0vz1o5d8k9qjpDS/YoFL+3P/CB6z14Gz4gJrVHENFmbDNEFb3lyR2ASksbm4vz4Zdoe2Qqc2QqVzif+VehL4+nPTRPDxi49a61KCD+Tgqk2CRe//DDtbUWDe6KyoS8H3bDQDqc4rHmUy7E21wOtTXcWoRLl2V5d2Rs9+TEcPtXx7MY4nqcq/M8xC4/KA+QXioG6BCMBAY6UqFoypNmgySvByXdZNRorNYss9aCsdXaj8wjhLDC6Ufgao9IL799enzfYCycTvtCkQQfglY00NJetXNLuRrLrbco7vRYspqBXcahrxZfEqfjOAtmYQExZOu0xPVBQ9DCy7Oa+WSVbjXtvPr5HpFN3W1MXyKeQvnbMhe+zul9XeC/FCxHcy9kLhTGIeWPRTCY+WlpuzNtjRlObB26Myg+wFUzu6AMyp2LnBr8hk6DZePOTfVyEmGyxwC+ma9rt4xTYafXgltGUQU1sGZ065g+6IhQoV/Im2de9/7w0eXvhDuFu6eER4eEuzxdWHfb4Yi+pz5tCKh8SkBkNinQequuAS+5gcedk4I2c8ASMviwEYDJabTKUd39y0XJQ7N1LfJGDF4J9jBuXOGRZmHuixcbRrb2vAybYaeyrhYZDHYC50KL14kbMD/IfPDaOUF1fs0x4eUP158rkD19+JYIRF1BT9wT4trhAMSpzwkkM39FJOgJzGwcFv5jweNDIwdTHfGBwAAXBN7JO1masQKyYmuyUzVEWTPRSFTo5C0KpMorZZvYZZ77fQoGt6DslUrGxUsvnvvTuQ/fR23pGC3tosJUlk3ddp5CspkszWOxTzF9SczgHI0vIqZx1zJIdrPdCkwxMIFAJPr+ubfeOfF+NMlyrBt7AZM9LLCyZtDRWkJuQjKkYqRNjJl9DcP9tBf9FLMJsvDtgMds967f9qJJZ6jNeqyLCmNoTnmTYZQK43AfCe1JhA5BK/Q7DtqQbMMb1gTVT6N2MOikeo3dLm9AYq44Q7wBrA6pkjDowAi44N1OtJ8+AAqFdM68x54W8+/U6gkTWJHN5fQVZf8r5OcHYSoHpqamcmHa1NTsPGHL7MLs43/zxJWrT/z71/kZ581Xthaqk1fuY6IDeUUzcgOLr78Wrp9xaMah64pm5P2v6wv+Cyb7dp8AAAAAAAABAAAAAMw9os8AAAAAxvkyTwAAAADJ9CXHeJxjYGRgYOADYgkGEGBiYARCTSBmAfMYAAYNAFwAAAB4nGNgYUpknMDAysDA1MW0h4GBoQdCMz5gMGRkYkACDQwM7wUY3ryF8QPSXFMYDjAovP/PIPf/EVBAjkFOgYGhP44ZJMu0ikEBCBkBG0IQ8HicY2BgYGaAYBkGRgYQiAHyGMF8FgYHIM3DwMHABGQrMFgyRDEseP///3+gqAKDAYMjkPcXyH34/9L/0//bBLSgJsABIxsDuhAGQJdnYmZhZWPn4OTihgrw8PLxCwgKCYuIiolLSEpJy8jKySsoKimrqBIwmdpAjSxdAD02FYAAeJxjYGRgYADiL8KHN8bz23xl4GZ+ARRhuBq7aj2M/v/ovwZLIbMokMvBwAQSBQCIvg3IAHicY2BkYGCQ+/+IgYFl4/9H/x6wFDKARJCBFgCqbgcVeJxj+MVgxPCLgYHxC4M6EIcBsQ4QawGxDBAbQdnmQKwNYjPLMcgxTWRQYOJn4GFmZhBmEgDyzzMIMQUz6DD7AmnF/4+YljHoM/0CqtnEoMCykUGG2eT/U2YZBiumHQzCzIYMRcwBQH1xILUMSkxF/98zpTJIMt9hkGQ6yWDCNIdBnukqgyrYTToQzJDCwAAArGwjmAAAUAAAKgAAeJy1VN1KG0EYPRuzSlNMFaEX9WauJMHN5qelYBBBlEAkKhqR0ovKmIzZkc1m2dlk9Qn6CL3uE/Si9AlKr3rZi170VUrpt5OxNiUVFcyyO2e//eacM983EwBPrTwsjH8OXhtsYQkfDM5gDt8MnsGq9dzgLJatdwbbeGx9NXgWy5knBs/jV7ZocB7P7DcGL2DJfm/wIubsL8RsZR/R2yutkmILK3hrcIZmfzZ4Bsf4YXAWL60Tg21ay0eDZyn+3eB562dm1eA8XtgFgxewYl8avIi8/QlbGCDEJSJI9OAhBkMBHRRprKFC1xpKGlXpZtiGgNK5Ab21KVNSJKBRUC0Zmhq7wNYgvIxkz4tZoVNktUplrVSrVCtsWyjZC1i7I0XQEQ5rBh3K3gUnaQ87NF7ghGxx+FomIhTSF0m02OWxt8MvTra4L3sRDz1JwUOS7mFI+ZyycSh6Q58TaNDSAmJNx4gyhF6Sq5dRp/t2mqV/+RuDIG4Mop5gNbfC6myKp9IfD/fUuJHzmHIj3YSBbkKV1lSlsIiUHASs6lYfRvduW8W5w2ZJedaR6MtF33g/195d070N0nGQowypvzLtXelajOjZpchVxxn2aG5fd/x2lXCJOYcj/aYmmNqEzgglukIp4zjD1/PS1SijPiTc1X6YVhR6dhMtGvdJSegqXDO3JhjSekzvrDvhbFKXkasR3VJ38JSeaey6RlwrbuJA45j2fU53LiY/dZTpUsSWdjSkmCItpbmuql4m5w1y+r/j7Ew9z6ywniSJ26fddM4vXDosG0Unl8jYY4dCiWgkuiw9RmyP98W0A+TmckeeVOOk9uAsTngkGAV82RGBounDoCsiFnuCtZstth+KYJzcGic47K/j4I7JzFzGR1z6/NQXTDvirLF5wHhcz3lxHNbLZdWJZBgrV0k/tV7eb9D671W0mwgf4B/vN8NCYPYAAAB4nGNgZgCD/80MRgxYAAAoRAG4AA==) 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These states transition based off three inputs: Coffee, Ideas they come up with, and Pressure from their advisor to make progress. Once they Graduate, they return to the Idle state. The FSM diagram below shows these states and transitions. Any unlabelled transition (i.e. when there are no inputs) returns a grad student to the Idle state instead of staying in the current state. The input precedence is coffee > idea > pressure, so when in the Idle state and receiving both coffee and pressure, a graduate student will move to the Coding state.")]),t._v(" "),s("p",[s("img",{attrs:{src:a(297),alt:"Untitled"}})]),t._v(" "),s("p",[t._v("检查逻辑：")]),t._v(" "),s("div",{staticClass:"language-scala extra-class"},[s("pre",{pre:!0,attrs:{class:"language-scala"}},[s("code",[s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("// state map")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("def")]),t._v(" states "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" Map"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),s("span",{pre:!0,attrs:{class:"token string"}},[t._v('"idle"')]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("->")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(",")]),t._v(" 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"),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("=>")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("{")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("// Another syntax, but curly braces are not required")]),t._v("\n "),s("span",{pre:!0,attrs:{class:"token string"}},[t._v('"two"')]),t._v("\n "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("}")]),t._v("\n "),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("case")]),t._v(" _ "),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("=>")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token string"}},[t._v('"many"')]),t._v(" "),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("// _ is a wildcard that matches all values")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("}")]),t._v("\nprintln"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),s("span",{pre:!0,attrs:{class:"token string"}},[t._v('"y is "')]),t._v(" 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0.0)')])]),t._v("，而不会影响**"),s("code",[t._v("foreach")]),s("strong",[t._v("和")]),s("code",[t._v("match")]),t._v("**语句的行为。")]),t._v(" "),s("h3",{attrs:{id:"example-multiple-type-matching"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#example-multiple-type-matching"}},[t._v("#")]),t._v(" Example: Multiple Type Matching")]),t._v(" "),s("p",[t._v("If you want to match on whether a value has one of many types, use the following syntax. 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\ No newline at end of file diff --git a/assets/js/32.b1be8e96.js b/assets/js/32.b1be8e96.js new file mode 100644 index 0000000..57e39d9 --- /dev/null +++ b/assets/js/32.b1be8e96.js @@ -0,0 +1 @@ +(window.webpackJsonp=window.webpackJsonp||[]).push([[32],{315:function(t,s,a){"use strict";a.r(s);var n=a(14),v=Object(n.a)({},(function(){var t=this,s=t._self._c;return s("ContentSlotsDistributor",{attrs:{"slot-key":t.$parent.slotKey}},[s("h1",{attrs:{id:"_2023-11-16-阻塞与非阻塞赋值"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#_2023-11-16-阻塞与非阻塞赋值"}},[t._v("#")]),t._v(" 2023.11.16-阻塞与非阻塞赋值")]),t._v(" "),s("p",[s("img",{attrs:{src:"2023.11.16-%E9%98%BB%E5%A1%9E%E4%B8%8E%E9%9D%9E%E9%98%BB%E5%A1%9E%E8%B5%8B%E5%80%BCUntitled.png",alt:"Untitled"}})]),t._v(" "),s("p",[s("img",{attrs:{src:"2023.11.16-%E9%98%BB%E5%A1%9E%E4%B8%8E%E9%9D%9E%E9%98%BB%E5%A1%9E%E8%B5%8B%E5%80%BCUntitled%201.png",alt:"Untitled"}})]),t._v(" "),s("p",[t._v("组合逻辑电路使用阻塞赋值")]),t._v(" "),s("p",[t._v("时序逻辑电路使用非阻塞赋值")]),t._v(" "),s("p",[t._v("在 Verilog 中，阻塞赋值（Blocking Assignment）和非阻塞赋值（Non-Blocking Assignment）是两种不同的信号赋值方法，它们在时序逻辑的模拟和硬件描述语言（HDL）代码的编写中有着重要的区别。")]),t._v(" "),s("h3",{attrs:{id:"阻塞赋值-blocking-assignment"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#阻塞赋值-blocking-assignment"}},[t._v("#")]),t._v(" "),s("strong",[t._v("阻塞赋值（Blocking Assignment）")])]),t._v(" "),s("ul",[s("li",[t._v("使用符号 "),s("strong",[s("code",[t._v("=")])]),t._v(" 进行赋值。")]),t._v(" "),s("li",[t._v("阻塞赋值在执行时会“阻塞”代码的进一步执行，直到赋值完成。")]),t._v(" "),s("li",[t._v("在执行下一条语句之前，当前语句必须完成其操作。")]),t._v(" "),s("li",[t._v("在组合逻辑设计中常用，但在时序逻辑中使用可能会导致问题，因为它们可能会引起模拟时序和硬件时序的不一致。")])]),t._v(" "),s("p",[s("strong",[t._v("举例")]),t._v("：")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("a "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" b"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nc "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" a"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n")])])]),s("p",[t._v("在这个例子中，"),s("strong",[s("code",[t._v("c = a;")])]),t._v(" 会等待 "),s("strong",[s("code",[t._v("a = b;")])]),t._v(" 完成后才执行。")]),t._v(" "),s("h3",{attrs:{id:"非阻塞赋值-non-blocking-assignment"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#非阻塞赋值-non-blocking-assignment"}},[t._v("#")]),t._v(" "),s("strong",[t._v("非阻塞赋值（Non-Blocking Assignment）")])]),t._v(" "),s("ul",[s("li",[t._v("使用符号 "),s("strong",[s("code",[t._v("<=")])]),t._v(" 进行赋值。")]),t._v(" "),s("li",[t._v("非阻塞赋值允许代码的后续部分在赋值完成之前继续执行。")]),t._v(" "),s("li",[t._v("这意味着所有非阻塞赋值都是并行发生的（或看起来如此），这更接近于硬件的实际行为。")]),t._v(" "),s("li",[t._v("在时序逻辑，特别是在描述触发器（如寄存器）的行为时非常重要和常用。")])]),t._v(" "),s("p",[s("strong",[t._v("举例")]),t._v("：")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("a "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("<=")]),t._v(" b"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nc "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("<=")]),t._v(" a"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n")])])]),s("p",[t._v("在这个例子中，"),s("strong",[s("code",[t._v("c <= a;")])]),t._v(" 不会等待 "),s("strong",[s("code",[t._v("a <= b;")])]),t._v(" 的完成。"),s("strong",[s("code",[t._v("a")])]),t._v(" 和 "),s("strong",[s("code",[t._v("c")])]),t._v(" 的赋值看似同时发生。")]),t._v(" "),s("p",[t._v("在一个always块中，不同地方对同一个变量的赋值会被同时执行，最终结果是变量变成最后一次赋值的结果（前面的操作被覆盖）")])])}),[],!1,null,null,null);s.default=v.exports}}]); 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operator"}},[t._v("+")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("begin")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n byte1"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),t._v("j"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" data1"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),t._v("j"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("+")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("8")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("-")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" j"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("8")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//把data1[7:0]…data1[31:24]依次赋值给byte1[0][7:0]…byte[3][7:0]*")]),t._v("\n "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("end")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("end")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n")])])]),s("p",[t._v("此例中，integer 信号 j 作为辅助信号，将 data1 的数据依次赋值给数组 byte1。综合后实际电路里并没有 j 这个信号，j 只是辅助生成相应的硬件电路。")]),t._v(" "),s("h3",{attrs:{id:"实数-real"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实数-real"}},[t._v("#")]),t._v(" "),s("strong",[t._v("实数（real）")])]),t._v(" "),s("p",[t._v("实数用关键字 real 来声明，可用十进制或科学计数法来表示。实数声明不能带有范围，默认值为 0。如果将一个实数赋值给一个整数，则只有实数的整数部分会赋值给整数。例如：")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("real")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" data1 "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("integer")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" temp "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("initial")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("begin")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n data1 "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("2e3")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n data1 "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3.75")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("end")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("initial")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("begin")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n temp "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" data1 "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//temp 值的大小为3*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("end")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n")])])]),s("h3",{attrs:{id:"时间-time"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#时间-time"}},[t._v("#")]),t._v(" "),s("strong",[t._v("时间（time）")])]),t._v(" "),s("p",[t._v("Verilog 使用特殊的时间寄存器 time 型变量，对仿真时间进行保存。其宽度一般为 64 bit，通过调用系统函数 $time 获取当前仿真时间。例如：")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("time")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" current_time "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("initial")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("begin")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("#100")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n current_time "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token kernel-function property"}},[t._v("$time")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//current_time 的大小为 100*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("end")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n")])])]),s("h3",{attrs:{id:"数组"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#数组"}},[t._v("#")]),t._v(" "),s("strong",[t._v("数组")])]),t._v(" "),s("p",[t._v("在 Verilog 中允许声明 "),s("code",[t._v("reg, wire, integer, time, real")]),t._v(" 及其向量类型的数组。")]),t._v(" "),s("p",[t._v("数组维数没有限制。线网数组也可以用于连接实例模块的端口。数组中的每个元素都可以作为一个标量或者向量，以同样的方式来使用，形如："),s("strong",[t._v("数组名[下标]")]),t._v("。对于多维数组来讲，用户需要说明其每一维的索引。例如：")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("integer")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" flag "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("7")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//8个整数组成的数组*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" counter "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//由4个4bit计数器组成的数组*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("wire")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("7")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" addr_bus "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//由4个8bit wire型变量组成的数组*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("wire")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" data_bit"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("7")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("5")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//声明1bit wire型变量的二维数组*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("31")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" data_4d"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("11")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("255")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//声明4维的32bit数据变量数组*")]),t._v("\n")])])]),s("p",[t._v("下面显示了对数组元素的赋值操作：")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("flag "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("32'd0")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//将flag数组中第二个元素赋值为32bit的0值*")]),t._v("\ncounter"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'hF")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//将数组counter中第4个元素的值赋值为4bit 十六进制数F，等效于counter[3][3:0] = 4'hF，即可省略宽度;*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("assign")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" addr_bus"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("8'b0")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//将数组addr_bus中第一个元素的值赋值为0*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("assign")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" data_bit"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1'b1")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token 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string"}},[t._v('"run.runoob.com"')]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("end")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n")])])]),s("p",[t._v("有一些特殊字符在显示字符串中有特殊意义，例如换行符，制表符等。如果需要在字符串中显示这些特殊的字符，则需要在前面加前缀转义字符 *"),s("em",[t._v("*")]),t._v(" 。例如下表所示：")]),t._v(" "),s("table",[s("thead",[s("tr",[s("th",[t._v("转义字符")]),t._v(" "),s("th",[t._v("显示字符")])])]),t._v(" "),s("tbody",[s("tr",[s("td",[t._v("\\n")]),t._v(" "),s("td",[t._v("换行")])]),t._v(" "),s("tr",[s("td",[t._v("\\t")]),t._v(" "),s("td",[t._v("制表符")])]),t._v(" "),s("tr",[s("td",[t._v("%%")]),t._v(" "),s("td",[t._v("%")])]),t._v(" "),s("tr",[s("td",[t._v("\\")]),t._v(" "),s("td",[t._v("\\")])]),t._v(" "),s("tr",[s("td",[t._v('"')]),t._v(" "),s("td",[t._v('"')])]),t._v(" "),s("tr",[s("td",[t._v("\\ooo")]),t._v(" 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punctuation"}},[t._v(",")]),t._v(" b"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(",")]),t._v(" c"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nc "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" a "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("+")]),t._v(" b "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//寄存器*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" cprmu_1"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(",")]),t._v(" cprmu_2 "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token important"}},[t._v("always")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" @"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("posedge")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" clk"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("begin")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n cprmu_2 "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" cprmu_1 "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("^")]),t._v(" cprmu_2 "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("end")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n \n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//函数*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" flag1 "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nflag "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token function"}},[t._v("calculate_result")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),t._v("A"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(",")]),t._v(" B"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//非法操作数*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" res"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("wire")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" temp"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token important"}},[t._v("always")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("@ （"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),t._v("）"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("begin")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n res "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" cprmu_2 – cprmu_1 "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//temp = cprmu_2 – cprmu_1 ; //不合法，always块里赋值对象不能是wire型*")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("end")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("endmodule")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v("\n")])])]),s("h3",{attrs:{id:"操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#操作符"}},[t._v("#")]),t._v(" 操作符")]),t._v(" "),s("p",[t._v("Verilog 中提供了大约 9 种操作符，分别是算术、关系、等价、逻辑、按位、归约、移位、拼接、条件操作符。")]),t._v(" "),s("p",[t._v("大部分操作符与 C 语言中类似。同类型操作符之间，除条件操作符从右往左关联，其余操作符都是自左向右关联。圆括号内表达式优先执行。例如下面每组的 2 种写法都是等价的。")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//自右向左关联，两种写法等价")]),t._v("\nA"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("+")]),t._v("B"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("-")]),t._v("C "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),t._v("A"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("+")]),t._v("B）"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("-")]),t._v("C "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n\n"),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//自右向左关联，两种写法等价，结果为 B、D 或 F")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" C "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" D "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" F "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),t._v("C "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" D "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" F"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n\n"),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//自右向左关联，两种写法不等价")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),t._v("A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" C"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" D "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" F "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果 D 或 F")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" C "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" D "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" F "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 B、D 或 F")]),t._v("\n")])])]),s("p",[t._v("不同操作符之间，优先级是不同的。下表列出了操作符优先级从高至低的排列顺序。当没有圆括号时，Verilog 会根据操作符优先级对表达式进行计算。为了避免由操作符优先级导致的计算混乱，在不确定优先级时，建议用圆括号将表达式区分开来。")]),t._v(" "),s("table",[s("thead",[s("tr",[s("th",[t._v("操作符")]),t._v(" "),s("th",[t._v("操作符号")]),t._v(" "),s("th",[t._v("优先级")])])]),t._v(" "),s("tbody",[s("tr",[s("td",[t._v("单目运算")]),t._v(" "),s("td",[t._v("+ - ! ~")]),t._v(" "),s("td",[t._v("最高")])]),t._v(" "),s("tr",[s("td",[t._v("乘、除、取模")]),t._v(" "),s("td",[t._v("* / %")]),t._v(" "),s("td")]),t._v(" "),s("tr",[s("td",[t._v("加减")]),t._v(" "),s("td",[t._v("+ -")]),t._v(" "),s("td")]),t._v(" "),s("tr",[s("td",[t._v("移位")]),t._v(" "),s("td",[t._v("<<  >>")]),t._v(" "),s("td")]),t._v(" "),s("tr",[s("td",[t._v("关系")]),t._v(" "),s("td",[t._v("<  <=  >  >=")]),t._v(" "),s("td")]),t._v(" "),s("tr",[s("td",[t._v("等价")]),t._v(" "),s("td",[t._v("==  !=  ===  !===")]),t._v(" "),s("td")]),t._v(" "),s("tr",[s("td",[t._v("归约")]),t._v(" "),s("td",[t._v("& ~&")]),t._v(" "),s("td")]),t._v(" "),s("tr",[s("td"),t._v(" "),s("td",[t._v("^ ~^")]),t._v(" "),s("td")]),t._v(" "),s("tr",[s("td"),t._v(" "),s("td"),t._v(" "),s("td",[t._v("~")])]),t._v(" "),s("tr",[s("td",[t._v("逻辑")]),t._v(" "),s("td",[t._v("&&")]),t._v(" "),s("td")]),t._v(" "),s("tr",[s("td"),t._v(" "),s("td"),t._v(" "),s("td")]),t._v(" "),s("tr",[s("td",[t._v("条件")]),t._v(" "),s("td",[t._v("?:")]),t._v(" "),s("td",[t._v("最低")])])])]),t._v(" "),s("h3",{attrs:{id:"算术操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#算术操作符"}},[t._v("#")]),t._v(" 算术操作符")]),t._v(" "),s("p",[t._v("算术操作符包括单目操作符和双目操作符。")]),t._v(" "),s("p",[t._v("双目操作符对 2 个操作数进行算术运算，包括乘（*）、除（/）、加（+）、减（-）、求幂（**）、取模（%）。")]),t._v(" "),s("h2",{attrs:{id:"实例-3"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-3"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" a"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(",")]),t._v(" b"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" c "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\na "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'b0010")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nb "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'b1001")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nc "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" a"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("+")]),t._v("b"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为c=b'b1011*")]),t._v("\nc "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" a"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("/")]),t._v("b"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为c=4，取整*")]),t._v("\n")])])]),s("p",[t._v("如果操作数某一位为 X，则计算结果也会全部出现 X。例如：")]),t._v(" "),s("h2",{attrs:{id:"实例-4"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-4"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("b "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'b100x")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nc "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" a"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("+")]),t._v("b "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为c=4'bxxxx*")]),t._v("\n")])])]),s("p",[t._v("对变量进行声明时，要根据变量的操作符对变量的位宽进行合理声明，不要让结果溢出。上述例子中，相加的 2 个变量位宽为 4bit，那么结果寄存器变量位宽最少为 5bit。否则，高位将被截断，导致结果高位丢失。无符号数乘法时，结果变量位宽应该为 2 个操作数位宽之和。")]),t._v(" "),s("h2",{attrs:{id:"实例-5"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-5"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" mula "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" mulb"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("reg")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("5")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" res "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nmula "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'he")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nmulb "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("2'h3")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nres "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" mula "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),t._v(" mulb "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为res=6'h2a, 数据结果没有丢失位数*")]),t._v("\n")])])]),s("ul",[s("li",[t._v("和 - 也可以作为单目操作符来使用，表示操作数的正负性。此类操作符优先级最高。")])]),t._v(" "),s("div",{staticClass:"language- extra-class"},[s("pre",{pre:!0,attrs:{class:"language-text"}},[s("code",[t._v("-4 //表示负4\n+3 //表示正3\n")])])]),s("p",[t._v("负数表示时，可以直接在十进制数字前面增加一个减号 -，也可以指定位宽。因为负数使用二进制补码来表示，不指定位宽来表示负数，编译器在转换时，会自动分配位宽，从而导致意想不到的结果。例如：")]),t._v(" "),s("h2",{attrs:{id:"实例-6"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-6"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("mula "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("-")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'd4")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nmulb "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("2")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nres "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" mula "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),t._v(" mulb "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//计算结果为res=-6'd8, 即res=6'h38，正常*")]),t._v("\nres "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" mula "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("-")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("'d4")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//(4的32次幂-4) * 2, 结果异常*")]),t._v("\n")])])]),s("h3",{attrs:{id:"关系操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#关系操作符"}},[t._v("#")]),t._v(" 关系操作符")]),t._v(" "),s("p",[t._v("关系操作符有大于（>），小于（<），大于等于（>=），小于等于（<=）。")]),t._v(" "),s("p",[t._v("关系操作符的正常结果有 2 种，真（1）或假（0）。")]),t._v(" "),s("p",[t._v("如果操作数中有一位为 x 或 z，则关系表达式的结果为 x。")]),t._v(" "),s("h2",{attrs:{id:"实例-7"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-7"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nB "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nX "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3'b1xx")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n \nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v(">")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//为真*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("<=")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//为假*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v(">=")]),t._v(" Z "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//为X，不确定*")]),t._v("\n")])])]),s("h3",{attrs:{id:"等价操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#等价操作符"}},[t._v("#")]),t._v(" 等价操作符")]),t._v(" "),s("p",[t._v("等价操作符包括逻辑相等（==），逻辑不等（!=），全等（===），非全等（!==）。")]),t._v(" "),s("p",[t._v("等价操作符的正常结果有 2 种：为真（1）或假（0）。")]),t._v(" "),s("p",[t._v("逻辑相等/不等操作符不能比较 x 或 z，当操作数包含一个 x 或 z，则结果为不确定值。")]),t._v(" "),s("p",[t._v("全等比较时，如果按位比较有相同的 x 或 z，返回结果也可以为 1，即全等比较可比较 x 或 z。所以，全等比较的结果一定不包含 x。举例如下：")]),t._v(" "),s("h2",{attrs:{id:"实例-8"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-8"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nB "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("8'h04")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nC "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'bxxxx")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nD "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'hx")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("==")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//为真*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("==")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),t._v("B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("+")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//为假*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("==")]),t._v(" C "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//为X，不确定*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("===")]),t._v(" C "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//为假，返回值为0*")]),t._v("\nC "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("===")]),t._v(" D "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//为真，返回值为1*")]),t._v("\n")])])]),s("h3",{attrs:{id:"逻辑操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#逻辑操作符"}},[t._v("#")]),t._v(" 逻辑操作符")]),t._v(" "),s("p",[t._v("逻辑操作符主要有 3 个：&&（逻辑与）, ||（逻辑或），!（逻辑非）。")]),t._v(" "),s("p",[t._v("逻辑操作符的计算结果是一个 1 bit 的值，0 表示假，1 表示真，x 表示不确定。")]),t._v(" "),s("p",[t._v("如果一个操作数不为 0，它等价于逻辑 1；如果一个操作数等于 0，它等价于逻辑 0。如果它任意一位为 x 或 z，它等价于 x。")]),t._v(" "),s("p",[t._v("如果任意一个操作数包含 x，逻辑操作符运算结果不一定为 x。")]),t._v(" "),s("p",[t._v("逻辑操作符的操作数可以为变量，也可以为表达式。例如：")]),t._v(" "),s("h2",{attrs:{id:"实例-9"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-9"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nB "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nC "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("2'b1x")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n \nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("&&")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("// 为假*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("||")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("// 为真*! A *// 为假*! B *// 为真*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("&&")]),t._v(" C "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("// 为X，不确定*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("||")]),t._v(" C "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("// 为真，因为A为真*(A==2) && (! B) *//为真，此时第一个操作数为表达式*")]),t._v("\n")])])]),s("h3",{attrs:{id:"按位操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#按位操作符"}},[t._v("#")]),t._v(" 按位操作符")]),t._v(" "),s("p",[t._v("按位操作符包括：取反（~），与（&），或（|），异或（^），同或（~^）。")]),t._v(" "),s("p",[t._v("按位操作符对 2 个操作数的每 1 bit 数据进行按位操作。")]),t._v(" "),s("p",[t._v("如果 2 个操作数位宽不相等，则用 0 向左扩展补充较短的操作数。")]),t._v(" "),s("p",[t._v("取反操作符只有一个操作数，它对操作数的每 1 bit 数据进行取反操作。")]),t._v(" "),s("p",[t._v("下图给出了按位操作符的逻辑规则。")]),t._v(" "),s("p",[t._v("| &(与） | 0 | 1 | x | | |(或) | 0 | 1 | x |\n| --- | --- | --- | --- | --- | --- | --- | --- | --- |\n| 0 | 0 | 0 | 0 | | 0 | 0 | 1 | x |\n| 1 | 0 | 1 | x | | 1 | 1 | 1 | 1 |\n| x | 0 | x | x | | x | x | 1 | x |")]),t._v(" "),s("table",[s("thead",[s("tr",[s("th",[t._v("^(异或)")]),t._v(" "),s("th",[t._v("0")]),t._v(" "),s("th",[t._v("1")]),t._v(" "),s("th",[t._v("x")]),t._v(" "),s("th"),t._v(" "),s("th",[t._v("~^(同或)")]),t._v(" "),s("th",[t._v("0")]),t._v(" "),s("th",[t._v("1")]),t._v(" "),s("th",[t._v("x")])])]),t._v(" "),s("tbody",[s("tr",[s("td",[t._v("0")]),t._v(" "),s("td",[t._v("0")]),t._v(" "),s("td",[t._v("1")]),t._v(" "),s("td",[t._v("x")]),t._v(" "),s("td"),t._v(" "),s("td",[t._v("0")]),t._v(" "),s("td",[t._v("1")]),t._v(" "),s("td",[t._v("0")]),t._v(" "),s("td",[t._v("x")])]),t._v(" "),s("tr",[s("td",[t._v("1")]),t._v(" "),s("td",[t._v("1")]),t._v(" "),s("td",[t._v("0")]),t._v(" "),s("td",[t._v("x")]),t._v(" "),s("td"),t._v(" "),s("td",[t._v("1")]),t._v(" "),s("td",[t._v("0")]),t._v(" "),s("td",[t._v("1")]),t._v(" "),s("td",[t._v("x")])]),t._v(" "),s("tr",[s("td",[t._v("x")]),t._v(" "),s("td",[t._v("x")]),t._v(" "),s("td",[t._v("x")]),t._v(" "),s("td",[t._v("x")]),t._v(" "),s("td"),t._v(" "),s("td",[t._v("x")]),t._v(" "),s("td",[t._v("x")]),t._v(" "),s("td",[t._v("x")]),t._v(" "),s("td",[t._v("x")])])])]),t._v(" "),s("h2",{attrs:{id:"实例-10"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-10"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'b0101")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nB "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'b1001")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nC "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'bx010")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("~")]),t._v("A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//4'b1010*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("&")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//4'b0001*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("|")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//4'b1101*")]),t._v("\nA"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("^")]),t._v("B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//4'b1100*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("~^")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//4'b0011*")]),t._v("\nB "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("|")]),t._v(" C "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//4'b1011*")]),t._v("\nB"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("&")]),t._v("C "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//4'bx000*")]),t._v("\n")])])]),s("h3",{attrs:{id:"归约操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#归约操作符"}},[t._v("#")]),t._v(" 归约操作符")]),t._v(" "),s("p",[t._v("归约操作符包括：归约与（&），归约与非（~&），归约或（|），归约或非（~|），归约异或（^），归约同或（~^）。")]),t._v(" "),s("p",[t._v("归约操作符只有一个操作数，它对这个向量操作数逐位进行操作，最终产生一个 1bit 结果。")]),t._v(" "),s("p",[t._v("逻辑操作符、按位操作符和归约操作符都使用相同的符号表示，因此有时候容易混淆。区分这些操作符的关键是分清操作数的数目，和计算结果的规则。")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'b1010")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("&")]),t._v("A "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 1 & 0 & 1 & 0 = 1'b0，可用来判断变量A是否全1")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("~|")]),t._v("A "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 ~(1 | 0 | 1 | 0) = 1'b0, 可用来判断变量A是否为全0")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("^")]),t._v("A "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 1 ^ 0 ^ 1 ^ 0 = 1'b0")]),t._v("\n")])])]),s("h3",{attrs:{id:"移位操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#移位操作符"}},[t._v("#")]),t._v(" 移位操作符")]),t._v(" "),s("p",[t._v("移位操作符包括左移（<<），右移（>>），算术左移（<<<），算术右移（>>>）。")]),t._v(" "),s("p",[t._v("移位操作符是双目操作符，两个操作数分别表示要进行移位的向量信号（操作符左侧）与移动的位数（操作符右侧）。")]),t._v(" "),s("p",[t._v("算术左移和逻辑左移时，右边低位会补 0。")]),t._v(" "),s("p",[t._v("逻辑右移时，左边高位会补 0；而算术右移时，左边高位会补充符号位，以保证数据缩小后值的正确性。")]),t._v(" "),s("h2",{attrs:{id:"实例-11"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-11"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'b1100")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nB "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'b0010")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v(">>")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("2")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 4'b0011*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("<<")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 4'b1000*")]),t._v("\nA "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("<<<")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 4'b1000*")]),t._v("\nC "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" B "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("+")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),t._v("A"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v(">>>")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("2")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 2 + (-4/4) = 1, 4'b0001*")]),t._v("\n")])])]),s("h3",{attrs:{id:"拼接操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#拼接操作符"}},[t._v("#")]),t._v(" 拼接操作符")]),t._v(" "),s("p",[t._v("拼接操作符用大括号 {，} 来表示，用于将多个操作数（向量）拼接成新的操作数（向量），信号间用逗号隔开。")]),t._v(" "),s("p",[t._v("拼接符操作数必须指定位宽，常数的话也需要指定位宽。例如：")]),t._v(" "),s("h2",{attrs:{id:"实例-12"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-12"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[t._v("A "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'b1010")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nB "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1'b1")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\nY1 "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("{")]),t._v("B"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(",")]),t._v(" A"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("2")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(",")]),t._v(" A"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(",")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4'h3")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("}")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为Y1='b1100_0011*")]),t._v("\nY2 "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("{")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("4")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("{")]),t._v("B"),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("}")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(",")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("3'd4")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("}")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 Y2=7'b111_1100*")]),t._v("\nY3 "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("{")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("32")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("{")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("1'b0")]),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("}}")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("*")]),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//结果为 Y3=32h0，常用作寄存器初始化时匹配位宽的赋初值*")]),t._v("\n")])])]),s("h3",{attrs:{id:"条件操作符"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#条件操作符"}},[t._v("#")]),t._v(" 条件操作符")]),t._v(" "),s("p",[t._v("条件表达式有 3 个操作符，结构描述如下：")]),t._v(" "),s("div",{staticClass:"language- extra-class"},[s("pre",{pre:!0,attrs:{class:"language-text"}},[s("code",[t._v("condition_expression ? true_expression : false_expression\n")])])]),s("p",[t._v("计算时，如果 condition_expression 为真（逻辑值为 1），则运算结果为 true_expression；如果 condition_expression 为假（逻辑值为 0），则计算结果为 false_expression。")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[s("span",{pre:!0,attrs:{class:"token keyword"}},[t._v("assign")]),t._v(" hsel "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("=")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),t._v("addr"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("9")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("8")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("==")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("2'b0")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" hsel_p1 "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v(" hsel_p2 "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(";")]),t._v("\n"),s("span",{pre:!0,attrs:{class:"token comment"}},[t._v("//当信号 addr 高 2bit 为 0 时，hsel 赋值为 hsel_p1; 否则，将 hsel_p2 赋值给 hsel。")]),t._v("\n")])])]),s("p",[t._v("其实，条件表达式类似于 2 路（或多路）选择器，其描述方式完全可以用 if-else 语句代替。")]),t._v(" "),s("p",[t._v("当然条件操作符也能进行嵌套，完成一个多次选择的逻辑。例如：")]),t._v(" "),s("h2",{attrs:{id:"实例-13"}},[s("a",{staticClass:"header-anchor",attrs:{href:"#实例-13"}},[t._v("#")]),t._v(" 实例")]),t._v(" "),s("div",{staticClass:"language-verilog extra-class"},[s("pre",{pre:!0,attrs:{class:"language-verilog"}},[s("code",[s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("**")]),s("span",{pre:!0,attrs:{class:"token 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punctuation"}},[t._v("(")]),t._v("addr"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("9")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("8")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("]")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("==")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("2'b01")]),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(")")]),t._v(" "),s("span",{pre:!0,attrs:{class:"token operator"}},[t._v("?")]),t._v(" hsel_p2 "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v(":")]),t._v("\n "),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("(")]),t._v("addr"),s("span",{pre:!0,attrs:{class:"token punctuation"}},[t._v("[")]),s("span",{pre:!0,attrs:{class:"token number"}},[t._v("9")]),s("span",{pre:!0,attrs:{class:"token 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It takes no arguments, but returns a list where each element is a tuple of the original elements, and the index (with the first one being zero). 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