From 5c1faa6b9d7c24cc77cace49c7fce1bf7347ed6c Mon Sep 17 00:00:00 2001 From: "Xu, Zefan" Date: Tue, 26 Nov 2024 21:30:26 +0800 Subject: [PATCH] fix(sstc): do not generate intr when writing CSR stimecmp In Difftest, all time interrupts should be generated by DUT and be passed to REF. REF should never generate any time interrupts. In Spike, time interrupts are generated in the following places: (It's easy to find them thorugh mip->backdoor_write_with_mask()) 1. In clint.cc, function clint_t::tick(). 2. In csrs.cc, function time_counter_csr_t::sync(), which is called by 1. 3. In csrs.cc, function stimecmp_csr_t::unlogged_write As we disabled clint in spike-difftest, 1 and 2 will never be used. However, 3 is still working and causes some problem. This patch wraps 3 with #ifndef DIFFTEST to disable it. --- riscv/csrs.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 8cdeb072b..78f4ec49c 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1761,8 +1761,11 @@ stimecmp_csr_t::stimecmp_csr_t(processor_t* const proc, const reg_t addr, const } bool stimecmp_csr_t::unlogged_write(const reg_t val) noexcept { + // When difftesting, ref should never generate any time interrupt. +#ifndef DIFFTEST const reg_t mask = ((state->menvcfg->read() & MENVCFG_STCE) ? MIP_STIP : 0) | ((state->henvcfg->read() & HENVCFG_STCE) ? MIP_VSTIP : 0); state->mip->backdoor_write_with_mask(mask, state->time->read() >= val ? intr_mask : 0); +#endif // DIFFTEST return basic_csr_t::unlogged_write(val); }