DCache: Block the writeback req when the addr matching a valid req in mshr

[bosscharlie]

Bug:

• When two req with different addr x and y enter MissQueue together, req y is real miss req, while req x is AcquireBlock BtoT. Req y receive the resp from L2 first and complete the refill operation by replacing the data block with addr x (decided by plru algorithm). MainPipe will release the data block with addr in writeback queue through req Release BtoN to L2. Addr x receive GrantData with permission toT at last.
• From the view of L2, the req sequence of addr x is: Acquire BtoT -> GrantData toT -> Release BtoN, which is abnormal.

Fix: When a valid req reaches wbq, check if there is any valid mshr with same block_addr. If a mshr is found, block current wbq_req.

[XiangShanRobot]

[Generated by IPC robot]
commit: c5a837f

commit	astar	copy_and_run	coremark	gcc	gromacs	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
c5a837f	1.784	0.458	2.003	1.199	2.920	2.498	2.207	0.928	1.374	1.441	3.153	2.600	2.385	2.956

master branch:

commit	astar	copy_and_run	coremark	gcc	gromacs	lbm	linux	mcf	microbench	milc	namd	povray	wrf	xalancbmk
ae21bd3
16ede6b
3840e44									1.374
2abaf61		0.458	2.003				2.207	0.928	1.374			2.600
b5a614b		0.458	2.003	1.199			2.207	0.928	1.374		3.153	2.600		2.956
4ab7f02		0.458	2.003	1.199	2.920	2.498	2.209	0.928	1.374	1.441	3.153	2.600		2.956
11d5798	1.784	0.458	2.003	1.199	2.920	2.498	2.207	0.928	1.374	1.441	3.153	2.600	2.385	2.956
db00024	1.784	0.458	2.003	1.199	2.920	2.498	2.207	0.928	1.374	1.441	3.153	2.600	2.385	2.956
1d2f6c6	1.784		2.003	1.199	2.920	2.498		0.928	1.374	1.441	3.153		2.385	2.956
94d703a	1.784	0.458	2.003	1.199	2.920	2.498	2.207	0.928	1.374	1.441	3.153	2.600	2.385	2.956