Decode related issue

[vincen-dev]

Before start

• I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the bug

When executing .word 0x6781 instruction to Xiangshan, riscv64-spike-so has an exception, but Xiangshan does not. I think this is a decoding related problem .

Expected behavior

When testing with riscv64-spike-so

When I debug with spike, the .word 0x6781 instruction corresponds to c.lui a5, 0x0

In addition, I don't know if nemu has such a problem, because when I use nemu as a reference model, the following log message appears:

To Reproduce

.section .text
.globl _start
_start:
   
     li     t0, 0x8000000a0014a00     
     csrw    mstatus, t0
     .word 0x6781

Environment

• XiangShan branch:
• XiangShan commit id: commit f12520c (HEAD -> master, origin/master, origin/HEAD)
• NEMU commit id: commit: ff37164781e23336ea7fc70f7bf7ea006ee9fbbc
• SPIKE commit id:
• ready-to-run:commit 3575e659bf3a1ed0e0de74bcef848b9be666725b (HEAD, origin/master, origin/HEAD)

Additional context

No response