Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

How did Xiangshan achieve 10Mhz uart_16550? #3666

Open
3 tasks done
LOCKEDGATE opened this issue Sep 27, 2024 · 2 comments
Open
3 tasks done

How did Xiangshan achieve 10Mhz uart_16550? #3666

LOCKEDGATE opened this issue Sep 27, 2024 · 2 comments
Labels
problem Problem requiring help

Comments

@LOCKEDGATE
Copy link

Before start

  • I have read the XiangShan Documents. 我已经阅读过香山文档。
  • I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue,并没有找到相关的。
  • I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions,并没有找到相关的。

Describe you problem

如下图所示,uart_16550的axi clock frequency最低支持到25Mhz。但是我也成功跑通了xiangshan 10M的bitfile,我想了解是怎么修改的uart_16550才能够实现让其能够接收低于25M的主时钟?
As shown in the figure below, the minimum supported axi clock frequency of uart_16550 is 25Mhz. But I also successfully ran the xiangshan 10M bitfile. I want to know how to modify uart_16550 to enable it to receive the main clock below 25M?
1727399145597

What did you do before

as above

Environment

  • XiangShan branch:
  • XiangShan commit id:
  • NEMU commit id:
  • SPIKE commit id:
  • Operating System:
  • gcc version:
  • mill version:
  • java version:

Additional context

No response

@LOCKEDGATE LOCKEDGATE added the problem Problem requiring help label Sep 27, 2024
@Tang-Haojin
Copy link
Member

Excuse me for the late reply. We actually wire a seperate 50MHz clock over UART, which is not affected by core or SoC frequency.

@LOCKEDGATE
Copy link
Author

I am sorry that it took me so long to reply to you. In my original project, I directly used uart 16550, as shown in Figure 1, and it was able to run through at this time. In order to give the uart a separate clock, I found the relevant design of Xiangshan to handle this. I designed the block design according to Xiangshan's method as shown in Figure 2, which only has three modules: axi interconnect, uart 16650 and xlconstant. I instantiated the wrapper generated by the block design in the code, as shown in Figure 3. I connected the pins in Figure 1 to Figure 3. The interfaces of the two are almost the same, except that a few signals such as S00_AXI_0_arprot are not in Figure 1. I assigned all these signals to 0, but Xiangshan seems to have other logic for these pins. The current situation is that I can't run it through according to the design in Figure 3. Is it because my pins are connected incorrectly, or is the value of my signal incorrect? I am looking forward to your reply.
image
image
image

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
problem Problem requiring help
Projects
None yet
Development

No branches or pull requests

2 participants