Problems about Load-Load Violation (CoPP Violation) in Xiangshan

[diantaowang]

When I read the micro-architecture description of Xiangshan and tied to figure out how to detect and slove the load-load violation in load pipeline, I can't understand some of the explanations in the official documentation.

Firstly, let's formalize the problem we need to solve -- the famous Coherence Read-Read (CoRR) problem.

hart0	hart 1
(a) ld t0, 0(s0)	(c) li t0, 1
(b) ld t1, 0(s0)	(d) sd t0, 0(s0)

The possible global memory order is (b)(d)(a), which leads to the result t0=1,t1=0 that is prohibited by RVWMO. There is a puzzling sentence in the Microarchitecture->Memory Access Subsystem->LSQ（微架构->访存子系统->LSQ） section of official documentation.

Problem 1

如果发现之后的 load 拿到了更老的结果 (即已经被 release), 从这条 load 开始重新执行.

“这条指令” refers to which load instaruction: (a) or (b)? And I think it refers to (b).

Problem 2

I assume:

• proble write meta in S0 cycle means: data is given in the S0 cycle and written on the rising edge of the clock from S0 to S1.
• load read meta in S0 cycle means: address is given in S0 cycle, and latched on the rising edge of the clock from S0 to S1, and returns data on S1.

Confusions:

• In case 1, why can instruction (b) be reissued from the issue queue (or reservation station) instead of triggering a rollback? Doesn't instruction (b) leave the issue queue?
• In case 2, DCache-Meta is implemented as a single-port SRAM, and a write request will invalidate the read request of the same cycle. The read request in case-2 should be blocked for one beat, and then get the new meta. Why does the image show that load gets the old meta?
• In case 3, the dcache release signal has not yet been delivered to the load queue. How can we detect the load-load violation?
• Why does a load-load violation not trigger redirection immediately, but waits for the load instruction to become the oldest instruction in the ROB?