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Because we employ a very small table for SMS and a PC-only index requires less storage than PC+index. [1] Jiang, S., Yang, Q., & Ci, Y. (2022). Merging Similar Patterns for Hardware Prefetching. Proceedings of the Annual International Symposium on Microarchitecture, MICRO, 2022-Octob, 1012–1026. https://doi.org/10.1109/MICRO56248.2022.00071 |
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Hi, I've got a question about SMS prefetching algorithm attached to L1D:
SMS in Xiangshan only uses hashed PC, instead of PC+Offset, to tag and index PHT:
XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
Lines 96 to 104 in 31fae68
but this could cause pattern aliasing (i.e., the same PC is correlated to different trigger offsets), thus is less accurate because it cannot distinguish among distinct access patterns to different data structures by the same code (i.e., PC), as the original paper (Spatial Memory Streaming, Somogyi, et.al., 2006) said. Is there any special considerations or additional performance evaluations?
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