From cc89a8a9c6a9b40495c48a5fc0668bad4d49c553 Mon Sep 17 00:00:00 2001 From: Tang Haojin Date: Mon, 18 Nov 2024 23:35:32 +0800 Subject: [PATCH] fix(vstart): fix vstart wrong update when other instruction handling interrupt (#3887) --- src/main/scala/xiangshan/backend/rob/Rob.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala index 04df187914..8aacd68b29 100644 --- a/src/main/scala/xiangshan/backend/rob/Rob.scala +++ b/src/main/scala/xiangshan/backend/rob/Rob.scala @@ -688,8 +688,8 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP vecExcpInfo.bits.vstart := exceptionDataRead.bits.vstart } - io.csr.vstart.valid := RegNext(Mux(exceptionHappen, exceptionDataRead.bits.vstartEn, resetVstart)) - io.csr.vstart.bits := RegNext(Mux(exceptionHappen, exceptionDataRead.bits.vstart, 0.U)) + io.csr.vstart.valid := RegNext(Mux(exceptionHappen && deqHasException, exceptionDataRead.bits.vstartEn, resetVstart)) + io.csr.vstart.bits := RegNext(Mux(exceptionHappen && deqHasException, exceptionDataRead.bits.vstart, 0.U)) val vxsat = Wire(Valid(Bool())) vxsat.valid := io.commits.isCommit && vxsat.bits