fix(critical-error): critical-error pass early then trap

* critical-error diff REF as xiangshan pass criticial-error too early * bump difftest to make critical_error more prominent
OpenXiangShan · Nov 18, 2024 · 9c2c99a · 9c2c99a
1 parent cfa1639
commit 9c2c99a
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/difftest b/difftest
diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
@@ -1372,6 +1372,11 @@ class NewCSR(implicit val p: Parameters) extends Module
       diffArchEvent.exceptionInst := RegEnable(io.fromRob.trap.bits.instr, hasTrap)
     }
 
+    val diffCriticalErrorEvent = DifftestModule(new DiffCriticalErrorEvent, delay = 4, dontCare = true)
+    diffCriticalErrorEvent.valid := io.status.criticalErrorState && trapValid
+    diffCriticalErrorEvent.coreid := hartId
+    diffCriticalErrorEvent.criticalError := io.status.criticalErrorState
+
     val diffCSRState = DifftestModule(new DiffCSRState)
     diffCSRState.coreid         := hartId
     diffCSRState.privilegeMode  := privState.PRVM.asUInt

diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala
@@ -1489,11 +1489,6 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
       difftest.code := trapCode
       difftest.pc := trapPC
     }
-
-    val diffCriticalErrorEvent = DifftestModule(new DiffCriticalErrorEvent)
-    diffCriticalErrorEvent.valid := criticalErrorState && !RegNext(criticalErrorState)
-    diffCriticalErrorEvent.coreid := io.hartId
-    diffCriticalErrorEvent.criticalError := criticalErrorState
   }
 
   //store evetn difftest information