From 3b733a2b6d9ced14077cf28781a48d5d02ba81bd Mon Sep 17 00:00:00 2001 From: chengguanghui Date: Fri, 15 Nov 2024 16:41:48 +0800 Subject: [PATCH] fix(xtval): fix selection of tval for trap --- .../backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala | 10 ++++------ .../backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala | 10 ++++------ .../backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala | 9 ++++----- 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala index 8b796c5862..dab9b3629a 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala @@ -84,12 +84,10 @@ class TrapEntryHSEventModule(implicit val p: Parameters) extends Module with CSR private val tvalFillInst = isIllegalInst private val tval = Mux1H(Seq( - (tvalFillPc ) -> trapPC, - (tvalFillPcPlus2 ) -> (trapPC + 2.U), - (tvalFillMemVaddr && !memIsVirt ) -> trapMemVA, - (tvalFillMemVaddr && memIsVirt ) -> trapMemVA, - (isLSGuestExcp ) -> trapMemVA, - (tvalFillInst ) -> trapInst, + (tvalFillPc ) -> trapPC, + (tvalFillPcPlus2 ) -> (trapPC + 2.U), + (tvalFillMemVaddr || isLSGuestExcp ) -> trapMemVA, + (tvalFillInst ) -> trapInst, )) private val tval2 = Mux1H(Seq( diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala index 0c7f8f21d8..682af498f4 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala @@ -81,12 +81,10 @@ class TrapEntryMEventModule(implicit val p: Parameters) extends Module with CSRE private val tvalFillInst = isIllegalInst private val tval = Mux1H(Seq( - (tvalFillPc ) -> trapPC, - (tvalFillPcPlus2 ) -> (trapPC + 2.U), - (tvalFillMemVaddr && !memIsVirt ) -> trapMemVA, - (tvalFillMemVaddr && memIsVirt ) -> trapMemVA, - (isLSGuestExcp ) -> trapMemVA, - (tvalFillInst ) -> trapInst, + (tvalFillPc ) -> trapPC, + (tvalFillPcPlus2 ) -> (trapPC + 2.U), + (tvalFillMemVaddr || isLSGuestExcp ) -> trapMemVA, + (tvalFillInst ) -> trapInst, )) private val tval2 = Mux1H(Seq( diff --git a/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala b/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala index ec7a62ceb9..8a82a141ee 100644 --- a/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala +++ b/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala @@ -92,11 +92,10 @@ class TrapEntryVSEventModule(implicit val p: Parameters) extends Module with CSR private val tvalFillInst = isIllegalInst private val tval = Mux1H(Seq( - (tvalFillPc ) -> trapPC, - (tvalFillPcPlus2 ) -> (trapPC + 2.U), - (tvalFillMemVaddr && !memIsVirt ) -> trapMemVA, - (tvalFillMemVaddr && memIsVirt ) -> trapMemVA, - (tvalFillInst ) -> trapInst, + tvalFillPc -> trapPC, + tvalFillPcPlus2 -> (trapPC + 2.U), + tvalFillMemVaddr -> trapMemVA, + tvalFillInst -> trapInst, )) private val instrAddrTransType = AddrTransType(