diff --git a/src/hal/ingenic_reginfo.h b/src/hal/ingenic_reginfo.h new file mode 100644 index 0000000..1348242 --- /dev/null +++ b/src/hal/ingenic_reginfo.h @@ -0,0 +1,227 @@ +#ifndef HAL_INGENIC_REGINFO_H +#define HAL_INGENIC_REGINFO_H + +#include "reginfo.h" + +MUXCTRL(T31_reg0, 0x10010000, "PAPIN") +MUXCTRL(T31_reg1, 0x10010010, "PAINT") +MUXCTRL(T31_reg2, 0x10010014, "PAINTS") +MUXCTRL(T31_reg3, 0x10010018, "PAINTC") +MUXCTRL(T31_reg4, 0x10010020, "PAMSK") +MUXCTRL(T31_reg5, 0x10010024, "PAMSKS") +MUXCTRL(T31_reg6, 0x10010028, "PAMSKC") +MUXCTRL(T31_reg7, 0x10010030, "PAPAT1") +MUXCTRL(T31_reg8, 0x10010034, "PAPAT1S") +MUXCTRL(T31_reg9, 0x10010038, "PAPAT1C") +MUXCTRL(T31_reg10, 0x10010040, "PAPAT0") +MUXCTRL(T31_reg11, 0x10010044, "PAPAT0S") +MUXCTRL(T31_reg12, 0x10010048, "PAPAT0C") +MUXCTRL(T31_reg13, 0x10010050, "PAFLG") +MUXCTRL(T31_reg14, 0x10010058, "PAFLGC") +MUXCTRL(T31_reg15, 0x10010070, "PAGFCFG0") +MUXCTRL(T31_reg16, 0x10010074, "PAGFCFG0S") +MUXCTRL(T31_reg17, 0x10010078, "PAGFCFG0C") +MUXCTRL(T31_reg18, 0x10010080, "PAGFCFG1") +MUXCTRL(T31_reg19, 0x10010084, "PAGFCFG1S") +MUXCTRL(T31_reg20, 0x10010088, "PAGFCFG1C") +MUXCTRL(T31_reg21, 0x10010090, "PAGFCFG2") +MUXCTRL(T31_reg22, 0x10010094, "PAGFCFG2S") +MUXCTRL(T31_reg23, 0x10010098, "PAGFCFG2C") +MUXCTRL(T31_reg24, 0x100100A0, "PAGFCFG3") +MUXCTRL(T31_reg25, 0x100100A4, "PAGFCFG3S") +MUXCTRL(T31_reg26, 0x100100A8, "PAGFCFG3C") +MUXCTRL(T31_reg27, 0x10010110, "PAPUEN") +MUXCTRL(T31_reg28, 0x10010114, "PAPUENS") +MUXCTRL(T31_reg29, 0x10010118, "PAPUENC") +MUXCTRL(T31_reg30, 0x10010120, "PAPDEN") +MUXCTRL(T31_reg31, 0x10010124, "PAPDENS") +MUXCTRL(T31_reg32, 0x10010128, "PAPDENC") +MUXCTRL(T31_reg33, 0x10010130, "PAPDRVL") +MUXCTRL(T31_reg34, 0x10010134, "PAPDRVLS") +MUXCTRL(T31_reg35, 0x10010138, "PAPDRVLC") +MUXCTRL(T31_reg36, 0x10010140, "PAPDRVH") +MUXCTRL(T31_reg37, 0x10010144, "PAPDRVHS") +MUXCTRL(T31_reg38, 0x10010148, "PAPDRVHC") +MUXCTRL(T31_reg39, 0x10010150, "PAPSLW") +MUXCTRL(T31_reg40, 0x10010154, "PAPSLWS") +MUXCTRL(T31_reg41, 0x10010158, "PAPSLWC") +MUXCTRL(T31_reg42, 0x10010160, "PAPSMT") +MUXCTRL(T31_reg43, 0x10010164, "PAPSMTS") +MUXCTRL(T31_reg44, 0x10010168, "PAPSMTC") +MUXCTRL(T31_reg45, 0x10011000, "PBPIN") +MUXCTRL(T31_reg46, 0x10011010, "PBINT") +MUXCTRL(T31_reg47, 0x10011014, "PBINTS") +MUXCTRL(T31_reg48, 0x10011018, "PBINTC") +MUXCTRL(T31_reg49, 0x10011020, "PBMSK") +MUXCTRL(T31_reg50, 0x10011024, "PBMSKS") +MUXCTRL(T31_reg51, 0x10011028, "PBMSKC") +MUXCTRL(T31_reg52, 0x10011030, "PBPAT1") +MUXCTRL(T31_reg53, 0x10011034, "PBPAT1S") +MUXCTRL(T31_reg54, 0x10011038, "PBPAT1C") +MUXCTRL(T31_reg55, 0x10011040, "PBPAT0") +MUXCTRL(T31_reg56, 0x10011044, "PBPAT0S") +MUXCTRL(T31_reg57, 0x10011048, "PBPAT0C") +MUXCTRL(T31_reg58, 0x10011050, "PBFLG") +MUXCTRL(T31_reg59, 0x10011058, "PBFLGC") +MUXCTRL(T31_reg60, 0x10011070, "PBGFCFG0") +MUXCTRL(T31_reg61, 0x10011074, "PBGFCFG0S") +MUXCTRL(T31_reg62, 0x10011078, "PBGFCFG0C") +MUXCTRL(T31_reg63, 0x10011080, "PBGFCFG1") +MUXCTRL(T31_reg64, 0x10011084, "PBGFCFG1S") +MUXCTRL(T31_reg65, 0x10011088, "PBGFCFG1C") +MUXCTRL(T31_reg66, 0x10011090, "PBGFCFG2") +MUXCTRL(T31_reg67, 0x10011094, "PBGFCFG2S") +MUXCTRL(T31_reg68, 0x10011098, "PBGFCFG2C") +MUXCTRL(T31_reg69, 0x100110A0, "PBGFCFG3") +MUXCTRL(T31_reg70, 0x100110A4, "PBGFCFG3S") +MUXCTRL(T31_reg71, 0x100110A8, "PBGFCFG3C") +MUXCTRL(T31_reg72, 0x10011110, "PBPUEN") +MUXCTRL(T31_reg73, 0x10011114, "PBPUENS") +MUXCTRL(T31_reg74, 0x10011118, "PBPUENC") +MUXCTRL(T31_reg75, 0x10011120, "PBPDEN") +MUXCTRL(T31_reg76, 0x10011124, "PBPDENS") +MUXCTRL(T31_reg77, 0x10011128, "PBPDENC") +MUXCTRL(T31_reg78, 0x10011130, "PBPDRVL") +MUXCTRL(T31_reg79, 0x10011134, "PBDRVLS") +MUXCTRL(T31_reg80, 0x10011138, "PBDRVLC") +MUXCTRL(T31_reg81, 0x10011140, "PBDRVH") +MUXCTRL(T31_reg82, 0x10011144, "PBDRVHS") +MUXCTRL(T31_reg83, 0x10011148, "PBDRVHC") +MUXCTRL(T31_reg84, 0x10011150, "PBSLW") +MUXCTRL(T31_reg85, 0x10011154, "PBSLWS") +MUXCTRL(T31_reg86, 0x10011158, "PBSLWC") +MUXCTRL(T31_reg87, 0x10011160, "PBSMT") +MUXCTRL(T31_reg88, 0x10011164, "PBSMTS") +MUXCTRL(T31_reg89, 0x10011168, "PBSMTC") +MUXCTRL(T31_reg90, 0x10012000, "PCPIN") +MUXCTRL(T31_reg91, 0x10012010, "PCINT") +MUXCTRL(T31_reg92, 0x10012014, "PCINTS") +MUXCTRL(T31_reg93, 0x10012018, "PCINTC") +MUXCTRL(T31_reg94, 0x10012020, "PCMSK") +MUXCTRL(T31_reg95, 0x10012024, "PCMSKS") +MUXCTRL(T31_reg96, 0x10012028, "PCMSKC") +MUXCTRL(T31_reg97, 0x10012030, "PCPAT1") +MUXCTRL(T31_reg98, 0x10012034, "PCPAT1S") +MUXCTRL(T31_reg99, 0x10012038, "PCPAT1C") +MUXCTRL(T31_reg100, 0x10012040, "PCPAT0") +MUXCTRL(T31_reg101, 0x10012044, "PCPAT0S") +MUXCTRL(T31_reg102, 0x10012048, "PCPAT0C") +MUXCTRL(T31_reg103, 0x10012050, "PCFLG") +MUXCTRL(T31_reg104, 0x10012058, "PCFLGC") +MUXCTRL(T31_reg105, 0x10012070, "PCGFCFG0") +MUXCTRL(T31_reg106, 0x10012074, "PCGFCFG0S") +MUXCTRL(T31_reg107, 0x10012078, "PCGFCFG0C") +MUXCTRL(T31_reg108, 0x10012080, "PCGFCFG1") +MUXCTRL(T31_reg109, 0x10012084, "PCGFCFG1S") +MUXCTRL(T31_reg110, 0x10012088, "PCGFCFG1C") +MUXCTRL(T31_reg111, 0x10012090, "PCGFCFG2") +MUXCTRL(T31_reg112, 0x10012094, "PCGFCFG2S") +MUXCTRL(T31_reg113, 0x10012098, "PCGFCFG2C") +MUXCTRL(T31_reg114, 0x100120A0, "PCGFCFG3") +MUXCTRL(T31_reg115, 0x100120A4, "PCGFCFG3S") +MUXCTRL(T31_reg116, 0x100120A8, "PCGFCFG3C") +MUXCTRL(T31_reg117, 0x10012110, "PCPUEN") +MUXCTRL(T31_reg118, 0x10012114, "PCPUENS") +MUXCTRL(T31_reg119, 0x10012118, "PCPUENC") +MUXCTRL(T31_reg120, 0x10012120, "PCPDEN") +MUXCTRL(T31_reg121, 0x10012124, "PCPDENS") +MUXCTRL(T31_reg122, 0x10012128, "PCPDENC") +MUXCTRL(T31_reg123, 0x10012130, "PCDRVL") +MUXCTRL(T31_reg124, 0x10012134, "PCDRVLS") +MUXCTRL(T31_reg125, 0x10012138, "PCDRVLC") +MUXCTRL(T31_reg126, 0x10012140, "PCDRVH") +MUXCTRL(T31_reg127, 0x10012144, "PCDRVHS") +MUXCTRL(T31_reg128, 0x10012148, "PCDRVHC") +MUXCTRL(T31_reg129, 0x10012150, "PCSLW") +MUXCTRL(T31_reg130, 0x10012154, "PCSLWS") +MUXCTRL(T31_reg131, 0x10012158, "PCSLWC") +MUXCTRL(T31_reg132, 0x10012160, "PCSMT") +MUXCTRL(T31_reg133, 0x10012164, "PCSMTS") +MUXCTRL(T31_reg134, 0x10012168, "PCSMTC") +MUXCTRL(T31_reg135, 0x10017014, "PZINTS") +MUXCTRL(T31_reg136, 0x10017018, "PZINTC") +MUXCTRL(T31_reg137, 0x10017024, "PZMSKS") +MUXCTRL(T31_reg138, 0x10017028, "PZMSKC") +MUXCTRL(T31_reg139, 0x10017034, "PZPAT1S") +MUXCTRL(T31_reg140, 0x10017038, "PZPAT1C") +MUXCTRL(T31_reg141, 0x10017044, "PZPAT0S") +MUXCTRL(T31_reg142, 0x10017048, "PZPAT0C") +MUXCTRL(T31_reg143, 0x100170F0, "PZGID2LD") + +static const muxctrl_reg_t *T31_regs[] = { + &T31_reg0, &T31_reg1, + &T31_reg2, &T31_reg3, + &T31_reg4, &T31_reg5, + &T31_reg6, &T31_reg7, + &T31_reg8, &T31_reg9, + &T31_reg10, &T31_reg11, + &T31_reg12, &T31_reg13, + &T31_reg14, &T31_reg15, + &T31_reg16, &T31_reg17, + &T31_reg18, &T31_reg19, + &T31_reg20, &T31_reg21, + &T31_reg22, &T31_reg23, + &T31_reg24, &T31_reg25, + &T31_reg26, &T31_reg27, + &T31_reg28, &T31_reg29, + &T31_reg30, &T31_reg31, + &T31_reg32, &T31_reg33, + &T31_reg34, &T31_reg35, + &T31_reg36, &T31_reg37, + &T31_reg38, &T31_reg39, + &T31_reg40, &T31_reg41, + &T31_reg42, &T31_reg43, + &T31_reg44, &T31_reg45, + &T31_reg46, &T31_reg47, + &T31_reg48, &T31_reg49, + &T31_reg50, &T31_reg51, + &T31_reg52, &T31_reg53, + &T31_reg54, &T31_reg55, + &T31_reg56, &T31_reg57, + &T31_reg58, &T31_reg59, + &T31_reg60, &T31_reg61, + &T31_reg62, &T31_reg63, + &T31_reg64, &T31_reg65, + &T31_reg66, &T31_reg67, + &T31_reg68, &T31_reg69, + &T31_reg70, &T31_reg71, + &T31_reg72, &T31_reg73, + &T31_reg74, &T31_reg75, + &T31_reg76, &T31_reg77, + &T31_reg78, &T31_reg79, + &T31_reg80, &T31_reg81, + &T31_reg82, &T31_reg83, + &T31_reg84, &T31_reg85, + &T31_reg86, &T31_reg87, + &T31_reg88, &T31_reg89, + &T31_reg90, &T31_reg91, + &T31_reg92, &T31_reg93, + &T31_reg94, &T31_reg95, + &T31_reg96, &T31_reg97, + &T31_reg98, &T31_reg99, + &T31_reg100, &T31_reg101, + &T31_reg102, &T31_reg103, + &T31_reg104, &T31_reg105, + &T31_reg106, &T31_reg107, + &T31_reg108, &T31_reg109, + &T31_reg110, &T31_reg111, + &T31_reg112, &T31_reg113, + &T31_reg114, &T31_reg115, + &T31_reg116, &T31_reg117, + &T31_reg118, &T31_reg119, + &T31_reg120, &T31_reg121, + &T31_reg122, &T31_reg123, + &T31_reg124, &T31_reg125, + &T31_reg126, &T31_reg127, + &T31_reg128, &T31_reg129, + &T31_reg130, &T31_reg131, + &T31_reg132, &T31_reg133, + &T31_reg134, &T31_reg135, + &T31_reg136, &T31_reg137, + &T31_reg138, &T31_reg139, + &T31_reg140, &T31_reg141, + &T31_reg142, &T31_reg143, + 0, +}; + +#endif diff --git a/src/reginfo.c b/src/reginfo.c index 13a0133..156a185 100644 --- a/src/reginfo.c +++ b/src/reginfo.c @@ -1,6 +1,8 @@ #include "reginfo.h" #include "chipid.h" #include "hal/hisi/hal_hisi.h" +#include "hal/ingenic.h" +#include "hal/ingenic_reginfo.h" #include "hal/sstar.h" #include "hal/sstar_reginfo.h" #include "tools.h" @@ -2201,12 +2203,15 @@ static const muxctrl_reg_t **regs_by_chip() { return I6C_regs; case INFINITY6E: return I6E_regs; + case T31: + return T31_regs; } fprintf(stderr, "Platform is not supported\n"); exit(EXIT_FAILURE); } static int dump_regs(bool script_mode) { + const char *vendor = getchipvendor(); const muxctrl_reg_t **regs = regs_by_chip(); for (int reg_num = 0; regs[reg_num]; reg_num++) { @@ -2221,7 +2226,12 @@ static int dump_regs(bool script_mode) { continue; } - val &= 0xf; + if (strstr(vendor, VENDOR_HISI) || strstr(vendor, VENDOR_GOKE)) { + val &= 0xf; + } else if (strstr(vendor, VENDOR_SSTAR)) { + val &= 0xffff; + } + printf("muxctrl_reg%d %#x %#x", reg_num, regs[reg_num]->address, val); show_function(regs[reg_num]->funcs, val); }