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nvme.c
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nvme.c
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/*
* QEMU NVM Express Controller
*
* Copyright (c) 2012, Intel Corporation
*
* Written by Keith Busch <[email protected]>
*
* This code is licensed under the GNU GPL v2 or later.
*/
/**
* Reference Specs: http://www.nvmexpress.org, 1.2, 1.1, 1.0e
*
* http://www.nvmexpress.org/resources/
*/
/**
* Usage: add options:
* -drive file=<file>,if=none,id=<drive_id>
* -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>
*
* The "file" option must point to a path to a real file that you will use as
* the backing storage for your NVMe device. It must be a non-zero length, as
* this will be the disk image that your nvme controller will use to carve up
* namespaces for storage.
*
* Note the "drive" option's "id" name must match the "device nvme" drive's
* name to link the block device used for backing storage to the nvme
* interface.
*
* Advanced optional options:
*
* namespaces=<int> : Namespaces to make out of the backing storage,
* Default:1
* num_queues=<int> : Number of possible IO Queues, Default:64
* cmb_size_mb=<int> : Size of CMB in MBs, Default:0
* entries=<int> : Maximum number of Queue entires possible,
* Default:0x7ff
* max_cqes=<int> : Maximum completion queue entry size, Default:0x4
* max_sqes=<int> : Maximum submission queue entry size, Default:0x6
* mpsmin=<int> : Minimum page size supported, Default:0
* mpsmax=<int> : Maximum page size supported, Default:0
* stride=<int> : Doorbell stride, Default:0
* aerl=<int> : Async event request limit, Default:3
* acl=<int> : Abort command limit, Default:3
* elpe=<int> : Error log page entries, Default:3
* mdts=<int> : Maximum data transfer size, Default:7
* cqr=<int> : Contiguous queues required, Default:1
* vwc=<int> : Volatile write cache enabled, Default:0
* intc=<int> : Interrupt configuration disabled, Default:0
* intc_thresh=<int> : Interrupt coalesce threshold, Default:0
* intc_ttime=<int> : Interrupt coalesce time 100's of usecs, Default:0
* extended=<int> : Use extended-lba for meta-data, Default:0
* dpc=<int> : Data protection capabilities, Default:0
* dps=<int> : Data protection settings, Default:0
* mc=<int> : Meta-data capabilities, Default:0x2
* ms=<int> : Meta-data size in bytes, Default:16, Max:64
* ms_max=<int> : Maximum meta-data size in bytes, Default:64
* dlfeat=<int> : Control DLFEAT, Default:0x1
* oncs=<oncs> : Optional NVMe command support, Default:DSM
* oacs=<oacs> : Optional Admin command support, Default:Format
* dialect=<dialect> : Set the dialect to implement, Default: 0x1,
* Supported: {0x0: NVMe v1.3, 0x1: OCSSD v2.0}
*
* LightNVM specific options:
*
* lmccap=<int> : Media and Controller Capabilities (MCCAP),
* Default:0
* lws_min=<int> : Mininum write size for device in sectors,
* Default:4
* lws_opt=<int> : Optimal write size for device in sectors,
* Default:8
* lmw_cunits=<int> : Number of written sectors required in chunk before
* read, Default:32
* lchunkstate=<file> : Load state table from file destination (Provide
* path to file. If no file is provided a state table
* will be generated.
* lchunkinfo_size : Size of the chunk info log page.
* Default:4194304 (4 MB)
* lresetfail=<file> : Reset fail injection configuration file.
* lwritefail=<file> : Write fail injection configuration file.
* ldebug : Enable LightNVM debugging, Default:0 (disabled)
* learly_reset : Allow early resets (reset open chunks),
* Default:1 (enabled)
* lsgl_lbal : If DPTR is an SGL, interpret LBAL as an SGL too,
* Default:0 (disabled)
*
* Parameters will be verified against conflicting capabilities and attributes
* and fail to load if there is a conflict or a configuration the emulated
* device is unable to handle.
*
* Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
* offset 0 in BAR2 and supports only WDS, RDS and SQS for now.
*
*/
/**
* Hot-plug support
*
* To hot add a new nvme device, startup the qemu monitor. The easiest way is
* to add '-monitor stdio' option on your startup. At the monitor command line,
* run:
*
* (qemu) drive_add "" if=none,id=<new_drive_id>,file=</path/to/backing/file>
* (qemu) device_add nvme,drive=<new_drive_id>,serial=<serial>,id=<new_id>[,<optional options>]
*
* To hot remove the device, run:
*
* (qemu) device_del <id>
*
* You must have provided the "id" field for device_del to work. You may query
* the available devices by running "info pci" from the qemu monitor.
*
* To query what disks are available to be used as a backing storage, run "info
* block". You cannot assign the same block device to more than one storage
* interface.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/block/block.h"
#include "hw/hw.h"
#include "hw/pci/msix.h"
#include "hw/pci/pci.h"
#include "sysemu/sysemu.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "sysemu/block-backend.h"
#include "qemu/log.h"
#include "qemu/cutils.h"
#include "trace.h"
#include "nvme.h"
#include "lightnvm.h"
#define NVME_MAX_QS PCI_MSIX_FLAGS_QSIZE
#define NVME_MAX_QUEUE_ENTRIES 0xffff
#define NVME_MAX_STRIDE 12
#define NVME_MAX_NUM_NAMESPACES 256
#define NVME_MAX_QUEUE_ES 0xf
#define NVME_MIN_CQUEUE_ES 0x4
#define NVME_MIN_SQUEUE_ES 0x6
#define NVME_SPARE_THRESHOLD 20
#define NVME_TEMPERATURE 0x143
#define NVME_OP_ABORTED 0xff
#define NVME_DIALECT_NVME13 0x0
#define NVME_DIALECT_OCSSD20 0x1
#define NVME_GUEST_ERR(trace, fmt, ...) \
do { \
(trace_##trace)(__VA_ARGS__); \
qemu_log_mask(LOG_GUEST_ERROR, #trace \
" in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
} while (0)
static void nvme_process_sq(void *opaque);
static inline uint8_t nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr)
{
return n->cmbsz && addr >= n->ctrl_mem.addr &&
addr < n ->ctrl_mem.addr + int128_get64(n->ctrl_mem.size);
}
void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
if (nvme_addr_is_cmb(n, addr)) {
memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size);
return;
}
pci_dma_read(&n->parent_obj, addr, buf, size);
}
void nvme_addr_write(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
if (nvme_addr_is_cmb(n, addr)) {
memcpy((void *)&n->cmbuf[addr - n->ctrl_mem.addr], buf, size);
return;
}
pci_dma_write(&n->parent_obj, addr, buf, size);
}
static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
{
return sqid < n->params.num_queues && n->sq[sqid] != NULL ? 0 : -1;
}
static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
{
return cqid < n->params.num_queues && n->cq[cqid] != NULL ? 0 : -1;
}
static void nvme_inc_cq_tail(NvmeCQueue *cq)
{
cq->tail++;
if (cq->tail >= cq->size) {
cq->tail = 0;
cq->phase = !cq->phase;
}
}
static int nvme_cqes_pending(NvmeCQueue *cq)
{
return cq->tail > cq->head ?
cq->head + (cq->size - cq->tail) :
cq->head - cq->tail;
}
static void nvme_inc_sq_head(NvmeSQueue *sq)
{
sq->head = (sq->head + 1) % sq->size;
}
static void nvme_update_cq_head(NvmeCQueue *cq)
{
if (cq->db_addr) {
nvme_addr_read(cq->ctrl, cq->db_addr, &cq->head, sizeof(cq->head));
}
}
static uint8_t nvme_cq_full(NvmeCQueue *cq)
{
nvme_update_cq_head(cq);
return (cq->tail + 1) % cq->size == cq->head;
}
static uint8_t nvme_sq_empty(NvmeSQueue *sq)
{
return sq->head == sq->tail;
}
static void nvme_irq_check(NvmeCtrl *n)
{
if (msix_enabled(&(n->parent_obj))) {
return;
}
if (~n->bar.intms & n->irq_status) {
pci_irq_assert(&n->parent_obj);
} else {
pci_irq_deassert(&n->parent_obj);
}
}
static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
{
if (cq->irq_enabled) {
if (msix_enabled(&(n->parent_obj))) {
trace_nvme_irq_msix(cq->vector);
msix_notify(&(n->parent_obj), cq->vector);
} else {
trace_nvme_irq_pin();
assert(cq->cqid < 64);
n->irq_status |= 1 << cq->cqid;
nvme_irq_check(n);
}
} else {
trace_nvme_irq_masked();
}
}
static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq)
{
if (cq->irq_enabled) {
if (msix_enabled(&(n->parent_obj))) {
return;
} else {
assert(cq->cqid < 64);
n->irq_status &= ~(1 << cq->cqid);
nvme_irq_check(n);
}
}
}
static uint64_t *nvme_setup_discontig(NvmeCtrl *n, uint64_t prp_addr,
uint16_t queue_depth, uint16_t entry_size)
{
int i;
uint16_t prps_per_page = n->page_size >> 3;
uint64_t prp[prps_per_page];
uint16_t total_prps = DIV_ROUND_UP(queue_depth * entry_size, n->page_size);
uint64_t *prp_list = g_malloc0_n(total_prps, sizeof(*prp_list));
for (i = 0; i < total_prps; i++) {
if (i % prps_per_page == 0 && i < total_prps - 1) {
if (!prp_addr || prp_addr & (n->page_size - 1)) {
g_free(prp_list);
return NULL;
}
nvme_addr_write(n, prp_addr, (uint8_t *)&prp, sizeof(prp));
prp_addr = le64_to_cpu(prp[prps_per_page - 1]);
}
prp_list[i] = le64_to_cpu(prp[i % prps_per_page]);
if (!prp_list[i] || prp_list[i] & (n->page_size - 1)) {
g_free(prp_list);
return NULL;
}
}
return prp_list;
}
void nvme_set_error_page(NvmeCtrl *n, uint16_t sqid, uint16_t cid,
uint16_t status, uint16_t location, uint64_t lba, uint32_t nsid)
{
NvmeErrorLog *elp;
elp = &n->elpes[n->elp_index];
elp->error_count = n->error_count++;
elp->sqid = sqid;
elp->cid = cid;
elp->status_field = status;
elp->param_error_location = location;
elp->lba = lba;
elp->nsid = nsid;
n->elp_index = (n->elp_index + 1) % n->params.elpe;
++n->num_errors;
}
static hwaddr nvme_discontig(uint64_t *dma_addr, uint16_t page_size,
uint16_t queue_idx, uint16_t entry_size)
{
uint16_t entries_per_page = page_size / entry_size;
uint16_t prp_index = queue_idx / entries_per_page;
uint16_t index_in_prp = queue_idx % entries_per_page;
return dma_addr[prp_index] + index_in_prp * entry_size;
}
NvmeBlockBackendRequest *nvme_blk_req_new(NvmeCtrl *n, NvmeRequest *req)
{
NvmeBlockBackendRequest *blk_req = g_malloc0(sizeof(*blk_req));
blk_req->req = req;
if (req->cmb) {
qemu_iovec_init(&blk_req->iov, 1);
} else {
pci_dma_sglist_init(&blk_req->qsg, &n->parent_obj, 1);
}
return blk_req;
}
static void nvme_blk_req_destroy(NvmeBlockBackendRequest *blk_req) {
if (blk_req->qsg.nalloc) {
qemu_sglist_destroy(&blk_req->qsg);
}
if (blk_req->iov.nalloc) {
qemu_iovec_destroy(&blk_req->iov);
}
g_free(blk_req);
}
static uint16_t nvme_map_prp(NvmeCtrl *n, QEMUSGList *qsg, uint64_t prp1,
uint64_t prp2, uint32_t len, NvmeRequest *req)
{
hwaddr trans_len = n->page_size - (prp1 % n->page_size);
trans_len = MIN(len, trans_len);
int num_prps = (len >> n->page_bits) + 1;
trace_nvme_map_prp(req->cmd_opcode, trans_len, len, prp1, prp2, num_prps);
if (unlikely(!prp1)) {
trace_nvme_err_invalid_prp();
return NVME_INVALID_FIELD | NVME_DNR;
}
if (nvme_addr_is_cmb(n, prp1)) {
NvmeSQueue *sq = req->sq;
if (!(sq->phys_contig && nvme_addr_is_cmb(n, sq->dma_addr))) {
return NVME_INVALID_USE_OF_CMB | NVME_DNR;
}
req->cmb = true;
} else {
req->cmb = false;
}
pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
qemu_sglist_add(qsg, prp1, trans_len);
len -= trans_len;
if (len) {
if (unlikely(!prp2)) {
trace_nvme_err_invalid_prp2_missing();
goto unmap;
}
if (req->cmb && !nvme_addr_is_cmb(n, prp2)) {
return NVME_INVALID_USE_OF_CMB | NVME_DNR;
}
if (len > n->page_size) {
uint64_t prp_list[n->max_prp_ents];
uint32_t nents, prp_trans;
int i = 0;
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
while (len != 0) {
uint64_t prp_ent = le64_to_cpu(prp_list[i]);
if (req->cmb && !nvme_addr_is_cmb(n, prp_ent)) {
return NVME_INVALID_USE_OF_CMB | NVME_DNR;
}
if (i == n->max_prp_ents - 1 && len > n->page_size) {
if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
trace_nvme_err_invalid_prplist_ent(prp_ent);
goto unmap;
}
i = 0;
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
nvme_addr_read(n, prp_ent, (void *)prp_list, prp_trans);
prp_ent = le64_to_cpu(prp_list[i]);
}
if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
trace_nvme_err_invalid_prplist_ent(prp_ent);
goto unmap;
}
trans_len = MIN(len, n->page_size);
qemu_sglist_add(qsg, prp_ent, trans_len);
len -= trans_len;
i++;
}
} else {
if (unlikely(prp2 & (n->page_size - 1))) {
trace_nvme_err_invalid_prp2_align(prp2);
goto unmap;
}
qemu_sglist_add(qsg, prp2, len);
}
}
return NVME_SUCCESS;
unmap:
qemu_sglist_destroy(qsg);
return NVME_INVALID_FIELD | NVME_DNR;
}
static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *qsg,
NvmeSglDescriptor sgl, uint32_t len, NvmeRequest *req)
{
NvmeSglDescriptor *sgl_descriptors;
uint64_t nsgld;
int cmb = 0;
switch (le64_to_cpu(sgl.generic.type)) {
case SGL_DESCR_TYPE_DATA_BLOCK:
sgl_descriptors = &sgl;
nsgld = 1;
break;
case SGL_DESCR_TYPE_LAST_SEGMENT:
sgl_descriptors = g_malloc0(le64_to_cpu(sgl.unkeyed.len));
nsgld = le64_to_cpu(sgl.unkeyed.len) / sizeof(NvmeSglDescriptor);
if (nvme_addr_is_cmb(n, sgl.addr)) {
cmb = 1;
}
nvme_addr_read(n, le64_to_cpu(sgl.addr), sgl_descriptors,
le64_to_cpu(sgl.unkeyed.len));
break;
default:
return NVME_SGL_DESCRIPTOR_TYPE_INVALID | NVME_DNR;
}
if (nvme_addr_is_cmb(n, le64_to_cpu(sgl_descriptors[0].addr))) {
if (!cmb) {
return NVME_INVALID_USE_OF_CMB | NVME_DNR;
}
req->cmb = true;
} else {
if (cmb) {
return NVME_INVALID_USE_OF_CMB | NVME_DNR;
}
req->cmb = false;
}
pci_dma_sglist_init(qsg, &n->parent_obj, nsgld);
for (int i = 0; i < nsgld; i++) {
uint64_t addr;
uint32_t trans_len;
if (len == 0) {
if (!NVME_CTRL_SGLS_EXCESS_LENGTH(n->sgls)) {
qemu_sglist_destroy(qsg);
return NVME_DATA_SGL_LENGTH_INVALID | NVME_DNR;
}
break;
}
addr = le64_to_cpu(sgl_descriptors[i].addr);
trans_len = MIN(len, le64_to_cpu(sgl_descriptors[i].unkeyed.len));
if (req->cmb && !nvme_addr_is_cmb(n,addr)) {
return NVME_INVALID_USE_OF_CMB | NVME_DNR;
}
qemu_sglist_add(qsg, addr, trans_len);
len -= trans_len;
}
if (nsgld > 1) {
g_free(sgl_descriptors);
}
return NVME_SUCCESS;
}
static uint16_t nvme_blk_setup(NvmeCtrl *n, QEMUSGList *qsg,
uint64_t blk_offset, uint32_t unit_len, NvmeRequest *req)
{
NvmeNamespace *ns = req->ns;
NvmeBlockBackendRequest *blk_req, *blk_req_predef;
size_t curr_offset = 0;
int curr_sge = 0;
uint64_t soffset = n->dialect.blk_idx(n, ns, req->slba);
if (NULL == (blk_req = nvme_blk_req_new(n, req))) {
return NVME_INTERNAL_DEV_ERROR;
}
blk_req->slba = req->slba;
blk_req->nlb = req->nlb;
blk_req->blk_offset = blk_offset + soffset * unit_len;
if (req->is_write || req->predef == -1) {
ScatterGatherEntry *tmp;
if (blk_req->qsg.nalloc < qsg->nsg) {
tmp = g_realloc(blk_req->qsg.sg,
qsg->nalloc * sizeof(ScatterGatherEntry));
if (!tmp) {
nvme_blk_req_destroy(blk_req);
return NVME_INTERNAL_DEV_ERROR;
}
blk_req->qsg.sg = tmp;
}
memcpy(blk_req->qsg.sg, qsg->sg,
qsg->nsg * sizeof(ScatterGatherEntry));
blk_req->qsg.nalloc = qsg->nalloc;
blk_req->qsg.nsg = qsg->nsg;
blk_req->qsg.size = qsg->size;
goto out;
}
blk_req->nlb = req->predef - req->slba;
qemu_sglist_yank(qsg, &blk_req->qsg, &curr_sge, &curr_offset,
blk_req->nlb * unit_len);
if (ns->id_ns.dlfeat) {
for (uint16_t i = 0; i < (req->nlb - blk_req->nlb); i++) {
if (NULL == (blk_req_predef = nvme_blk_req_new(n, req))) {
return NVME_INTERNAL_DEV_ERROR;
}
blk_req_predef->slba = req->predef + i;
blk_req_predef->nlb = 1;
blk_req_predef->blk_offset = NVME_NS_PREDEF_BLK_OFFSET(n, ns);
qemu_sglist_yank(qsg, &blk_req_predef->qsg, &curr_sge,
&curr_offset, unit_len);
QTAILQ_INSERT_TAIL(&req->blk_req_tailq_head, blk_req_predef,
blk_req_tailq);
}
}
out:
QTAILQ_INSERT_TAIL(&req->blk_req_tailq_head, blk_req, blk_req_tailq);
return NVME_SUCCESS;
}
uint16_t nvme_blk_map(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req,
NvmeBlockSetupFn blk_setup)
{
NvmeNamespace *ns = req->ns;
uint16_t err;
QEMUSGList qsg;
NvmeSglDescriptor sgl;
uint32_t unit_len = 1 << NVME_ID_NS_LBADS(ns);
uint32_t len = req->nlb * unit_len;
uint32_t meta_unit_len = NVME_ID_NS_MS(ns);
uint32_t meta_len = req->nlb * meta_unit_len;
if (cmd->psdt) {
err = nvme_map_sgl(n, &qsg, cmd->dptr.sgl, len, req);
if (err) {
nvme_set_error_page(n, req->sq->sqid, req->cqe.cid, err,
offsetof(NvmeRwCmd, dptr.sgl), 0, req->ns->id);
return err;
}
} else {
uint64_t prp1 = le64_to_cpu(cmd->dptr.prp.prp1);
uint64_t prp2 = le64_to_cpu(cmd->dptr.prp.prp2);
err = nvme_map_prp(n, &qsg, prp1, prp2, len, req);
if (err) {
nvme_set_error_page(n, req->sq->sqid, req->cqe.cid, err,
offsetof(NvmeRwCmd, dptr.prp.prp1), 0, req->ns->id);
return err;
}
}
err = blk_setup(n, &qsg, ns->blk.data, unit_len, req);
if (err) {
return err;
}
qemu_sglist_reset(&qsg);
if (cmd->mptr) {
if (cmd->psdt & PSDT_SGL_MPTR_SGL) {
nvme_addr_read(n, le64_to_cpu(cmd->mptr), &sgl,
sizeof(NvmeSglDescriptor));
err = nvme_map_sgl(n, &qsg, sgl, meta_len, req);
if (err) {
// nvme_map_sgl does not know if it was mapping a data or meta
// data SGL, so fix the error code if needed.
if (err & NVME_DATA_SGL_LENGTH_INVALID) {
err &= ~NVME_DATA_SGL_LENGTH_INVALID;
err |= NVME_METADATA_SGL_LENGTH_INVALID;
}
nvme_set_error_page(n, req->sq->sqid, req->cqe.cid, err,
offsetof(NvmeRwCmd, mptr), 0, req->ns->id);
return err;
}
} else {
qemu_sglist_add(&qsg, le64_to_cpu(cmd->mptr), meta_len);
}
err = blk_setup(n, &qsg, ns->blk.meta, meta_unit_len, req);
if (err) {
return err;
}
}
return NVME_SUCCESS;
}
static void dma_to_cmb(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov)
{
for (int i = 0; i < qsg->nsg; i++) {
void *addr = &n->cmbuf[qsg->sg[i].base - n->ctrl_mem.addr];
qemu_iovec_add(iov, addr, qsg->sg[i].len);
}
}
static uint16_t nvme_dma_write_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
uint64_t prp1, uint64_t prp2, NvmeRequest *req)
{
QEMUSGList qsg;
uint16_t err = NVME_SUCCESS;
err = nvme_map_prp(n, &qsg, prp1, prp2, len, req);
if (err) {
return err;
}
if (req->cmb) {
QEMUIOVector iov;
qemu_iovec_init(&iov, qsg.nsg);
dma_to_cmb(n, &qsg, &iov);
if (unlikely(qemu_iovec_to_buf(&iov, 0, ptr, len) != len)) {
trace_nvme_err_invalid_dma();
err = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
return err;
}
if (unlikely(dma_buf_write(ptr, len, &qsg))) {
trace_nvme_err_invalid_dma();
err = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
return err;
}
static uint16_t nvme_dma_write_sgl(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
NvmeSglDescriptor sgl, NvmeRequest *req)
{
QEMUSGList qsg;
uint16_t err = NVME_SUCCESS;
err = nvme_map_sgl(n, &qsg, sgl, len, req);
if (err) {
return err;
}
if (req->cmb) {
QEMUIOVector iov;
qemu_iovec_init(&iov, qsg.nsg);
dma_to_cmb(n, &qsg, &iov);
if (unlikely(qemu_iovec_to_buf(&iov, 0, ptr, len) != len)) {
trace_nvme_err_invalid_dma();
err = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
return err;
}
if (unlikely(dma_buf_write(ptr, len, &qsg))) {
trace_nvme_err_invalid_dma();
err = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
return err;
}
uint16_t nvme_dma_write(NvmeCtrl *n, uint8_t *ptr, uint32_t len, NvmeCmd *cmd,
NvmeRequest *req)
{
if (cmd->psdt) {
return nvme_dma_write_sgl(n, ptr, len, cmd->dptr.sgl, req);
}
uint64_t prp1 = le64_to_cpu(cmd->dptr.prp.prp1);
uint64_t prp2 = le64_to_cpu(cmd->dptr.prp.prp2);
return nvme_dma_write_prp(n, ptr, len, prp1, prp2, req);
}
static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
uint64_t prp1, uint64_t prp2, NvmeRequest *req)
{
QEMUSGList qsg;
uint16_t err = NVME_SUCCESS;
err = nvme_map_prp(n, &qsg, prp1, prp2, len, req);
if (err) {
return err;
}
if (req->cmb) {
QEMUIOVector iov;
qemu_iovec_init(&iov, qsg.nsg);
dma_to_cmb(n, &qsg, &iov);
if (unlikely(qemu_iovec_from_buf(&iov, 0, ptr, len) != len)) {
trace_nvme_err_invalid_dma();
err = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
return err;
}
if (unlikely(dma_buf_read(ptr, len, &qsg))) {
trace_nvme_err_invalid_dma();
err = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
return err;
}
uint16_t nvme_dma_read_sgl(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
NvmeSglDescriptor sgl, NvmeRequest *req)
{
QEMUSGList qsg;
uint16_t err = NVME_SUCCESS;
err = nvme_map_sgl(n, &qsg, sgl, len, req);
if (err) {
return err;
}
if (req->cmb) {
QEMUIOVector iov;
qemu_iovec_init(&iov, qsg.nsg);
dma_to_cmb(n, &qsg, &iov);
if (unlikely(qemu_iovec_from_buf(&iov, 0, ptr, len) != len)) {
trace_nvme_err_invalid_dma();
err = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
return err;
}
if (unlikely(dma_buf_read(ptr, len, &qsg))) {
trace_nvme_err_invalid_dma();
err = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
return err;
}
uint16_t nvme_dma_read(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
NvmeCmd *cmd, NvmeRequest *req)
{
if (cmd->psdt) {
return nvme_dma_read_sgl(n, ptr, len, cmd->dptr.sgl, req);
}
uint64_t prp1 = le64_to_cpu(cmd->dptr.prp.prp1);
uint64_t prp2 = le64_to_cpu(cmd->dptr.prp.prp2);
return nvme_dma_read_prp(n, ptr, len, prp1, prp2, req);
}
static void nvme_post_cqe(NvmeCQueue *cq, NvmeRequest *req)
{
NvmeCtrl *n = cq->ctrl;
NvmeSQueue *sq = req->sq;
NvmeCqe *cqe = &req->cqe;
hwaddr addr;
if (cq->phys_contig) {
addr = cq->dma_addr + cq->tail * n->cqe_size;
} else {
addr = nvme_discontig(cq->prp_list, cq->tail, n->page_size,
n->cqe_size);
}
if (n->dialect.post_cqe) {
n->dialect.post_cqe(n, req);
}
cqe->status = cpu_to_le16((req->status << 1) | cq->phase);
cqe->sq_id = cpu_to_le16(sq->sqid);
cqe->sq_head = cpu_to_le16(sq->head);
nvme_addr_write(n, addr, (void *)cqe, sizeof(*cqe));
nvme_inc_cq_tail(cq);
QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
}
static void nvme_post_cqes(void *opaque)
{
NvmeCQueue *cq = opaque;
NvmeCtrl *n = cq->ctrl;
NvmeRequest *req, *next;
QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
if (nvme_cq_full(cq)) {
break;
}
QTAILQ_REMOVE(&cq->req_list, req, entry);
nvme_post_cqe(cq, req);
}
if (cq->tail != cq->head) {
nvme_irq_assert(n, cq);
}
}
static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
{
NvmeCtrl *n = cq->ctrl;
uint64_t time_ns = NVME_INTC_TIME(n->features.int_coalescing) * 100 * 1000;
uint8_t thresh = NVME_INTC_THR(n->features.int_coalescing) + 1;
uint8_t coalesce_disabled =
(n->features.int_vector_config[cq->vector] >> 16) & 1;
uint8_t notify;
assert(cq->cqid == req->sq->cqid);
QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
if (nvme_cq_full(cq) || !QTAILQ_EMPTY(&cq->req_list)) {
QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
return;
}
nvme_post_cqe(cq, req);
notify = coalesce_disabled || !req->sq->sqid || !time_ns ||
req->status != NVME_SUCCESS || nvme_cqes_pending(cq) >= thresh;
if (!notify) {
if (!timer_pending(cq->timer)) {
timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
time_ns);
}
} else {
nvme_irq_assert(n, cq);
if (timer_pending(cq->timer)) {
timer_del(cq->timer);
}
}
}
static void nvme_enqueue_event(NvmeCtrl *n, uint8_t event_type,
uint8_t event_info, uint8_t log_page)
{
NvmeAsyncEvent *event;
if (!(n->bar.csts & NVME_CSTS_READY))
return;
event = (NvmeAsyncEvent *)g_malloc0(sizeof(*event));
event->result.event_type = event_type;
event->result.event_info = event_info;
event->result.log_page = log_page;
QSIMPLEQ_INSERT_TAIL(&(n->aer_queue), event, entry);
timer_mod(n->aer_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
}
static void nvme_aer_process_cb(void *param)
{
NvmeCtrl *n = param;
NvmeRequest *req;
NvmeAerResult *result;
NvmeAsyncEvent *event, *next;
QSIMPLEQ_FOREACH_SAFE(event, &n->aer_queue, entry, next) {
if (n->outstanding_aers <= 0) {
break;
}
if (n->aer_mask & (1 << event->result.event_type)) {
continue;
}
QSIMPLEQ_REMOVE_HEAD(&n->aer_queue, entry);
n->aer_mask |= 1 << event->result.event_type;
n->outstanding_aers--;
req = n->aer_reqs[n->outstanding_aers];
result = (NvmeAerResult *)&req->cqe.n.result;
result->event_type = event->result.event_type;
result->event_info = event->result.event_info;
result->log_page = event->result.log_page;
g_free(event);
req->status = NVME_SUCCESS;
nvme_enqueue_req_completion(n->cq[0], req);
}
}
void nvme_rw_cb(void *opaque, int ret)
{
NvmeBlockBackendRequest *blk_req = opaque;
NvmeRequest *req = blk_req->req;
NvmeSQueue *sq = req->sq;
NvmeCtrl *n = sq->ctrl;
NvmeCQueue *cq = n->cq[sq->cqid];
NvmeNamespace *ns = req->ns;
trace_nvme_rw_cb(req->cqe.cid);
QTAILQ_REMOVE(&req->blk_req_tailq_head, blk_req, blk_req_tailq);
if (!ret) {
block_acct_done(blk_get_stats(n->conf.blk), &blk_req->acct);