From a493388a1c778cf196f6cb3bbe5baed428601291 Mon Sep 17 00:00:00 2001 From: lihuanhuan Date: Thu, 15 Aug 2024 17:09:13 +0800 Subject: [PATCH] SDRAM operating at 100MHz & optimize the camera. (#149) * Reconfigure SDRAM frequency to 100MHz in the firmware. * Optimize camera configuration. --- core/embed/firmware/main.c | 2 +- core/embed/trezorhal/camera.c | 21 ++++---------- core/embed/trezorhal/sdram.c | 53 +++++++++++++++++++++++++++++++++-- core/embed/trezorhal/sdram.h | 2 +- 4 files changed, 59 insertions(+), 19 deletions(-) diff --git a/core/embed/firmware/main.c b/core/embed/firmware/main.c index c46b438f9..8b2e0036d 100644 --- a/core/embed/firmware/main.c +++ b/core/embed/firmware/main.c @@ -101,7 +101,7 @@ int main(void) { SCB->VTOR = (uint32_t)&_vector_offset; SystemCoreClockUpdate(); - sdram_gpio_reinit(); + sdram_reinit(); display_backlight(0); lcd_init(DISPLAY_RESX, DISPLAY_RESY, LCD_PIXEL_FORMAT_RGB565); diff --git a/core/embed/trezorhal/camera.c b/core/embed/trezorhal/camera.c index 78f8fe207..928fb34a5 100644 --- a/core/embed/trezorhal/camera.c +++ b/core/embed/trezorhal/camera.c @@ -101,7 +101,7 @@ static void dcmi_init() DMA_DCMI_Handle.Init.Mode = DMA_CIRCULAR; DMA_DCMI_Handle.Init.Priority = DMA_PRIORITY_HIGH; DMA_DCMI_Handle.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - DMA_DCMI_Handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + DMA_DCMI_Handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL; DMA_DCMI_Handle.Init.MemBurst = DMA_MBURST_SINGLE; DMA_DCMI_Handle.Init.PeriphBurst = DMA_PBURST_SINGLE; @@ -140,11 +140,6 @@ void DCMI_IRQHandler(void) void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef* hdcmi) { -#if CAMERA_CAPTURE_MODE == 0 - camera_dcmi_stop(); -#else - camera_suspend(); -#endif capture_done = true; } @@ -228,14 +223,10 @@ unsigned char camera_is_online(void) void camera_start(uint8_t* buffer_address, uint32_t mode) { - if ( camera_opened ) - { - camera_resume(); - return; - } - + HAL_DCMI_Stop(&DCMI_Handle); HAL_DCMI_Start_DMA(&DCMI_Handle, mode, (uint32_t)buffer_address, (WIN_W * WIN_H) / 2); camera_opened = true; + capture_done = false; } void camera_dcmi_stop(void) @@ -277,9 +268,8 @@ int camera_capture_done(void) while ( !capture_done ) { - if ( (HAL_GetTick() - tickstart) > 200 ) + if ( (HAL_GetTick() - tickstart) > 100 ) { - camera_dcmi_stop(); return 0; } } @@ -331,13 +321,14 @@ void camera_power_on(void) CAMERA_RST_LOW(); camera_delay(10); CAMERA_RST_HIGH(); - camera_delay(20); + camera_delay(100); camera_powered = true; } if ( !camera_configured ) { camera_config_init(); + camera_delay(10); camera_configured = true; } } diff --git a/core/embed/trezorhal/sdram.c b/core/embed/trezorhal/sdram.c index b69e80c80..e9b65de87 100644 --- a/core/embed/trezorhal/sdram.c +++ b/core/embed/trezorhal/sdram.c @@ -205,12 +205,29 @@ int sdram_init(void) { return HAL_OK; } -int sdram_gpio_reinit(void) { +int sdram_reinit(void) { GPIO_InitTypeDef gpio_init_structure; /* Enable FMC clock */ __HAL_RCC_FMC_CLK_DISABLE(); + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC; + PeriphClkInitStruct.PLL2.PLL2M = 5; + PeriphClkInitStruct.PLL2.PLL2N = 80; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 2; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; + PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return HAL_ERROR; + } + + __HAL_RCC_FMC_CLK_ENABLE(); + /* Enable GPIOs clock */ __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE(); @@ -297,7 +314,39 @@ int sdram_gpio_reinit(void) { HAL_GPIO_Init(GPIOG, &gpio_init_structure); - __HAL_RCC_FMC_CLK_ENABLE(); + FMC_SDRAM_TimingTypeDef sdram_timing; + + /* SDRAM device configuration */ + hsdram[0].Instance = FMC_SDRAM_DEVICE; + + /* SDRAM handle configuration */ + hsdram[0].Init.SDBank = FMC_SDRAM_BANK2; + hsdram[0].Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9; + hsdram[0].Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + hsdram[0].Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32; + hsdram[0].Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + hsdram[0].Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; + hsdram[0].Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + hsdram[0].Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; + hsdram[0].Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; + hsdram[0].Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_2; + + /* Timing configuration for 100Mhz as SDRAM clock frequency (System clock is + * up to 200Mhz) */ + sdram_timing.LoadToActiveDelay = 2; + sdram_timing.ExitSelfRefreshDelay = 7; + sdram_timing.SelfRefreshTime = 4; + sdram_timing.RowCycleDelay = 7; + sdram_timing.WriteRecoveryTime = 2; + sdram_timing.RPDelay = 2; + sdram_timing.RCDDelay = 2; + + /* SDRAM controller initialization */ + if (HAL_SDRAM_Init(&hsdram[0], &sdram_timing) != HAL_OK) { + return HAL_ERROR; + } + + sdram_init_sequence(); return HAL_OK; } diff --git a/core/embed/trezorhal/sdram.h b/core/embed/trezorhal/sdram.h index ddd99aa09..abcd979f4 100644 --- a/core/embed/trezorhal/sdram.h +++ b/core/embed/trezorhal/sdram.h @@ -52,7 +52,7 @@ #define FMC_SDRAM_ADDRESS_END ((uint32_t)0xD0000000 + (32 * 1024 * 1024)) int sdram_init(void); -int sdram_gpio_reinit(void); +int sdram_reinit(void); void sdram_set_self_refresh(void); void sdram_set_normal_mode(void); #endif