Incorrect Register Update on Page Fault Exception in M-Mode

[youzi27]

Describe the Bug:
In the NutShell implementation, when a store instruction causes a page fault exception in M-mode (mcause=0x0f), it incorrectly updates the stval register instead of the mtval register. According to the RISC-V Privileged Specification, during a page fault exception in M-mode, the mtval register should be updated with the faulting address or relevant information related to the exception. The behavior observed in NutShell deviates from the specification, as stval is updated, which is inconsistent with the defined behavior for handling exceptions in M-mode.

To Reproduce:

1. Set the processor to M-mode and execute a store instruction that will cause a page fault exception (mcause=0x0f).
2. Observe the values of mtval and stval registers after the exception is raised.
3. Note that stval is updated with the faulting address, whereas mtval remains unchanged.

Expected Behavior:
Upon a page fault exception in M-mode triggered by a store instruction, the mtval register should be updated with the faulting address or related exception information, not stval. This is in line with the RISC-V Privileged Specification, ensuring that exception handling behaves consistently across different implementations and modes of operation.

Screenshots

Additional context
None