From 4bb506b26e72f4df7759a9c1a610df7f969a5126 Mon Sep 17 00:00:00 2001
From: Yinan Xu <xuyinan@ict.ac.cn>
Date: Sat, 9 Dec 2023 10:45:44 +0800
Subject: [PATCH] makefile: replace error with fwrite (#152)

Verilator will abort the simulation if $error is triggered.
---
 Makefile | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index e4e7a83e..33d9170a 100644
--- a/Makefile
+++ b/Makefile
@@ -30,8 +30,8 @@ SPLIT_VERILOG = 0
 
 ifneq (,$(filter 3%,$(CHISEL_VERSION)))
 MILL_ARGS += --output-file $(@F)
-FPGA_ARGS += --infer-rw $(FPGATOP) --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf 
-else 
+FPGA_ARGS += --infer-rw $(FPGATOP) --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf
+else
 SPLIT_VERILOG = 1
 endif
 
@@ -74,6 +74,9 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	mkdir -p $(@D)
 	mill -i generator[$(CHISEL_VERSION)].test.runMain $(SIMTOP) $(MILL_ARGS)
 	@sed -i 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
+ifeq ($(MFC), 1)
+	@sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(SIM_TOP_V)
+endif
 ifeq ($(SPLIT_VERILOG), 1)
 	@cd $(BUILD_DIR) && bash ../scripts/extract_files.sh $(SIM_TOP_V)
 endif