diff --git a/tests/hwt/expected/decoder_using_case.py.txt b/tests/hwt/expected/decoder_using_case.py.txt
index 0196497e..8acafb9b 100644
--- a/tests/hwt/expected/decoder_using_case.py.txt
+++ b/tests/hwt/expected/decoder_using_case.py.txt
@@ -18,7 +18,7 @@ class decoder_using_case(HwModule):
     -----------------------------------------------------
     
     """
-    def _declr(self):
+    def hwDeclr(self):
         # ports
         self.binary_in = HwIOSignal(HBits(5))
         # 4 bit binary input
@@ -27,7 +27,7 @@ class decoder_using_case(HwModule):
         self.enable = HwIOSignal()
         # component instances
 
-    def _impl(self):
+    def hwImpl(self):
         binary_in, decoder_out, enable = \
         self.binary_in, self.decoder_out, self.enable
         # internal signals
diff --git a/tests/hwt/expected/uart.py.txt b/tests/hwt/expected/uart.py.txt
index 52fc9093..5751e9bc 100644
--- a/tests/hwt/expected/uart.py.txt
+++ b/tests/hwt/expected/uart.py.txt
@@ -18,7 +18,7 @@ class uart(HwModule):
     -----------------------------------------------------
     
     """
-    def _declr(self):
+    def hwDeclr(self):
         # ports
         # Port declarations
         self.reset = HwIOSignal()
@@ -36,7 +36,7 @@ class uart(HwModule):
         self.rx_empty = HwIOSignal()._m()
         # component instances
 
-    def _impl(self):
+    def hwImpl(self):
         reset, txclk, ld_tx_data, tx_data, tx_enable, tx_out, tx_empty, rxclk, uld_rx_data, rx_data, rx_enable, \
         rx_in, rx_empty = \
         self.reset, self.txclk, self.ld_tx_data, self.tx_data, self.tx_enable, self.tx_out, self.tx_empty, self.rxclk, self.uld_rx_data, self.rx_data, self.rx_enable, \