verilog-alu-qupj.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
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# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 15.0.0 Build 145 04/22/2015 SJ Full Version
# Date created = 11:27:57  November 12, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		verilog-alu-qupj_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Arria II GZ"
set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY "verilog-alu-qupj-block"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:27:57  NOVEMBER 12, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VERILOG_FILE library/or3.v
set_global_assignment -name VERILOG_FILE library/or2.v
set_global_assignment -name VERILOG_FILE library/not1.v
set_global_assignment -name VERILOG_FILE library/nor3.v
set_global_assignment -name VERILOG_FILE library/nand2.v
set_global_assignment -name VERILOG_FILE library/ha2.v
set_global_assignment -name VERILOG_FILE library/fa2.v
set_global_assignment -name VERILOG_FILE library/exor2.v
set_global_assignment -name VERILOG_FILE library/decoder3.v
set_global_assignment -name VERILOG_FILE library/dataselector2.v
set_global_assignment -name VERILOG_FILE library/and3.v
set_global_assignment -name VERILOG_FILE library/and2.v
set_global_assignment -name VERILOG_FILE alu_32bit.v
set_global_assignment -name VERILOG_FILE alu_8bit.v
set_global_assignment -name VERILOG_FILE alu_16bit.v
set_global_assignment -name VERILOG_FILE alu_1bit.v
set_global_assignment -name BDF_FILE "verilog-alu-qupj-block.bdf"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top