diff --git a/ARM/gcc_clang/cmake/stm/delays/stm32h7s3v8_z8.cmake b/ARM/gcc_clang/cmake/stm/delays/stm32h7s3v8_z8.cmake new file mode 100644 index 000000000..05b5f6023 --- /dev/null +++ b/ARM/gcc_clang/cmake/stm/delays/stm32h7s3v8_z8.cmake @@ -0,0 +1,3 @@ +if(${MCU_NAME} MATCHES "^STM32H7S3V8$|^STM32H7S3Z8$") + list(APPEND local_list_macros "getClockValue(_clock) (_clock/1000UL/2)") +endif() diff --git a/ARM/gcc_clang/cmake/stm/stm32h7s3v8_z8.cmake b/ARM/gcc_clang/cmake/stm/stm32h7s3v8_z8.cmake new file mode 100644 index 000000000..45efadf93 --- /dev/null +++ b/ARM/gcc_clang/cmake/stm/stm32h7s3v8_z8.cmake @@ -0,0 +1,5 @@ +if(${MCU_NAME} MATCHES "^STM32H7S3V8$|^STM32H7S3Z8$") + set(${linkerScript} linker_scripts/${vendor}/${mcu_match}.ld PARENT_SCOPE) + set(${startupFile} startup/${vendor}/${mcu_match}.s PARENT_SCOPE) + list(APPEND local_list_include system/src/stm/doc_ds_193_3/init_clock.c) +endif() diff --git a/ARM/gcc_clang/def/STM32H7S3V8.json b/ARM/gcc_clang/def/STM32H7S3V8.json new file mode 100644 index 000000000..3bc28deb9 --- /dev/null +++ b/ARM/gcc_clang/def/STM32H7S3V8.json @@ -0,0 +1,6 @@ +{ + "core": "M7", + "delay_src_path": "delays/m7/__lib_delays.c", + "mcu": "STM32H7S3V8", + "clock": 1 +} \ No newline at end of file diff --git a/ARM/gcc_clang/def/STM32H7S3Z8.json b/ARM/gcc_clang/def/STM32H7S3Z8.json new file mode 100644 index 000000000..ee8e74e35 --- /dev/null +++ b/ARM/gcc_clang/def/STM32H7S3Z8.json @@ -0,0 +1,6 @@ +{ + "core": "M7", + "delay_src_path": "delays/m7/__lib_delays.c", + "mcu": "STM32H7S3Z8", + "clock": 1 +} \ No newline at end of file diff --git a/ARM/gcc_clang/def/stm/STM32H7S3V8/mcu.h b/ARM/gcc_clang/def/stm/STM32H7S3V8/mcu.h new file mode 100644 index 000000000..877034634 --- /dev/null +++ b/ARM/gcc_clang/def/stm/STM32H7S3V8/mcu.h @@ -0,0 +1,24245 @@ +/** + ****************************************************************************** + * @file stm32h7s3xx.h + * @author MCD Application Team + * @brief CMSIS STM32H7S3xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H7S3xx_H +#define STM32H7S3xx_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H7S3xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M7 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H7S3xx Specific Interrupt Numbers ====================================== */ + PVD_PVM_IRQn = 0, /*!< PVD/PVM through EXTI Line detection */ + DTS_IRQn = 2, /*!< Digital Temperature Sensor interrupt */ + IWDG_IRQn = 3, /*!< Internal Watchdog interrupt */ + WWDG_IRQn = 4, /*!< Window Watchdog interrupt */ + RCC_IRQn = 5, /*!< RCC global interrupts through EXTI Line detection */ + FLASH_IRQn = 8, /*!< FLASH interrupts */ + RAMECC_IRQn = 9, /*!< RAMECC interrupts */ + FPU_IRQn = 10, /*!< FPU interrupt */ + TAMP_IRQn = 13, /*!< Tamper and TimeStamp interrupts through EXTI Line detection */ + EXTI0_IRQn = 16, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 17, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 18, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 19, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 20, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 21, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 22, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 23, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 24, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 25, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 26, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 27, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 28, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 29, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 30, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 31, /*!< EXTI Line15 interrupt */ + RTC_IRQn = 32, /*!< RTC Wakeup and Alarm interrupts through EXTI Line detection */ + SAES_IRQn = 33, /*!< SAES interrupt */ + CRYP_IRQn = 34, /*!< CRYP interrupt */ + PKA_IRQn = 35, /*!< PKA interrupt */ + HASH_IRQn = 36, /*!< HASH interrupt */ + RNG_IRQn = 37, /*!< RNG global interrupt */ + ADC1_2_IRQn = 38, /*!< ADC1 & ADC2 interrupt */ + GPDMA1_Channel0_IRQn = 39, /*!< GPDMA1 Channel 0 interrupt */ + GPDMA1_Channel1_IRQn = 40, /*!< GPDMA1 Channel 1 interrupt */ + GPDMA1_Channel2_IRQn = 41, /*!< GPDMA1 Channel 2 interrupt */ + GPDMA1_Channel3_IRQn = 42, /*!< GPDMA1 Channel 3 interrupt */ + GPDMA1_Channel4_IRQn = 43, /*!< GPDMA1 Channel 4 interrupt */ + GPDMA1_Channel5_IRQn = 44, /*!< GPDMA1 Channel 5 interrupt */ + GPDMA1_Channel6_IRQn = 45, /*!< GPDMA1 Channel 6 interrupt */ + GPDMA1_Channel7_IRQn = 46, /*!< GPDMA1 Channel 7 interrupt */ + TIM1_BRK_IRQn = 47, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 48, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 49, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 50, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 51, /*!< TIM2 global interrupt */ + TIM3_IRQn = 52, /*!< TIM3 global interrupt */ + TIM4_IRQn = 53, /*!< TIM4 global interrupt */ + TIM5_IRQn = 54, /*!< TIM5 global interrupt */ + TIM6_IRQn = 55, /*!< TIM6 global interrupt */ + TIM7_IRQn = 56, /*!< TIM7 global interrupt */ + TIM9_IRQn = 57, /*!< TIM9 global interrupt */ + SPI1_IRQn = 58, /*!< SPI1 global interrupt */ + SPI2_IRQn = 59, /*!< SPI2 global interrupt */ + SPI3_IRQn = 60, /*!< SPI3 global interrupt */ + SPI4_IRQn = 61, /*!< SPI4 global interrupt */ + SPI5_IRQn = 62, /*!< SPI5 global interrupt */ + SPI6_IRQn = 63, /*!< SPI6 global interrupt */ + HPDMA1_Channel0_IRQn = 64, /*!< HPDMA1 Channel 0 global interrupt */ + HPDMA1_Channel1_IRQn = 65, /*!< HPDMA1 Channel 1 global interrupt */ + HPDMA1_Channel2_IRQn = 66, /*!< HPDMA1 Channel 2 global interrupt */ + HPDMA1_Channel3_IRQn = 67, /*!< HPDMA1 Channel 3 global interrupt */ + HPDMA1_Channel4_IRQn = 68, /*!< HPDMA1 Channel 4 global interrupt */ + HPDMA1_Channel5_IRQn = 69, /*!< HPDMA1 Channel 5 global interrupt */ + HPDMA1_Channel6_IRQn = 70, /*!< HPDMA1 Channel 6 global interrupt */ + HPDMA1_Channel7_IRQn = 71, /*!< HPDMA1 Channel 7 global interrupt */ + SAI1_A_IRQn = 72, /*!< Serial Audio Interface 1 block A interrupt */ + SAI1_B_IRQn = 73, /*!< Serial Audio Interface 1 block B interrupt */ + SAI2_A_IRQn = 74, /*!< Serial Audio Interface 2 block A interrupt */ + SAI2_B_IRQn = 75, /*!< Serial Audio Interface 2 block B interrupt */ + I2C1_EV_IRQn = 76, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 77, /*!< I2C1 error interrupt */ + I2C2_EV_IRQn = 78, /*!< I2C2 event interrupt */ + I2C2_ER_IRQn = 79, /*!< I2C2 error interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + USART1_IRQn = 82, /*!< USART1 global interrupt */ + USART2_IRQn = 83, /*!< USART2 global interrupt */ + USART3_IRQn = 84, /*!< USART3 global interrupt */ + UART4_IRQn = 85, /*!< UART4 global interrupt */ + UART5_IRQn = 86, /*!< UART5 global interrupt */ + UART7_IRQn = 87, /*!< UART7 global interrupt */ + UART8_IRQn = 88, /*!< UART8 global interrupt */ + I3C1_EV_IRQn = 89, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 90, /*!< I3C1 error interrupt */ + OTG_HS_IRQn = 91, /*!< USB OTG HS interrupt */ + ETH_IRQn = 92, /*!< Ethernet global interrupt */ + CORDIC_IRQn = 93, /*!< CORDIC global interrupt */ + GFXTIM_IRQn = 94, /*!< GFXTIM global interrupt */ + DCMIPP_IRQn = 95, /*!< DCMIPP global interrupt */ + DMA2D_IRQn = 98, /*!< DMA2D global interrupt */ + JPEG_IRQn = 99, /*!< JPEG global interrupt */ + GFXMMU_IRQn = 100, /*!< GFXMMU global interrupt */ + I3C1_WKUP_IRQn = 101, /*!< I3C1 wakeup global interrupt */ + MCE1_IRQn = 102, /*!< MCE1 global interrupt */ + MCE2_IRQn = 103, /*!< MCE2 global interrupt */ + MCE3_IRQn = 104, /*!< MCE3 global interrupt */ + XSPI1_IRQn = 105, /*!< XSPI1 global interrupt */ + XSPI2_IRQn = 106, /*!< XSPI2 global interrupt */ + FMC_IRQn = 107, /*!< FMC global interrupt */ + SDMMC1_IRQn = 108, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 109, /*!< SDMMC2 global interrupt */ + OTG_FS_IRQn = 112, /*!< USB OTG FS interrupt */ + TIM12_IRQn = 113, /*!< TIM12 global interrupt */ + TIM13_IRQn = 114, /*!< TIM13 global interrupt */ + TIM14_IRQn = 115, /*!< TIM14 global interrupt */ + TIM15_IRQn = 116, /*!< TIM15 global interrupt */ + TIM16_IRQn = 117, /*!< TIM16 global interrupt */ + TIM17_IRQn = 118, /*!< TIM17 global interrupt */ + LPTIM1_IRQn = 119, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 120, /*!< LPTIM2 global interrupt */ + LPTIM3_IRQn = 121, /*!< LPTIM3 global interrupt */ + LPTIM4_IRQn = 122, /*!< LPTIM4 global interrupt */ + LPTIM5_IRQn = 123, /*!< LPTIM5 global interrupt */ + SPDIF_RX_IRQn = 124, /*!< SPDIF_RX global interrupt */ + MDIOS_IRQn = 125, /*!< MDIOS global interrupt */ + ADF1_FLT0_IRQn = 126, /*!< ADF1 Filter 0 global Interrupt */ + CRS_IRQn = 127, /*!< CRS global interrupt */ + UCPD1_IRQn = 128, /*!< UCPD1 global interrupt */ + CEC_IRQn = 129, /*!< HDMI_CEC global Interrupt */ + PSSI_IRQn = 130, /*!< PSSI global interrupt */ + LPUART1_IRQn = 131, /*!< LPUART1 global interrupt */ + WAKEUP_PIN_IRQn = 132, /*!< Wake-up pins interrupt */ + GPDMA1_Channel8_IRQn = 133, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 134, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 135, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 136, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 137, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 138, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 139, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 140, /*!< GPDMA1 Channel 15 global interrupt */ + HPDMA1_Channel8_IRQn = 141, /*!< HPDMA1 Channel 8 global interrupt */ + HPDMA1_Channel9_IRQn = 142, /*!< HPDMA1 Channel 9 global interrupt */ + HPDMA1_Channel10_IRQn = 143, /*!< HPDMA1 Channel 10 global interrupt */ + HPDMA1_Channel11_IRQn = 144, /*!< HPDMA1 Channel 11 global interrupt */ + HPDMA1_Channel12_IRQn = 145, /*!< HPDMA1 Channel 12 global interrupt */ + HPDMA1_Channel13_IRQn = 146, /*!< HPDMA1 Channel 13 global interrupt */ + HPDMA1_Channel14_IRQn = 147, /*!< HPDMA1 Channel 14 global interrupt */ + HPDMA1_Channel15_IRQn = 148, /*!< HPDMA1 Channel 15 global interrupt */ + FDCAN1_IT0_IRQn = 152, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 153, /*!< FDCAN1 interrupt 1 */ + FDCAN2_IT0_IRQn = 154, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 155 /*!< FDCAN2 interrupt 1 */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ +#define __CM7_REV 0x0102U /*!< Cortex-M7 revision r1p2 */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __MPU_REGIONCOUNT 16U /*!< CM7 provides MPU region number */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M7 processor and core peripherals */ +// Note: Changed for MikroE implementation. +// #include "system_stm32h7rsxx.h" /*!< STM32H7RSxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xC8 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief AXIM ASIB + */ +typedef struct +{ + uint32_t RESERVED1[9]; /*!< Reserved, Address offset: 0x00-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM ASIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x28-0xFC */ + __IO uint32_t READQOS; /*!< AXIM ASIB read_qos register Address offset: 0x100 */ + __IO uint32_t WRITEQOS; /*!< AXIM ASIB write_qos register Address offset: 0x104 */ + __IO uint32_t FNMOD; /*!< AXIM ASIB fn_mod register Address offset: 0x108 */ +} AXIM_ASIB_TypeDef; + +typedef struct +{ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x00-0x04 */ + __IO uint32_t FNMODBMISS; /*!< AXIM AMIB fn_mod_bm_iss register Address offset: 0x08 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x0C-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM AMIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[1]; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t FNMODLB; /*!< AXIM AMIB fn_mod_lb register Address offset: 0x2C */ + uint32_t RESERVED5[54]; /*!< Reserved, Address offset: 0x30-0x104 */ + __IO uint32_t FNMOD; /*!< AXIM AMIB fn_mod register Address offset: 0x108 */ +} AXIM_AMIB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +} CEC_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC Control and Status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Cryp Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t AHB5FZR; /*!< Debug MCU AHB5FZR freeze register, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1FZR freeze register, Address offset: 0x24 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x28-0x38 */ + __IO uint32_t APB1FZR; /*!< Debug MCU APB1FZR freeze register, Address offset: 0x3C */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x40-0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2FZR freeze register, Address offset: 0x4C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZR; /*!< Debug MCU APB4FZR freeze register, Address offset: 0x54 */ + uint32_t RESERVED6[41]; /*!< Reserved, Address offset: 0x58-0xF8 */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU Authentication Host register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU Authentication Device register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU Authentication Ack register, Address offset: 0x108 */ + uint32_t RESERVED7[945]; /*!< Reserved, Address offset: 0x10C-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMIPP + */ +typedef struct +{ + __IO uint32_t IPGR1; /*!< IP-Plug global register 1 Address offset: 0x00 */ + __IO uint32_t IPGR2; /*!< IP-Plug global register 2 Address offset: 0x04 */ + __IO uint32_t IPGR3; /*!< IP-Plug global register 3 Address offset: 0x08 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x0C-0x18 */ + __IO uint32_t IPGR8; /*!< IP-Plug global register 8 Address offset: 0x1C */ + __IO uint32_t IPC1R1; /*!< IP-Plug client 1 register 1 Address offset: 0x20 */ + __IO uint32_t IPC1R2; /*!< IP-Plug client 1 register 2 Address offset: 0x24 */ + __IO uint32_t IPC1R3; /*!< IP-Plug client 1 register 3 Address offset: 0x28 */ + __IO uint32_t RESERVED2[54]; /*!< Reserved, Address offset: 0x2C-0x100 */ + __IO uint32_t PRCR; /*!< Parallel interface control register Address offset: 0x104 */ + __IO uint32_t PRESCR; /*!< Parallel interface embedded sync code register Address offset: 0x108 */ + __IO uint32_t PRESUR; /*!< Parallel interface embedded sync unmask register Address offset: 0x10C */ + __IO uint32_t RESERVED3[57]; /*!< Reserved, Address offset: 0x110-0x1F0 */ + __IO uint32_t PRIER; /*!< Parallel interface interrupt enable register Address offset: 0x1F4 */ + __IO uint32_t PRSR; /*!< Parallel interface status register Address offset: 0x1F8 */ + __IO uint32_t PRFCR; /*!< Parallel interface interrupt clear register Address offset: 0x1FC */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x200 */ + __IO uint32_t CMCR; /*!< Common configuration register Address offset: 0x204 */ + __IO uint32_t CMFRCR; /*!< Common frame counter register Address offset: 0x208 */ + __IO uint32_t RESERVED5[121]; /*!< Reserved, Address offset: 0x20C-0x3EC */ + __IO uint32_t CMIER; /*!< Common interrupt enable register Address offset: 0x3F0 */ + __IO uint32_t CMSR1; /*!< Common status register 1 Address offset: 0x3F4 */ + __IO uint32_t CMSR2; /*!< Common status register 2 Address offset: 0x3F8 */ + __IO uint32_t CMFCR; /*!< Common interrupt clear register Address offset: 0x3FC */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x400 */ + __IO uint32_t P0FSCR; /*!< Pipe0 flow selection configuration register Address offset: 0x404 */ + __IO uint32_t RESERVED7[62]; /*!< Reserved, Address offset: 0x408-0x4FC */ + __IO uint32_t P0FCTCR; /*!< Pipe0 flow control configuration register Address offset: 0x500 */ + __IO uint32_t P0SCSTR; /*!< Pipe0 stat/crop start register Address offset: 0x504 */ + __IO uint32_t P0SCSZR; /*!< Pipe0 stat/crop size register Address offset: 0x508 */ + __IO uint32_t RESERVED8[41]; /*!< Reserved, Address offset: 0x50C-0x5AC */ + __IO uint32_t P0DCCNTR; /*!< Pipe0 dump counter register Address offset: 0x5B0 */ + __IO uint32_t P0DCLMTR; /*!< Pipe0 dump limit register Address offset: 0x5B4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x5B8-0x5BC */ + __IO uint32_t P0PPCR; /*!< Pipe0 pixel packer configuration register Address offset: 0x5C0 */ + __IO uint32_t P0PPM0AR1; /*!< Pipe0 pixel packer memory0 address register 1 Address offset: 0x5C4 */ + __IO uint32_t P0PPM0AR2; /*!< Pipe0 pixel packer memory0 address register 2 Address offset: 0x5C8 */ + __IO uint32_t RESERVED10[10]; /*!< Reserved, Address offset: 0x5CC-0x5F0 */ + __IO uint32_t P0IER; /*!< Pipe0 interrupt enable register Address offset: 0x5F4 */ + __IO uint32_t P0SR; /*!< Pipe0 status register Address offset: 0x5F8 */ + __IO uint32_t P0FCR; /*!< Pipe0 interrupt clear register Address offset: 0x5FC */ + __IO uint32_t RESERVED11[64]; /*!< Reserved, Address offset: 0x600-0x6FC */ + __IO uint32_t P0CFCTCR; /*!< Pipe0 current flow control configuration register Address offset: 0x700 */ + __IO uint32_t P0CSCSTR; /*!< Pipe0 current stat/crop start register Address offset: 0x704 */ + __IO uint32_t P0CSCSZR; /*!< Pipe0 current stat/crop size register Address offset: 0x708 */ + __IO uint32_t RESERVED12[45]; /*!< Reserved, Address offset: 0x70C-0x7BC */ + __IO uint32_t P0CPPCR; /*!< Pipe0 current pixel packer configuration register Address offset: 0x700 */ + __IO uint32_t P0CPPM0AR1; /*!< Pipe0 current pixel packer memory0 address register 1 Address offset: 0x7C4 */ + __IO uint32_t P0CPPM0AR2; /*!< Pipe0 current pixel packer memory0 address register 2 Address offset: 0x7C8 */ +} DCMIPP_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ +} DMA2D_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} DTS_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x08 */ + uint32_t RESERVED1[5]; /*!< Reserved 1, Address offset: 0x0C-0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x28 */ + uint32_t RESERVED2[21]; /*!< Reserved 2, Address offset: 0x2C-0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x84 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x88 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x94 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x98 */ + uint32_t RESERVED4; /*!< Reserved 4, Address offset: 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __IO uint32_t KEYR; /*!< FLASH control key register, Address offset: 0x004 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x008 - 0x00C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x010 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t IER; /*!< FLASH interrupt enable register, Address offset: 0x020 */ + __IO uint32_t ISR; /*!< FLASH interrupt status register, Address offset: 0x024 */ + __IO uint32_t ICR; /*!< FLASH interrupt clear register, Address offset: 0x028 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t CRCCR; /*!< FLASH CRC control register, Address offset: 0x030 */ + __IO uint32_t CRCSADDR; /*!< FLASH CRC start address register, Address offset: 0x034 */ + __IO uint32_t CRCEADDR; /*!< FLASH CRC end address register, Address offset: 0x038 */ + __IO uint32_t CRCDATAR; /*!< FLASH CRC data register, Address offset: 0x03C */ + __IO uint32_t ECCSFADDR; /*!< FLASH ECC single fail address register, Address offset: 0x040 */ + __IO uint32_t ECCDFADDR; /*!< FLASH ECC double fail address register, Address offset: 0x044 */ + uint32_t RESERVED4[46]; /*!< Reserved, Address offset: 0x048 - 0x0FC */ + __IO uint32_t OPTKEYR; /*!< FLASH options key register, Address offset: 0x100 */ + __IO uint32_t OPTCR; /*!< FLASH options control register, Address offset: 0x104 */ + __IO uint32_t OPTISR; /*!< FLASH options interrupt status register, Address offset: 0x108 */ + __IO uint32_t OPTICR; /*!< FLASH options interrupt clear register, Address offset: 0x10C */ + __IO uint32_t OBKCR; /*!< FLASH option byte key control register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x114 */ + __IO uint32_t OBKDR[8]; /*!< FLASH option bytes key data register, Address offset: 0x118 - 0x134 */ + uint32_t RESERVED6[50]; /*!< Reserved, Address offset: 0x138 - 0x1FC */ + __IO uint32_t NVSR; /*!< FLASH non-volatile status register, Address offset: 0x200 */ + __IO uint32_t NVSRP; /*!< FLASH security status register programming, Address offset: 0x204 */ + __IO uint32_t ROTSR; /*!< FLASH RoT status register, Address offset: 0x208 */ + __IO uint32_t ROTSRP; /*!< FLASH RoT status register programming, Address offset: 0x20C */ + __IO uint32_t OTPLSR; /*!< FLASH OTP lock status register, Address offset: 0x210 */ + __IO uint32_t OTPLSRP; /*!< FLASH OTP lock status programming register, Address offset: 0x214 */ + __IO uint32_t WRPSR; /*!< FLASH write protection status register, Address offset: 0x218 */ + __IO uint32_t WRPSRP; /*!< FLASH write protection status register programming, Address offset: 0x21C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x220 - 0x22C */ + __IO uint32_t HDPSR; /*!< FLASH hide protection status register, Address offset: 0x230 */ + __IO uint32_t HDPSRP; /*!< FLASH hide protection status register programming, Address offset: 0x234 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x238 - 0x24C */ + __IO uint32_t EPOCHSR; /*!< FLASH epoch status register, Address offset: 0x250 */ + __IO uint32_t EPOCHSRP; /*!< FLASH epoch status register programming, Address offset: 0x254 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x258 - 0x25C */ + __IO uint32_t OBW1SR; /*!< FLASH option byte word 1 status register, Address offset: 0x260 */ + __IO uint32_t OBW1SRP; /*!< FLASH option byte word 1 status register programming, Address offset: 0x264 */ + __IO uint32_t OBW2SR; /*!< FLASH option byte word 2 status register, Address offset: 0x268 */ + __IO uint32_t OBW2SRP; /*!< FLASH option byte word 2 status register programming, Address offset: 0x26C */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 + */ +typedef struct { + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 Extended + */ +typedef struct { + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct { + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 & 6 + */ +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140 - 0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148 - 0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief GFXMMU + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + __IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 0x00 */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 0x04 */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 0x08 */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0x0C */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 0x10 */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 0x14 */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 0x18 */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 0x1C */ + uint32_t RESERVED0[4]; /* Reserved Address offset: 0x20-0x2C */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 0x30 */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 0x34 */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 0x38 */ + uint32_t RESERVED1; /* Reserved Address offset: 0x3C */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 0x40 */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 0x44 */ + uint32_t RESERVED2[2]; /* Reserved Address offset: 0x48-0x4C */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 0x50-0x8C */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 0x90-0xCC */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: 0xD0-0x10C */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 0x110-0x14C */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 0x150-0x18C */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 0x190-0x20C */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 0x210-0x35C */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 0x360-0x4F8 */ + uint32_t RESERVED3; /* Reserved Address offset: 0x4FC */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 0x500-0x65C */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 0x660-0x7BC */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 0x7C0-0x7DC */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 0x7E0-0x7FC */ +} JPEG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Memory Cipher Engine (MCE) + */ +typedef struct +{ + __IO uint32_t REGCR; /*!< MCE region configuration register, Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t SADDR; /*!< MCE region start address register, Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t EADDR; /*!< MCE region end address register, Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t ATTR; /*!< MCE region attribute register, Address offset: 0x04C + 0x10 * (x-1) (x = 1 to 4) */ +} MCE_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CCCFGR; /*!< MCE cipher context configuration register, Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR0; /*!< MCE cipher context nonce register 0, Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR1; /*!< MCE cipher context nonce register 1, Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR0; /*!< MCE cipher context key register 0, Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR1; /*!< MCE cipher context key register 1, Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR2; /*!< MCE cipher context key register 2, Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR3; /*!< MCE cipher context key register 3, Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */ +} MCE_Context_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MCE configuration register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< MCE status register, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< MCE illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< MCE illegal access clear register, Address offset: 0x00C */ + __IO uint32_t IAIER; /*!< MCE illegal access interrupt enable register, Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x014-0x018 */ + __IO uint32_t PRIVCFGR; /*!< MCE privileged configuration register, Address offset: 0x01C */ + __IO uint32_t IAESR; /*!< MCE illegal access error status register, Address offset: 0x020 */ + __IO uint32_t IADDR; /*!< MCE illegal address register, Address offset: 0x024 */ + uint32_t RESERVED2[118]; /*!< Reserved, Address offset: 0x028-0x1FC */ + __IO uint32_t MKEYR0; /*!< MCE master key register 0, Address offset: 0x200 */ + __IO uint32_t MKEYR1; /*!< MCE master key register 1, Address offset: 0x204 */ + __IO uint32_t MKEYR2; /*!< MCE master key register 2, Address offset: 0x208 */ + __IO uint32_t MKEYR3; /*!< MCE master key register 3, Address offset: 0x20C */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x210-0x21C */ + __IO uint32_t FMKEYR0; /*!< MCE fast master key register 0, Address offset: 0x220 */ + __IO uint32_t FMKEYR1; /*!< MCE fast master key register 1, Address offset: 0x224 */ + __IO uint32_t FMKEYR2; /*!< MCE fast master key register 2, Address offset: 0x228 */ + __IO uint32_t FMKEYR3; /*!< MCE fast master key register 3, Address offset: 0x22C */ +} MCE_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + +/** + * @brief ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ +} MDF_TypeDef; + +/** + * @brief ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief XSPI + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPIM IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x04 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control status register 2, Address offset: 0x0C */ + __IO uint32_t CSR3; /*!< PWR power control status register 3, Address offset: 0x10 */ + __IO uint32_t CSR4; /*!< PWR power control status register 4, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< PWR USB Type-C and power delivery register, Address offset: 0x2C */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x30 */ + __IO uint32_t PUCRN; /*!< PWR port N pull-up control register, Address offset: 0x34 */ + __IO uint32_t PDCRN; /*!< PWR port N pull-down control register, Address offset: 0x38 */ + __IO uint32_t PUCRO; /*!< PWR port O pull-up control register, Address offset: 0x3C */ + __IO uint32_t PDCRO; /*!< PWR port O pull-down control register, Address offset: 0x40 */ + __IO uint32_t PDCRP; /*!< PWR port P pull-down control register, Address offset: 0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved */ + __IO uint32_t PDR1; /*!< PWR debug register 1, Address offset: 0x50 */ +} PWR_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved, Address offset: 0x000C-0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x0400-0x18D8 */ +} PKA_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI clock calibration register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock recovery RC register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI clock calibration register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CDCFGR; /*!< RCC CPU domain configuration register, Address offset: 0x18 */ + __IO uint32_t BMCFGR; /*!< RCC Bus matrix configuration register, Address offset: 0x1C */ + __IO uint32_t APBCFGR; /*!< RCC APB clock configuration register, Address offset: 0x20 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs clock source selection register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs configuration register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR1; /*!< RCC PLL1 dividers configuration register 1, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 fractional divider configuration register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR1; /*!< RCC PLL2 dividers configuration register 1, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 fractional divider configuration register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR1; /*!< RCC PLL3 dividers configuration register 1, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 fractional divider configuration register, Address offset: 0x44 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t CCIPR1; /*!< RCC AHB peripherals kernel clock configuration register Address offset: 0x4C */ + __IO uint32_t CCIPR2; /*!< RCC APB1 peripherals kernel clock configuration register Address offset: 0x50 */ + __IO uint32_t CCIPR3; /*!< RCC APB2 peripherals kernel clock configuration register Address offset: 0x54 */ + __IO uint32_t CCIPR4; /*!< RCC APB4/APB5 peripherals kernel clock configuration register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x68 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x90 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0xA0 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0xA4 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xA8-0xAC */ + __IO uint32_t CKGDISR ; /*!< RCC AXI clocks gating disable register, Address offset: 0xB0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xB4-0xBC */ + __IO uint32_t PLL1DIVR2; /*!< RCC PLL1 dividers configuration register 2, Address offset: 0xC0 */ + __IO uint32_t PLL2DIVR2; /*!< RCC PLL2 dividers configuration register 2, Address offset: 0xC4 */ + __IO uint32_t PLL3DIVR2; /*!< RCC PLL3 dividers configuration register 2, Address offset: 0xC8 */ + __IO uint32_t PLL1SSCGR; /*!< RCC PLL1 spread spectrum clock generator register, Address offset: 0xCC */ + __IO uint32_t PLL2SSCGR; /*!< RCC PLL2 spread spectrum clock generator register, Address offset: 0xD0 */ + __IO uint32_t PLL3SSCGR; /*!< RCC PLL3 spread spectrum clock generator register, Address offset: 0xD4 */ + uint32_t RESERVED9[10]; /*!< Reserved, Address offset: 0xD8-0xFC */ + __IO uint32_t CKPROTR; /*!< RCC clock protection register, Address offset: 0x100 */ + uint32_t RESERVED10[11]; /*!< Reserved, Address offset: 0x104-0x12C */ + __IO uint32_t RSR; /*!< RCC reset status register, Address offset: 0x130 */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, Address offset: 0x134 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x138 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x13C */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clocks enable register, Address offset: 0x140 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 peripheral clocks enable register, Address offset: 0x144 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x148 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x14C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x150 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clocks enable register, Address offset: 0x154 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x158 */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 peripheral sleep clocks enable register, Address offset: 0x15C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clocks enable register, Address offset: 0x160 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clocks enable register, Address offset: 0x164 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clocks enable register, Address offset: 0x168 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clocks enable register, Address offset: 0x16C */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 peripheral sleep clocks enable register 1, Address offset: 0x170 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 peripheral sleep clocks enable register 2, Address offset: 0x174 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clocks enable register, Address offset: 0x178 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clocks enable register, Address offset: 0x17C */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 peripheral sleep clocks enable register, Address offset: 0x180 */ +} RCC_TypeDef; + +/** + * @brief Random Number Generator + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief SAES Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< SAES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< SAES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< SAES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< SAES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< SAES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< SAES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< SAES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< SAES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< SAES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< SAES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< SAES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< SAES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< SAES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< SAES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< SAES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< SAES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< SAES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< SAES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< SAES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< SAES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< SAES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< SAES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< SAES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< SAES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168]; /*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< SAES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< SAES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< SAES Interrupt Clear Register, Address offset: 0x308 */ +} SAES_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration, boot and security controller + */ +typedef struct +{ + __IO uint32_t BOOTSR; /*!< SBS Boot Status register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04-0x0C */ + __IO uint32_t HDPLCR; /*!< SBS Hide Protection Control register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS Hide Protection Status register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x28-0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command register, Address offset: 0x34 */ + uint32_t RESERVED4[50]; /*!< Reserved, Address offset: 0x38-0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status register, Address offset: 0x108 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS IO Compensation Cell Control and Status register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS IO Compensation Cell Value register, Address offset: 0x114 */ + __IO uint32_t CCSWVALR; /*!< SBS IO Compensation Cell Software Value register, Address offset: 0x118 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x11C */ + __IO uint32_t BKLOCKR; /*!< SBS Break Lockup register, Address offset: 0x120 */ + uint32_t RESERVED7[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t EXTICR[4]; /*!< SBS External Interrupt Configuration registers, Address offset: 0x130-0x13C */ +} SBS_TypeDef; + +/** + * @brief Secure Digital Card/IO Embedded MultiMediaCard Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC Power control register, Address offset : 0x000 */ + __IO uint32_t CLKCR; /*!< SDMMC Clock control register, Address offset : 0x004 */ + __IO uint32_t ARG; /*!< SDMMC Argument register, Address offset : 0x008 */ + __IO uint32_t CMD; /*!< SDMMC Command register, Address offset : 0x00C */ + __IO uint32_t RESPCMD; /*!< SDMMC Command response register, Address offset : 0x010 */ + __IO uint32_t RESP1; /*!< SDMMC Response 1 register, Address offset : 0x014 */ + __IO uint32_t RESP2; /*!< SDMMC Response 2 register, Address offset : 0x018 */ + __IO uint32_t RESP3; /*!< SDMMC Response 3 register, Address offset : 0x01C */ + __IO uint32_t RESP4; /*!< SDMMC Response 4 register, Address offset : 0x020 */ + __IO uint32_t DTIMER; /*!< SDMMC Data timer register, Address offset : 0x024 */ + __IO uint32_t DLEN; /*!< SDMMC Data length register, Address offset : 0x028 */ + __IO uint32_t DCTRL; /*!< SDMMC Data control register, Address offset : 0x02C */ + __IO uint32_t DCOUNT; /*!< SDMMC Data counter register, Address offset : 0x030 */ + __IO uint32_t STA; /*!< SDMMC Status register, Address offset : 0x034 */ + __IO uint32_t ICR; /*!< SDMMC Interrupt clear register, Address offset : 0x038 */ + __IO uint32_t MASK; /*!< SDMMC Mask register, Address offset : 0x03C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset : 0x040 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset : 0x044 - 0x04C */ + __IO uint32_t IDMACTRL; /*!< SDMMC IDMA control register, Address offset : 0x050 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC IDMA buffer size register, Address offset : 0x054 */ + __IO uint32_t IDMABASER; /*!< SDMMC IDMA buffer base address register, Address offset : 0x058 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset : 0x05C - 0x060 */ + __IO uint32_t IDMALAR; /*!< SDMMC IDMA linked list address register, Address offset : 0x064 */ + __IO uint32_t IDMABAR; /*!< SDMMC IDMA linked list memory base register, Address offset : 0x068 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset : 0x06C - 0x07C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset : 0x080 */ +} SDMMC_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t CFGR; /*!< TAMP configuration control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED0[221]; /*!< Reserved, Address offset: 0x68 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32H7RSxx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup STM32H7RSxx_Peripheral_peripheralAddr + * @{ + */ +#define ITCM_BASE 0x00000000UL /*!< ITCM base address */ +#define FLASH_BASE 0x08000000UL /*!< User Flash address */ +#define OTP_AREA_BASE 0x08FFF000UL /*!< OTP Area base address */ +#define ENGI_BYTES_BASE 0x52002800UL /*!< Engi Bytes */ +#define SYSTEM_FLASH_BASE 0x1FF00000UL /*!< System Flash base address */ +#define DTCM_BASE 0x20000000UL /*!< DTCM base address */ +#define SRAM1_AXI_BASE 0x24000000UL /*!< SRAM1 base address - accessible over AXI */ +#define SRAM2_AXI_BASE 0x24020000UL /*!< SRAM2 base address - accessible over AXI */ +#define SRAM3_AXI_BASE 0x24040000UL /*!< SRAM3 base address - accessible over AXI */ +#define SRAM4_AXI_BASE 0x24060000UL /*!< SRAM4 base address - accessible over AXI */ + +#define GFXMMU_VIRTUAL_BUFFER0_BASE 0x25000000UL /*!< GFXMMU virtual buffer 0 base address */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE 0x25400000UL /*!< GFXMMU virtual buffer 1 base address */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE 0x25800000UL /*!< GFXMMU virtual buffer 2 base address */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE 0x25C00000UL /*!< GFXMMU virtual buffer 3 base address */ + +#define SRAM1_AHB_BASE 0x30000000UL /*!< SRAM1 base address */ +#define SRAM2_AHB_BASE 0x30004000UL /*!< SRAM2 base address */ +#define BKPSRAM_BASE 0x38800000UL /*!< Backup SRAM */ + +#define PERIPH_BASE 0x40000000UL /*!< AHB and APB Peripherals base address */ +#define XSPI2_BASE 0x70000000UL /*!< XSPI2 base address */ +#define XSPI1_BASE 0x90000000UL /*!< XSPI1 base address */ + +/*!< Internal memory size */ +#define ITCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define DTCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define FLASH_SIZE 0x00010000UL /*!< 64 KB */ +#define SRAM1_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase ITCM */ +#define SRAM2_AXI_SIZE 0x00020000UL /*!< 128 KB */ +#define SRAM3_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase DTCM */ +#define SRAM4_AXI_SIZE 0x00012000UL /*!< 72 KB default, can be decreased to 0 KB when RAM ECC is disable */ +#define SRAM_AHB_SIZE 0x00004000UL /*!< Both AHB SRAMs are 16 KB */ +#define BKPSRAM_SIZE 0x00001000UL /*!< 4 KB */ + +/*!< OTP Area size */ +#define OTP_SIZE 0x400U /* 1 KB */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) +#define APB5PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define AHB5PERIPH_BASE (PERIPH_BASE + 0x12000000UL) +#define APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x8400UL) +#define MDIOS_BASE (APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA100UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA400UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xEC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00UL) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPDMA1_Channel0_BASE (GPDMA1_BASE + 0x0050UL) +#define GPDMA1_Channel1_BASE (GPDMA1_BASE + 0x00D0UL) +#define GPDMA1_Channel2_BASE (GPDMA1_BASE + 0x0150UL) +#define GPDMA1_Channel3_BASE (GPDMA1_BASE + 0x01D0UL) +#define GPDMA1_Channel4_BASE (GPDMA1_BASE + 0x0250UL) +#define GPDMA1_Channel5_BASE (GPDMA1_BASE + 0x02D0UL) +#define GPDMA1_Channel6_BASE (GPDMA1_BASE + 0x0350UL) +#define GPDMA1_Channel7_BASE (GPDMA1_BASE + 0x03D0UL) +#define GPDMA1_Channel8_BASE (GPDMA1_BASE + 0x0450UL) +#define GPDMA1_Channel9_BASE (GPDMA1_BASE + 0x04D0UL) +#define GPDMA1_Channel10_BASE (GPDMA1_BASE + 0x0550UL) +#define GPDMA1_Channel11_BASE (GPDMA1_BASE + 0x05D0UL) +#define GPDMA1_Channel12_BASE (GPDMA1_BASE + 0x0650UL) +#define GPDMA1_Channel13_BASE (GPDMA1_BASE + 0x06D0UL) +#define GPDMA1_Channel14_BASE (GPDMA1_BASE + 0x0750UL) +#define GPDMA1_Channel15_BASE (GPDMA1_BASE + 0x07D0UL) +#define ADC1_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ADF1_BASE (AHB1PERIPH_BASE + 0xF000UL) +#define ADF1_Filter0_BASE (ADF1_BASE + 0x0080UL) +#define USB_OTG_HS_PERIPH_BASE (AHB1PERIPH_BASE + 0x20000UL) +#define USB_OTG_FS_PERIPH_BASE (AHB1PERIPH_BASE + 0x60000UL) + +/*!< AHB2 peripherals */ +#define PSSI_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define SDMMC2_BASE (AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (AHB2PERIPH_BASE + 0x2800UL) +#define CORDIC_BASE (AHB2PERIPH_BASE + 0x4400UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE AHB3PERIPH_BASE +#define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL) +#define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL) +#define CRYP_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define SAES_BASE (AHB3PERIPH_BASE + 0x1000UL) +#define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL) + +/*!< APB5 peripherals */ +#define DCMIPP_BASE (APB5PERIPH_BASE + 0x2000UL) +#define GFXTIM_BASE (APB5PERIPH_BASE + 0x4000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE AHB5PERIPH_BASE +#define HPDMA1_Channel0_BASE (HPDMA1_BASE + 0x0050UL) +#define HPDMA1_Channel1_BASE (HPDMA1_BASE + 0x00D0UL) +#define HPDMA1_Channel2_BASE (HPDMA1_BASE + 0x0150UL) +#define HPDMA1_Channel3_BASE (HPDMA1_BASE + 0x01D0UL) +#define HPDMA1_Channel4_BASE (HPDMA1_BASE + 0x0250UL) +#define HPDMA1_Channel5_BASE (HPDMA1_BASE + 0x02D0UL) +#define HPDMA1_Channel6_BASE (HPDMA1_BASE + 0x0350UL) +#define HPDMA1_Channel7_BASE (HPDMA1_BASE + 0x03D0UL) +#define HPDMA1_Channel8_BASE (HPDMA1_BASE + 0x0450UL) +#define HPDMA1_Channel9_BASE (HPDMA1_BASE + 0x04D0UL) +#define HPDMA1_Channel10_BASE (HPDMA1_BASE + 0x0550UL) +#define HPDMA1_Channel11_BASE (HPDMA1_BASE + 0x05D0UL) +#define HPDMA1_Channel12_BASE (HPDMA1_BASE + 0x0650UL) +#define HPDMA1_Channel13_BASE (HPDMA1_BASE + 0x06D0UL) +#define HPDMA1_Channel14_BASE (HPDMA1_BASE + 0x0750UL) +#define HPDMA1_Channel15_BASE (HPDMA1_BASE + 0x07D0UL) +#define DMA2D_BASE (AHB5PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB5PERIPH_BASE + 0x2000UL) +#define JPEG_BASE (AHB5PERIPH_BASE + 0x3000UL) +#define FMC_R_BASE (AHB5PERIPH_BASE + 0x4000UL) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) +#define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) +#define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) +#define RAMECC1_Monitor0_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) +#define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) +#define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) +#define MCE1_BASE (AHB5PERIPH_BASE + 0xB800UL) +#define MCE1_REGION1_BASE (MCE1_BASE + 0x040UL) +#define MCE1_REGION2_BASE (MCE1_BASE + 0x050UL) +#define MCE1_REGION3_BASE (MCE1_BASE + 0x060UL) +#define MCE1_REGION4_BASE (MCE1_BASE + 0x070UL) +#define MCE1_CONTEXT1_BASE (MCE1_BASE + 0x240UL) +#define MCE1_CONTEXT2_BASE (MCE1_BASE + 0x270UL) +#define MCE2_BASE (AHB5PERIPH_BASE + 0xBC00UL) +#define MCE2_REGION1_BASE (MCE2_BASE + 0x040UL) +#define MCE2_REGION2_BASE (MCE2_BASE + 0x050UL) +#define MCE2_REGION3_BASE (MCE2_BASE + 0x060UL) +#define MCE2_REGION4_BASE (MCE2_BASE + 0x070UL) +#define MCE3_BASE (AHB5PERIPH_BASE + 0xC000UL) +#define MCE3_REGION1_BASE (MCE3_BASE + 0x040UL) +#define MCE3_REGION2_BASE (MCE3_BASE + 0x050UL) +#define MCE3_REGION3_BASE (MCE3_BASE + 0x060UL) +#define MCE3_REGION4_BASE (MCE3_BASE + 0x070UL) +#define GFXMMU_BASE (AHB5PERIPH_BASE + 0x010000UL) + +/*!< APB4 peripherals */ +#define EXTI_BASE APB4PERIPH_BASE +#define SBS_BASE (APB4PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB4PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (APB4PERIPH_BASE + 0x1400UL) +#define LPTIM2_BASE (APB4PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (APB4PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (APB4PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (APB4PERIPH_BASE + 0x3000UL) +#define VREFBUF_BASE (APB4PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (APB4PERIPH_BASE + 0x4000UL) +#define TAMP_BASE (APB4PERIPH_BASE + 0x4400UL) +#define IWDG_BASE (APB4PERIPH_BASE + 0x4800UL) +#define DTS_BASE (APB4PERIPH_BASE + 0x6800UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE AHB4PERIPH_BASE +#define GPIOB_BASE (AHB4PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB4PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB4PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB4PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB4PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB4PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB4PERIPH_BASE + 0x1C00UL) +#define GPIOM_BASE (AHB4PERIPH_BASE + 0x3000UL) +#define GPION_BASE (AHB4PERIPH_BASE + 0x3400UL) +#define GPIOO_BASE (AHB4PERIPH_BASE + 0x3800UL) +#define GPIOP_BASE (AHB4PERIPH_BASE + 0x3C00UL) +#define RCC_BASE (AHB4PERIPH_BASE + 0x4400UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x4800UL) +#define CRC_BASE (AHB4PERIPH_BASE + 0x4C00UL) +#define RAMECC2_BASE (AHB4PERIPH_BASE + 0x7000UL) +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x40UL) + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +/*!< AXIM registers base address */ +#define AXIM_BASE (0xBFF00000UL) +#define AXIM_ASIB1_BASE (AXIM_BASE + 0x42000UL) +#define AXIM_ASIB2_BASE (AXIM_BASE + 0x43000UL) +#define AXIM_ASIB3_BASE (AXIM_BASE + 0x44000UL) +#define AXIM_ASIB4_BASE (AXIM_BASE + 0x45000UL) +#define AXIM_ASIB5_BASE (AXIM_BASE + 0x46000UL) +#define AXIM_ASIB6_BASE (AXIM_BASE + 0x47000UL) +#define AXIM_ASIB7_BASE (AXIM_BASE + 0x48000UL) +#define AXIM_ASIB8_BASE (AXIM_BASE + 0x49000UL) +#define AXIM_ASIB9_BASE (AXIM_BASE + 0x4A000UL) +#define AXIM_ASIB10_BASE (AXIM_BASE + 0x4B000UL) +#define AXIM_ASIB11_BASE (AXIM_BASE + 0x4C000UL) +#define AXIM_AMIB1_BASE (AXIM_BASE + 0x02000UL) +#define AXIM_AMIB2_BASE (AXIM_BASE + 0x03000UL) +#define AXIM_AMIB3_BASE (AXIM_BASE + 0x04000UL) +#define AXIM_AMIB4_BASE (AXIM_BASE + 0x05000UL) +#define AXIM_AMIB5_BASE (AXIM_BASE + 0x06000UL) +#define AXIM_AMIB6_BASE (AXIM_BASE + 0x07000UL) +#define AXIM_AMIB7_BASE (AXIM_BASE + 0x08000UL) +#define AXIM_AMIB8_BASE (AXIM_BASE + 0x09000UL) +#define AXIM_AMIB9_BASE (AXIM_BASE + 0x0A000UL) +#define AXIM_AMIB10_BASE (AXIM_BASE + 0x0B000UL) + +/*!< Unique device ID register base address */ +#define UID_BASE (0x08FFF800UL) + +/*!< Flash size data register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) + +/*!< Package data register base address */ +#define PACKAGE_BASE (0x08FFF80CUL) + +/* USB OTG registers base addresses */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_PFUNC_START (0x1FF1FD4CUL) +#define RSSLIB_SYS_FLASH_PFUNC_END (0x1FF1FD78UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x1FF1FD4CUL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t Destination; /*!< OBKeys destination information where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + +/** + * @brief Prototype of RSSLIB Set Secure OB Function + * @detail This function configure a secure OB. + * @param OB address among following values: + * &(FLASH->WRPSRP), &(FLASH->HDPSRP) or &(FLASH->ROTSRP) + * @param OB mask (example 0x000000FF for updating WRP OB). + * @param OB value + * @param OB Pos: bit position of OB value. + * ObValue << ObPos must be aligned on ObMask. + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetSecOB_TypeDef)(uint32_t ObAddr, uint32_t ObMask, uint32_t ObValue, uint32_t ObPos); + +/** + * @brief Prototype of RSSLIB Get RSS Status Function + * @detail This function return RSS Status. + * Calling GetRssStatus is only relevant after calling + * SetSecOB or DataProvisioning. + * @param none. + * @retval RSSLIB_SUCCESS on success, otherwise return an error 0xF5F5xxxx. + */ +typedef uint32_t (*RSSLIB_GetRssStatus_TypeDef)(void); + +/** + * @brief Prototype of RSSLIB Set Product State Function + * @detail This function change Product State. + * @param Requested Product State among following values: + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetProductState_TypeDef)(uint32_t ProductState); + +/** + * @brief Prototype of RSSLIB Get Product State Function + * @detail This function return current Product State. + * @param none. + * @retval RSSLIB_RSS_ERROR on error, + * otherwise return product state among following values: + * 0x39 : Open + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + */ +typedef uint32_t (*RSSLIB_GetProductState_TypeDef)(void); + + +/** + * @brief RSSLib callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_SetSecOB_TypeDef SetSecOB; + uint32_t RESERVED1[4]; + __IM RSSLIB_GetRssStatus_TypeDef GetRssStatus; + __IM RSSLIB_SetProductState_TypeDef SetProductState; + __IM RSSLIB_DataProvisioning_TypeDef DataProvisioning; + __IM RSSLIB_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_GetProductState_TypeDef GetProductState; +} RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H7RSxx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_Peripheral_declaration + * @{ + */ + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADF1 ((MDF_TypeDef *) ADF1_BASE) +#define ADF1_Filter0 ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE) +#define AXIM_AMIB_1 ((AXIM_AMIB_TypeDef *) AXIM_AMIB1_BASE ) +#define AXIM_AMIB_2 ((AXIM_AMIB_TypeDef *) AXIM_AMIB2_BASE ) +#define AXIM_AMIB_3 ((AXIM_AMIB_TypeDef *) AXIM_AMIB3_BASE ) +#define AXIM_AMIB_4 ((AXIM_AMIB_TypeDef *) AXIM_AMIB4_BASE ) +#define AXIM_AMIB_5 ((AXIM_AMIB_TypeDef *) AXIM_AMIB5_BASE ) +#define AXIM_AMIB_6 ((AXIM_AMIB_TypeDef *) AXIM_AMIB6_BASE ) +#define AXIM_AMIB_7 ((AXIM_AMIB_TypeDef *) AXIM_AMIB7_BASE ) +#define AXIM_AMIB_8 ((AXIM_AMIB_TypeDef *) AXIM_AMIB8_BASE ) +#define AXIM_AMIB_9 ((AXIM_AMIB_TypeDef *) AXIM_AMIB9_BASE ) +#define AXIM_AMIB_10 ((AXIM_AMIB_TypeDef *) AXIM_AMIB10_BASE) +#define AXIM_ASIB_1 ((AXIM_ASIB_TypeDef *) AXIM_ASIB1_BASE ) +#define AXIM_ASIB_2 ((AXIM_ASIB_TypeDef *) AXIM_ASIB2_BASE ) +#define AXIM_ASIB_3 ((AXIM_ASIB_TypeDef *) AXIM_ASIB3_BASE ) +#define AXIM_ASIB_4 ((AXIM_ASIB_TypeDef *) AXIM_ASIB4_BASE ) +#define AXIM_ASIB_5 ((AXIM_ASIB_TypeDef *) AXIM_ASIB5_BASE ) +#define AXIM_ASIB_6 ((AXIM_ASIB_TypeDef *) AXIM_ASIB6_BASE ) +#define AXIM_ASIB_7 ((AXIM_ASIB_TypeDef *) AXIM_ASIB7_BASE ) +#define AXIM_ASIB_8 ((AXIM_ASIB_TypeDef *) AXIM_ASIB8_BASE ) +#define AXIM_ASIB_9 ((AXIM_ASIB_TypeDef *) AXIM_ASIB9_BASE ) +#define AXIM_ASIB_10 ((AXIM_ASIB_TypeDef *) AXIM_ASIB10_BASE) +#define AXIM_ASIB_11 ((AXIM_ASIB_TypeDef *) AXIM_ASIB11_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define GFXTIM ((GFXTIM_TypeDef *) GFXTIM_BASE) +#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE) +#define GPDMA1 ((DMA_TypeDef *) GPDMA1_BASE) +#define GPDMA1_Channel0 ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE) +#define GPDMA1_Channel1 ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE) +#define GPDMA1_Channel2 ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE) +#define GPDMA1_Channel3 ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE) +#define GPDMA1_Channel4 ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE) +#define GPDMA1_Channel5 ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE) +#define GPDMA1_Channel6 ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE) +#define GPDMA1_Channel7 ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE) +#define GPDMA1_Channel8 ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE) +#define GPDMA1_Channel9 ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE) +#define GPDMA1_Channel10 ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE) +#define GPDMA1_Channel11 ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE) +#define GPDMA1_Channel12 ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE) +#define GPDMA1_Channel13 ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE) +#define GPDMA1_Channel14 ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE) +#define GPDMA1_Channel15 ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) +#define GPION ((GPIO_TypeDef *) GPION_BASE) +#define GPIOO ((GPIO_TypeDef *) GPIOO_BASE) +#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define HPDMA1 ((DMA_TypeDef *) HPDMA1_BASE) +#define HPDMA1_Channel0 ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE) +#define HPDMA1_Channel1 ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE) +#define HPDMA1_Channel2 ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE) +#define HPDMA1_Channel3 ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE) +#define HPDMA1_Channel4 ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE) +#define HPDMA1_Channel5 ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE) +#define HPDMA1_Channel6 ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE) +#define HPDMA1_Channel7 ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE) +#define HPDMA1_Channel8 ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE) +#define HPDMA1_Channel9 ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE) +#define HPDMA1_Channel10 ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE) +#define HPDMA1_Channel11 ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE) +#define HPDMA1_Channel12 ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE) +#define HPDMA1_Channel13 ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE) +#define HPDMA1_Channel14 ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE) +#define HPDMA1_Channel15 ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE) +#define JPEG ((JPEG_TypeDef *) JPEG_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define MCE1 ((MCE_TypeDef *) MCE1_BASE) +#define MCE1_REGION1 ((MCE_Region_TypeDef *) MCE1_REGION1_BASE) +#define MCE1_REGION2 ((MCE_Region_TypeDef *) MCE1_REGION2_BASE) +#define MCE1_REGION3 ((MCE_Region_TypeDef *) MCE1_REGION3_BASE) +#define MCE1_REGION4 ((MCE_Region_TypeDef *) MCE1_REGION4_BASE) +#define MCE1_CONTEXT1 ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE) +#define MCE1_CONTEXT2 ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE) +#define MCE2 ((MCE_TypeDef *) MCE2_BASE) +#define MCE2_REGION1 ((MCE_Region_TypeDef *) MCE2_REGION1_BASE) +#define MCE2_REGION2 ((MCE_Region_TypeDef *) MCE2_REGION2_BASE) +#define MCE2_REGION3 ((MCE_Region_TypeDef *) MCE2_REGION3_BASE) +#define MCE2_REGION4 ((MCE_Region_TypeDef *) MCE2_REGION4_BASE) +#define MCE3 ((MCE_TypeDef *) MCE3_BASE) +#define MCE3_REGION1 ((MCE_Region_TypeDef *) MCE3_REGION1_BASE) +#define MCE3_REGION2 ((MCE_Region_TypeDef *) MCE3_REGION2_BASE) +#define MCE3_REGION3 ((MCE_Region_TypeDef *) MCE3_REGION3_BASE) +#define MCE3_REGION4 ((MCE_Region_TypeDef *) MCE3_REGION4_BASE) +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC1_Monitor0 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor0_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SAES ((SAES_TypeDef *) SAES_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *) SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *) SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *) SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *) SAI2_Block_B_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define XSPI1 ((XSPI_TypeDef *) XSPI1_R_BASE) +#define XSPI2 ((XSPI_TypeDef *) XSPI2_R_BASE) +#define XSPIM ((XSPIM_TypeDef *) XSPIM_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) + +/** @} */ /* End of group STM32H7RSxx_Peripheral_declaration */ + +/** @addtogroup STM32H7RSxx_Peripheral_Exported_constants + * @{ + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Registers_Bits_Definition + * @{ + */ +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_ADFCFG_Pos (2U) +#define ADC_CFGR_ADFCFG_Msk (0x1UL << ADC_CFGR_ADFCFG_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_ADFCFG ADC_CFGR_ADFCFG_Msk /*!< ADC ADF transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register ***************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal path to VDDCORE */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* AXIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AXIM_ASIB_FNMOD2 register **********/ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_ASIB_READQOS register ********/ +#define AXIM_ASIB_READQOS_AR_QOS_Pos (0U) +#define AXIM_ASIB_READQOS_AR_QOS_Msk (0xFUL << AXIM_ASIB_READQOS_AR_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_READQOS_AR_QOS AXIM_ASIB_READQOS_AR_QOS_Msk /*!< Read channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_WRITEQOS register *******/ +#define AXIM_ASIB_WRITEQOS_AW_QOS_Pos (0U) +#define AXIM_ASIB_WRITEQOS_AW_QOS_Msk (0xFUL << AXIM_ASIB_WRITEQOS_AW_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_WRITEQOS_AW_QOS AXIM_ASIB_WRITEQOS_AW_QOS_Msk /*!< Write channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_FNMOD register **********/ +#define AXIM_ASIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_ASIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD_READ_ISS AXIM_ASIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_ASIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS AXIM_ASIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMODBMISS register **********/ +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODBMISS_READ_ISS AXIM_AMIB_FNMODBMISS_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMOD2 register **********/ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_AMIB_FNMODLB register **********/ +#define AXIM_AMIB_FNMODLB_LONG_BURST_Pos (0U) +#define AXIM_AMIB_FNMODLB_LONG_BURST_Msk (0x1UL << AXIM_AMIB_FNMODLB_LONG_BURST_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODLB_LONG_BURST AXIM_AMIB_FNMODLB_LONG_BURST_Msk /*!< Long bursts can be generated */ + +/******************* Bit definition for AXIM_AMIB_FNMOD register **********/ +#define AXIM_AMIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD_READ_ISS AXIM_AMIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS AXIM_AMIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5U) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6U) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8U) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10U) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14U) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18U) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29U) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30U) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31U) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2U) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3U) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register ******************/ +#define PSSI_RIS_OVR_RIS_Pos (1U) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register ******************/ +#define PSSI_IER_OVR_IE_Pos (1U) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register ******************/ +#define PSSI_MIS_OVR_MIS_Pos (1U) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register ******************/ +#define PSSI_ICR_OVR_ISC_Pos (1U) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0U) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_SVOS_Pos (0U) +#define PWR_CR1_SVOS_Msk (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */ + +#define PWR_CR1_PVDE_Pos (4U) +#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Programmable Voltage detector enable. */ + +#define PWR_CR1_PLS_Pos (5U) +#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */ +#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */ + +#define PWR_CR1_DBP_Pos (8U) +#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */ + +#define PWR_CR1_FLPS_Pos (9U) +#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in STOP */ + +#define PWR_CR1_BOOSTE_Pos (11U) +#define PWR_CR1_BOOSTE_Msk (0x1UL << PWR_CR1_BOOSTE_Pos) /*!< 0x00000800 */ +#define PWR_CR1_BOOSTE PWR_CR1_BOOSTE_Msk /*!< Analog Switch VBoost control. */ + +#define PWR_CR1_AVDREADY_Pos (12) +#define PWR_CR1_AVDREADY_Msk (0x1UL << PWR_CR1_AVDREADY_Pos) /*!< 0x00001000 */ +#define PWR_CR1_AVDREADY PWR_CR1_AVDREADY_Msk /*!< Analog Voltage Ready. */ + +#define PWR_CR1_AVDEN_Pos (13U) +#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00002000 */ +#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */ + +#define PWR_CR1_ALS_Pos (14U) +#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x0000A000 */ +#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */ +#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00004000 */ +#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_SR1 register ********************/ +#define PWR_SR1_ACTVOS_Pos (0U) +#define PWR_SR1_ACTVOS_Msk (0x1UL << PWR_SR1_ACTVOS_Pos) /*!< 0x00000001 */ +#define PWR_SR1_ACTVOS PWR_SR1_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ + +#define PWR_SR1_ACTVOSRDY_Pos (1U) +#define PWR_SR1_ACTVOSRDY_Msk (0x1UL << PWR_SR1_ACTVOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_SR1_ACTVOSRDY PWR_SR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */ + +#define PWR_SR1_PVDO_Pos (4U) +#define PWR_SR1_PVDO_Msk (0x1UL << PWR_SR1_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SR1_PVDO PWR_SR1_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +#define PWR_SR1_AVDO_Pos (13U) +#define PWR_SR1_AVDO_Msk (0x1UL << PWR_SR1_AVDO_Pos) /*!< 0x00002000 */ +#define PWR_SR1_AVDO PWR_SR1_AVDO_Msk /*!< Analog Voltage Detect Output on VDDA */ + +/******************** Bit definition for PWR_CSR1 register ********************/ +#define PWR_CSR1_BREN_Pos (0U) +#define PWR_CSR1_BREN_Msk (0x1UL << PWR_CSR1_BREN_Pos) /*!< 0x00000001 */ +#define PWR_CSR1_BREN PWR_CSR1_BREN_Msk /*!< Backup regulator enable */ + +#define PWR_CSR1_MONEN_Pos (4U) +#define PWR_CSR1_MONEN_Msk (0x1UL << PWR_CSR1_MONEN_Pos) /*!< 0x00000010 */ +#define PWR_CSR1_MONEN PWR_CSR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ + +#define PWR_CSR1_BRRDY_Pos (16U) +#define PWR_CSR1_BRRDY_Msk (0x1UL << PWR_CSR1_BRRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR1_BRRDY PWR_CSR1_BRRDY_Msk /*!< Backup regulator ready */ + +#define PWR_CSR1_VBATL_Pos (20U) +#define PWR_CSR1_VBATL_Msk (0x1UL << PWR_CSR1_VBATL_Pos) /*!< 0x00100000 */ +#define PWR_CSR1_VBATL PWR_CSR1_VBATL_Msk /*!< Monitored VBAT level above low threshold */ + +#define PWR_CSR1_VBATH_Pos (21U) +#define PWR_CSR1_VBATH_Msk (0x1UL << PWR_CSR1_VBATH_Pos) /*!< 0x00200000 */ +#define PWR_CSR1_VBATH PWR_CSR1_VBATH_Msk /*!< Monitored VBAT level above high threshold */ + +#define PWR_CSR1_TEMPL_Pos (22U) +#define PWR_CSR1_TEMPL_Msk (0x1UL << PWR_CSR1_TEMPL_Pos) /*!< 0x00400000 */ +#define PWR_CSR1_TEMPL PWR_CSR1_TEMPL_Msk /*!< Monitored temperature level above low threshold */ + +#define PWR_CSR1_TEMPH_Pos (23U) +#define PWR_CSR1_TEMPH_Msk (0x1UL << PWR_CSR1_TEMPH_Pos) /*!< 0x00800000 */ +#define PWR_CSR1_TEMPH PWR_CSR1_TEMPH_Msk /*!< Monitored temperature level above high threshold */ + +/******************** Bit definition for PWR_CSR2 register ********************/ +#define PWR_CSR2_BYPASS_Pos (0U) +#define PWR_CSR2_BYPASS_Msk (0x1UL << PWR_CSR2_BYPASS_Pos) /*!< 0x00000001 */ +#define PWR_CSR2_BYPASS PWR_CSR2_BYPASS_Msk /*!< Power Management Unit bypass */ + +#define PWR_CSR2_LDOEN_Pos (1U) +#define PWR_CSR2_LDOEN_Msk (0x1UL << PWR_CSR2_LDOEN_Pos) /*!< 0x00000002 */ +#define PWR_CSR2_LDOEN PWR_CSR2_LDOEN_Msk /*!< Low Drop-Out regulator enable */ + +#define PWR_CSR2_SDEN_Pos (2U) +#define PWR_CSR2_SDEN_Msk (0x1UL << PWR_CSR2_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CSR2_SDEN PWR_CSR2_SDEN_Msk /*!< SMPS Step-down converter enable */ + +#define PWR_CSR2_SMPSEXTHP_Pos (3U) +#define PWR_CSR2_SMPSEXTHP_Msk (0x1UL << PWR_CSR2_SMPSEXTHP_Pos) /*!< 0x00000008 */ +#define PWR_CSR2_SMPSEXTHP PWR_CSR2_SMPSEXTHP_Msk /*!< SMPS external power delivery selection */ + +#define PWR_CSR2_SDHILEVEL_Pos (4U) +#define PWR_CSR2_SDHILEVEL_Msk (0x1UL << PWR_CSR2_SDHILEVEL_Pos) /*!< 0x00000030 */ +#define PWR_CSR2_SDHILEVEL PWR_CSR2_SDHILEVEL_Msk /*!< SMPS step-down converter voltage output for LDO or external supply */ + +#define PWR_CSR2_VBE_Pos (8U) +#define PWR_CSR2_VBE_Msk (0x1UL << PWR_CSR2_VBE_Pos) /*!< 0x00000100 */ +#define PWR_CSR2_VBE PWR_CSR2_VBE_Msk /*!< VBAT charging enable */ + +#define PWR_CSR2_VBRS_Pos (9U) +#define PWR_CSR2_VBRS_Msk (0x1UL << PWR_CSR2_VBRS_Pos) /*!< 0x00000200 */ +#define PWR_CSR2_VBRS PWR_CSR2_VBRS_Msk /*!< VBAT charging resistor selection */ + +#define PWR_CSR2_XSPICAP1_Pos (10U) +#define PWR_CSR2_XSPICAP1_Msk (0x3UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000C00 */ +#define PWR_CSR2_XSPICAP1 PWR_CSR2_XSPICAP1_Msk /*!< XSPI port 1 capacitor control bits */ +#define PWR_CSR2_XSPICAP1_0 (0x1UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000400 */ +#define PWR_CSR2_XSPICAP1_1 (0x2UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000800 */ + +#define PWR_CSR2_XSPICAP2_Pos (12U) +#define PWR_CSR2_XSPICAP2_Msk (0x3UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00003000 */ +#define PWR_CSR2_XSPICAP2 PWR_CSR2_XSPICAP2_Msk /*!< XSPI port 2 capacitor control bits */ +#define PWR_CSR2_XSPICAP2_0 (0x1UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00001000 */ +#define PWR_CSR2_XSPICAP2_1 (0x2UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00002000 */ + +#define PWR_CSR2_EN_XSPIM1_Pos (14U) +#define PWR_CSR2_EN_XSPIM1_Msk (0x1UL << PWR_CSR2_EN_XSPIM1_Pos) /*!< 0x00004000 */ +#define PWR_CSR2_EN_XSPIM1 PWR_CSR2_EN_XSPIM1_Msk /*!< XSPIM1 external supply enable */ + +#define PWR_CSR2_EN_XSPIM2_Pos (15U) +#define PWR_CSR2_EN_XSPIM2_Msk (0x1UL << PWR_CSR2_EN_XSPIM2_Pos) /*!< 0x00008000 */ +#define PWR_CSR2_EN_XSPIM2 PWR_CSR2_EN_XSPIM2_Msk /*!< XSPIM2 external supply enable */ + +#define PWR_CSR2_SDEXTRDY_Pos (16U) +#define PWR_CSR2_SDEXTRDY_Msk (0x1UL << PWR_CSR2_SDEXTRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR2_SDEXTRDY PWR_CSR2_SDEXTRDY_Msk /*!< SMPS External supply ready */ + +#define PWR_CSR2_USB33DEN_Pos (24U) +#define PWR_CSR2_USB33DEN_Msk (0x1UL << PWR_CSR2_USB33DEN_Pos) /*!< 0x01000000 */ +#define PWR_CSR2_USB33DEN PWR_CSR2_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */ + +#define PWR_CSR2_USBREGEN_Pos (25U) +#define PWR_CSR2_USBREGEN_Msk (0x1UL << PWR_CSR2_USBREGEN_Pos) /*!< 0x02000000 */ +#define PWR_CSR2_USBREGEN PWR_CSR2_USBREGEN_Msk /*!< USB regulator enable */ + +#define PWR_CSR2_USB33RDY_Pos (26U) +#define PWR_CSR2_USB33RDY_Msk (0x1UL << PWR_CSR2_USB33RDY_Pos) /*!< 0x04000000 */ +#define PWR_CSR2_USB33RDY PWR_CSR2_USB33RDY_Msk /*!< USB supply ready */ + +#define PWR_CSR2_USBHSREGEN_Pos (27U) +#define PWR_CSR2_USBHSREGEN_Msk (0x1UL << PWR_CSR2_USBHSREGEN_Pos) /*!< 0x08000000 */ +#define PWR_CSR2_USBHSREGEN PWR_CSR2_USBHSREGEN_Msk /*!< USB HS regulator enable */ + +/******************** Bit definition for PWR_CSR3 register ********************/ +#define PWR_CSR3_PDDS_Pos (0U) +#define PWR_CSR3_PDDS_Msk (0x1UL << PWR_CSR3_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CSR3_PDDS PWR_CSR3_PDDS_Msk /*!< D1 domain Power Down Deepsleep */ + +#define PWR_CSR3_CSSF_Pos (1U) +#define PWR_CSR3_CSSF_Msk (0x1UL << PWR_CSR3_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CSR3_CSSF PWR_CSR3_CSSF_Msk /*!< Clear Standby and Stop flag */ + +#define PWR_CSR3_STOPF_Pos (8U) +#define PWR_CSR3_STOPF_Msk (0x1UL << PWR_CSR3_STOPF_Pos) /*!< 0x00000080 */ +#define PWR_CSR3_STOPF PWR_CSR3_STOPF_Msk /*!< STOP Flag */ + +#define PWR_CSR3_SBF_Pos (9U) +#define PWR_CSR3_SBF_Msk (0x1UL << PWR_CSR3_SBF_Pos) /*!< 0x00000100 */ +#define PWR_CSR3_SBF PWR_CSR3_SBF_Msk /*!< System STANDBY Flag */ + +/******************** Bit definition for PWR_CSR4 register ********************/ +#define PWR_CSR4_VOS_Pos (0U) +#define PWR_CSR4_VOS_Msk (0x1UL << PWR_CSR4_VOS_Pos) /*!< 0x00000001 */ +#define PWR_CSR4_VOS PWR_CSR4_VOS_Msk /*!< Voltage Scaling selection according performance */ + +#define PWR_CSR4_VOSRDY_Pos (1U) +#define PWR_CSR4_VOSRDY_Msk (0x1UL << PWR_CSR4_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_CSR4_VOSRDY PWR_CSR4_VOSRDY_Msk /*!< VOSRDY: VOS Ready bit for VCORE voltage scaling output selection. */ + +/******************** Bit definition for PWR_WKUPCR register ********************/ +#define PWR_WKUPCR_WKUPC_Pos (0U) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Pin Flag 1 to 4 */ +#define PWR_WKUPCR_WKUPC1_Pos (0U) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */ +#define PWR_WKUPCR_WKUPC2_Pos (1U) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */ +#define PWR_WKUPCR_WKUPC3_Pos (2U) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */ +#define PWR_WKUPCR_WKUPC4_Pos (3U) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPFR register ********************/ +#define PWR_WKUPFR_WKUPF1_Pos (0U) +#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */ +#define PWR_WKUPFR_WKUPF2_Pos (1U) +#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */ +#define PWR_WKUPFR_WKUPF3_Pos (2U) +#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */ +#define PWR_WKUPFR_WKUPF4_Pos (3U) +#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPEPR register ********************/ +#define PWR_WKUPEPR_WKUPEN_Pos (0U) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000000F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ +#define PWR_WKUPEPR_WKUPEN1_Pos (0U) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1U) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2U) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3U) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */ + +#define PWR_WKUPEPR_WKUPP_Pos (8U) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000F00 */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8U) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */ +#define PWR_WKUPEPR_WKUPP2_Pos (9U) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */ +#define PWR_WKUPEPR_WKUPP3_Pos (10U) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */ +#define PWR_WKUPEPR_WKUPP4_Pos (11U) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */ + +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for PWR_UCPDRR register ********************/ +#define PWR_UCPDR_UCPD_DBDIS_Pos (0U) +#define PWR_UCPDR_UCPD_DBDIS_Msk (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos) /*!< 0x00000001 */ +#define PWR_UCPDR_UCPD_DBDIS PWR_UCPDR_UCPD_DBDIS_Msk /*!< UCPD dead battery disable */ + +#define PWR_UCPDR_UCPD_STBY_Pos (1U) +#define PWR_UCPDR_UCPD_STBY_Msk (0x1UL << PWR_UCPDR_UCPD_STBY_Pos) /*!< 0x00000002 */ +#define PWR_UCPDR_UCPD_STBY PWR_UCPDR_UCPD_STBY_Msk /*!< UCPD Standby mode */ + +/******************** Bit definition for PWR_APCR register ********************/ +#define PWR_APCR_APC_Pos (0U) +#define PWR_APCR_APC_Msk (0x1UL << PWR_APCR_APC_Pos) /*!< 0x00000001 */ +#define PWR_APCR_APC PWR_APCR_APC_Msk /*!< Apply pull configuration register */ + +#define PWR_APCR_PN7_PUPD_Pos (16U) +#define PWR_APCR_PN7_PUPD_Msk (0x1UL << PWR_APCR_PN7_PUPD_Pos) /*!< 0x00010000 */ +#define PWR_APCR_PN7_PUPD PWR_APCR_PN7_PUPD_Msk /*!< Port N bit 7 pull-up/down configuration */ + +#define PWR_APCR_PO5_PUPD_Pos (17) +#define PWR_APCR_PO5_PUPD_Msk (0x1UL << PWR_APCR_PO5_PUPD_Pos) /*!< 0x00020000 */ +#define PWR_APCR_PO5_PUPD PWR_APCR_PO5_PUPD_Msk /*!< Port O bit 5 pull-up/down configuration */ + +#define PWR_APCR_I3CPB6_PU_Pos (28U) +#define PWR_APCR_I3CPB6_PU_Msk (0x1UL << PWR_APCR_I3CPB6_PU_Pos) /*!< 0x10000000 */ +#define PWR_APCR_I3CPB6_PU PWR_APCR_I3CPB6_PU_Msk /*!< Port PB6 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB7_PU_Pos (29U) +#define PWR_APCR_I3CPB7_PU_Msk (0x1UL << PWR_APCR_I3CPB7_PU_Pos) /*!< 0x20000000 */ +#define PWR_APCR_I3CPB7_PU PWR_APCR_I3CPB7_PU_Msk /*!< Port PB7 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB8_PU_Pos (30U) +#define PWR_APCR_I3CPB8_PU_Msk (0x1UL << PWR_APCR_I3CPB8_PU_Pos) /*!< 0x40000000 */ +#define PWR_APCR_I3CPB8_PU PWR_APCR_I3CPB8_PU_Msk /*!< Port PB8 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB9_PU_Pos (31U) +#define PWR_APCR_I3CPB9_PU_Msk (0x1UL << PWR_APCR_I3CPB9_PU_Pos) /*!< 0x80000000 */ +#define PWR_APCR_I3CPB9_PU PWR_APCR_I3CPB9_PU_Msk /*!< Port PB9 I3C pull-up bit configuration */ + +/******************** Bit definition for PWR_PUCRN register ********************/ +#define PWR_PUCRN_PUN1_Pos (1U) +#define PWR_PUCRN_PUN1_Msk (0x1UL << PWR_PUCRN_PUN1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRN_PUN1 PWR_PUCRN_PUN1_Msk /*!< PUN1: Port N pull-up */ + +#define PWR_PUCRN_PUN6_Pos (6U) +#define PWR_PUCRN_PUN6_Msk (0x1UL << PWR_PUCRN_PUN6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRN_PUN6 PWR_PUCRN_PUN6_Msk /*!< PUN6: Port N pull-up */ + +#define PWR_PUCRN_PUN12_Pos (12U) +#define PWR_PUCRN_PUN12_Msk (0x1UL << PWR_PUCRN_PUN12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRN_PUN12 PWR_PUCRN_PUN12_Msk /*!< PUN12: Port N pull-up */ + +/******************** Bit definition for PWR_PDCRN register ********************/ +#define PWR_PDCRN_PDN0_Pos (0U) +#define PWR_PDCRN_PDN0_Msk (0x1UL << PWR_PDCRN_PDN0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRN_PDN0 PWR_PDCRN_PDN0_Msk /*!< PDN0: Port N pull-down */ + +#define PWR_PDCRN_PDN1_Pos (1U) +#define PWR_PDCRN_PDN1_Msk (0x1UL << PWR_PDCRN_PDN1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRN_PDN1 PWR_PDCRN_PDN1_Msk /*!< PDN1: Port N pull-down */ + +#define PWR_PDCRN_PDN2N5_Pos (2U) +#define PWR_PDCRN_PDN2N5_Msk (0x1UL << PWR_PDCRN_PDN2N5_Pos) /*!< 0x00000004 */ +#define PWR_PDCRN_PDN2N5 PWR_PDCRN_PDN2N5_Msk /*!< PDN2 to PDN5: Port N pull-down */ + +#define PWR_PDCRN_PDN6_Pos (6U) +#define PWR_PDCRN_PDN6_Msk (0x1UL << PWR_PDCRN_PDN6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRN_PDN6 PWR_PDCRN_PDN6_Msk /*!< PDN6: Port N pull-down */ + +#define PWR_PDCRN_PDN8N11_Pos (8U) +#define PWR_PDCRN_PDN8N11_Msk (0x1UL << PWR_PDCRN_PDN8N11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRN_PDN8N11 PWR_PDCRN_PDN8N11_Msk /*!< PDN8 to PDN11: Port N pull-down */ + +#define PWR_PDCRN_PDN12_Pos (12U) +#define PWR_PDCRN_PDN12_Msk (0x1UL << PWR_PDCRN_PDN12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRN_PDN12 PWR_PDCRN_PDN12_Msk /*!< PDN12: Port N pull-down */ + +/******************** Bit definition for PWR_PUCRO register ********************/ +#define PWR_PUCRO_PUO0_Pos (0U) +#define PWR_PUCRO_PUO0_Msk (0x1UL << PWR_PUCRO_PUO0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRO_PUO0 PWR_PUCRO_PUO0_Msk /*!< PUO0: Port O pull-up */ + +#define PWR_PUCRO_PUO1_Pos (1U) +#define PWR_PUCRO_PUO1_Msk (0x1UL << PWR_PUCRO_PUO1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRO_PUO1 PWR_PUCRO_PUO1_Msk /*!< PUO1: Port O pull-up */ + +#define PWR_PUCRO_PUO4_Pos (4U) +#define PWR_PUCRO_PUO4_Msk (0x1UL << PWR_PUCRO_PUO4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRO_PUO4 PWR_PUCRO_PUO4_Msk /*!< PUO4: Port O pull-up */ + +/******************** Bit definition for PWR_PDCRO register ********************/ +#define PWR_PDCRO_PDO0_Pos (0U) +#define PWR_PDCRO_PDO0_Msk (0x1UL << PWR_PDCRO_PDO0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRO_PDO0 PWR_PDCRO_PDO0_Msk /*!< PDO0: Port O pull-down */ + +#define PWR_PDCRO_PDO1_Pos (1U) +#define PWR_PDCRO_PDO1_Msk (0x1UL << PWR_PDCRO_PDO1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRO_PDO1 PWR_PDCRO_PDO1_Msk /*!< PDO1: Port O pull-down */ + +#define PWR_PDCRO_PDO2_Pos (2U) +#define PWR_PDCRO_PDO2_Msk (0x1UL << PWR_PDCRO_PDO2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRO_PDO2 PWR_PDCRO_PDO2_Msk /*!< PDO2: Port O pull-down */ + +#define PWR_PDCRO_PDO3_Pos (3U) +#define PWR_PDCRO_PDO3_Msk (0x1UL << PWR_PDCRO_PDO3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRO_PDO3 PWR_PDCRO_PDO3_Msk /*!< PDO3: Port O pull-down */ + +#define PWR_PDCRO_PDO4_Pos (4U) +#define PWR_PDCRO_PDO4_Msk (0x1UL << PWR_PDCRO_PDO4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRO_PDO4 PWR_PDCRO_PDO4_Msk /*!< PDO4: Port O pull-down */ + +/******************** Bit definition for PWR_PDCRP register ********************/ +#define PWR_PDCRP_PDP0P3_Pos (0U) +#define PWR_PDCRP_PDP0P3_Msk (0x1UL << PWR_PDCRP_PDP0P3_Pos) /*!< 0x00000001 */ +#define PWR_PDCRP_PDP0P3 PWR_PDCRP_PDP0P3_Msk /*!< PPO0 to PP03 : Port P pull-down */ + +#define PWR_PDCRP_PDP4P7_Pos (4U) +#define PWR_PDCRP_PDP4P7_Msk (0x1UL << PWR_PDCRP_PDP4P7_Pos) /*!< 0x00000010 */ +#define PWR_PDCRP_PDP4P7 PWR_PDCRP_PDP4P7_Msk /*!< PPO4 to PP07 : Port P pull-down */ + +#define PWR_PDCRP_PDP8P11_Pos (8U) +#define PWR_PDCRP_PDP8P11_Msk (0x1UL << PWR_PDCRP_PDP8P11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRP_PDP8P11 PWR_PDCRP_PDP8P11_Msk /*!< PPO8 to PP11 : Port P pull-down */ + +#define PWR_PDCRP_PDP12P15_Pos (12U) +#define PWR_PDCRP_PDP12P15_Msk (0x1UL << PWR_PDCRP_PDP12P15_Pos) /*!< 0x00001000 */ +#define PWR_PDCRP_PDP12P15 PWR_PDCRP_PDP12P15_Msk /*!< PP12 to PP15 : Port P pull-down */ + + +/******************************************************************************/ +/* */ +/* RAM ECC monitoring */ +/* */ +/******************************************************************************/ +/****************** Bit definition for RAMECC_IER register ******************/ +#define RAMECC_IER_GIE_Pos (0U) +#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */ +#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */ +#define RAMECC_IER_GECCSEIE_Pos (1U) +#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */ +#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */ +#define RAMECC_IER_GECCDEIE_Pos (2U) +#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */ +#define RAMECC_IER_GECCDEBWIE_Pos (3U) +#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */ +#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */ + +/******************* Bit definition for RAMECC_CR register ******************/ +#define RAMECC_CR_ECCSEIE_Pos (2U) +#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMECC_CR_ECCDEIE_Pos (3U) +#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */ +#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMECC_CR_ECCDEBWIE_Pos (4U) +#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */ +#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */ +#define RAMECC_CR_ECCELEN_Pos (5U) +#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */ +#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */ + +/******************* Bit definition for RAMECC_SR register ******************/ +#define RAMECC_SR_SEDCF_Pos (0U) +#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */ +#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */ +#define RAMECC_SR_DEDF_Pos (1U) +#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */ +#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */ +#define RAMECC_SR_DEBWDF_Pos (2U) +#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */ +#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */ + +/****************** Bit definition for RAMECC_FAR register ******************/ +#define RAMECC_FAR_FADD_Pos (0U) +#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */ + +/****************** Bit definition for RAMECC_FDRL register *****************/ +#define RAMECC_FDRL_FDATAL_Pos (0U) +#define RAMECC_FDRL_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FDRL_FDATAL_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRL_FDATAL RAMECC_FDRL_FDATAL_Msk /*!< Failing data low */ + +/****************** Bit definition for RAMECC_FDRH register *****************/ +#define RAMECC_FDRH_FDATAH_Pos (0U) +#define RAMECC_FDRH_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FDRH_FDATAH_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRH_FDATAH RAMECC_FDRH_FDATAH_Msk /* Failing data high (64-bit memory) */ + +/***************** Bit definition for RAMECC_FECR register ******************/ +#define RAMECC_FECR_FEC_Pos (0U) +#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable in Stop mode */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_Pos (3U) +#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */ +#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */ +#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */ + +#define RCC_CR_HSIDIVF_Pos (5U) +#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */ +#define RCC_CR_CSION_Pos (7U) +#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */ +#define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY_Pos (8U) +#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */ +#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON_Pos (9U) +#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable in Stop mode */ +#define RCC_CR_HSI48ON_Pos (12U) +#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY_Pos (13U) +#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock bypass */ +#define RCC_CR_HSEEXT_Pos (19U) +#define RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk /*!< External High Speed clock type in bypass mode */ +#define RCC_CR_HSECSSON_Pos (20U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< HSE Clock security System enable */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready flag */ +#define RCC_CR_PLL2ON_Pos (26U) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */ +#define RCC_CR_PLL2RDY_Pos (27U) +#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ +#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready flag */ +#define RCC_CR_PLL3ON_Pos (28U) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */ +#define RCC_CR_PLL3RDY_Pos (29U) +#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ +#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready flag */ + +/******************** Bit definition for RCC_HSICFGR register ***************/ +/*!< HSICAL configuration */ +#define RCC_HSICFGR_HSICAL_Pos (0U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */ + +/*!< HSITRIM configuration */ +#define RCC_HSICFGR_HSITRIM_Pos (24U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ +#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CRRCR register *****************/ +/*!< HSI48CAL configuration */ +#define RCC_CRRCR_HSI48CAL_Pos (0U) +#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */ +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */ +#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */ +#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */ +#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */ +#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */ +#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */ +#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */ +#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */ +#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */ +#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */ +#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */ + +/******************** Bit definition for RCC_CSICFGR register ***************/ +/*!< CSICAL configuration */ +#define RCC_CSICFGR_CSICAL_Pos (0U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */ +#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */ +#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */ +#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */ +#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */ +#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */ +#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */ +#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */ +#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */ + +/*!< CSITRIM configuration */ +#define RCC_CSICFGR_CSITRIM_Pos (24U) +#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */ +#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (3U) +#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System clock switch status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ + +#define RCC_CFGR_STOPWUCK_Pos (6U) +#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK_Pos (7U) +#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */ +#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from Stop */ + +/*!< RTCPRE configuration */ +#define RCC_CFGR_RTCPRE_Pos (8U) +#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00003F00 */ +#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< RTCPRE[5:0] bits (HSE division factor for RTC clock) */ +#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_TIMPRE_Pos (15U) +#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< TIMPRE configuration */ + +#define RCC_CFGR_MCO1PRE_Pos (18U) +#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< MCO1 configuration */ +#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_MCO1SEL_Pos (22U) +#define RCC_CFGR_MCO1SEL_Msk (0x7UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR_MCO1SEL RCC_CFGR_MCO1SEL_Msk /*!< MCO1SEL [2:0] bits (MCO1 clock output selection) */ +#define RCC_CFGR_MCO1SEL_0 (0x1UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_MCO1SEL_1 (0x2UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_MCO1SEL_2 (0x4UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01000000 */ + +#define RCC_CFGR_MCO2PRE_Pos (25U) +#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO2 configuration */ +#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ + +#define RCC_CFGR_MCO2SEL_Pos (29U) +#define RCC_CFGR_MCO2SEL_Msk (0x7UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [2:0] bits (MCO2 clock output selection) */ +#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_CDCFGR register ****************/ +/*!< CPRE configuration */ +#define RCC_CDCFGR_CPRE_Pos (0U) +#define RCC_CDCFGR_CPRE_Msk (0xFUL << RCC_CDCFGR_CPRE_Pos) /*!< 0x0000000F */ +#define RCC_CDCFGR_CPRE RCC_CDCFGR_CPRE_Msk /*!< CPRE[3:0] bits */ +#define RCC_CDCFGR_CPRE_0 (0x1UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000001 */ +#define RCC_CDCFGR_CPRE_1 (0x2UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000002 */ +#define RCC_CDCFGR_CPRE_2 (0x4UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000004 */ +#define RCC_CDCFGR_CPRE_3 (0x8UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_BMCFGR register ****************/ +/*!< BMPRE configuration */ +#define RCC_BMCFGR_BMPRE_Pos (0U) +#define RCC_BMCFGR_BMPRE_Msk (0xFUL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x0000000F */ +#define RCC_BMCFGR_BMPRE RCC_BMCFGR_BMPRE_Msk /*!< BMPRE[3:0] bits */ +#define RCC_BMCFGR_BMPRE_0 (0x1UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000001 */ +#define RCC_BMCFGR_BMPRE_1 (0x2UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000002 */ +#define RCC_BMCFGR_BMPRE_2 (0x4UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000004 */ +#define RCC_BMCFGR_BMPRE_3 (0x8UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_APBCFGR register ***************/ +/*!< APB1 prescaler configuration */ +#define RCC_APBCFGR_PPRE1_Pos (0U) +#define RCC_APBCFGR_PPRE1_Msk (0x7UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_APBCFGR_PPRE1 RCC_APBCFGR_PPRE1_Msk /*!< PPRE1[2:0] bits */ +#define RCC_APBCFGR_PPRE1_0 (0x1UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_APBCFGR_PPRE1_1 (0x2UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_APBCFGR_PPRE1_2 (0x4UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000004 */ + +/*!< APB2 prescaler configuration */ +#define RCC_APBCFGR_PPRE2_Pos (4U) +#define RCC_APBCFGR_PPRE2_Msk (0x7UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_APBCFGR_PPRE2 RCC_APBCFGR_PPRE2_Msk /*!< PPRE2[2:0] bits */ +#define RCC_APBCFGR_PPRE2_0 (0x1UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_APBCFGR_PPRE2_1 (0x2UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_APBCFGR_PPRE2_2 (0x4UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000040 */ + +/*!< APB4 prescaler configuration */ +#define RCC_APBCFGR_PPRE4_Pos (8U) +#define RCC_APBCFGR_PPRE4_Msk (0x7UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000700 */ +#define RCC_APBCFGR_PPRE4 RCC_APBCFGR_PPRE4_Msk /*!< PPRE4[2:0] bits */ +#define RCC_APBCFGR_PPRE4_0 (0x1UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000100 */ +#define RCC_APBCFGR_PPRE4_1 (0x2UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000200 */ +#define RCC_APBCFGR_PPRE4_2 (0x4UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000400 */ + +/*!< APB5 prescaler configuration */ +#define RCC_APBCFGR_PPRE5_Pos (12U) +#define RCC_APBCFGR_PPRE5_Msk (0x7UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00007000 */ +#define RCC_APBCFGR_PPRE5 RCC_APBCFGR_PPRE5_Msk /*!< PPRE5[2:0] bits */ +#define RCC_APBCFGR_PPRE5_0 (0x1UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00001000 */ +#define RCC_APBCFGR_PPRE5_1 (0x2UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00002000 */ +#define RCC_APBCFGR_PPRE5_2 (0x4UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_PLLCKSELR register *************/ +#define RCC_PLLCKSELR_PLLSRC_Pos (0U) +#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ +#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk /*!< DIVMx and PLLs clock source selection */ +#define RCC_PLLCKSELR_PLLSRC_0 (0x01UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_PLLSRC_1 (0x02UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000020 */ + +#define RCC_PLLCKSELR_DIVM1_Pos (4U) +#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */ +#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk /*!< DIVM1[5:0] bits */ +#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */ +#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */ +#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */ +#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */ +#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */ + +#define RCC_PLLCKSELR_DIVM2_Pos (12U) +#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */ +#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk /*!< DIVM2[5:0] bits */ +#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */ +#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */ +#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */ +#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */ +#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */ + +#define RCC_PLLCKSELR_DIVM3_Pos (20U) +#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */ +#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk /*!< DIVM3[5:0] bits */ +#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */ +#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */ +#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */ +#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U) +#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */ +#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk /*!< PLL1 fractional latch enable */ +#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U) +#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */ +#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk /*!< PLL1 VCO selection */ +#define RCC_PLLCFGR_PLL1SSCGEN_Pos (2U) +#define RCC_PLLCFGR_PLL1SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SSCGEN_Pos) /*!< 0x00000004 */ +#define RCC_PLLCFGR_PLL1SSCGEN RCC_PLLCFGR_PLL1SSCGEN_Msk /*!< PLL1 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL1RGE_Pos (3U) +#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000018 */ +#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk /*!< PLL1RGE[1:0] bits: PLL1 input frequency range */ +#define RCC_PLLCFGR_PLL1RGE_0 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ + +#define RCC_PLLCFGR_PLL1PEN_Pos (5U) +#define RCC_PLLCFGR_PLL1PEN_Msk (0x1UL << RCC_PLLCFGR_PLL1PEN_Pos) /*!< 0x00000020 */ +#define RCC_PLLCFGR_PLL1PEN RCC_PLLCFGR_PLL1PEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL1QEN_Pos (6U) +#define RCC_PLLCFGR_PLL1QEN_Msk (0x1UL << RCC_PLLCFGR_PLL1QEN_Pos) /*!< 0x00000040 */ +#define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL1REN_Pos (7U) +#define RCC_PLLCFGR_PLL1REN_Msk (0x1UL << RCC_PLLCFGR_PLL1REN_Pos) /*!< 0x00000080 */ +#define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL1SEN_Pos (8U) +#define RCC_PLLCFGR_PLL1SEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SEN_Pos) /*!< 0x00000100 */ +#define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divider output enable */ + +#define RCC_PLLCFGR_PLL2FRACEN_Pos (11U) +#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000800 */ +#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk /*!< PLL2 fractional latch enable */ +#define RCC_PLLCFGR_PLL2VCOSEL_Pos (12U) +#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00001000 */ +#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk /*!< PLL2 VCO selection */ +#define RCC_PLLCFGR_PLL2SSCGEN_Pos (13U) +#define RCC_PLLCFGR_PLL2SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SSCGEN_Pos) /*!< 0x00002000 */ +#define RCC_PLLCFGR_PLL2SSCGEN RCC_PLLCFGR_PLL2SSCGEN_Msk /*!< PLL2 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL2RGE_Pos (14U) +#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x0000C000 */ +#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk /*!< PLL2RGE[1:0] bits: PLL2 input frequency range */ +#define RCC_PLLCFGR_PLL2RGE_0 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00004000 */ +#define RCC_PLLCFGR_PLL2RGE_1 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00008000 */ + +#define RCC_PLLCFGR_PLL2PEN_Pos (16U) +#define RCC_PLLCFGR_PLL2PEN_Msk (0x1UL << RCC_PLLCFGR_PLL2PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLLCFGR_PLL2PEN RCC_PLLCFGR_PLL2PEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL2QEN_Pos (17U) +#define RCC_PLLCFGR_PLL2QEN_Msk (0x1UL << RCC_PLLCFGR_PLL2QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLLCFGR_PLL2QEN RCC_PLLCFGR_PLL2QEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL2REN_Pos (18U) +#define RCC_PLLCFGR_PLL2REN_Msk (0x1UL << RCC_PLLCFGR_PLL2REN_Pos) /*!< 0x00040000 */ +#define RCC_PLLCFGR_PLL2REN RCC_PLLCFGR_PLL2REN_Msk /*!< PLL2 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL2SEN_Pos (19U) +#define RCC_PLLCFGR_PLL2SEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SEN_Pos) /*!< 0x00080000 */ +#define RCC_PLLCFGR_PLL2SEN RCC_PLLCFGR_PLL2SEN_Msk /*!< PLL2 DIVS divider output enable */ +#define RCC_PLLCFGR_PLL2TEN_Pos (20U) +#define RCC_PLLCFGR_PLL2TEN_Msk (0x1UL << RCC_PLLCFGR_PLL2TEN_Pos) /*!< 0x00100000 */ +#define RCC_PLLCFGR_PLL2TEN RCC_PLLCFGR_PLL2TEN_Msk /*!< PLL2 DIVT divider output enable */ + +#define RCC_PLLCFGR_PLL3FRACEN_Pos (22U) +#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00400000 */ +#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk /*!< PLL3 fractional latch enable */ +#define RCC_PLLCFGR_PLL3VCOSEL_Pos (23U) +#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00800000 */ +#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk /*!< PLL3 VCO selection */ +#define RCC_PLLCFGR_PLL3SSCGEN_Pos (24U) +#define RCC_PLLCFGR_PLL3SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SSCGEN_Pos) /*!< 0x01000000 */ +#define RCC_PLLCFGR_PLL3SSCGEN RCC_PLLCFGR_PLL3SSCGEN_Msk /*!< PLL3 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL3RGE_Pos (25U) +#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x06000000 */ +#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk /*!< PLL3RGE[1:0] bits: PLL3 input frequency range */ +#define RCC_PLLCFGR_PLL3RGE_0 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x02000000 */ +#define RCC_PLLCFGR_PLL3RGE_1 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x04000000 */ + +#define RCC_PLLCFGR_PLL3PEN_Pos (27U) +#define RCC_PLLCFGR_PLL3PEN_Msk (0x1UL << RCC_PLLCFGR_PLL3PEN_Pos) /*!< 0x08000000 */ +#define RCC_PLLCFGR_PLL3PEN RCC_PLLCFGR_PLL3PEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL3QEN_Pos (28U) +#define RCC_PLLCFGR_PLL3QEN_Msk (0x1UL << RCC_PLLCFGR_PLL3QEN_Pos) /*!< 0x10000000 */ +#define RCC_PLLCFGR_PLL3QEN RCC_PLLCFGR_PLL3QEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL3REN_Pos (29U) +#define RCC_PLLCFGR_PLL3REN_Msk (0x1UL << RCC_PLLCFGR_PLL3REN_Pos) /*!< 0x20000000 */ +#define RCC_PLLCFGR_PLL3REN RCC_PLLCFGR_PLL3REN_Msk /*!< PLL3 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL3SEN_Pos (30U) +#define RCC_PLLCFGR_PLL3SEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SEN_Pos) /*!< 0x40000000 */ +#define RCC_PLLCFGR_PLL3SEN RCC_PLLCFGR_PLL3SEN_Msk /*!< PLL3 DIVS divider output enable */ + +/******************** Bit definition for RCC_PLL1DIVR1 register *************/ +#define RCC_PLL1DIVR1_DIVN_Pos (0U) +#define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR1_DIVN RCC_PLL1DIVR1_DIVN_Msk /*!< DIVN1[8:0] bits: PLL1 DIVN division factor */ +#define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR1_DIVN_8 (0x100UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL1DIVR1_DIVP_Pos (9U) +#define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: PLL1 DIVP division factor */ +#define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL1DIVR1_DIVQ_Pos (16U) +#define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: PLL1 DIVQ division factor */ +#define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL1DIVR1_DIVR_Pos (24U) +#define RCC_PLL1DIVR1_DIVR_Msk (0x7FUL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR1_DIVR RCC_PLL1DIVR1_DIVR_Msk /*!< DIVR1[6:0] bits: PLL1 DIVR division factor */ +#define RCC_PLL1DIVR1_DIVR_0 (0x001UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR1_DIVR_1 (0x002UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR1_DIVR_2 (0x004UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR1_DIVR_3 (0x008UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR1_DIVR_4 (0x010UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR1_DIVR_5 (0x020UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR1_DIVR_6 (0x040UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register *************/ +#define RCC_PLL1FRACR_FRACN_Pos (3U) +#define RCC_PLL1FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACN RCC_PLL1FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL2DIVR1 register *************/ +#define RCC_PLL2DIVR1_DIVN_Pos (0U) +#define RCC_PLL2DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2DIVR1_DIVN RCC_PLL2DIVR1_DIVN_Msk /*!< DIVN2[8:0] bits: PLL2 DIVN division factor */ +#define RCC_PLL2DIVR1_DIVN_0 (0x001UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR1_DIVN_1 (0x002UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR1_DIVN_2 (0x004UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2DIVR1_DIVN_3 (0x008UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2DIVR1_DIVN_4 (0x010UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2DIVR1_DIVN_5 (0x020UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2DIVR1_DIVN_6 (0x040UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2DIVR1_DIVN_7 (0x080UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2DIVR1_DIVN_8 (0x100UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL2DIVR1_DIVP_Pos (9U) +#define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL2DIVR1_DIVP RCC_PLL2DIVR1_DIVP_Msk /*!< DIVP2[6:0] bits: PLL2 DIVP division factor */ +#define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL2DIVR1_DIVQ_Pos (16U) +#define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2DIVR1_DIVQ RCC_PLL2DIVR1_DIVQ_Msk /*!< DIVQ2[6:0] bits: PLL2 DIVQ division factor */ +#define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL2DIVR1_DIVR_Pos (24U) +#define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL2DIVR1_DIVR RCC_PLL2DIVR1_DIVR_Msk /*!< DIVR2[6:0] bits: PLL2 DIVR division factor */ +#define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2FRACR register *************/ +#define RCC_PLL2FRACR_FRACN_Pos (3U) +#define RCC_PLL2FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACN RCC_PLL2FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL3DIVR1 register *************/ +#define RCC_PLL3DIVR1_DIVN_Pos (0U) +#define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3DIVR1_DIVN RCC_PLL3DIVR1_DIVN_Msk /*!< DIVN3[8:0] bits: PLL3 DIVN division factor */ +#define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3DIVR1_DIVN_8 (0x100UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL3DIVR1_DIVP_Pos (9U) +#define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL3DIVR1_DIVP RCC_PLL3DIVR1_DIVP_Msk /*!< DIVP3[6:0] bits: PLL3 DIVP division factor */ +#define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL3DIVR1_DIVQ_Pos (16U) +#define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3DIVR1_DIVQ RCC_PLL3DIVR1_DIVQ_Msk /*!< DIVQ3[6:0] bits: PLL3 DIVQ division factor */ +#define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL3DIVR1_DIVR_Pos (24U) +#define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL3DIVR1_DIVR RCC_PLL3DIVR1_DIVR_Msk /*!< DIVR3[6:0] bits: PLL3 DIVR division factor */ +#define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3FRACR register *************/ +#define RCC_PLL3FRACR_FRACN_Pos (3U) +#define RCC_PLL3FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACN RCC_PLL3FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_CCIPR1 register **************/ +#define RCC_CCIPR1_FMCSEL_Pos (0U) +#define RCC_CCIPR1_FMCSEL_Msk (0x3UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_FMCSEL RCC_CCIPR1_FMCSEL_Msk +#define RCC_CCIPR1_FMCSEL_0 (0x1UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_FMCSEL_1 (0x2UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000002 */ + +#define RCC_CCIPR1_SDMMC12SEL_Pos (2U) +#define RCC_CCIPR1_SDMMC12SEL_Msk (0x1UL << RCC_CCIPR1_SDMMC12SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_SDMMC12SEL RCC_CCIPR1_SDMMC12SEL_Msk + +#define RCC_CCIPR1_XSPI1SEL_Pos (4U) +#define RCC_CCIPR1_XSPI1SEL_Msk (0x3UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_XSPI1SEL RCC_CCIPR1_XSPI1SEL_Msk +#define RCC_CCIPR1_XSPI1SEL_0 (0x1UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_XSPI1SEL_1 (0x2UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000020 */ + +#define RCC_CCIPR1_XSPI2SEL_Pos (6U) +#define RCC_CCIPR1_XSPI2SEL_Msk (0x3UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_XSPI2SEL RCC_CCIPR1_XSPI2SEL_Msk +#define RCC_CCIPR1_XSPI2SEL_0 (0x1UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_XSPI2SEL_1 (0x2UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000080 */ + +#define RCC_CCIPR1_USBREFCKSEL_Pos (8U) +#define RCC_CCIPR1_USBREFCKSEL_Msk (0xFUL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000F00 */ +#define RCC_CCIPR1_USBREFCKSEL RCC_CCIPR1_USBREFCKSEL_Msk +#define RCC_CCIPR1_USBREFCKSEL_0 (0x1UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_USBREFCKSEL_1 (0x2UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_USBREFCKSEL_2 (0x4UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_USBREFCKSEL_3 (0x8UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000800 */ + +#define RCC_CCIPR1_USBPHYCSEL_Pos (12U) +#define RCC_CCIPR1_USBPHYCSEL_Msk (0x3UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_USBPHYCSEL RCC_CCIPR1_USBPHYCSEL_Msk +#define RCC_CCIPR1_USBPHYCSEL_0 (0x1UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_USBPHYCSEL_1 (0x2UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR1_OTGFSSEL_Pos (14U) +#define RCC_CCIPR1_OTGFSSEL_Msk (0x3UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_OTGFSSEL RCC_CCIPR1_OTGFSSEL_Msk +#define RCC_CCIPR1_OTGFSSEL_0 (0x1UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_OTGFSSEL_1 (0x2UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00008000 */ + +#define RCC_CCIPR1_ETH1REFCKSEL_Pos (16U) +#define RCC_CCIPR1_ETH1REFCKSEL_Msk (0x3UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_ETH1REFCKSEL RCC_CCIPR1_ETH1REFCKSEL_Msk +#define RCC_CCIPR1_ETH1REFCKSEL_0 (0x1UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_ETH1REFCKSEL_1 (0x2UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00020000 */ + +#define RCC_CCIPR1_ETH1PHYCKSEL_Pos (18U) +#define RCC_CCIPR1_ETH1PHYCKSEL_Msk (0x1UL << RCC_CCIPR1_ETH1PHYCKSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_ETH1PHYCKSEL RCC_CCIPR1_ETH1PHYCKSEL_Msk + +#define RCC_CCIPR1_ADF1SEL_Pos (20U) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00400000 */ + +#define RCC_CCIPR1_ADCSEL_Pos (24U) +#define RCC_CCIPR1_ADCSEL_Msk (0x3UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR1_ADCSEL RCC_CCIPR1_ADCSEL_Msk +#define RCC_CCIPR1_ADCSEL_0 (0x1UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR1_ADCSEL_1 (0x2UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR1_PSSISEL_Pos (27U) +#define RCC_CCIPR1_PSSISEL_Msk (0x1UL << RCC_CCIPR1_PSSISEL_Pos) /*!< 0x08000000 */ +#define RCC_CCIPR1_PSSISEL RCC_CCIPR1_PSSISEL_Msk + +#define RCC_CCIPR1_CKPERSEL_Pos (28U) +#define RCC_CCIPR1_CKPERSEL_Msk (0x3UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x30000000 */ +#define RCC_CCIPR1_CKPERSEL RCC_CCIPR1_CKPERSEL_Msk +#define RCC_CCIPR1_CKPERSEL_0 (0x1UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR1_CKPERSEL_1 (0x2UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CCIPR2 register *************/ +#define RCC_CCIPR2_UART234578SEL_Pos (0U) +#define RCC_CCIPR2_UART234578SEL_Msk (0x7UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR2_UART234578SEL RCC_CCIPR2_UART234578SEL_Msk +#define RCC_CCIPR2_UART234578SEL_0 (0x1UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_UART234578SEL_1 (0x2UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_UART234578SEL_2 (0x4UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR2_SPI23SEL_Pos (4U) +#define RCC_CCIPR2_SPI23SEL_Msk (0x7UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR2_SPI23SEL RCC_CCIPR2_SPI23SEL_Msk +#define RCC_CCIPR2_SPI23SEL_0 (0x1UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_SPI23SEL_1 (0x2UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SPI23SEL_2 (0x4UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR2_I2C23SEL_Pos (8U) +#define RCC_CCIPR2_I2C23SEL_Msk (0x3UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR2_I2C23SEL RCC_CCIPR2_I2C23SEL_Msk +#define RCC_CCIPR2_I2C23SEL_0 (0x1UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_I2C23SEL_1 (0x2UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000200 */ + +#define RCC_CCIPR2_I2C1_I3C1SEL_Pos (12U) +#define RCC_CCIPR2_I2C1_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL RCC_CCIPR2_I2C1_I3C1SEL_Msk +#define RCC_CCIPR2_I2C1_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR2_FDCANSEL_Pos (22U) +#define RCC_CCIPR2_FDCANSEL_Msk (0x3UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR2_FDCANSEL RCC_CCIPR2_FDCANSEL_Msk +#define RCC_CCIPR2_FDCANSEL_0 (0x1UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR2_FDCANSEL_1 (0x2UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00800000 */ + +#define RCC_CCIPR2_SPDIFRXSEL_Pos (24U) +#define RCC_CCIPR2_SPDIFRXSEL_Msk (0x3UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_SPDIFRXSEL RCC_CCIPR2_SPDIFRXSEL_Msk +#define RCC_CCIPR2_SPDIFRXSEL_0 (0x1UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_SPDIFRXSEL_1 (0x2UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR2_CECSEL_Pos (28U) +#define RCC_CCIPR2_CECSEL_Msk (0x3UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CECSEL RCC_CCIPR2_CECSEL_Msk +#define RCC_CCIPR2_CECSEL_0 (0x1UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CECSEL_1 (0x2UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_CCIPR3 register *************/ +#define RCC_CCIPR3_USART1SEL_Pos (0U) +#define RCC_CCIPR3_USART1SEL_Msk (0x7UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR3_USART1SEL RCC_CCIPR3_USART1SEL_Msk +#define RCC_CCIPR3_USART1SEL_0 (0x1UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_USART1SEL_1 (0x2UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_USART1SEL_2 (0x4UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR3_SPI45SEL_Pos (4U) +#define RCC_CCIPR3_SPI45SEL_Msk (0x7UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR3_SPI45SEL RCC_CCIPR3_SPI45SEL_Msk +#define RCC_CCIPR3_SPI45SEL_0 (0x1UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_SPI45SEL_1 (0x2UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_SPI45SEL_2 (0x4UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR3_SPI1SEL_Pos (8U) +#define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR3_SPI1SEL RCC_CCIPR3_SPI1SEL_Msk +#define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR3_SAI1SEL_Pos (16U) +#define RCC_CCIPR3_SAI1SEL_Msk (0x7UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR3_SAI1SEL RCC_CCIPR3_SAI1SEL_Msk +#define RCC_CCIPR3_SAI1SEL_0 (0x1UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR3_SAI1SEL_1 (0x2UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR3_SAI1SEL_2 (0x4UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR3_SAI2SEL_Pos (20U) +#define RCC_CCIPR3_SAI2SEL_Msk (0x7UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR3_SAI2SEL RCC_CCIPR3_SAI2SEL_Msk +#define RCC_CCIPR3_SAI2SEL_0 (0x1UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR3_SAI2SEL_1 (0x2UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR3_SAI2SEL_2 (0x4UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for RCC_CCIPR4 register ************/ +#define RCC_CCIPR4_LPUART1SEL_Pos (0U) +#define RCC_CCIPR4_LPUART1SEL_Msk (0x7UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_LPUART1SEL RCC_CCIPR4_LPUART1SEL_Msk +#define RCC_CCIPR4_LPUART1SEL_0 (0x1UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_LPUART1SEL_1 (0x2UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_LPUART1SEL_2 (0x4UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR4_SPI6SEL_Pos (4U) +#define RCC_CCIPR4_SPI6SEL_Msk (0x7UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_SPI6SEL RCC_CCIPR4_SPI6SEL_Msk +#define RCC_CCIPR4_SPI6SEL_0 (0x1UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_SPI6SEL_1 (0x2UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_SPI6SEL_2 (0x4UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR4_LPTIM23SEL_Pos (8U) +#define RCC_CCIPR4_LPTIM23SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_LPTIM23SEL RCC_CCIPR4_LPTIM23SEL_Msk +#define RCC_CCIPR4_LPTIM23SEL_0 (0x1UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_LPTIM23SEL_1 (0x2UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_LPTIM23SEL_2 (0x4UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR4_LPTIM45SEL_Pos (12U) +#define RCC_CCIPR4_LPTIM45SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_LPTIM45SEL RCC_CCIPR4_LPTIM45SEL_Msk +#define RCC_CCIPR4_LPTIM45SEL_0 (0x1UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_LPTIM45SEL_1 (0x2UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_LPTIM45SEL_2 (0x4UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_CSIRDYIE_Pos (4U) +#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk +#define RCC_CIER_HSI48RDYIE_Pos (5U) +#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_PLL2RDYIE_Pos (7U) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk +#define RCC_CIER_PLL3RDYIE_Pos (8U) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk +#define RCC_CIER_LSECSSIE_Pos (9U) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk + +/******************** Bit definition for RCC_CIFR register ******************/ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_CSIRDYF_Pos (4U) +#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk +#define RCC_CIFR_HSI48RDYF_Pos (5U) +#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_PLL2RDYF_Pos (7U) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk +#define RCC_CIFR_PLL3RDYF_Pos (8U) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk +#define RCC_CIFR_LSECSSF_Pos (9U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ******************/ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_CSIRDYC_Pos (4U) +#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk +#define RCC_CICR_HSI48RDYC_Pos (5U) +#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_PLL2RDYC_Pos (7U) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk +#define RCC_CICR_PLL3RDYC_Pos (8U) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk +#define RCC_CICR_LSECSSC_Pos (9U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk +#define RCC_BDCR_LSEDRV_Pos (3U) +#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk +#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ + +#define RCC_BDCR_LSECSSON_Pos (5U) +#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk +#define RCC_BDCR_LSECSSD_Pos (6U) +#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk +#define RCC_BDCR_LSEEXT_Pos (7U) +#define RCC_BDCR_LSEEXT_Msk (0x1UL << RCC_BDCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_BDCR_LSEEXT RCC_BDCR_LSEEXT_Msk +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSRA_Pos (12U) +#define RCC_BDCR_LSECSSRA_Msk (0x1UL << RCC_BDCR_LSECSSRA_Pos) /*!< 0x00001000 */ +#define RCC_BDCR_LSECSSRA RCC_BDCR_LSECSSRA_Msk + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk +#define RCC_BDCR_VSWRST_Pos (16U) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_ADC12RST_Pos (5U) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk +#define RCC_AHB1RSTR_ETH1RST_Pos (15U) +#define RCC_AHB1RSTR_ETH1RST_Msk (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos) /*!< 0x00008000 */ +#define RCC_AHB1RSTR_ETH1RST RCC_AHB1RSTR_ETH1RST_Msk +#define RCC_AHB1RSTR_OTGHSRST_Pos (25U) +#define RCC_AHB1RSTR_OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHSRST_Pos) /*!< 0x02000000 */ +#define RCC_AHB1RSTR_OTGHSRST RCC_AHB1RSTR_OTGHSRST_Msk +#define RCC_AHB1RSTR_USBPHYCRST_Pos (26U) +#define RCC_AHB1RSTR_USBPHYCRST_Msk (0x1UL << RCC_AHB1RSTR_USBPHYCRST_Pos) /*!< 0x04000000 */ +#define RCC_AHB1RSTR_USBPHYCRST RCC_AHB1RSTR_USBPHYCRST_Msk +#define RCC_AHB1RSTR_OTGFSRST_Pos (27U) +#define RCC_AHB1RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGFSRST_Pos) /*!< 0x08000000 */ +#define RCC_AHB1RSTR_OTGFSRST RCC_AHB1RSTR_OTGFSRST_Msk +#define RCC_AHB1RSTR_ADF1RST_Pos (31U) +#define RCC_AHB1RSTR_ADF1RST_Msk (0x1UL << RCC_AHB1RSTR_ADF1RST_Pos) /*!< 0x80000000 */ +#define RCC_AHB1RSTR_ADF1RST RCC_AHB1RSTR_ADF1RST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_PSSIRST_Pos (1U) +#define RCC_AHB2RSTR_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_PSSIRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_PSSIRST RCC_AHB2RSTR_PSSIRST_Msk +#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U) +#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */ +#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk +#define RCC_AHB2RSTR_CORDICRST_Pos (14U) +#define RCC_AHB2RSTR_CORDICRST_Msk (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB2RSTR_CORDICRST RCC_AHB2RSTR_CORDICRST_Msk + +/******************** Bit definition for RCC_AHB3RSTR register **************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0U) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk +#define RCC_AHB3RSTR_HASHRST_Pos (1U) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk +#define RCC_AHB3RSTR_CRYPRST_Pos (2U) +#define RCC_AHB3RSTR_CRYPRST_Msk (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTR_CRYPRST RCC_AHB3RSTR_CRYPRST_Msk +#define RCC_AHB3RSTR_SAESRST_Pos (4U) +#define RCC_AHB3RSTR_SAESRST_Msk (0x1UL << RCC_AHB3RSTR_SAESRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTR_SAESRST RCC_AHB3RSTR_SAESRST_Msk +#define RCC_AHB3RSTR_PKARST_Pos (6U) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk +#define RCC_AHB4RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk +#define RCC_AHB4RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk +#define RCC_AHB4RSTR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk +#define RCC_AHB4RSTR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk +#define RCC_AHB4RSTR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk +#define RCC_AHB4RSTR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk +#define RCC_AHB4RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk +#define RCC_AHB4RSTR_GPIOMRST_Pos (12U) +#define RCC_AHB4RSTR_GPIOMRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOMRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB4RSTR_GPIOMRST RCC_AHB4RSTR_GPIOMRST_Msk +#define RCC_AHB4RSTR_GPIONRST_Pos (13U) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk +#define RCC_AHB4RSTR_GPIOORST_Pos (14U) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk +#define RCC_AHB4RSTR_GPIOPRST_Pos (15U) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk +#define RCC_AHB4RSTR_CRCRST_Pos (19U) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0U) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk +#define RCC_AHB5RSTR_DMA2DRST_Pos (1U) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk +#define RCC_AHB5RSTR_JPEGRST_Pos (3U) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk +#define RCC_AHB5RSTR_FMCRST_Pos (4U) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk +#define RCC_AHB5RSTR_XSPI1RST_Pos (5U) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8U) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk +#define RCC_AHB5RSTR_XSPI2RST_Pos (12U) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk +#define RCC_AHB5RSTR_XSPIMRST_Pos (14U) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk +#define RCC_AHB5RSTR_GFXMMURST_Pos (19U) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register *************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_TIM4RST_Pos (2U) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk +#define RCC_APB1RSTR1_TIM5RST_Pos (3U) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk +#define RCC_APB1RSTR1_TIM6RST_Pos (4U) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk +#define RCC_APB1RSTR1_TIM7RST_Pos (5U) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk +#define RCC_APB1RSTR1_TIM12RST_Pos (6U) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk +#define RCC_APB1RSTR1_TIM13RST_Pos (7U) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk +#define RCC_APB1RSTR1_TIM14RST_Pos (8U) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk +#define RCC_APB1RSTR1_SPI2RST_Pos (14U) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk +#define RCC_APB1RSTR1_SPI3RST_Pos (15U) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk +#define RCC_APB1RSTR1_SPDIFRXRST_Pos (16U) +#define RCC_APB1RSTR1_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRXRST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRXRST RCC_APB1RSTR1_SPDIFRXRST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_USART3RST_Pos (18U) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk +#define RCC_APB1RSTR1_UART4RST_Pos (19U) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk +#define RCC_APB1RSTR1_UART5RST_Pos (20U) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk +#define RCC_APB1RSTR1_I2C1_I3C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1_I3C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1_I3C1RST RCC_APB1RSTR1_I2C1_I3C1RST_Msk +#define RCC_APB1RSTR1_I2C2RST_Pos (22U) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk +#define RCC_APB1RSTR1_I2C3RST_Pos (23U) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk +#define RCC_APB1RSTR1_CECRST_Pos (27U) +#define RCC_APB1RSTR1_CECRST_Msk (0x1UL << RCC_APB1RSTR1_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR1_CECRST RCC_APB1RSTR1_CECRST_Msk +#define RCC_APB1RSTR1_UART7RST_Pos (30U) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk +#define RCC_APB1RSTR1_UART8RST_Pos (31U) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register *************/ +#define RCC_APB1RSTR2_CRSRST_Pos (1U) +#define RCC_APB1RSTR2_CRSRST_Msk (0x1UL << RCC_APB1RSTR2_CRSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR2_CRSRST RCC_APB1RSTR2_CRSRST_Msk +#define RCC_APB1RSTR2_MDIOSRST_Pos (5U) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk +#define RCC_APB1RSTR2_FDCANRST_Pos (8U) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk +#define RCC_APB1RSTR2_UCPD1RST_Pos (27U) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (4U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_SPI4RST_Pos (13U) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_TIM9RST_Pos (19U) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk +#define RCC_APB2RSTR_SPI5RST_Pos (20U) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (22U) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk +#define RCC_APB2RSTR_SAI2RST_Pos (23U) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk + +/******************** Bit definition for RCC_APB4RSTR register **************/ +#define RCC_APB4RSTR_SBSRST_Pos (1U) +#define RCC_APB4RSTR_SBSRST_Msk (0x1UL << RCC_APB4RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB4RSTR_SBSRST RCC_APB4RSTR_SBSRST_Msk +#define RCC_APB4RSTR_LPUART1RST_Pos (3U) +#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk +#define RCC_APB4RSTR_SPI6RST_Pos (5U) +#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk +#define RCC_APB4RSTR_LPTIM2RST_Pos (9U) +#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk +#define RCC_APB4RSTR_LPTIM3RST_Pos (10U) +#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk +#define RCC_APB4RSTR_LPTIM4RST_Pos (11U) +#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk +#define RCC_APB4RSTR_LPTIM5RST_Pos (12U) +#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk +#define RCC_APB4RSTR_VREFRST_Pos (15U) +#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk +#define RCC_APB4RSTR_DTSRST_Pos (26U) +#define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */ +#define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk + +/******************** Bit definition for RCC_APB5RSTR register **************/ +#define RCC_APB5RSTR_DCMIPPRST_Pos (2U) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk +#define RCC_APB5RSTR_GFXTIMRST_Pos (4U) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk + +/******************** Bit definition for RCC_CKGDISR register ***************/ +#define RCC_CKGDISR_AXICKG_Pos (0U) +#define RCC_CKGDISR_AXICKG_Msk (0x1UL << RCC_CKGDISR_AXICKG_Pos) /*!< 0x00000001 */ +#define RCC_CKGDISR_AXICKG RCC_CKGDISR_AXICKG_Msk +#define RCC_CKGDISR_AHBMCKG_Pos (1U) +#define RCC_CKGDISR_AHBMCKG_Msk (0x1UL << RCC_CKGDISR_AHBMCKG_Pos) /*!< 0x00000002 */ +#define RCC_CKGDISR_AHBMCKG RCC_CKGDISR_AHBMCKG_Msk +#define RCC_CKGDISR_SDMMC1CKG_Pos (2U) +#define RCC_CKGDISR_SDMMC1CKG_Msk (0x1UL << RCC_CKGDISR_SDMMC1CKG_Pos) /*!< 0x00000004 */ +#define RCC_CKGDISR_SDMMC1CKG RCC_CKGDISR_SDMMC1CKG_Msk +#define RCC_CKGDISR_HPDMA1CKG_Pos (3U) +#define RCC_CKGDISR_HPDMA1CKG_Msk (0x1UL << RCC_CKGDISR_HPDMA1CKG_Pos) /*!< 0x00000008 */ +#define RCC_CKGDISR_HPDMA1CKG RCC_CKGDISR_HPDMA1CKG_Msk +#define RCC_CKGDISR_CPUCKG_Pos (4U) +#define RCC_CKGDISR_CPUCKG_Msk (0x1UL << RCC_CKGDISR_CPUCKG_Pos) /*!< 0x00000010 */ +#define RCC_CKGDISR_CPUCKG RCC_CKGDISR_CPUCKG_Msk +#define RCC_CKGDISR_DCMIPPCKG_Pos (8U) +#define RCC_CKGDISR_DCMIPPCKG_Msk (0x1UL << RCC_CKGDISR_DCMIPPCKG_Pos) /*!< 0x00000100 */ +#define RCC_CKGDISR_DCMIPPCKG RCC_CKGDISR_DCMIPPCKG_Msk +#define RCC_CKGDISR_DMA2DCKG_Pos (9U) +#define RCC_CKGDISR_DMA2DCKG_Msk (0x1UL << RCC_CKGDISR_DMA2DCKG_Pos) /*!< 0x00000200 */ +#define RCC_CKGDISR_DMA2DCKG RCC_CKGDISR_DMA2DCKG_Msk +#define RCC_CKGDISR_GFXMMUSCKG_Pos (10U) +#define RCC_CKGDISR_GFXMMUSCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUSCKG_Pos) /*!< 0x00000400 */ +#define RCC_CKGDISR_GFXMMUSCKG RCC_CKGDISR_GFXMMUSCKG_Msk +#define RCC_CKGDISR_GFXMMUMCKG_Pos (12U) +#define RCC_CKGDISR_GFXMMUMCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUMCKG_Pos) /*!< 0x00001000 */ +#define RCC_CKGDISR_GFXMMUMCKG RCC_CKGDISR_GFXMMUMCKG_Msk +#define RCC_CKGDISR_AHBSCKG_Pos (13U) +#define RCC_CKGDISR_AHBSCKG_Msk (0x1UL << RCC_CKGDISR_AHBSCKG_Pos) /*!< 0x00002000 */ +#define RCC_CKGDISR_AHBSCKG RCC_CKGDISR_AHBSCKG_Msk +#define RCC_CKGDISR_FMCCKG_Pos (14U) +#define RCC_CKGDISR_FMCCKG_Msk (0x1UL << RCC_CKGDISR_FMCCKG_Pos) /*!< 0x00004000 */ +#define RCC_CKGDISR_FMCCKG RCC_CKGDISR_FMCCKG_Msk +#define RCC_CKGDISR_XSPI1CKG_Pos (15U) +#define RCC_CKGDISR_XSPI1CKG_Msk (0x1UL << RCC_CKGDISR_XSPI1CKG_Pos) /*!< 0x00008000 */ +#define RCC_CKGDISR_XSPI1CKG RCC_CKGDISR_XSPI1CKG_Msk +#define RCC_CKGDISR_XSPI2CKG_Pos (16U) +#define RCC_CKGDISR_XSPI2CKG_Msk (0x1UL << RCC_CKGDISR_XSPI2CKG_Pos) /*!< 0x00010000 */ +#define RCC_CKGDISR_XSPI2CKG RCC_CKGDISR_XSPI2CKG_Msk +#define RCC_CKGDISR_AXISRAM4CKG_Pos (17U) +#define RCC_CKGDISR_AXISRAM4CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM4CKG_Pos) /*!< 0x00020000 */ +#define RCC_CKGDISR_AXISRAM4CKG RCC_CKGDISR_AXISRAM4CKG_Msk +#define RCC_CKGDISR_AXISRAM3CKG_Pos (18U) +#define RCC_CKGDISR_AXISRAM3CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM3CKG_Pos) /*!< 0x00040000 */ +#define RCC_CKGDISR_AXISRAM3CKG RCC_CKGDISR_AXISRAM3CKG_Msk +#define RCC_CKGDISR_AXISRAM2CKG_Pos (19U) +#define RCC_CKGDISR_AXISRAM2CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM2CKG_Pos) /*!< 0x00080000 */ +#define RCC_CKGDISR_AXISRAM2CKG RCC_CKGDISR_AXISRAM2CKG_Msk +#define RCC_CKGDISR_AXISRAM1CKG_Pos (20U) +#define RCC_CKGDISR_AXISRAM1CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM1CKG_Pos) /*!< 0x00100000 */ +#define RCC_CKGDISR_AXISRAM1CKG RCC_CKGDISR_AXISRAM1CKG_Msk +#define RCC_CKGDISR_FLASHCKG_Pos (21U) +#define RCC_CKGDISR_FLASHCKG_Msk (0x1UL << RCC_CKGDISR_FLASHCKG_Pos) /*!< 0x00200000 */ +#define RCC_CKGDISR_FLASHCKG RCC_CKGDISR_FLASHCKG_Msk +#define RCC_CKGDISR_EXTICKG_Pos (30U) +#define RCC_CKGDISR_EXTICKG_Msk (0x1UL << RCC_CKGDISR_EXTICKG_Pos) /*!< 0x40000000 */ +#define RCC_CKGDISR_EXTICKG RCC_CKGDISR_EXTICKG_Msk +#define RCC_CKGDISR_JTAGCKG_Pos (31U) +#define RCC_CKGDISR_JTAGCKG_Msk (0x1UL << RCC_CKGDISR_JTAGCKG_Pos) /*!< 0x80000000 */ +#define RCC_CKGDISR_JTAGCKG RCC_CKGDISR_JTAGCKG_Msk + +/******************** Bit definition for RCC_PLL1DIVR2 register *************/ +#define RCC_PLL1DIVR2_DIVS_Pos (0U) +#define RCC_PLL1DIVR2_DIVS_Msk (0x7UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL1DIVR2_DIVS RCC_PLL1DIVR2_DIVS_Msk /*!< DIVS1[2:0] bits: PLL1 DIVS division factor */ +#define RCC_PLL1DIVR2_DIVS_0 (0x1UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR2_DIVS_1 (0x2UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR2_DIVS_2 (0x4UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL2DIVR2 register *************/ +#define RCC_PLL2DIVR2_DIVS_Pos (0U) +#define RCC_PLL2DIVR2_DIVS_Msk (0x7UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL2DIVR2_DIVS RCC_PLL2DIVR2_DIVS_Msk /*!< DIVS2[2:0] bits: PLL2 DIVS division factor */ +#define RCC_PLL2DIVR2_DIVS_0 (0x1UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR2_DIVS_1 (0x2UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR2_DIVS_2 (0x4UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +#define RCC_PLL2DIVR2_DIVT_Pos (8U) +#define RCC_PLL2DIVR2_DIVT_Msk (0x7UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000700 */ +#define RCC_PLL2DIVR2_DIVT RCC_PLL2DIVR2_DIVT_Msk /*!< DIVT2[2:0] bits: PLL2 DIVT division factor */ +#define RCC_PLL2DIVR2_DIVT_0 (0x1UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000100 */ +#define RCC_PLL2DIVR2_DIVT_1 (0x2UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR2_DIVT_2 (0x4UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_PLL3DIVR2 register *************/ +#define RCC_PLL3DIVR2_DIVS_Pos (0U) +#define RCC_PLL3DIVR2_DIVS_Msk (0x7UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL3DIVR2_DIVS RCC_PLL3DIVR2_DIVS_Msk /*!< DIVS3[2:0] bits: PLL3 DIVS division factor */ +#define RCC_PLL3DIVR2_DIVS_0 (0x1UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR2_DIVS_1 (0x2UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR2_DIVS_2 (0x4UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL1SSCGR register *************/ +#define RCC_PLL1SSCGR_MODPER_Pos (0U) +#define RCC_PLL1SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1SSCGR_MODPER RCC_PLL1SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL1SSCGR_MODPER_0 (0x0001UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1SSCGR_MODPER_1 (0x0002UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1SSCGR_MODPER_2 (0x0004UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1SSCGR_MODPER_3 (0x0008UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1SSCGR_MODPER_4 (0x0010UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1SSCGR_MODPER_5 (0x0020UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1SSCGR_MODPER_6 (0x0040UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1SSCGR_MODPER_7 (0x0080UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1SSCGR_MODPER_8 (0x0100UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1SSCGR_MODPER_9 (0x0200UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1SSCGR_MODPER_10 (0x0400UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1SSCGR_MODPER_11 (0x0800UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1SSCGR_MODPER_12 (0x1000UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL1SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1SSCGR_TPDFNDIS RCC_PLL1SSCGR_TPDFNDIS_Msk +#define RCC_PLL1SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL1SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1SSCGR_RPDFNDIS RCC_PLL1SSCGR_RPDFNDIS_Msk +#define RCC_PLL1SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL1SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL1SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL1SSCGR_SPREADSEL RCC_PLL1SSCGR_SPREADSEL_Msk +#define RCC_PLL1SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL1SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1SSCGR_INCSTEP RCC_PLL1SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL1SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2SSCGR register *************/ +#define RCC_PLL2SSCGR_MODPER_Pos (0U) +#define RCC_PLL2SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2SSCGR_MODPER RCC_PLL2SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL2SSCGR_MODPER_0 (0x0001UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2SSCGR_MODPER_1 (0x0002UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2SSCGR_MODPER_2 (0x0004UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2SSCGR_MODPER_3 (0x0008UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2SSCGR_MODPER_4 (0x0010UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2SSCGR_MODPER_5 (0x0020UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2SSCGR_MODPER_6 (0x0040UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2SSCGR_MODPER_7 (0x0080UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2SSCGR_MODPER_8 (0x0100UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2SSCGR_MODPER_9 (0x0200UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2SSCGR_MODPER_10 (0x0400UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2SSCGR_MODPER_11 (0x0800UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2SSCGR_MODPER_12 (0x1000UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL2SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2SSCGR_TPDFNDIS RCC_PLL2SSCGR_TPDFNDIS_Msk +#define RCC_PLL2SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL2SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2SSCGR_RPDFNDIS RCC_PLL2SSCGR_RPDFNDIS_Msk +#define RCC_PLL2SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL2SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL2SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL2SSCGR_SPREADSEL RCC_PLL2SSCGR_SPREADSEL_Msk +#define RCC_PLL2SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL2SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2SSCGR_INCSTEP RCC_PLL2SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL2SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3SSCGR register *************/ +#define RCC_PLL3SSCGR_MODPER_Pos (0U) +#define RCC_PLL3SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL3SSCGR_MODPER RCC_PLL3SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL3SSCGR_MODPER_0 (0x0001UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL3SSCGR_MODPER_1 (0x0002UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL3SSCGR_MODPER_2 (0x0004UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL3SSCGR_MODPER_3 (0x0008UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL3SSCGR_MODPER_4 (0x0010UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL3SSCGR_MODPER_5 (0x0020UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL3SSCGR_MODPER_6 (0x0040UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL3SSCGR_MODPER_7 (0x0080UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL3SSCGR_MODPER_8 (0x0100UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL3SSCGR_MODPER_9 (0x0200UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL3SSCGR_MODPER_10 (0x0400UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL3SSCGR_MODPER_11 (0x0800UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL3SSCGR_MODPER_12 (0x1000UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL3SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL3SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL3SSCGR_TPDFNDIS RCC_PLL3SSCGR_TPDFNDIS_Msk +#define RCC_PLL3SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL3SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL3SSCGR_RPDFNDIS RCC_PLL3SSCGR_RPDFNDIS_Msk +#define RCC_PLL3SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL3SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL3SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL3SSCGR_SPREADSEL RCC_PLL3SSCGR_SPREADSEL_Msk +#define RCC_PLL3SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL3SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3SSCGR_INCSTEP RCC_PLL3SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL3SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL3SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL3SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL3SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL3SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL3SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL3SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL3SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL3SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL3SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL3SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL3SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL3SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL3SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CKPROTR register ***************/ +#define RCC_CKPROTR_XSPICKP_Pos (0U) +#define RCC_CKPROTR_XSPICKP_Msk (0x1UL << RCC_CKPROTR_XSPICKP_Pos) /*!< 0x00000001 */ +#define RCC_CKPROTR_XSPICKP RCC_CKPROTR_XSPICKP_Msk +#define RCC_CKPROTR_FMCCKP_Pos (1U) +#define RCC_CKPROTR_FMCCKP_Msk (0x1UL << RCC_CKPROTR_FMCCKP_Pos) /*!< 0x00000002 */ +#define RCC_CKPROTR_FMCCKP RCC_CKPROTR_FMCCKP_Msk +#define RCC_CKPROTR_XSPI1SWP_Pos (4U) +#define RCC_CKPROTR_XSPI1SWP_Msk (0x7UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000070 */ +#define RCC_CKPROTR_XSPI1SWP RCC_CKPROTR_XSPI1SWP_Msk +#define RCC_CKPROTR_XSPI1SWP_0 (0x1UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000010 */ +#define RCC_CKPROTR_XSPI1SWP_1 (0x2UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000020 */ +#define RCC_CKPROTR_XSPI1SWP_2 (0x4UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000040 */ +#define RCC_CKPROTR_XSPI2SWP_Pos (8U) +#define RCC_CKPROTR_XSPI2SWP_Msk (0x7UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000700 */ +#define RCC_CKPROTR_XSPI2SWP RCC_CKPROTR_XSPI2SWP_Msk +#define RCC_CKPROTR_XSPI2SWP_0 (0x1UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000100 */ +#define RCC_CKPROTR_XSPI2SWP_1 (0x2UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000200 */ +#define RCC_CKPROTR_XSPI2SWP_2 (0x4UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000400 */ +#define RCC_CKPROTR_FMCSWP_Pos (12U) +#define RCC_CKPROTR_FMCSWP_Msk (0x7UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00007000 */ +#define RCC_CKPROTR_FMCSWP RCC_CKPROTR_FMCSWP_Msk +#define RCC_CKPROTR_FMCSWP_0 (0x1UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00001000 */ +#define RCC_CKPROTR_FMCSWP_1 (0x2UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00002000 */ +#define RCC_CKPROTR_FMCSWP_2 (0x4UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_RSR register *******************/ +#define RCC_RSR_RMVF_Pos (16U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk +#define RCC_RSR_OBLRSTF_Pos (17U) +#define RCC_RSR_OBLRSTF_Msk (0x1UL << RCC_RSR_OBLRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_OBLRSTF RCC_RSR_OBLRSTF_Msk +#define RCC_RSR_BORRSTF_Pos (21U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk +#define RCC_RSR_PINRSTF_Pos (22U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk +#define RCC_RSR_PORRSTF_Pos (23U) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk +#define RCC_RSR_SFTRSTF_Pos (24U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk +#define RCC_RSR_IWDGRSTF_Pos (26U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk +#define RCC_RSR_WWDGRSTF_Pos (28U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk +#define RCC_RSR_LPWRRSTF_Pos (30U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_AHB1ENR register ***************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_ADC12EN_Pos (5U) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk +#define RCC_AHB1ENR_ETH1MACEN_Pos (15U) +#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk +#define RCC_AHB1ENR_ETH1TXEN_Pos (16U) +#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk +#define RCC_AHB1ENR_ETH1RXEN_Pos (17U) +#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk +#define RCC_AHB1ENR_OTGHSEN_Pos (25U) +#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk +#define RCC_AHB1ENR_USBPHYCEN_Pos (26U) +#define RCC_AHB1ENR_USBPHYCEN_Msk (0x1UL << RCC_AHB1ENR_USBPHYCEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1ENR_USBPHYCEN RCC_AHB1ENR_USBPHYCEN_Msk +#define RCC_AHB1ENR_OTGFSEN_Pos (27U) +#define RCC_AHB1ENR_OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_OTGFSEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1ENR_OTGFSEN RCC_AHB1ENR_OTGFSEN_Msk +#define RCC_AHB1ENR_ADF1EN_Pos (31U) +#define RCC_AHB1ENR_ADF1EN_Msk (0x1UL << RCC_AHB1ENR_ADF1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_ADF1EN RCC_AHB1ENR_ADF1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register ***************/ +#define RCC_AHB2ENR_PSSIEN_Pos (1U) +#define RCC_AHB2ENR_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_PSSIEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_PSSIEN RCC_AHB2ENR_PSSIEN_Msk +#define RCC_AHB2ENR_SDMMC2EN_Pos (9U) +#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk +#define RCC_AHB2ENR_CORDICEN_Pos (14U) +#define RCC_AHB2ENR_CORDICEN_Msk (0x1UL << RCC_AHB2ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2ENR_CORDICEN RCC_AHB2ENR_CORDICEN_Msk +#define RCC_AHB2ENR_SRAM1EN_Pos (29U) +#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB3ENR register ***************/ +#define RCC_AHB3ENR_RNGEN_Pos (0U) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk +#define RCC_AHB3ENR_HASHEN_Pos (1U) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk +#define RCC_AHB3ENR_CRYPEN_Pos (2U) +#define RCC_AHB3ENR_CRYPEN_Msk (0x1UL << RCC_AHB3ENR_CRYPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENR_CRYPEN RCC_AHB3ENR_CRYPEN_Msk +#define RCC_AHB3ENR_SAESEN_Pos (4U) +#define RCC_AHB3ENR_SAESEN_Msk (0x1UL << RCC_AHB3ENR_SAESEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENR_SAESEN RCC_AHB3ENR_SAESEN_Msk +#define RCC_AHB3ENR_PKAEN_Pos (6U) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk + +/******************** Bit definition for RCC_AHB4ENR register ***************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0U) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk +#define RCC_AHB4ENR_GPIOBEN_Pos (1U) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk +#define RCC_AHB4ENR_GPIOCEN_Pos (2U) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk +#define RCC_AHB4ENR_GPIODEN_Pos (3U) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk +#define RCC_AHB4ENR_GPIOEEN_Pos (4U) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk +#define RCC_AHB4ENR_GPIOFEN_Pos (5U) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk +#define RCC_AHB4ENR_GPIOGEN_Pos (6U) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk +#define RCC_AHB4ENR_GPIOHEN_Pos (7U) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk +#define RCC_AHB4ENR_GPIOMEN_Pos (12U) +#define RCC_AHB4ENR_GPIOMEN_Msk (0x1UL << RCC_AHB4ENR_GPIOMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4ENR_GPIOMEN RCC_AHB4ENR_GPIOMEN_Msk +#define RCC_AHB4ENR_GPIONEN_Pos (13U) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk +#define RCC_AHB4ENR_GPIOOEN_Pos (14U) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk +#define RCC_AHB4ENR_GPIOPEN_Pos (15U) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk +#define RCC_AHB4ENR_CRCEN_Pos (19U) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk +#define RCC_AHB4ENR_BKPRAMEN_Pos (28U) +#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk + +/******************** Bit definition for RCC_AHB5ENR register ***************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0U) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk +#define RCC_AHB5ENR_DMA2DEN_Pos (1U) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk +#define RCC_AHB5ENR_JPEGEN_Pos (3U) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk +#define RCC_AHB5ENR_FMCEN_Pos (4U) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk +#define RCC_AHB5ENR_XSPI1EN_Pos (5U) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk +#define RCC_AHB5ENR_SDMMC1EN_Pos (8U) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk +#define RCC_AHB5ENR_XSPI2EN_Pos (12U) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk +#define RCC_AHB5ENR_XSPIMEN_Pos (14U) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk +#define RCC_AHB5ENR_GFXMMUEN_Pos (19U) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_TIM4EN_Pos (2U) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk +#define RCC_APB1ENR1_TIM5EN_Pos (3U) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk +#define RCC_APB1ENR1_TIM6EN_Pos (4U) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk +#define RCC_APB1ENR1_TIM7EN_Pos (5U) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk +#define RCC_APB1ENR1_TIM12EN_Pos (6U) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk +#define RCC_APB1ENR1_TIM13EN_Pos (7U) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk +#define RCC_APB1ENR1_TIM14EN_Pos (8U) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk +#define RCC_APB1ENR1_LPTIM1EN_Pos (9U) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_SPI2EN_Pos (14U) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk +#define RCC_APB1ENR1_SPI3EN_Pos (15U) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk +#define RCC_APB1ENR1_SPDIFRXEN_Pos (16U) +#define RCC_APB1ENR1_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRXEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRXEN RCC_APB1ENR1_SPDIFRXEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_USART3EN_Pos (18U) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk +#define RCC_APB1ENR1_UART4EN_Pos (19U) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk +#define RCC_APB1ENR1_UART5EN_Pos (20U) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk +#define RCC_APB1ENR1_I2C1_I3C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1_I3C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1_I3C1EN RCC_APB1ENR1_I2C1_I3C1EN_Msk +#define RCC_APB1ENR1_I2C2EN_Pos (22U) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk +#define RCC_APB1ENR1_I2C3EN_Pos (23U) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk +#define RCC_APB1ENR1_CECEN_Pos (27U) +#define RCC_APB1ENR1_CECEN_Msk (0x1UL << RCC_APB1ENR1_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR1_CECEN RCC_APB1ENR1_CECEN_Msk +#define RCC_APB1ENR1_UART7EN_Pos (30U) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk +#define RCC_APB1ENR1_UART8EN_Pos (31U) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_CRSEN_Pos (1U) +#define RCC_APB1ENR2_CRSEN_Msk (0x1UL << RCC_APB1ENR2_CRSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR2_CRSEN RCC_APB1ENR2_CRSEN_Msk +#define RCC_APB1ENR2_MDIOSEN_Pos (5U) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk +#define RCC_APB1ENR2_FDCANEN_Pos (8U) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk +#define RCC_APB1ENR2_UCPD1EN_Pos (27U) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk + +/******************** Bit definition for RCC_APB2ENR register ***************/ +#define RCC_APB2ENR_TIM1EN_Pos (0U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (4U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_SPI4EN_Pos (13U) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_TIM9EN_Pos (19U) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk +#define RCC_APB2ENR_SPI5EN_Pos (20U) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (22U) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk +#define RCC_APB2ENR_SAI2EN_Pos (23U) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk + +/******************** Bit definition for RCC_APB4ENR register ***************/ +#define RCC_APB4ENR_SBSEN_Pos (1U) +#define RCC_APB4ENR_SBSEN_Msk (0x1UL << RCC_APB4ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR_SBSEN RCC_APB4ENR_SBSEN_Msk +#define RCC_APB4ENR_LPUART1EN_Pos (3U) +#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk +#define RCC_APB4ENR_SPI6EN_Pos (5U) +#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk +#define RCC_APB4ENR_LPTIM2EN_Pos (9U) +#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk +#define RCC_APB4ENR_LPTIM3EN_Pos (10U) +#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk +#define RCC_APB4ENR_LPTIM4EN_Pos (11U) +#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk +#define RCC_APB4ENR_LPTIM5EN_Pos (12U) +#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk +#define RCC_APB4ENR_VREFEN_Pos (15U) +#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk +#define RCC_APB4ENR_RTCAPBEN_Pos (16U) +#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk +#define RCC_APB4ENR_DTSEN_Pos (26U) +#define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk + +/******************** Bit definition for RCC_APB5ENR register ***************/ +#define RCC_APB5ENR_DCMIPPEN_Pos (2U) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk +#define RCC_APB5ENR_GFXTIMEN_Pos (4U) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk + +/******************** Bit definition for RCC_AHB1LPENR register *************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4U) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk +#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U) +#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk +#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U) +#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk +#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U) +#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk +#define RCC_AHB1LPENR_UCPDCTRL_Pos (24U) +#define RCC_AHB1LPENR_UCPDCTRL_Msk (0x1UL << RCC_AHB1LPENR_UCPDCTRL_Pos) /*!< 0x01000000 */ +#define RCC_AHB1LPENR_UCPDCTRL RCC_AHB1LPENR_UCPDCTRL_Msk +#define RCC_AHB1LPENR_OTGHSLPEN_Pos (25U) +#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk +#define RCC_AHB1LPENR_USBPHYCLPEN_Pos (26U) +#define RCC_AHB1LPENR_USBPHYCLPEN_Msk (0x1UL << RCC_AHB1LPENR_USBPHYCLPEN_Pos)/*!< 0x04000000 */ +#define RCC_AHB1LPENR_USBPHYCLPEN RCC_AHB1LPENR_USBPHYCLPEN_Msk +#define RCC_AHB1LPENR_OTGFSLPEN_Pos (27U) +#define RCC_AHB1LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGFSLPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1LPENR_OTGFSLPEN RCC_AHB1LPENR_OTGFSLPEN_Msk +#define RCC_AHB1LPENR_ADF1LPEN_Pos (31U) +#define RCC_AHB1LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADF1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_ADF1LPEN RCC_AHB1LPENR_ADF1LPEN_Msk + +/******************** Bit definition for RCC_AHB2LPENR register *************/ +#define RCC_AHB2LPENR_PSSILPEN_Pos (1U) +#define RCC_AHB2LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_PSSILPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_PSSILPEN RCC_AHB2LPENR_PSSILPEN_Msk +#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U) +#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk +#define RCC_AHB2LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB2LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2LPENR_CORDICLPEN RCC_AHB2LPENR_CORDICLPEN_Msk +#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U) +#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk +#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk + +/******************** Bit definition for RCC_AHB3LPENR register *************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0U) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk +#define RCC_AHB3LPENR_HASHLPEN_Pos (1U) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk +#define RCC_AHB3LPENR_CRYPLPEN_Pos (2U) +#define RCC_AHB3LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENR_CRYPLPEN RCC_AHB3LPENR_CRYPLPEN_Msk +#define RCC_AHB3LPENR_SAESLPEN_Pos (4U) +#define RCC_AHB3LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENR_SAESLPEN RCC_AHB3LPENR_SAESLPEN_Msk +#define RCC_AHB3LPENR_PKALPEN_Pos (6U) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk + +/******************** Bit definition for RCC_AHB4LPENR register *************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk +#define RCC_AHB4LPENR_GPIOMLPEN_Pos (12U) +#define RCC_AHB4LPENR_GPIOMLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4LPENR_GPIOMLPEN RCC_AHB4LPENR_GPIOMLPEN_Msk +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13U) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14U) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15U) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk +#define RCC_AHB4LPENR_CRCLPEN_Pos (19U) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk +#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U) +#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk + +/******************** Bit definition for RCC_AHB5LPENR register *************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0U) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1U) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk +#define RCC_AHB5LPENR_FLASHLPEN_Pos (2U) +#define RCC_AHB5LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB5LPENR_FLASHLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB5LPENR_FLASHLPEN RCC_AHB5LPENR_FLASHLPEN_Msk +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3U) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk +#define RCC_AHB5LPENR_FMCLPEN_Pos (4U) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5U) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8U) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12U) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (14U) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19U) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk +#define RCC_AHB5LPENR_DTCM1LPEN_Pos (28U) +#define RCC_AHB5LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_DTCM1LPEN RCC_AHB5LPENR_DTCM1LPEN_Msk +#define RCC_AHB5LPENR_DTCM2LPEN_Pos (29U) +#define RCC_AHB5LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_DTCM2LPEN RCC_AHB5LPENR_DTCM2LPEN_Msk +#define RCC_AHB5LPENR_ITCMLPEN_Pos (30U) +#define RCC_AHB5LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB5LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENR_ITCMLPEN RCC_AHB5LPENR_ITCMLPEN_Msk +#define RCC_AHB5LPENR_AXISRAMLPEN_Pos (31U) +#define RCC_AHB5LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB5LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5LPENR_AXISRAMLPEN RCC_AHB5LPENR_AXISRAMLPEN_Msk + +/******************** Bit definition for RCC_APB1LPENR1 register ************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0U) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1U) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2U) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3U) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4U) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5U) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6U) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7U) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8U) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9U) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)/*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11U) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14U) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15U) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk +#define RCC_APB1LPENR1_SPDIFRXLPEN_Pos (16U) +#define RCC_APB1LPENR1_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRXLPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRXLPEN RCC_APB1LPENR1_SPDIFRXLPEN_Msk +#define RCC_APB1LPENR1_USART2LPEN_Pos (17U) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk +#define RCC_APB1LPENR1_USART3LPEN_Pos (18U) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk +#define RCC_APB1LPENR1_UART4LPEN_Pos (19U) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk +#define RCC_APB1LPENR1_UART5LPEN_Pos (20U) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos (21U) +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1_I3C1LPEN RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22U) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23U) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk +#define RCC_APB1LPENR1_CECLPEN_Pos (27U) +#define RCC_APB1LPENR1_CECLPEN_Msk (0x1UL << RCC_APB1LPENR1_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR1_CECLPEN RCC_APB1LPENR1_CECLPEN_Msk +#define RCC_APB1LPENR1_UART7LPEN_Pos (30U) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk +#define RCC_APB1LPENR1_UART8LPEN_Pos (31U) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk + +/******************** Bit definition for RCC_PB1LPENR2 register ************/ +#define RCC_APB1LPENR2_CRSLPEN_Pos (1U) +#define RCC_APB1LPENR2_CRSLPEN_Msk (0x1UL << RCC_APB1LPENR2_CRSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR2_CRSLPEN RCC_APB1LPENR2_CRSLPEN_Msk +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5U) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8U) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (27U) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk + +/******************** Bit definition for RCC_APB2LPENR register *************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk +#define RCC_APB2LPENR_USART1LPEN_Pos (4U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk +#define RCC_APB2LPENR_SPI4LPEN_Pos (13U) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk +#define RCC_APB2LPENR_TIM9LPEN_Pos (19U) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk +#define RCC_APB2LPENR_SPI5LPEN_Pos (20U) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk +#define RCC_APB2LPENR_SAI1LPEN_Pos (22U) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk +#define RCC_APB2LPENR_SAI2LPEN_Pos (23U) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk + +/******************** Bit definition for RCC_APB4LPENR register *************/ +#define RCC_APB4LPENR_SBSLPEN_Pos (1U) +#define RCC_APB4LPENR_SBSLPEN_Msk (0x1UL << RCC_APB4LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENR_SBSLPEN RCC_APB4LPENR_SBSLPEN_Msk +#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U) +#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk +#define RCC_APB4LPENR_SPI6LPEN_Pos (5U) +#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk +#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U) +#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk +#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U) +#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk +#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U) +#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk +#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U) +#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk +#define RCC_APB4LPENR_VREFLPEN_Pos (15U) +#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk +#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U) +#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk +#define RCC_APB4LPENR_DTSLPEN_Pos (26U) +#define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk + +/******************** Bit definition for RCC_APB5LPENR register *************/ +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2U) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4U) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Secure Advanced Encryption Standard (SAES) */ +/* */ +/******************************************************************************/ +/******************* Bits definition for SAES_CR register *********************/ +#define SAES_CR_EN_Pos (0U) +#define SAES_CR_EN_Msk (0x1UL << SAES_CR_EN_Pos) /*!< 0x00000001 */ +#define SAES_CR_EN SAES_CR_EN_Msk /*!< SAES Enable */ +#define SAES_CR_DATATYPE_Pos (1U) +#define SAES_CR_DATATYPE_Msk (0x3UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define SAES_CR_DATATYPE SAES_CR_DATATYPE_Msk /*!< Data type selection */ +#define SAES_CR_DATATYPE_0 (0x1UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define SAES_CR_DATATYPE_1 (0x2UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define SAES_CR_MODE_Pos (3U) +#define SAES_CR_MODE_Msk (0x3UL << SAES_CR_MODE_Pos) /*!< 0x00000018 */ +#define SAES_CR_MODE SAES_CR_MODE_Msk /*!< SAES Mode Of Operation */ +#define SAES_CR_MODE_0 (0x1UL << SAES_CR_MODE_Pos) /*!< 0x00000008 */ +#define SAES_CR_MODE_1 (0x2UL << SAES_CR_MODE_Pos) /*!< 0x00000010 */ +#define SAES_CR_CHMOD_Pos (5U) +#define SAES_CR_CHMOD_Msk (0x803UL << SAES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define SAES_CR_CHMOD SAES_CR_CHMOD_Msk /*!< SAES Chaining Mode */ +#define SAES_CR_CHMOD_0 (0x001UL << SAES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define SAES_CR_CHMOD_1 (0x002UL << SAES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define SAES_CR_CHMOD_2 (0x800UL << SAES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define SAES_CR_DMAINEN_Pos (11U) +#define SAES_CR_DMAINEN_Msk (0x1UL << SAES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define SAES_CR_DMAINEN SAES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define SAES_CR_DMAOUTEN_Pos (12U) +#define SAES_CR_DMAOUTEN_Msk (0x1UL << SAES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define SAES_CR_DMAOUTEN SAES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define SAES_CR_GCMPH_Pos (13U) +#define SAES_CR_GCMPH_Msk (0x3UL << SAES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define SAES_CR_GCMPH SAES_CR_GCMPH_Msk /*!< GCM Phase */ +#define SAES_CR_GCMPH_0 (0x1UL << SAES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define SAES_CR_GCMPH_1 (0x2UL << SAES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define SAES_CR_KEYSIZE_Pos (18U) +#define SAES_CR_KEYSIZE_Msk (0x1UL << SAES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE SAES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define SAES_CR_NPBLB_Pos (20U) +#define SAES_CR_NPBLB_Msk (0xFUL << SAES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define SAES_CR_NPBLB SAES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define SAES_CR_NPBLB_0 (0x1UL << SAES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define SAES_CR_NPBLB_1 (0x2UL << SAES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define SAES_CR_NPBLB_2 (0x4UL << SAES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define SAES_CR_NPBLB_3 (0x8UL << SAES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define SAES_CR_KMOD_Pos (24U) +#define SAES_CR_KMOD_Msk (0x3UL << SAES_CR_KMOD_Pos) /*!< 0x00000006 */ +#define SAES_CR_KMOD SAES_CR_KMOD_Msk /*!< Key mode selection */ +#define SAES_CR_KMOD_0 (0x1UL << SAES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define SAES_CR_KMOD_1 (0x2UL << SAES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define SAES_CR_KSHAREID_Pos (26U) +#define SAES_CR_KSHAREID_Msk (0x3UL << SAES_CR_KSHAREID_Pos) /*!< 0x00000006 */ +#define SAES_CR_KSHAREID SAES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define SAES_CR_KEYSEL_Pos (28U) +#define SAES_CR_KEYSEL_Msk (0x7UL << SAES_CR_KEYSEL_Pos) /*!< 0x00000006 */ +#define SAES_CR_KEYSEL SAES_CR_KEYSEL_Msk /*!< Key Selection */ +#define SAES_CR_KEYSEL_0 (0x1UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_KEYSEL_1 (0x2UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_KEYSEL_2 (0x4UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_IPRST_Pos (31U) +#define SAES_CR_IPRST_Msk (0x1UL << SAES_CR_IPRST_Pos) /*!< 0x80000001 */ +#define SAES_CR_IPRST SAES_CR_IPRST_Msk /*!< SAES IP software reset */ + +/******************* Bits definition for SAES_SR register *********************/ +#define SAES_SR_CCF_Pos (0U) +#define SAES_SR_CCF_Msk (0x1UL << SAES_SR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_SR_CCF SAES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define SAES_SR_RDERR_Pos (1U) +#define SAES_SR_RDERR_Msk (0x1UL << SAES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define SAES_SR_RDERR SAES_SR_RDERR_Msk /*!< Read Error Flag */ +#define SAES_SR_WRERR_Pos (2U) +#define SAES_SR_WRERR_Msk (0x1UL << SAES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define SAES_SR_WRERR SAES_SR_WRERR_Msk /*!< Write Error Flag */ +#define SAES_SR_BUSY_Pos (3U) +#define SAES_SR_BUSY_Msk (0x1UL << SAES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define SAES_SR_BUSY SAES_SR_BUSY_Msk /*!< Busy Flag */ +#define SAES_SR_KEYVALID_Pos (7U) +#define SAES_SR_KEYVALID_Msk (0x1UL << SAES_SR_KEYVALID_Pos) /*!< 0x00000008 */ +#define SAES_SR_KEYVALID SAES_SR_KEYVALID_Msk /*!< KEYVALID Flag */ + +/******************* Bits definition for SAES_DINR register *******************/ +#define SAES_DINR_Pos (0U) +#define SAES_DINR_Msk (0xFFFFFFFFUL << SAES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DINR SAES_DINR_Msk /*!< SAES Data Input Register */ + +/******************* Bits definition for SAES_DOUTR register ******************/ +#define SAES_DOUTR_Pos (0U) +#define SAES_DOUTR_Msk (0xFFFFFFFFUL << SAES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DOUTR SAES_DOUTR_Msk /*!< SAES Data Output Register */ + +/******************* Bits definition for SAES_KEYR0 register ******************/ +#define SAES_KEYR0_Pos (0U) +#define SAES_KEYR0_Msk (0xFFFFFFFFUL << SAES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR0 SAES_KEYR0_Msk /*!< SAES Key Register 0 */ + +/******************* Bits definition for SAES_KEYR1 register ******************/ +#define SAES_KEYR1_Pos (0U) +#define SAES_KEYR1_Msk (0xFFFFFFFFUL << SAES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR1 SAES_KEYR1_Msk /*!< SAES Key Register 1 */ + +/******************* Bits definition for SAES_KEYR2 register ******************/ +#define SAES_KEYR2_Pos (0U) +#define SAES_KEYR2_Msk (0xFFFFFFFFUL << SAES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR2 SAES_KEYR2_Msk /*!< SAES Key Register 2 */ + +/******************* Bits definition for SAES_KEYR3 register ******************/ +#define SAES_KEYR3_Pos (0U) +#define SAES_KEYR3_Msk (0xFFFFFFFFUL << SAES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR3 SAES_KEYR3_Msk /*!< SAES Key Register 3 */ + +/******************* Bits definition for SAES_KEYR4 register ******************/ +#define SAES_KEYR4_Pos (0U) +#define SAES_KEYR4_Msk (0xFFFFFFFFUL << SAES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR4 SAES_KEYR4_Msk /*!< SAES Key Register 4 */ + +/******************* Bits definition for SAES_KEYR5 register ******************/ +#define SAES_KEYR5_Pos (0U) +#define SAES_KEYR5_Msk (0xFFFFFFFFUL << SAES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR5 SAES_KEYR5_Msk /*!< SAES Key Register 5 */ + +/******************* Bits definition for SAES_KEYR6 register ******************/ +#define SAES_KEYR6_Pos (0U) +#define SAES_KEYR6_Msk (0xFFFFFFFFUL << SAES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR6 SAES_KEYR6_Msk /*!< SAES Key Register 6 */ + +/******************* Bits definition for SAES_KEYR7 register ******************/ +#define SAES_KEYR7_Pos (0U) +#define SAES_KEYR7_Msk (0xFFFFFFFFUL << SAES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR7 SAES_KEYR7_Msk /*!< SAES Key Register 7 */ + +/******************* Bits definition for SAES_IVR0 register ******************/ +#define SAES_IVR0_Pos (0U) +#define SAES_IVR0_Msk (0xFFFFFFFFUL << SAES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR0 SAES_IVR0_Msk /*!< SAES Initialization Vector Register 0 */ + +/******************* Bits definition for SAES_IVR1 register ******************/ +#define SAES_IVR1_Pos (0U) +#define SAES_IVR1_Msk (0xFFFFFFFFUL << SAES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR1 SAES_IVR1_Msk /*!< SAES Initialization Vector Register 1 */ + +/******************* Bits definition for SAES_IVR2 register ******************/ +#define SAES_IVR2_Pos (0U) +#define SAES_IVR2_Msk (0xFFFFFFFFUL << SAES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR2 SAES_IVR2_Msk /*!< SAES Initialization Vector Register 2 */ + +/******************* Bits definition for SAES_IVR3 register ******************/ +#define SAES_IVR3_Pos (0U) +#define SAES_IVR3_Msk (0xFFFFFFFFUL << SAES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR3 SAES_IVR3_Msk /*!< SAES Initialization Vector Register 3 */ + +/******************* Bit definition for SAES_SUSP0R register ******************/ +#define SAES_SUSP0R_Pos (0U) +#define SAES_SUSP0R_Msk (0xFFFFFFFFUL << SAES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP0R SAES_SUSP0R_Msk /*!< SAES Suspend registers 0 */ + +/******************* Bit definition for SAES_SUSP1R register ******************/ +#define SAES_SUSP1R_Pos (0U) +#define SAES_SUSP1R_Msk (0xFFFFFFFFUL << SAES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP1R SAES_SUSP1R_Msk /*!< SAES Suspend registers 1 */ + +/******************* Bit definition for SAES_SUSP2R register ******************/ +#define SAES_SUSP2R_Pos (0U) +#define SAES_SUSP2R_Msk (0xFFFFFFFFUL << SAES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP2R SAES_SUSP2R_Msk /*!< SAES Suspend registers 2 */ + +/******************* Bit definition for SAES_SUSP3R register ******************/ +#define SAES_SUSP3R_Pos (0U) +#define SAES_SUSP3R_Msk (0xFFFFFFFFUL << SAES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP3R SAES_SUSP3R_Msk /*!< SAES Suspend registers 3 */ + +/******************* Bit definition for SAES_SUSP4R register ******************/ +#define SAES_SUSP4R_Pos (0U) +#define SAES_SUSP4R_Msk (0xFFFFFFFFUL << SAES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP4R SAES_SUSP4R_Msk /*!< SAES Suspend registers 4 */ + +/******************* Bit definition for SAES_SUSP5R register ******************/ +#define SAES_SUSP5R_Pos (0U) +#define SAES_SUSP5R_Msk (0xFFFFFFFFUL << SAES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP5R SAES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for SAES_SUSP6R register ******************/ +#define SAES_SUSP6R_Pos (0U) +#define SAES_SUSP6R_Msk (0xFFFFFFFFUL << SAES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP6R SAES_SUSP6R_Msk /*!< SAES Suspend registers 6 */ + +/******************* Bit definition for SAES_SUSP7R register ******************/ +#define SAES_SUSP7R_Pos (0U) +#define SAES_SUSP7R_Msk (0xFFFFFFFFUL << SAES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP7R SAES_SUSP7R_Msk /*!< SAES Suspend registers 7 */ + +/******************* Bits definition for SAES_IER register ******************/ +#define SAES_IER_CCFIE_Pos (0U) +#define SAES_IER_CCFIE_Msk (0x1UL << SAES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define SAES_IER_CCFIE SAES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define SAES_IER_RWEIE_Pos (1U) +#define SAES_IER_RWEIE_Msk (0x1UL << SAES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define SAES_IER_RWEIE SAES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define SAES_IER_KEIE_Pos (2U) +#define SAES_IER_KEIE_Msk (0x1UL << SAES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define SAES_IER_KEIE SAES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define SAES_IER_RNGEIE_Pos (3U) +#define SAES_IER_RNGEIE_Msk (0x1UL << SAES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define SAES_IER_RNGEIE SAES_IER_RNGEIE_Msk /*!< Rng error interrupt enable */ + +/******************* Bits definition for SAES_ISR register ******************/ +#define SAES_ISR_CCF_Pos (0U) +#define SAES_ISR_CCF_Msk (0x1UL << SAES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ISR_CCF SAES_ISR_CCF_Msk /*!< Computation complete flag */ +#define SAES_ISR_RWEIF_Pos (1U) +#define SAES_ISR_RWEIF_Msk (0x1UL << SAES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ISR_RWEIF SAES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define SAES_ISR_KEIF_Pos (2U) +#define SAES_ISR_KEIF_Msk (0x1UL << SAES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ISR_KEIF SAES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define SAES_ISR_RNGEIF_Pos (3U) +#define SAES_ISR_RNGEIF_Msk (0x1UL << SAES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ISR_RNGEIF SAES_ISR_RNGEIF_Msk /*!< Rng error interrupt flag */ + +/******************* Bits definition for SAES_ICR register ******************/ +#define SAES_ICR_CCF_Pos (0U) +#define SAES_ICR_CCF_Msk (0x1UL << SAES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ICR_CCF SAES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define SAES_ICR_RWEIF_Pos (1U) +#define SAES_ICR_RWEIF_Msk (0x1UL << SAES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ICR_RWEIF SAES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define SAES_ICR_KEIF_Pos (2U) +#define SAES_ICR_KEIF_Msk (0x1UL << SAES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ICR_KEIF SAES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define SAES_ICR_RNGEIF_Pos (3U) +#define SAES_ICR_RNGEIF_Msk (0x1UL << SAES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ICR_RNGEIF SAES_ICR_RNGEIF_Msk /*!< Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*! /*!< ARM Cortex-M7 processor and core peripherals */ +// Note: Changed for MikroE implementation. +// #include "system_stm32h7rsxx.h" /*!< STM32H7RSxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0BC */ + __IO uint32_t OR; /*!< ADC option register, Address offset: 0xC8 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */ +} ADC_Common_TypeDef; + +/** + * @brief AXIM ASIB + */ +typedef struct +{ + uint32_t RESERVED1[9]; /*!< Reserved, Address offset: 0x00-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM ASIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[54]; /*!< Reserved, Address offset: 0x28-0xFC */ + __IO uint32_t READQOS; /*!< AXIM ASIB read_qos register Address offset: 0x100 */ + __IO uint32_t WRITEQOS; /*!< AXIM ASIB write_qos register Address offset: 0x104 */ + __IO uint32_t FNMOD; /*!< AXIM ASIB fn_mod register Address offset: 0x108 */ +} AXIM_ASIB_TypeDef; + +typedef struct +{ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x00-0x04 */ + __IO uint32_t FNMODBMISS; /*!< AXIM AMIB fn_mod_bm_iss register Address offset: 0x08 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x0C-0x20 */ + __IO uint32_t FNMOD2; /*!< AXIM AMIB fn_mod2 register Address offset: 0x24 */ + uint32_t RESERVED3[1]; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t FNMODLB; /*!< AXIM AMIB fn_mod_lb register Address offset: 0x2C */ + uint32_t RESERVED5[54]; /*!< Reserved, Address offset: 0x30-0x104 */ + __IO uint32_t FNMOD; /*!< AXIM AMIB fn_mod register Address offset: 0x108 */ +} AXIM_AMIB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +} CEC_TypeDef; + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC Control and Status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Cryp Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ + __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */ + __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ + __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ + __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ + __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ + __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ + __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ + __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ + __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ + __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ + __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ + __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ + __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ + __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ + __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ + __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ + __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ + __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ + __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ + __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ + __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ + __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ + __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ + __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ + __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ + __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ + __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ + __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ + __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ + __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ + __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ + __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ + __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ + __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ +} CRYP_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x08-0x18 */ + __IO uint32_t AHB5FZR; /*!< Debug MCU AHB5FZR freeze register, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1FZR freeze register, Address offset: 0x24 */ + uint32_t RESERVED3[5]; /*!< Reserved, Address offset: 0x28-0x38 */ + __IO uint32_t APB1FZR; /*!< Debug MCU APB1FZR freeze register, Address offset: 0x3C */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x40-0x48 */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2FZR freeze register, Address offset: 0x4C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZR; /*!< Debug MCU APB4FZR freeze register, Address offset: 0x54 */ + uint32_t RESERVED6[41]; /*!< Reserved, Address offset: 0x58-0xF8 */ + __IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU Authentication Host register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU Authentication Device register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU Authentication Ack register, Address offset: 0x108 */ + uint32_t RESERVED7[945]; /*!< Reserved, Address offset: 0x10C-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMIPP + */ +typedef struct +{ + __IO uint32_t IPGR1; /*!< IP-Plug global register 1 Address offset: 0x00 */ + __IO uint32_t IPGR2; /*!< IP-Plug global register 2 Address offset: 0x04 */ + __IO uint32_t IPGR3; /*!< IP-Plug global register 3 Address offset: 0x08 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x0C-0x18 */ + __IO uint32_t IPGR8; /*!< IP-Plug global register 8 Address offset: 0x1C */ + __IO uint32_t IPC1R1; /*!< IP-Plug client 1 register 1 Address offset: 0x20 */ + __IO uint32_t IPC1R2; /*!< IP-Plug client 1 register 2 Address offset: 0x24 */ + __IO uint32_t IPC1R3; /*!< IP-Plug client 1 register 3 Address offset: 0x28 */ + __IO uint32_t RESERVED2[54]; /*!< Reserved, Address offset: 0x2C-0x100 */ + __IO uint32_t PRCR; /*!< Parallel interface control register Address offset: 0x104 */ + __IO uint32_t PRESCR; /*!< Parallel interface embedded sync code register Address offset: 0x108 */ + __IO uint32_t PRESUR; /*!< Parallel interface embedded sync unmask register Address offset: 0x10C */ + __IO uint32_t RESERVED3[57]; /*!< Reserved, Address offset: 0x110-0x1F0 */ + __IO uint32_t PRIER; /*!< Parallel interface interrupt enable register Address offset: 0x1F4 */ + __IO uint32_t PRSR; /*!< Parallel interface status register Address offset: 0x1F8 */ + __IO uint32_t PRFCR; /*!< Parallel interface interrupt clear register Address offset: 0x1FC */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x200 */ + __IO uint32_t CMCR; /*!< Common configuration register Address offset: 0x204 */ + __IO uint32_t CMFRCR; /*!< Common frame counter register Address offset: 0x208 */ + __IO uint32_t RESERVED5[121]; /*!< Reserved, Address offset: 0x20C-0x3EC */ + __IO uint32_t CMIER; /*!< Common interrupt enable register Address offset: 0x3F0 */ + __IO uint32_t CMSR1; /*!< Common status register 1 Address offset: 0x3F4 */ + __IO uint32_t CMSR2; /*!< Common status register 2 Address offset: 0x3F8 */ + __IO uint32_t CMFCR; /*!< Common interrupt clear register Address offset: 0x3FC */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x400 */ + __IO uint32_t P0FSCR; /*!< Pipe0 flow selection configuration register Address offset: 0x404 */ + __IO uint32_t RESERVED7[62]; /*!< Reserved, Address offset: 0x408-0x4FC */ + __IO uint32_t P0FCTCR; /*!< Pipe0 flow control configuration register Address offset: 0x500 */ + __IO uint32_t P0SCSTR; /*!< Pipe0 stat/crop start register Address offset: 0x504 */ + __IO uint32_t P0SCSZR; /*!< Pipe0 stat/crop size register Address offset: 0x508 */ + __IO uint32_t RESERVED8[41]; /*!< Reserved, Address offset: 0x50C-0x5AC */ + __IO uint32_t P0DCCNTR; /*!< Pipe0 dump counter register Address offset: 0x5B0 */ + __IO uint32_t P0DCLMTR; /*!< Pipe0 dump limit register Address offset: 0x5B4 */ + __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x5B8-0x5BC */ + __IO uint32_t P0PPCR; /*!< Pipe0 pixel packer configuration register Address offset: 0x5C0 */ + __IO uint32_t P0PPM0AR1; /*!< Pipe0 pixel packer memory0 address register 1 Address offset: 0x5C4 */ + __IO uint32_t P0PPM0AR2; /*!< Pipe0 pixel packer memory0 address register 2 Address offset: 0x5C8 */ + __IO uint32_t RESERVED10[10]; /*!< Reserved, Address offset: 0x5CC-0x5F0 */ + __IO uint32_t P0IER; /*!< Pipe0 interrupt enable register Address offset: 0x5F4 */ + __IO uint32_t P0SR; /*!< Pipe0 status register Address offset: 0x5F8 */ + __IO uint32_t P0FCR; /*!< Pipe0 interrupt clear register Address offset: 0x5FC */ + __IO uint32_t RESERVED11[64]; /*!< Reserved, Address offset: 0x600-0x6FC */ + __IO uint32_t P0CFCTCR; /*!< Pipe0 current flow control configuration register Address offset: 0x700 */ + __IO uint32_t P0CSCSTR; /*!< Pipe0 current stat/crop start register Address offset: 0x704 */ + __IO uint32_t P0CSCSZR; /*!< Pipe0 current stat/crop size register Address offset: 0x708 */ + __IO uint32_t RESERVED12[45]; /*!< Reserved, Address offset: 0x70C-0x7BC */ + __IO uint32_t P0CPPCR; /*!< Pipe0 current pixel packer configuration register Address offset: 0x700 */ + __IO uint32_t P0CPPM0AR1; /*!< Pipe0 current pixel packer memory0 address register 1 Address offset: 0x7C4 */ + __IO uint32_t P0CPPM0AR2; /*!< Pipe0 current pixel packer memory0 address register 2 Address offset: 0x7C8 */ +} DCMIPP_TypeDef; + +/** + * @ brief Delay Block + */ +typedef struct +{ + __IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA masked interrupt status register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ +} DMA2D_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} DTS_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x08 */ + uint32_t RESERVED1[5]; /*!< Reserved 1, Address offset: 0x0C-0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x28 */ + uint32_t RESERVED2[21]; /*!< Reserved 2, Address offset: 0x2C-0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x84 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x88 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x94 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x98 */ + uint32_t RESERVED4; /*!< Reserved 4, Address offset: 0x9C */ + __IO uint32_t IMR3; /*!< EXTI Interrupt mask register 3, Address offset: 0xA0 */ + __IO uint32_t EMR3; /*!< EXTI Event mask register 3, Address offset: 0xA4 */ +} EXTI_TypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x000 */ + __IO uint32_t KEYR; /*!< FLASH control key register, Address offset: 0x004 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x008 - 0x00C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x010 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t IER; /*!< FLASH interrupt enable register, Address offset: 0x020 */ + __IO uint32_t ISR; /*!< FLASH interrupt status register, Address offset: 0x024 */ + __IO uint32_t ICR; /*!< FLASH interrupt clear register, Address offset: 0x028 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x02C */ + __IO uint32_t CRCCR; /*!< FLASH CRC control register, Address offset: 0x030 */ + __IO uint32_t CRCSADDR; /*!< FLASH CRC start address register, Address offset: 0x034 */ + __IO uint32_t CRCEADDR; /*!< FLASH CRC end address register, Address offset: 0x038 */ + __IO uint32_t CRCDATAR; /*!< FLASH CRC data register, Address offset: 0x03C */ + __IO uint32_t ECCSFADDR; /*!< FLASH ECC single fail address register, Address offset: 0x040 */ + __IO uint32_t ECCDFADDR; /*!< FLASH ECC double fail address register, Address offset: 0x044 */ + uint32_t RESERVED4[46]; /*!< Reserved, Address offset: 0x048 - 0x0FC */ + __IO uint32_t OPTKEYR; /*!< FLASH options key register, Address offset: 0x100 */ + __IO uint32_t OPTCR; /*!< FLASH options control register, Address offset: 0x104 */ + __IO uint32_t OPTISR; /*!< FLASH options interrupt status register, Address offset: 0x108 */ + __IO uint32_t OPTICR; /*!< FLASH options interrupt clear register, Address offset: 0x10C */ + __IO uint32_t OBKCR; /*!< FLASH option byte key control register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x114 */ + __IO uint32_t OBKDR[8]; /*!< FLASH option bytes key data register, Address offset: 0x118 - 0x134 */ + uint32_t RESERVED6[50]; /*!< Reserved, Address offset: 0x138 - 0x1FC */ + __IO uint32_t NVSR; /*!< FLASH non-volatile status register, Address offset: 0x200 */ + __IO uint32_t NVSRP; /*!< FLASH security status register programming, Address offset: 0x204 */ + __IO uint32_t ROTSR; /*!< FLASH RoT status register, Address offset: 0x208 */ + __IO uint32_t ROTSRP; /*!< FLASH RoT status register programming, Address offset: 0x20C */ + __IO uint32_t OTPLSR; /*!< FLASH OTP lock status register, Address offset: 0x210 */ + __IO uint32_t OTPLSRP; /*!< FLASH OTP lock status programming register, Address offset: 0x214 */ + __IO uint32_t WRPSR; /*!< FLASH write protection status register, Address offset: 0x218 */ + __IO uint32_t WRPSRP; /*!< FLASH write protection status register programming, Address offset: 0x21C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x220 - 0x22C */ + __IO uint32_t HDPSR; /*!< FLASH hide protection status register, Address offset: 0x230 */ + __IO uint32_t HDPSRP; /*!< FLASH hide protection status register programming, Address offset: 0x234 */ + uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0x238 - 0x24C */ + __IO uint32_t EPOCHSR; /*!< FLASH epoch status register, Address offset: 0x250 */ + __IO uint32_t EPOCHSRP; /*!< FLASH epoch status register programming, Address offset: 0x254 */ + uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0x258 - 0x25C */ + __IO uint32_t OBW1SR; /*!< FLASH option byte word 1 status register, Address offset: 0x260 */ + __IO uint32_t OBW1SRP; /*!< FLASH option byte word 1 status register programming, Address offset: 0x264 */ + __IO uint32_t OBW2SR; /*!< FLASH option byte word 2 status register, Address offset: 0x268 */ + __IO uint32_t OBW2SRP; /*!< FLASH option byte word 2 status register programming, Address offset: 0x26C */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 + */ +typedef struct { + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1 Extended + */ +typedef struct { + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct { + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 & 6 + */ +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140 - 0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148 - 0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief GFXMMU + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + __IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 0x00 */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 0x04 */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 0x08 */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0x0C */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 0x10 */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 0x14 */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 0x18 */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 0x1C */ + uint32_t RESERVED0[4]; /* Reserved Address offset: 0x20-0x2C */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 0x30 */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 0x34 */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 0x38 */ + uint32_t RESERVED1; /* Reserved Address offset: 0x3C */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 0x40 */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 0x44 */ + uint32_t RESERVED2[2]; /* Reserved Address offset: 0x48-0x4C */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 0x50-0x8C */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 0x90-0xCC */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: 0xD0-0x10C */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 0x110-0x14C */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 0x150-0x18C */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 0x190-0x20C */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 0x210-0x35C */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 0x360-0x4F8 */ + uint32_t RESERVED3; /* Reserved Address offset: 0x4FC */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 0x500-0x65C */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 0x660-0x7BC */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 0x7C0-0x7DC */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 0x7E0-0x7FC */ +} JPEG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Memory Cipher Engine (MCE) + */ +typedef struct +{ + __IO uint32_t REGCR; /*!< MCE region configuration register, Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t SADDR; /*!< MCE region start address register, Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t EADDR; /*!< MCE region end address register, Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */ + __IO uint32_t ATTR; /*!< MCE region attribute register, Address offset: 0x04C + 0x10 * (x-1) (x = 1 to 4) */ +} MCE_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CCCFGR; /*!< MCE cipher context configuration register, Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR0; /*!< MCE cipher context nonce register 0, Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCNR1; /*!< MCE cipher context nonce register 1, Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR0; /*!< MCE cipher context key register 0, Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR1; /*!< MCE cipher context key register 1, Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR2; /*!< MCE cipher context key register 2, Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */ + __IO uint32_t CCKEYR3; /*!< MCE cipher context key register 3, Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */ +} MCE_Context_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MCE configuration register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< MCE status register, Address offset: 0x004 */ + __IO uint32_t IASR; /*!< MCE illegal access status register, Address offset: 0x008 */ + __IO uint32_t IACR; /*!< MCE illegal access clear register, Address offset: 0x00C */ + __IO uint32_t IAIER; /*!< MCE illegal access interrupt enable register, Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x014-0x018 */ + __IO uint32_t PRIVCFGR; /*!< MCE privileged configuration register, Address offset: 0x01C */ + __IO uint32_t IAESR; /*!< MCE illegal access error status register, Address offset: 0x020 */ + __IO uint32_t IADDR; /*!< MCE illegal address register, Address offset: 0x024 */ + uint32_t RESERVED2[118]; /*!< Reserved, Address offset: 0x028-0x1FC */ + __IO uint32_t MKEYR0; /*!< MCE master key register 0, Address offset: 0x200 */ + __IO uint32_t MKEYR1; /*!< MCE master key register 1, Address offset: 0x204 */ + __IO uint32_t MKEYR2; /*!< MCE master key register 2, Address offset: 0x208 */ + __IO uint32_t MKEYR3; /*!< MCE master key register 3, Address offset: 0x20C */ + uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x210-0x21C */ + __IO uint32_t FMKEYR0; /*!< MCE fast master key register 0, Address offset: 0x220 */ + __IO uint32_t FMKEYR1; /*!< MCE fast master key register 1, Address offset: 0x224 */ + __IO uint32_t FMKEYR2; /*!< MCE fast master key register 2, Address offset: 0x228 */ + __IO uint32_t FMKEYR3; /*!< MCE fast master key register 3, Address offset: 0x22C */ +} MCE_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + +/** + * @brief ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ +} MDF_TypeDef; + +/** + * @brief ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x94-0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + uint32_t RESERVED1[1]; /*!< Reserved, 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED3[10]; /*!< Reserved, 0xC8-0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief XSPI + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */ + __IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */ + uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */ + uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */ + uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */ + uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */ + uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */ + uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */ + uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */ + uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */ + uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */ + __IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */ + uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */ + uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */ +} XSPI_TypeDef; + +/** + * @brief XSPI IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< XSPIM IO Manager Control Register, Address offset: 0x00 */ +} XSPIM_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x04 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control status register 2, Address offset: 0x0C */ + __IO uint32_t CSR3; /*!< PWR power control status register 3, Address offset: 0x10 */ + __IO uint32_t CSR4; /*!< PWR power control status register 4, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< PWR USB Type-C and power delivery register, Address offset: 0x2C */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x30 */ + __IO uint32_t PUCRN; /*!< PWR port N pull-up control register, Address offset: 0x34 */ + __IO uint32_t PDCRN; /*!< PWR port N pull-down control register, Address offset: 0x38 */ + __IO uint32_t PUCRO; /*!< PWR port O pull-up control register, Address offset: 0x3C */ + __IO uint32_t PDCRO; /*!< PWR port O pull-down control register, Address offset: 0x40 */ + __IO uint32_t PDCRP; /*!< PWR port P pull-down control register, Address offset: 0x44 */ + uint32_t RESERVED2[2]; /*!< Reserved */ + __IO uint32_t PDR1; /*!< PWR debug register 1, Address offset: 0x50 */ +} PWR_TypeDef; + +/** + * @brief Public Key Accelerator (PKA) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved1[253]; /*!< Reserved, Address offset: 0x000C-0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x0400-0x18D8 */ +} PKA_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI clock calibration register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock recovery RC register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI clock calibration register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CDCFGR; /*!< RCC CPU domain configuration register, Address offset: 0x18 */ + __IO uint32_t BMCFGR; /*!< RCC Bus matrix configuration register, Address offset: 0x1C */ + __IO uint32_t APBCFGR; /*!< RCC APB clock configuration register, Address offset: 0x20 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs clock source selection register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs configuration register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR1; /*!< RCC PLL1 dividers configuration register 1, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 fractional divider configuration register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR1; /*!< RCC PLL2 dividers configuration register 1, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 fractional divider configuration register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR1; /*!< RCC PLL3 dividers configuration register 1, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 fractional divider configuration register, Address offset: 0x44 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t CCIPR1; /*!< RCC AHB peripherals kernel clock configuration register Address offset: 0x4C */ + __IO uint32_t CCIPR2; /*!< RCC APB1 peripherals kernel clock configuration register Address offset: 0x50 */ + __IO uint32_t CCIPR3; /*!< RCC APB2 peripherals kernel clock configuration register Address offset: 0x54 */ + __IO uint32_t CCIPR4; /*!< RCC APB4/APB5 peripherals kernel clock configuration register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x68 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB5RSTR; /*!< RCC AHB5 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB5RSTR; /*!< RCC APB5 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x90 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0xA0 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0xA4 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xA8-0xAC */ + __IO uint32_t CKGDISR ; /*!< RCC AXI clocks gating disable register, Address offset: 0xB0 */ + uint32_t RESERVED8[3]; /*!< Reserved, Address offset: 0xB4-0xBC */ + __IO uint32_t PLL1DIVR2; /*!< RCC PLL1 dividers configuration register 2, Address offset: 0xC0 */ + __IO uint32_t PLL2DIVR2; /*!< RCC PLL2 dividers configuration register 2, Address offset: 0xC4 */ + __IO uint32_t PLL3DIVR2; /*!< RCC PLL3 dividers configuration register 2, Address offset: 0xC8 */ + __IO uint32_t PLL1SSCGR; /*!< RCC PLL1 spread spectrum clock generator register, Address offset: 0xCC */ + __IO uint32_t PLL2SSCGR; /*!< RCC PLL2 spread spectrum clock generator register, Address offset: 0xD0 */ + __IO uint32_t PLL3SSCGR; /*!< RCC PLL3 spread spectrum clock generator register, Address offset: 0xD4 */ + uint32_t RESERVED9[10]; /*!< Reserved, Address offset: 0xD8-0xFC */ + __IO uint32_t CKPROTR; /*!< RCC clock protection register, Address offset: 0x100 */ + uint32_t RESERVED10[11]; /*!< Reserved, Address offset: 0x104-0x12C */ + __IO uint32_t RSR; /*!< RCC reset status register, Address offset: 0x130 */ + __IO uint32_t AHB5ENR; /*!< RCC AHB5 peripheral clocks enable register, Address offset: 0x134 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x138 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x13C */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clocks enable register, Address offset: 0x140 */ + __IO uint32_t APB5ENR; /*!< RCC APB5 peripheral clocks enable register, Address offset: 0x144 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x148 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x14C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x150 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clocks enable register, Address offset: 0x154 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x158 */ + __IO uint32_t AHB5LPENR; /*!< RCC AHB5 peripheral sleep clocks enable register, Address offset: 0x15C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clocks enable register, Address offset: 0x160 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clocks enable register, Address offset: 0x164 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clocks enable register, Address offset: 0x168 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clocks enable register, Address offset: 0x16C */ + __IO uint32_t APB1LPENR1; /*!< RCC APB1 peripheral sleep clocks enable register 1, Address offset: 0x170 */ + __IO uint32_t APB1LPENR2; /*!< RCC APB1 peripheral sleep clocks enable register 2, Address offset: 0x174 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clocks enable register, Address offset: 0x178 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clocks enable register, Address offset: 0x17C */ + __IO uint32_t APB5LPENR; /*!< RCC APB5 peripheral sleep clocks enable register, Address offset: 0x180 */ +} RCC_TypeDef; + +/** + * @brief Random Number Generator + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief SAES Processor + */ +typedef struct +{ + __IO uint32_t CR; /*!< SAES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< SAES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< SAES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< SAES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< SAES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< SAES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< SAES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< SAES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< SAES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< SAES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< SAES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< SAES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< SAES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< SAES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< SAES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< SAES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< SAES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< SAES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< SAES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< SAES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< SAES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< SAES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< SAES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< SAES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168]; /*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< SAES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< SAES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< SAES Interrupt Clear Register, Address offset: 0x308 */ +} SAES_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration, boot and security controller + */ +typedef struct +{ + __IO uint32_t BOOTSR; /*!< SBS Boot Status register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04-0x0C */ + __IO uint32_t HDPLCR; /*!< SBS Hide Protection Control register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS Hide Protection Status register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x28-0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command register, Address offset: 0x34 */ + uint32_t RESERVED4[50]; /*!< Reserved, Address offset: 0x38-0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status register, Address offset: 0x108 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS IO Compensation Cell Control and Status register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS IO Compensation Cell Value register, Address offset: 0x114 */ + __IO uint32_t CCSWVALR; /*!< SBS IO Compensation Cell Software Value register, Address offset: 0x118 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x11C */ + __IO uint32_t BKLOCKR; /*!< SBS Break Lockup register, Address offset: 0x120 */ + uint32_t RESERVED7[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t EXTICR[4]; /*!< SBS External Interrupt Configuration registers, Address offset: 0x130-0x13C */ +} SBS_TypeDef; + +/** + * @brief Secure Digital Card/IO Embedded MultiMediaCard Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC Power control register, Address offset : 0x000 */ + __IO uint32_t CLKCR; /*!< SDMMC Clock control register, Address offset : 0x004 */ + __IO uint32_t ARG; /*!< SDMMC Argument register, Address offset : 0x008 */ + __IO uint32_t CMD; /*!< SDMMC Command register, Address offset : 0x00C */ + __IO uint32_t RESPCMD; /*!< SDMMC Command response register, Address offset : 0x010 */ + __IO uint32_t RESP1; /*!< SDMMC Response 1 register, Address offset : 0x014 */ + __IO uint32_t RESP2; /*!< SDMMC Response 2 register, Address offset : 0x018 */ + __IO uint32_t RESP3; /*!< SDMMC Response 3 register, Address offset : 0x01C */ + __IO uint32_t RESP4; /*!< SDMMC Response 4 register, Address offset : 0x020 */ + __IO uint32_t DTIMER; /*!< SDMMC Data timer register, Address offset : 0x024 */ + __IO uint32_t DLEN; /*!< SDMMC Data length register, Address offset : 0x028 */ + __IO uint32_t DCTRL; /*!< SDMMC Data control register, Address offset : 0x02C */ + __IO uint32_t DCOUNT; /*!< SDMMC Data counter register, Address offset : 0x030 */ + __IO uint32_t STA; /*!< SDMMC Status register, Address offset : 0x034 */ + __IO uint32_t ICR; /*!< SDMMC Interrupt clear register, Address offset : 0x038 */ + __IO uint32_t MASK; /*!< SDMMC Mask register, Address offset : 0x03C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset : 0x040 */ + uint32_t RESERVED0[3]; /*!< Reserved, Address offset : 0x044 - 0x04C */ + __IO uint32_t IDMACTRL; /*!< SDMMC IDMA control register, Address offset : 0x050 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC IDMA buffer size register, Address offset : 0x054 */ + __IO uint32_t IDMABASER; /*!< SDMMC IDMA buffer base address register, Address offset : 0x058 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset : 0x05C - 0x060 */ + __IO uint32_t IDMALAR; /*!< SDMMC IDMA linked list address register, Address offset : 0x064 */ + __IO uint32_t IDMABAR; /*!< SDMMC IDMA linked list memory base register, Address offset : 0x068 */ + uint32_t RESERVED2[5]; /*!< Reserved, Address offset : 0x06C - 0x07C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset : 0x080 */ +} SDMMC_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ +} SPI_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t CFGR; /*!< TAMP configuration control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + uint32_t RESERVED0[221]; /*!< Reserved, Address offset: 0x68 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Window Watchdog + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32H7RSxx_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup STM32H7RSxx_Peripheral_peripheralAddr + * @{ + */ +#define ITCM_BASE 0x00000000UL /*!< ITCM base address */ +#define FLASH_BASE 0x08000000UL /*!< User Flash address */ +#define OTP_AREA_BASE 0x08FFF000UL /*!< OTP Area base address */ +#define ENGI_BYTES_BASE 0x52002800UL /*!< Engi Bytes */ +#define SYSTEM_FLASH_BASE 0x1FF00000UL /*!< System Flash base address */ +#define DTCM_BASE 0x20000000UL /*!< DTCM base address */ +#define SRAM1_AXI_BASE 0x24000000UL /*!< SRAM1 base address - accessible over AXI */ +#define SRAM2_AXI_BASE 0x24020000UL /*!< SRAM2 base address - accessible over AXI */ +#define SRAM3_AXI_BASE 0x24040000UL /*!< SRAM3 base address - accessible over AXI */ +#define SRAM4_AXI_BASE 0x24060000UL /*!< SRAM4 base address - accessible over AXI */ + +#define GFXMMU_VIRTUAL_BUFFER0_BASE 0x25000000UL /*!< GFXMMU virtual buffer 0 base address */ +#define GFXMMU_VIRTUAL_BUFFER1_BASE 0x25400000UL /*!< GFXMMU virtual buffer 1 base address */ +#define GFXMMU_VIRTUAL_BUFFER2_BASE 0x25800000UL /*!< GFXMMU virtual buffer 2 base address */ +#define GFXMMU_VIRTUAL_BUFFER3_BASE 0x25C00000UL /*!< GFXMMU virtual buffer 3 base address */ + +#define SRAM1_AHB_BASE 0x30000000UL /*!< SRAM1 base address */ +#define SRAM2_AHB_BASE 0x30004000UL /*!< SRAM2 base address */ +#define BKPSRAM_BASE 0x38800000UL /*!< Backup SRAM */ + +#define PERIPH_BASE 0x40000000UL /*!< AHB and APB Peripherals base address */ +#define XSPI2_BASE 0x70000000UL /*!< XSPI2 base address */ +#define XSPI1_BASE 0x90000000UL /*!< XSPI1 base address */ + +/*!< Internal memory size */ +#define ITCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define DTCM_SIZE 0x00010000UL /*!< 64 KB default, can be increased up to 192 KB */ +#define FLASH_SIZE 0x00010000UL /*!< 64 KB */ +#define SRAM1_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase ITCM */ +#define SRAM2_AXI_SIZE 0x00020000UL /*!< 128 KB */ +#define SRAM3_AXI_SIZE 0x00020000UL /*!< 128 KB default, can be decreased down to 0 KB to increase DTCM */ +#define SRAM4_AXI_SIZE 0x00012000UL /*!< 72 KB default, can be decreased to 0 KB when RAM ECC is disable */ +#define SRAM_AHB_SIZE 0x00004000UL /*!< Both AHB SRAMs are 16 KB */ +#define BKPSRAM_SIZE 0x00001000UL /*!< 4 KB */ + +/*!< OTP Area size */ +#define OTP_SIZE 0x400U /* 1 KB */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x08020000UL) +#define APB5PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define AHB5PERIPH_BASE (PERIPH_BASE + 0x12000000UL) +#define APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I3C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (APB1PERIPH_BASE + 0x8400UL) +#define MDIOS_BASE (APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (APB1PERIPH_BASE + 0xA000UL) +#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0xA100UL) /*!< FDCAN configuration registers base address */ +#define FDCAN2_BASE (APB1PERIPH_BASE + 0xA400UL) +#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xAC00UL) +#define UCPD1_BASE (APB1PERIPH_BASE + 0xEC00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00UL) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) + +/*!< AHB1 peripherals */ +#define GPDMA1_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPDMA1_Channel0_BASE (GPDMA1_BASE + 0x0050UL) +#define GPDMA1_Channel1_BASE (GPDMA1_BASE + 0x00D0UL) +#define GPDMA1_Channel2_BASE (GPDMA1_BASE + 0x0150UL) +#define GPDMA1_Channel3_BASE (GPDMA1_BASE + 0x01D0UL) +#define GPDMA1_Channel4_BASE (GPDMA1_BASE + 0x0250UL) +#define GPDMA1_Channel5_BASE (GPDMA1_BASE + 0x02D0UL) +#define GPDMA1_Channel6_BASE (GPDMA1_BASE + 0x0350UL) +#define GPDMA1_Channel7_BASE (GPDMA1_BASE + 0x03D0UL) +#define GPDMA1_Channel8_BASE (GPDMA1_BASE + 0x0450UL) +#define GPDMA1_Channel9_BASE (GPDMA1_BASE + 0x04D0UL) +#define GPDMA1_Channel10_BASE (GPDMA1_BASE + 0x0550UL) +#define GPDMA1_Channel11_BASE (GPDMA1_BASE + 0x05D0UL) +#define GPDMA1_Channel12_BASE (GPDMA1_BASE + 0x0650UL) +#define GPDMA1_Channel13_BASE (GPDMA1_BASE + 0x06D0UL) +#define GPDMA1_Channel14_BASE (GPDMA1_BASE + 0x0750UL) +#define GPDMA1_Channel15_BASE (GPDMA1_BASE + 0x07D0UL) +#define ADC1_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ADF1_BASE (AHB1PERIPH_BASE + 0xF000UL) +#define ADF1_Filter0_BASE (ADF1_BASE + 0x0080UL) +#define USB_OTG_HS_PERIPH_BASE (AHB1PERIPH_BASE + 0x20000UL) +#define USB_OTG_FS_PERIPH_BASE (AHB1PERIPH_BASE + 0x60000UL) + +/*!< AHB2 peripherals */ +#define PSSI_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define SDMMC2_BASE (AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (AHB2PERIPH_BASE + 0x2800UL) +#define CORDIC_BASE (AHB2PERIPH_BASE + 0x4400UL) + +/*!< AHB3 peripherals */ +#define RNG_BASE AHB3PERIPH_BASE +#define HASH_BASE (AHB3PERIPH_BASE + 0x0400UL) +#define HASH_DIGEST_BASE (AHB3PERIPH_BASE + 0x0710UL) +#define CRYP_BASE (AHB3PERIPH_BASE + 0x0800UL) +#define SAES_BASE (AHB3PERIPH_BASE + 0x1000UL) +#define PKA_BASE (AHB3PERIPH_BASE + 0x2000UL) + +/*!< APB5 peripherals */ +#define DCMIPP_BASE (APB5PERIPH_BASE + 0x2000UL) +#define GFXTIM_BASE (APB5PERIPH_BASE + 0x4000UL) + +/*!< AHB5 peripherals */ +#define HPDMA1_BASE AHB5PERIPH_BASE +#define HPDMA1_Channel0_BASE (HPDMA1_BASE + 0x0050UL) +#define HPDMA1_Channel1_BASE (HPDMA1_BASE + 0x00D0UL) +#define HPDMA1_Channel2_BASE (HPDMA1_BASE + 0x0150UL) +#define HPDMA1_Channel3_BASE (HPDMA1_BASE + 0x01D0UL) +#define HPDMA1_Channel4_BASE (HPDMA1_BASE + 0x0250UL) +#define HPDMA1_Channel5_BASE (HPDMA1_BASE + 0x02D0UL) +#define HPDMA1_Channel6_BASE (HPDMA1_BASE + 0x0350UL) +#define HPDMA1_Channel7_BASE (HPDMA1_BASE + 0x03D0UL) +#define HPDMA1_Channel8_BASE (HPDMA1_BASE + 0x0450UL) +#define HPDMA1_Channel9_BASE (HPDMA1_BASE + 0x04D0UL) +#define HPDMA1_Channel10_BASE (HPDMA1_BASE + 0x0550UL) +#define HPDMA1_Channel11_BASE (HPDMA1_BASE + 0x05D0UL) +#define HPDMA1_Channel12_BASE (HPDMA1_BASE + 0x0650UL) +#define HPDMA1_Channel13_BASE (HPDMA1_BASE + 0x06D0UL) +#define HPDMA1_Channel14_BASE (HPDMA1_BASE + 0x0750UL) +#define HPDMA1_Channel15_BASE (HPDMA1_BASE + 0x07D0UL) +#define DMA2D_BASE (AHB5PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB5PERIPH_BASE + 0x2000UL) +#define JPEG_BASE (AHB5PERIPH_BASE + 0x3000UL) +#define FMC_R_BASE (AHB5PERIPH_BASE + 0x4000UL) +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) +#define XSPI1_R_BASE (AHB5PERIPH_BASE + 0x5000UL) +#define SDMMC1_BASE (AHB5PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (AHB5PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (AHB5PERIPH_BASE + 0x9000UL) +#define RAMECC1_Monitor0_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0xA0UL) +#define XSPI2_R_BASE (AHB5PERIPH_BASE + 0xA000UL) +#define XSPIM_BASE (AHB5PERIPH_BASE + 0xB400UL) +#define MCE1_BASE (AHB5PERIPH_BASE + 0xB800UL) +#define MCE1_REGION1_BASE (MCE1_BASE + 0x040UL) +#define MCE1_REGION2_BASE (MCE1_BASE + 0x050UL) +#define MCE1_REGION3_BASE (MCE1_BASE + 0x060UL) +#define MCE1_REGION4_BASE (MCE1_BASE + 0x070UL) +#define MCE1_CONTEXT1_BASE (MCE1_BASE + 0x240UL) +#define MCE1_CONTEXT2_BASE (MCE1_BASE + 0x270UL) +#define MCE2_BASE (AHB5PERIPH_BASE + 0xBC00UL) +#define MCE2_REGION1_BASE (MCE2_BASE + 0x040UL) +#define MCE2_REGION2_BASE (MCE2_BASE + 0x050UL) +#define MCE2_REGION3_BASE (MCE2_BASE + 0x060UL) +#define MCE2_REGION4_BASE (MCE2_BASE + 0x070UL) +#define MCE3_BASE (AHB5PERIPH_BASE + 0xC000UL) +#define MCE3_REGION1_BASE (MCE3_BASE + 0x040UL) +#define MCE3_REGION2_BASE (MCE3_BASE + 0x050UL) +#define MCE3_REGION3_BASE (MCE3_BASE + 0x060UL) +#define MCE3_REGION4_BASE (MCE3_BASE + 0x070UL) +#define GFXMMU_BASE (AHB5PERIPH_BASE + 0x010000UL) + +/*!< APB4 peripherals */ +#define EXTI_BASE APB4PERIPH_BASE +#define SBS_BASE (APB4PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (APB4PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (APB4PERIPH_BASE + 0x1400UL) +#define LPTIM2_BASE (APB4PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (APB4PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (APB4PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (APB4PERIPH_BASE + 0x3000UL) +#define VREFBUF_BASE (APB4PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (APB4PERIPH_BASE + 0x4000UL) +#define TAMP_BASE (APB4PERIPH_BASE + 0x4400UL) +#define IWDG_BASE (APB4PERIPH_BASE + 0x4800UL) +#define DTS_BASE (APB4PERIPH_BASE + 0x6800UL) + +/*!< AHB4 peripherals */ +#define GPIOA_BASE AHB4PERIPH_BASE +#define GPIOB_BASE (AHB4PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB4PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB4PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB4PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB4PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB4PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB4PERIPH_BASE + 0x1C00UL) +#define GPIOM_BASE (AHB4PERIPH_BASE + 0x3000UL) +#define GPION_BASE (AHB4PERIPH_BASE + 0x3400UL) +#define GPIOO_BASE (AHB4PERIPH_BASE + 0x3800UL) +#define GPIOP_BASE (AHB4PERIPH_BASE + 0x3C00UL) +#define RCC_BASE (AHB4PERIPH_BASE + 0x4400UL) +#define PWR_BASE (AHB4PERIPH_BASE + 0x4800UL) +#define CRC_BASE (AHB4PERIPH_BASE + 0x4C00UL) +#define RAMECC2_BASE (AHB4PERIPH_BASE + 0x7000UL) +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x40UL) + +/*!< Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +/*!< AXIM registers base address */ +#define AXIM_BASE (0xBFF00000UL) +#define AXIM_ASIB1_BASE (AXIM_BASE + 0x42000UL) +#define AXIM_ASIB2_BASE (AXIM_BASE + 0x43000UL) +#define AXIM_ASIB3_BASE (AXIM_BASE + 0x44000UL) +#define AXIM_ASIB4_BASE (AXIM_BASE + 0x45000UL) +#define AXIM_ASIB5_BASE (AXIM_BASE + 0x46000UL) +#define AXIM_ASIB6_BASE (AXIM_BASE + 0x47000UL) +#define AXIM_ASIB7_BASE (AXIM_BASE + 0x48000UL) +#define AXIM_ASIB8_BASE (AXIM_BASE + 0x49000UL) +#define AXIM_ASIB9_BASE (AXIM_BASE + 0x4A000UL) +#define AXIM_ASIB10_BASE (AXIM_BASE + 0x4B000UL) +#define AXIM_ASIB11_BASE (AXIM_BASE + 0x4C000UL) +#define AXIM_AMIB1_BASE (AXIM_BASE + 0x02000UL) +#define AXIM_AMIB2_BASE (AXIM_BASE + 0x03000UL) +#define AXIM_AMIB3_BASE (AXIM_BASE + 0x04000UL) +#define AXIM_AMIB4_BASE (AXIM_BASE + 0x05000UL) +#define AXIM_AMIB5_BASE (AXIM_BASE + 0x06000UL) +#define AXIM_AMIB6_BASE (AXIM_BASE + 0x07000UL) +#define AXIM_AMIB7_BASE (AXIM_BASE + 0x08000UL) +#define AXIM_AMIB8_BASE (AXIM_BASE + 0x09000UL) +#define AXIM_AMIB9_BASE (AXIM_BASE + 0x0A000UL) +#define AXIM_AMIB10_BASE (AXIM_BASE + 0x0B000UL) + +/*!< Unique device ID register base address */ +#define UID_BASE (0x08FFF800UL) + +/*!< Flash size data register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) + +/*!< Package data register base address */ +#define PACKAGE_BASE (0x08FFF80CUL) + +/* USB OTG registers base addresses */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_PFUNC_START (0x1FF1FD4CUL) +#define RSSLIB_SYS_FLASH_PFUNC_END (0x1FF1FD78UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0x1FF1FD4CUL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t Destination; /*!< OBKeys destination information where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + +/** + * @brief Prototype of RSSLIB Set Secure OB Function + * @detail This function configure a secure OB. + * @param OB address among following values: + * &(FLASH->WRPSRP), &(FLASH->HDPSRP) or &(FLASH->ROTSRP) + * @param OB mask (example 0x000000FF for updating WRP OB). + * @param OB value + * @param OB Pos: bit position of OB value. + * ObValue << ObPos must be aligned on ObMask. + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetSecOB_TypeDef)(uint32_t ObAddr, uint32_t ObMask, uint32_t ObValue, uint32_t ObPos); + +/** + * @brief Prototype of RSSLIB Get RSS Status Function + * @detail This function return RSS Status. + * Calling GetRssStatus is only relevant after calling + * SetSecOB or DataProvisioning. + * @param none. + * @retval RSSLIB_SUCCESS on success, otherwise return an error 0xF5F5xxxx. + */ +typedef uint32_t (*RSSLIB_GetRssStatus_TypeDef)(void); + +/** + * @brief Prototype of RSSLIB Set Product State Function + * @detail This function change Product State. + * @param Requested Product State among following values: + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + * @retval RSSLIB_RSS_ERROR on error, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_SetProductState_TypeDef)(uint32_t ProductState); + +/** + * @brief Prototype of RSSLIB Get Product State Function + * @detail This function return current Product State. + * @param none. + * @retval RSSLIB_RSS_ERROR on error, + * otherwise return product state among following values: + * 0x39 : Open + * 0x17 : Provisioning + * 0x72 : Closed + * 0x5C : Locked + */ +typedef uint32_t (*RSSLIB_GetProductState_TypeDef)(void); + + +/** + * @brief RSSLib callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_SetSecOB_TypeDef SetSecOB; + uint32_t RESERVED1[4]; + __IM RSSLIB_GetRssStatus_TypeDef GetRssStatus; + __IM RSSLIB_SetProductState_TypeDef SetProductState; + __IM RSSLIB_DataProvisioning_TypeDef DataProvisioning; + __IM RSSLIB_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_GetProductState_TypeDef GetProductState; +} RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H7RSxx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H7RSxx_Peripheral_declaration + * @{ + */ + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) +#define ADF1 ((MDF_TypeDef *) ADF1_BASE) +#define ADF1_Filter0 ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE) +#define AXIM_AMIB_1 ((AXIM_AMIB_TypeDef *) AXIM_AMIB1_BASE ) +#define AXIM_AMIB_2 ((AXIM_AMIB_TypeDef *) AXIM_AMIB2_BASE ) +#define AXIM_AMIB_3 ((AXIM_AMIB_TypeDef *) AXIM_AMIB3_BASE ) +#define AXIM_AMIB_4 ((AXIM_AMIB_TypeDef *) AXIM_AMIB4_BASE ) +#define AXIM_AMIB_5 ((AXIM_AMIB_TypeDef *) AXIM_AMIB5_BASE ) +#define AXIM_AMIB_6 ((AXIM_AMIB_TypeDef *) AXIM_AMIB6_BASE ) +#define AXIM_AMIB_7 ((AXIM_AMIB_TypeDef *) AXIM_AMIB7_BASE ) +#define AXIM_AMIB_8 ((AXIM_AMIB_TypeDef *) AXIM_AMIB8_BASE ) +#define AXIM_AMIB_9 ((AXIM_AMIB_TypeDef *) AXIM_AMIB9_BASE ) +#define AXIM_AMIB_10 ((AXIM_AMIB_TypeDef *) AXIM_AMIB10_BASE) +#define AXIM_ASIB_1 ((AXIM_ASIB_TypeDef *) AXIM_ASIB1_BASE ) +#define AXIM_ASIB_2 ((AXIM_ASIB_TypeDef *) AXIM_ASIB2_BASE ) +#define AXIM_ASIB_3 ((AXIM_ASIB_TypeDef *) AXIM_ASIB3_BASE ) +#define AXIM_ASIB_4 ((AXIM_ASIB_TypeDef *) AXIM_ASIB4_BASE ) +#define AXIM_ASIB_5 ((AXIM_ASIB_TypeDef *) AXIM_ASIB5_BASE ) +#define AXIM_ASIB_6 ((AXIM_ASIB_TypeDef *) AXIM_ASIB6_BASE ) +#define AXIM_ASIB_7 ((AXIM_ASIB_TypeDef *) AXIM_ASIB7_BASE ) +#define AXIM_ASIB_8 ((AXIM_ASIB_TypeDef *) AXIM_ASIB8_BASE ) +#define AXIM_ASIB_9 ((AXIM_ASIB_TypeDef *) AXIM_ASIB9_BASE ) +#define AXIM_ASIB_10 ((AXIM_ASIB_TypeDef *) AXIM_ASIB10_BASE) +#define AXIM_ASIB_11 ((AXIM_ASIB_TypeDef *) AXIM_ASIB11_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define CRYP ((CRYP_TypeDef *) CRYP_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define DCMIPP ((DCMIPP_TypeDef *) DCMIPP_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define GFXTIM ((GFXTIM_TypeDef *) GFXTIM_BASE) +#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE) +#define GPDMA1 ((DMA_TypeDef *) GPDMA1_BASE) +#define GPDMA1_Channel0 ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE) +#define GPDMA1_Channel1 ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE) +#define GPDMA1_Channel2 ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE) +#define GPDMA1_Channel3 ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE) +#define GPDMA1_Channel4 ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE) +#define GPDMA1_Channel5 ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE) +#define GPDMA1_Channel6 ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE) +#define GPDMA1_Channel7 ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE) +#define GPDMA1_Channel8 ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE) +#define GPDMA1_Channel9 ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE) +#define GPDMA1_Channel10 ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE) +#define GPDMA1_Channel11 ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE) +#define GPDMA1_Channel12 ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE) +#define GPDMA1_Channel13 ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE) +#define GPDMA1_Channel14 ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE) +#define GPDMA1_Channel15 ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) +#define GPION ((GPIO_TypeDef *) GPION_BASE) +#define GPIOO ((GPIO_TypeDef *) GPIOO_BASE) +#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE) +#define HASH ((HASH_TypeDef *) HASH_BASE) +#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) +#define HPDMA1 ((DMA_TypeDef *) HPDMA1_BASE) +#define HPDMA1_Channel0 ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE) +#define HPDMA1_Channel1 ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE) +#define HPDMA1_Channel2 ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE) +#define HPDMA1_Channel3 ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE) +#define HPDMA1_Channel4 ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE) +#define HPDMA1_Channel5 ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE) +#define HPDMA1_Channel6 ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE) +#define HPDMA1_Channel7 ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE) +#define HPDMA1_Channel8 ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE) +#define HPDMA1_Channel9 ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE) +#define HPDMA1_Channel10 ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE) +#define HPDMA1_Channel11 ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE) +#define HPDMA1_Channel12 ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE) +#define HPDMA1_Channel13 ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE) +#define HPDMA1_Channel14 ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE) +#define HPDMA1_Channel15 ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE) +#define JPEG ((JPEG_TypeDef *) JPEG_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I3C1 ((I3C_TypeDef *) I3C1_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define MCE1 ((MCE_TypeDef *) MCE1_BASE) +#define MCE1_REGION1 ((MCE_Region_TypeDef *) MCE1_REGION1_BASE) +#define MCE1_REGION2 ((MCE_Region_TypeDef *) MCE1_REGION2_BASE) +#define MCE1_REGION3 ((MCE_Region_TypeDef *) MCE1_REGION3_BASE) +#define MCE1_REGION4 ((MCE_Region_TypeDef *) MCE1_REGION4_BASE) +#define MCE1_CONTEXT1 ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE) +#define MCE1_CONTEXT2 ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE) +#define MCE2 ((MCE_TypeDef *) MCE2_BASE) +#define MCE2_REGION1 ((MCE_Region_TypeDef *) MCE2_REGION1_BASE) +#define MCE2_REGION2 ((MCE_Region_TypeDef *) MCE2_REGION2_BASE) +#define MCE2_REGION3 ((MCE_Region_TypeDef *) MCE2_REGION3_BASE) +#define MCE2_REGION4 ((MCE_Region_TypeDef *) MCE2_REGION4_BASE) +#define MCE3 ((MCE_TypeDef *) MCE3_BASE) +#define MCE3_REGION1 ((MCE_Region_TypeDef *) MCE3_REGION1_BASE) +#define MCE3_REGION2 ((MCE_Region_TypeDef *) MCE3_REGION2_BASE) +#define MCE3_REGION3 ((MCE_Region_TypeDef *) MCE3_REGION3_BASE) +#define MCE3_REGION4 ((MCE_Region_TypeDef *) MCE3_REGION4_BASE) +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) +#define PKA ((PKA_TypeDef *) PKA_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC1_Monitor0 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor0_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define SAES ((SAES_TypeDef *) SAES_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *) SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *) SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *) SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *) SAI2_Block_B_BASE) +#define SBS ((SBS_TypeDef *) SBS_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define XSPI1 ((XSPI_TypeDef *) XSPI1_R_BASE) +#define XSPI2 ((XSPI_TypeDef *) XSPI2_R_BASE) +#define XSPIM ((XSPIM_TypeDef *) XSPIM_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) + +/** @} */ /* End of group STM32H7RSxx_Peripheral_declaration */ + +/** @addtogroup STM32H7RSxx_Peripheral_Exported_constants + * @{ + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + +/** @addtogroup STM32H7RSxx_Peripheral_Registers_Bits_Definition + * @{ + */ +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G4 series) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_ADFCFG_Pos (2U) +#define ADC_CFGR_ADFCFG_Msk (0x1UL << ADC_CFGR_ADFCFG_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_ADFCFG ADC_CFGR_ADFCFG_Msk /*!< ADC ADF transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register ***************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal path to VDDCORE */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ + +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************************************************************************/ +/* */ +/* AXIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AXIM_ASIB_FNMOD2 register **********/ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_ASIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD2_BYPASS_MERGE AXIM_ASIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_ASIB_READQOS register ********/ +#define AXIM_ASIB_READQOS_AR_QOS_Pos (0U) +#define AXIM_ASIB_READQOS_AR_QOS_Msk (0xFUL << AXIM_ASIB_READQOS_AR_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_READQOS_AR_QOS AXIM_ASIB_READQOS_AR_QOS_Msk /*!< Read channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_WRITEQOS register *******/ +#define AXIM_ASIB_WRITEQOS_AW_QOS_Pos (0U) +#define AXIM_ASIB_WRITEQOS_AW_QOS_Msk (0xFUL << AXIM_ASIB_WRITEQOS_AW_QOS_Pos) /*!< 0x0000000F */ +#define AXIM_ASIB_WRITEQOS_AW_QOS AXIM_ASIB_WRITEQOS_AW_QOS_Msk /*!< Write channel QoS setting */ + +/******************* Bit definition for AXIM_ASIB_FNMOD register **********/ +#define AXIM_ASIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_ASIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_ASIB_FNMOD_READ_ISS AXIM_ASIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_ASIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_ASIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_ASIB_FNMOD_WRITE_ISS AXIM_ASIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMODBMISS register **********/ +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMODBMISS_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODBMISS_READ_ISS AXIM_AMIB_FNMODBMISS_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMODBMISS_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMODBMISS_WRITE_ISS AXIM_AMIB_FNMODBMISS_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************* Bit definition for AXIM_AMIB_FNMOD2 register **********/ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos (0U) +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk (0x1UL << AXIM_AMIB_FNMOD2_BYPASS_MERGE_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD2_BYPASS_MERGE AXIM_AMIB_FNMOD2_BYPASS_MERGE_Msk /*!< Bypass Merge enable */ + +/******************* Bit definition for AXIM_AMIB_FNMODLB register **********/ +#define AXIM_AMIB_FNMODLB_LONG_BURST_Pos (0U) +#define AXIM_AMIB_FNMODLB_LONG_BURST_Msk (0x1UL << AXIM_AMIB_FNMODLB_LONG_BURST_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMODLB_LONG_BURST AXIM_AMIB_FNMODLB_LONG_BURST_Msk /*!< Long bursts can be generated */ + +/******************* Bit definition for AXIM_AMIB_FNMOD register **********/ +#define AXIM_AMIB_FNMOD_READ_ISS_Pos (0U) +#define AXIM_AMIB_FNMOD_READ_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_READ_ISS_Pos) /*!< 0x00000001 */ +#define AXIM_AMIB_FNMOD_READ_ISS AXIM_AMIB_FNMOD_READ_ISS_Msk /*!< Force read issuing capability to 1 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS_Pos (1U) +#define AXIM_AMIB_FNMOD_WRITE_ISS_Msk (0x1UL << AXIM_AMIB_FNMOD_WRITE_ISS_Pos) /*!< 0x00000002 */ +#define AXIM_AMIB_FNMOD_WRITE_ISS AXIM_AMIB_FNMOD_WRITE_ISS_Msk /*!< Force write issuing capability to 1 */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Parallel Synchronous Slave Interface (PSSI ) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PSSI_CR register *******************/ +#define PSSI_CR_CKPOL_Pos (5U) +#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */ +#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */ +#define PSSI_CR_DEPOL_Pos (6U) +#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */ +#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */ +#define PSSI_CR_RDYPOL_Pos (8U) +#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */ +#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */ +#define PSSI_CR_EDM_Pos (10U) +#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */ +#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */ +#define PSSI_CR_ENABLE_Pos (14U) +#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */ +#define PSSI_CR_DERDYCFG_Pos (18U) +#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */ +#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */ +#define PSSI_CR_CKSRC_Pos (29U) +#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */ +#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */ +#define PSSI_CR_DMAEN_Pos (30U) +#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */ +#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */ +#define PSSI_CR_OUTEN_Pos (31U) +#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */ +#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */ + +/******************** Bit definition for PSSI_SR register *******************/ +#define PSSI_SR_RTT4B_Pos (2U) +#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */ +#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */ +#define PSSI_SR_RTT1B_Pos (3U) +#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */ +#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */ + +/******************** Bit definition for PSSI_RIS register ******************/ +#define PSSI_RIS_OVR_RIS_Pos (1U) +#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */ + +/******************** Bit definition for PSSI_IER register ******************/ +#define PSSI_IER_OVR_IE_Pos (1U) +#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */ + +/******************** Bit definition for PSSI_MIS register ******************/ +#define PSSI_MIS_OVR_MIS_Pos (1U) +#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */ + +/******************** Bit definition for PSSI_ICR register ******************/ +#define PSSI_ICR_OVR_ISC_Pos (1U) +#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */ + +/******************** Bit definition for PSSI_DR register *******************/ +#define PSSI_DR_DR_Pos (0U) +#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */ +#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_SVOS_Pos (0U) +#define PWR_CR1_SVOS_Msk (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection. */ + +#define PWR_CR1_PVDE_Pos (4U) +#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Programmable Voltage detector enable. */ + +#define PWR_CR1_PLS_Pos (5U) +#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */ +#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */ +#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */ +#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */ +#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */ + +#define PWR_CR1_DBP_Pos (8U) +#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ +#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */ + +#define PWR_CR1_FLPS_Pos (9U) +#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */ +#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in STOP */ + +#define PWR_CR1_BOOSTE_Pos (11U) +#define PWR_CR1_BOOSTE_Msk (0x1UL << PWR_CR1_BOOSTE_Pos) /*!< 0x00000800 */ +#define PWR_CR1_BOOSTE PWR_CR1_BOOSTE_Msk /*!< Analog Switch VBoost control. */ + +#define PWR_CR1_AVDREADY_Pos (12) +#define PWR_CR1_AVDREADY_Msk (0x1UL << PWR_CR1_AVDREADY_Pos) /*!< 0x00001000 */ +#define PWR_CR1_AVDREADY PWR_CR1_AVDREADY_Msk /*!< Analog Voltage Ready. */ + +#define PWR_CR1_AVDEN_Pos (13U) +#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00002000 */ +#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */ + +#define PWR_CR1_ALS_Pos (14U) +#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x0000A000 */ +#define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */ +#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00004000 */ +#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_SR1 register ********************/ +#define PWR_SR1_ACTVOS_Pos (0U) +#define PWR_SR1_ACTVOS_Msk (0x1UL << PWR_SR1_ACTVOS_Pos) /*!< 0x00000001 */ +#define PWR_SR1_ACTVOS PWR_SR1_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */ + +#define PWR_SR1_ACTVOSRDY_Pos (1U) +#define PWR_SR1_ACTVOSRDY_Msk (0x1UL << PWR_SR1_ACTVOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_SR1_ACTVOSRDY PWR_SR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */ + +#define PWR_SR1_PVDO_Pos (4U) +#define PWR_SR1_PVDO_Msk (0x1UL << PWR_SR1_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SR1_PVDO PWR_SR1_PVDO_Msk /*!< Programmable Voltage Detect Output */ + +#define PWR_SR1_AVDO_Pos (13U) +#define PWR_SR1_AVDO_Msk (0x1UL << PWR_SR1_AVDO_Pos) /*!< 0x00002000 */ +#define PWR_SR1_AVDO PWR_SR1_AVDO_Msk /*!< Analog Voltage Detect Output on VDDA */ + +/******************** Bit definition for PWR_CSR1 register ********************/ +#define PWR_CSR1_BREN_Pos (0U) +#define PWR_CSR1_BREN_Msk (0x1UL << PWR_CSR1_BREN_Pos) /*!< 0x00000001 */ +#define PWR_CSR1_BREN PWR_CSR1_BREN_Msk /*!< Backup regulator enable */ + +#define PWR_CSR1_MONEN_Pos (4U) +#define PWR_CSR1_MONEN_Msk (0x1UL << PWR_CSR1_MONEN_Pos) /*!< 0x00000010 */ +#define PWR_CSR1_MONEN PWR_CSR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */ + +#define PWR_CSR1_BRRDY_Pos (16U) +#define PWR_CSR1_BRRDY_Msk (0x1UL << PWR_CSR1_BRRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR1_BRRDY PWR_CSR1_BRRDY_Msk /*!< Backup regulator ready */ + +#define PWR_CSR1_VBATL_Pos (20U) +#define PWR_CSR1_VBATL_Msk (0x1UL << PWR_CSR1_VBATL_Pos) /*!< 0x00100000 */ +#define PWR_CSR1_VBATL PWR_CSR1_VBATL_Msk /*!< Monitored VBAT level above low threshold */ + +#define PWR_CSR1_VBATH_Pos (21U) +#define PWR_CSR1_VBATH_Msk (0x1UL << PWR_CSR1_VBATH_Pos) /*!< 0x00200000 */ +#define PWR_CSR1_VBATH PWR_CSR1_VBATH_Msk /*!< Monitored VBAT level above high threshold */ + +#define PWR_CSR1_TEMPL_Pos (22U) +#define PWR_CSR1_TEMPL_Msk (0x1UL << PWR_CSR1_TEMPL_Pos) /*!< 0x00400000 */ +#define PWR_CSR1_TEMPL PWR_CSR1_TEMPL_Msk /*!< Monitored temperature level above low threshold */ + +#define PWR_CSR1_TEMPH_Pos (23U) +#define PWR_CSR1_TEMPH_Msk (0x1UL << PWR_CSR1_TEMPH_Pos) /*!< 0x00800000 */ +#define PWR_CSR1_TEMPH PWR_CSR1_TEMPH_Msk /*!< Monitored temperature level above high threshold */ + +/******************** Bit definition for PWR_CSR2 register ********************/ +#define PWR_CSR2_BYPASS_Pos (0U) +#define PWR_CSR2_BYPASS_Msk (0x1UL << PWR_CSR2_BYPASS_Pos) /*!< 0x00000001 */ +#define PWR_CSR2_BYPASS PWR_CSR2_BYPASS_Msk /*!< Power Management Unit bypass */ + +#define PWR_CSR2_LDOEN_Pos (1U) +#define PWR_CSR2_LDOEN_Msk (0x1UL << PWR_CSR2_LDOEN_Pos) /*!< 0x00000002 */ +#define PWR_CSR2_LDOEN PWR_CSR2_LDOEN_Msk /*!< Low Drop-Out regulator enable */ + +#define PWR_CSR2_SDEN_Pos (2U) +#define PWR_CSR2_SDEN_Msk (0x1UL << PWR_CSR2_SDEN_Pos) /*!< 0x00000004 */ +#define PWR_CSR2_SDEN PWR_CSR2_SDEN_Msk /*!< SMPS Step-down converter enable */ + +#define PWR_CSR2_SMPSEXTHP_Pos (3U) +#define PWR_CSR2_SMPSEXTHP_Msk (0x1UL << PWR_CSR2_SMPSEXTHP_Pos) /*!< 0x00000008 */ +#define PWR_CSR2_SMPSEXTHP PWR_CSR2_SMPSEXTHP_Msk /*!< SMPS external power delivery selection */ + +#define PWR_CSR2_SDHILEVEL_Pos (4U) +#define PWR_CSR2_SDHILEVEL_Msk (0x1UL << PWR_CSR2_SDHILEVEL_Pos) /*!< 0x00000030 */ +#define PWR_CSR2_SDHILEVEL PWR_CSR2_SDHILEVEL_Msk /*!< SMPS step-down converter voltage output for LDO or external supply */ + +#define PWR_CSR2_VBE_Pos (8U) +#define PWR_CSR2_VBE_Msk (0x1UL << PWR_CSR2_VBE_Pos) /*!< 0x00000100 */ +#define PWR_CSR2_VBE PWR_CSR2_VBE_Msk /*!< VBAT charging enable */ + +#define PWR_CSR2_VBRS_Pos (9U) +#define PWR_CSR2_VBRS_Msk (0x1UL << PWR_CSR2_VBRS_Pos) /*!< 0x00000200 */ +#define PWR_CSR2_VBRS PWR_CSR2_VBRS_Msk /*!< VBAT charging resistor selection */ + +#define PWR_CSR2_XSPICAP1_Pos (10U) +#define PWR_CSR2_XSPICAP1_Msk (0x3UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000C00 */ +#define PWR_CSR2_XSPICAP1 PWR_CSR2_XSPICAP1_Msk /*!< XSPI port 1 capacitor control bits */ +#define PWR_CSR2_XSPICAP1_0 (0x1UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000400 */ +#define PWR_CSR2_XSPICAP1_1 (0x2UL << PWR_CSR2_XSPICAP1_Pos) /*!< 0x00000800 */ + +#define PWR_CSR2_XSPICAP2_Pos (12U) +#define PWR_CSR2_XSPICAP2_Msk (0x3UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00003000 */ +#define PWR_CSR2_XSPICAP2 PWR_CSR2_XSPICAP2_Msk /*!< XSPI port 2 capacitor control bits */ +#define PWR_CSR2_XSPICAP2_0 (0x1UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00001000 */ +#define PWR_CSR2_XSPICAP2_1 (0x2UL << PWR_CSR2_XSPICAP2_Pos) /*!< 0x00002000 */ + +#define PWR_CSR2_EN_XSPIM1_Pos (14U) +#define PWR_CSR2_EN_XSPIM1_Msk (0x1UL << PWR_CSR2_EN_XSPIM1_Pos) /*!< 0x00004000 */ +#define PWR_CSR2_EN_XSPIM1 PWR_CSR2_EN_XSPIM1_Msk /*!< XSPIM1 external supply enable */ + +#define PWR_CSR2_EN_XSPIM2_Pos (15U) +#define PWR_CSR2_EN_XSPIM2_Msk (0x1UL << PWR_CSR2_EN_XSPIM2_Pos) /*!< 0x00008000 */ +#define PWR_CSR2_EN_XSPIM2 PWR_CSR2_EN_XSPIM2_Msk /*!< XSPIM2 external supply enable */ + +#define PWR_CSR2_SDEXTRDY_Pos (16U) +#define PWR_CSR2_SDEXTRDY_Msk (0x1UL << PWR_CSR2_SDEXTRDY_Pos) /*!< 0x00010000 */ +#define PWR_CSR2_SDEXTRDY PWR_CSR2_SDEXTRDY_Msk /*!< SMPS External supply ready */ + +#define PWR_CSR2_USB33DEN_Pos (24U) +#define PWR_CSR2_USB33DEN_Msk (0x1UL << PWR_CSR2_USB33DEN_Pos) /*!< 0x01000000 */ +#define PWR_CSR2_USB33DEN PWR_CSR2_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */ + +#define PWR_CSR2_USBREGEN_Pos (25U) +#define PWR_CSR2_USBREGEN_Msk (0x1UL << PWR_CSR2_USBREGEN_Pos) /*!< 0x02000000 */ +#define PWR_CSR2_USBREGEN PWR_CSR2_USBREGEN_Msk /*!< USB regulator enable */ + +#define PWR_CSR2_USB33RDY_Pos (26U) +#define PWR_CSR2_USB33RDY_Msk (0x1UL << PWR_CSR2_USB33RDY_Pos) /*!< 0x04000000 */ +#define PWR_CSR2_USB33RDY PWR_CSR2_USB33RDY_Msk /*!< USB supply ready */ + +#define PWR_CSR2_USBHSREGEN_Pos (27U) +#define PWR_CSR2_USBHSREGEN_Msk (0x1UL << PWR_CSR2_USBHSREGEN_Pos) /*!< 0x08000000 */ +#define PWR_CSR2_USBHSREGEN PWR_CSR2_USBHSREGEN_Msk /*!< USB HS regulator enable */ + +/******************** Bit definition for PWR_CSR3 register ********************/ +#define PWR_CSR3_PDDS_Pos (0U) +#define PWR_CSR3_PDDS_Msk (0x1UL << PWR_CSR3_PDDS_Pos) /*!< 0x00000001 */ +#define PWR_CSR3_PDDS PWR_CSR3_PDDS_Msk /*!< D1 domain Power Down Deepsleep */ + +#define PWR_CSR3_CSSF_Pos (1U) +#define PWR_CSR3_CSSF_Msk (0x1UL << PWR_CSR3_CSSF_Pos) /*!< 0x00000002 */ +#define PWR_CSR3_CSSF PWR_CSR3_CSSF_Msk /*!< Clear Standby and Stop flag */ + +#define PWR_CSR3_STOPF_Pos (8U) +#define PWR_CSR3_STOPF_Msk (0x1UL << PWR_CSR3_STOPF_Pos) /*!< 0x00000080 */ +#define PWR_CSR3_STOPF PWR_CSR3_STOPF_Msk /*!< STOP Flag */ + +#define PWR_CSR3_SBF_Pos (9U) +#define PWR_CSR3_SBF_Msk (0x1UL << PWR_CSR3_SBF_Pos) /*!< 0x00000100 */ +#define PWR_CSR3_SBF PWR_CSR3_SBF_Msk /*!< System STANDBY Flag */ + +/******************** Bit definition for PWR_CSR4 register ********************/ +#define PWR_CSR4_VOS_Pos (0U) +#define PWR_CSR4_VOS_Msk (0x1UL << PWR_CSR4_VOS_Pos) /*!< 0x00000001 */ +#define PWR_CSR4_VOS PWR_CSR4_VOS_Msk /*!< Voltage Scaling selection according performance */ + +#define PWR_CSR4_VOSRDY_Pos (1U) +#define PWR_CSR4_VOSRDY_Msk (0x1UL << PWR_CSR4_VOSRDY_Pos) /*!< 0x00000002 */ +#define PWR_CSR4_VOSRDY PWR_CSR4_VOSRDY_Msk /*!< VOSRDY: VOS Ready bit for VCORE voltage scaling output selection. */ + +/******************** Bit definition for PWR_WKUPCR register ********************/ +#define PWR_WKUPCR_WKUPC_Pos (0U) +#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */ +#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Pin Flag 1 to 4 */ +#define PWR_WKUPCR_WKUPC1_Pos (0U) +#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */ +#define PWR_WKUPCR_WKUPC2_Pos (1U) +#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */ +#define PWR_WKUPCR_WKUPC3_Pos (2U) +#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */ +#define PWR_WKUPCR_WKUPC4_Pos (3U) +#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPFR register ********************/ +#define PWR_WKUPFR_WKUPF1_Pos (0U) +#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */ +#define PWR_WKUPFR_WKUPF2_Pos (1U) +#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */ +#define PWR_WKUPFR_WKUPF3_Pos (2U) +#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */ +#define PWR_WKUPFR_WKUPF4_Pos (3U) +#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */ + +/******************** Bit definition for PWR_WKUPEPR register ********************/ +#define PWR_WKUPEPR_WKUPEN_Pos (0U) +#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000000F */ +#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */ +#define PWR_WKUPEPR_WKUPEN1_Pos (0U) +#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */ +#define PWR_WKUPEPR_WKUPEN2_Pos (1U) +#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */ +#define PWR_WKUPEPR_WKUPEN3_Pos (2U) +#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */ +#define PWR_WKUPEPR_WKUPEN4_Pos (3U) +#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */ + +#define PWR_WKUPEPR_WKUPP_Pos (8U) +#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000F00 */ +#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */ +#define PWR_WKUPEPR_WKUPP1_Pos (8U) +#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */ +#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */ +#define PWR_WKUPEPR_WKUPP2_Pos (9U) +#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */ +#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */ +#define PWR_WKUPEPR_WKUPP3_Pos (10U) +#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */ +#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */ +#define PWR_WKUPEPR_WKUPP4_Pos (11U) +#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */ +#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */ + +#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U) +#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */ +#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */ +#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */ +#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */ +#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U) +#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */ +#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */ +#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */ +#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */ +#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U) +#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */ +#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */ +#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */ +#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */ +#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U) +#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */ +#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */ +#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */ +#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for PWR_UCPDRR register ********************/ +#define PWR_UCPDR_UCPD_DBDIS_Pos (0U) +#define PWR_UCPDR_UCPD_DBDIS_Msk (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos) /*!< 0x00000001 */ +#define PWR_UCPDR_UCPD_DBDIS PWR_UCPDR_UCPD_DBDIS_Msk /*!< UCPD dead battery disable */ + +#define PWR_UCPDR_UCPD_STBY_Pos (1U) +#define PWR_UCPDR_UCPD_STBY_Msk (0x1UL << PWR_UCPDR_UCPD_STBY_Pos) /*!< 0x00000002 */ +#define PWR_UCPDR_UCPD_STBY PWR_UCPDR_UCPD_STBY_Msk /*!< UCPD Standby mode */ + +/******************** Bit definition for PWR_APCR register ********************/ +#define PWR_APCR_APC_Pos (0U) +#define PWR_APCR_APC_Msk (0x1UL << PWR_APCR_APC_Pos) /*!< 0x00000001 */ +#define PWR_APCR_APC PWR_APCR_APC_Msk /*!< Apply pull configuration register */ + +#define PWR_APCR_PN7_PUPD_Pos (16U) +#define PWR_APCR_PN7_PUPD_Msk (0x1UL << PWR_APCR_PN7_PUPD_Pos) /*!< 0x00010000 */ +#define PWR_APCR_PN7_PUPD PWR_APCR_PN7_PUPD_Msk /*!< Port N bit 7 pull-up/down configuration */ + +#define PWR_APCR_PO5_PUPD_Pos (17) +#define PWR_APCR_PO5_PUPD_Msk (0x1UL << PWR_APCR_PO5_PUPD_Pos) /*!< 0x00020000 */ +#define PWR_APCR_PO5_PUPD PWR_APCR_PO5_PUPD_Msk /*!< Port O bit 5 pull-up/down configuration */ + +#define PWR_APCR_I3CPB6_PU_Pos (28U) +#define PWR_APCR_I3CPB6_PU_Msk (0x1UL << PWR_APCR_I3CPB6_PU_Pos) /*!< 0x10000000 */ +#define PWR_APCR_I3CPB6_PU PWR_APCR_I3CPB6_PU_Msk /*!< Port PB6 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB7_PU_Pos (29U) +#define PWR_APCR_I3CPB7_PU_Msk (0x1UL << PWR_APCR_I3CPB7_PU_Pos) /*!< 0x20000000 */ +#define PWR_APCR_I3CPB7_PU PWR_APCR_I3CPB7_PU_Msk /*!< Port PB7 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB8_PU_Pos (30U) +#define PWR_APCR_I3CPB8_PU_Msk (0x1UL << PWR_APCR_I3CPB8_PU_Pos) /*!< 0x40000000 */ +#define PWR_APCR_I3CPB8_PU PWR_APCR_I3CPB8_PU_Msk /*!< Port PB8 I3C pull-up bit configuration */ + +#define PWR_APCR_I3CPB9_PU_Pos (31U) +#define PWR_APCR_I3CPB9_PU_Msk (0x1UL << PWR_APCR_I3CPB9_PU_Pos) /*!< 0x80000000 */ +#define PWR_APCR_I3CPB9_PU PWR_APCR_I3CPB9_PU_Msk /*!< Port PB9 I3C pull-up bit configuration */ + +/******************** Bit definition for PWR_PUCRN register ********************/ +#define PWR_PUCRN_PUN1_Pos (1U) +#define PWR_PUCRN_PUN1_Msk (0x1UL << PWR_PUCRN_PUN1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRN_PUN1 PWR_PUCRN_PUN1_Msk /*!< PUN1: Port N pull-up */ + +#define PWR_PUCRN_PUN6_Pos (6U) +#define PWR_PUCRN_PUN6_Msk (0x1UL << PWR_PUCRN_PUN6_Pos) /*!< 0x00000040 */ +#define PWR_PUCRN_PUN6 PWR_PUCRN_PUN6_Msk /*!< PUN6: Port N pull-up */ + +#define PWR_PUCRN_PUN12_Pos (12U) +#define PWR_PUCRN_PUN12_Msk (0x1UL << PWR_PUCRN_PUN12_Pos) /*!< 0x00001000 */ +#define PWR_PUCRN_PUN12 PWR_PUCRN_PUN12_Msk /*!< PUN12: Port N pull-up */ + +/******************** Bit definition for PWR_PDCRN register ********************/ +#define PWR_PDCRN_PDN0_Pos (0U) +#define PWR_PDCRN_PDN0_Msk (0x1UL << PWR_PDCRN_PDN0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRN_PDN0 PWR_PDCRN_PDN0_Msk /*!< PDN0: Port N pull-down */ + +#define PWR_PDCRN_PDN1_Pos (1U) +#define PWR_PDCRN_PDN1_Msk (0x1UL << PWR_PDCRN_PDN1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRN_PDN1 PWR_PDCRN_PDN1_Msk /*!< PDN1: Port N pull-down */ + +#define PWR_PDCRN_PDN2N5_Pos (2U) +#define PWR_PDCRN_PDN2N5_Msk (0x1UL << PWR_PDCRN_PDN2N5_Pos) /*!< 0x00000004 */ +#define PWR_PDCRN_PDN2N5 PWR_PDCRN_PDN2N5_Msk /*!< PDN2 to PDN5: Port N pull-down */ + +#define PWR_PDCRN_PDN6_Pos (6U) +#define PWR_PDCRN_PDN6_Msk (0x1UL << PWR_PDCRN_PDN6_Pos) /*!< 0x00000040 */ +#define PWR_PDCRN_PDN6 PWR_PDCRN_PDN6_Msk /*!< PDN6: Port N pull-down */ + +#define PWR_PDCRN_PDN8N11_Pos (8U) +#define PWR_PDCRN_PDN8N11_Msk (0x1UL << PWR_PDCRN_PDN8N11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRN_PDN8N11 PWR_PDCRN_PDN8N11_Msk /*!< PDN8 to PDN11: Port N pull-down */ + +#define PWR_PDCRN_PDN12_Pos (12U) +#define PWR_PDCRN_PDN12_Msk (0x1UL << PWR_PDCRN_PDN12_Pos) /*!< 0x00001000 */ +#define PWR_PDCRN_PDN12 PWR_PDCRN_PDN12_Msk /*!< PDN12: Port N pull-down */ + +/******************** Bit definition for PWR_PUCRO register ********************/ +#define PWR_PUCRO_PUO0_Pos (0U) +#define PWR_PUCRO_PUO0_Msk (0x1UL << PWR_PUCRO_PUO0_Pos) /*!< 0x00000001 */ +#define PWR_PUCRO_PUO0 PWR_PUCRO_PUO0_Msk /*!< PUO0: Port O pull-up */ + +#define PWR_PUCRO_PUO1_Pos (1U) +#define PWR_PUCRO_PUO1_Msk (0x1UL << PWR_PUCRO_PUO1_Pos) /*!< 0x00000002 */ +#define PWR_PUCRO_PUO1 PWR_PUCRO_PUO1_Msk /*!< PUO1: Port O pull-up */ + +#define PWR_PUCRO_PUO4_Pos (4U) +#define PWR_PUCRO_PUO4_Msk (0x1UL << PWR_PUCRO_PUO4_Pos) /*!< 0x00000010 */ +#define PWR_PUCRO_PUO4 PWR_PUCRO_PUO4_Msk /*!< PUO4: Port O pull-up */ + +/******************** Bit definition for PWR_PDCRO register ********************/ +#define PWR_PDCRO_PDO0_Pos (0U) +#define PWR_PDCRO_PDO0_Msk (0x1UL << PWR_PDCRO_PDO0_Pos) /*!< 0x00000001 */ +#define PWR_PDCRO_PDO0 PWR_PDCRO_PDO0_Msk /*!< PDO0: Port O pull-down */ + +#define PWR_PDCRO_PDO1_Pos (1U) +#define PWR_PDCRO_PDO1_Msk (0x1UL << PWR_PDCRO_PDO1_Pos) /*!< 0x00000002 */ +#define PWR_PDCRO_PDO1 PWR_PDCRO_PDO1_Msk /*!< PDO1: Port O pull-down */ + +#define PWR_PDCRO_PDO2_Pos (2U) +#define PWR_PDCRO_PDO2_Msk (0x1UL << PWR_PDCRO_PDO2_Pos) /*!< 0x00000004 */ +#define PWR_PDCRO_PDO2 PWR_PDCRO_PDO2_Msk /*!< PDO2: Port O pull-down */ + +#define PWR_PDCRO_PDO3_Pos (3U) +#define PWR_PDCRO_PDO3_Msk (0x1UL << PWR_PDCRO_PDO3_Pos) /*!< 0x00000008 */ +#define PWR_PDCRO_PDO3 PWR_PDCRO_PDO3_Msk /*!< PDO3: Port O pull-down */ + +#define PWR_PDCRO_PDO4_Pos (4U) +#define PWR_PDCRO_PDO4_Msk (0x1UL << PWR_PDCRO_PDO4_Pos) /*!< 0x00000010 */ +#define PWR_PDCRO_PDO4 PWR_PDCRO_PDO4_Msk /*!< PDO4: Port O pull-down */ + +/******************** Bit definition for PWR_PDCRP register ********************/ +#define PWR_PDCRP_PDP0P3_Pos (0U) +#define PWR_PDCRP_PDP0P3_Msk (0x1UL << PWR_PDCRP_PDP0P3_Pos) /*!< 0x00000001 */ +#define PWR_PDCRP_PDP0P3 PWR_PDCRP_PDP0P3_Msk /*!< PPO0 to PP03 : Port P pull-down */ + +#define PWR_PDCRP_PDP4P7_Pos (4U) +#define PWR_PDCRP_PDP4P7_Msk (0x1UL << PWR_PDCRP_PDP4P7_Pos) /*!< 0x00000010 */ +#define PWR_PDCRP_PDP4P7 PWR_PDCRP_PDP4P7_Msk /*!< PPO4 to PP07 : Port P pull-down */ + +#define PWR_PDCRP_PDP8P11_Pos (8U) +#define PWR_PDCRP_PDP8P11_Msk (0x1UL << PWR_PDCRP_PDP8P11_Pos) /*!< 0x00000100 */ +#define PWR_PDCRP_PDP8P11 PWR_PDCRP_PDP8P11_Msk /*!< PPO8 to PP11 : Port P pull-down */ + +#define PWR_PDCRP_PDP12P15_Pos (12U) +#define PWR_PDCRP_PDP12P15_Msk (0x1UL << PWR_PDCRP_PDP12P15_Pos) /*!< 0x00001000 */ +#define PWR_PDCRP_PDP12P15 PWR_PDCRP_PDP12P15_Msk /*!< PP12 to PP15 : Port P pull-down */ + + +/******************************************************************************/ +/* */ +/* RAM ECC monitoring */ +/* */ +/******************************************************************************/ +/****************** Bit definition for RAMECC_IER register ******************/ +#define RAMECC_IER_GIE_Pos (0U) +#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */ +#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */ +#define RAMECC_IER_GECCSEIE_Pos (1U) +#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */ +#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */ +#define RAMECC_IER_GECCDEIE_Pos (2U) +#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */ +#define RAMECC_IER_GECCDEBWIE_Pos (3U) +#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */ +#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */ + +/******************* Bit definition for RAMECC_CR register ******************/ +#define RAMECC_CR_ECCSEIE_Pos (2U) +#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */ +#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */ +#define RAMECC_CR_ECCDEIE_Pos (3U) +#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */ +#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */ +#define RAMECC_CR_ECCDEBWIE_Pos (4U) +#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */ +#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */ +#define RAMECC_CR_ECCELEN_Pos (5U) +#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */ +#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */ + +/******************* Bit definition for RAMECC_SR register ******************/ +#define RAMECC_SR_SEDCF_Pos (0U) +#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */ +#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */ +#define RAMECC_SR_DEDF_Pos (1U) +#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */ +#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */ +#define RAMECC_SR_DEBWDF_Pos (2U) +#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */ +#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */ + +/****************** Bit definition for RAMECC_FAR register ******************/ +#define RAMECC_FAR_FADD_Pos (0U) +#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */ + +/****************** Bit definition for RAMECC_FDRL register *****************/ +#define RAMECC_FDRL_FDATAL_Pos (0U) +#define RAMECC_FDRL_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FDRL_FDATAL_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRL_FDATAL RAMECC_FDRL_FDATAL_Msk /*!< Failing data low */ + +/****************** Bit definition for RAMECC_FDRH register *****************/ +#define RAMECC_FDRH_FDATAH_Pos (0U) +#define RAMECC_FDRH_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FDRH_FDATAH_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FDRH_FDATAH RAMECC_FDRH_FDATAH_Msk /* Failing data high (64-bit memory) */ + +/***************** Bit definition for RAMECC_FECR register ******************/ +#define RAMECC_FECR_FEC_Pos (0U) +#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */ +#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (0U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIKERON_Pos (1U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable in Stop mode */ +#define RCC_CR_HSIRDY_Pos (2U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_Pos (3U) +#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */ +#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */ +#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */ +#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */ + +#define RCC_CR_HSIDIVF_Pos (5U) +#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */ +#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */ +#define RCC_CR_CSION_Pos (7U) +#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */ +#define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY_Pos (8U) +#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */ +#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON_Pos (9U) +#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable in Stop mode */ +#define RCC_CR_HSI48ON_Pos (12U) +#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */ +#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY_Pos (13U) +#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */ +#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP_Pos (18U) +#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ +#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock bypass */ +#define RCC_CR_HSEEXT_Pos (19U) +#define RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos) /*!< 0x00100000 */ +#define RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk /*!< External High Speed clock type in bypass mode */ +#define RCC_CR_HSECSSON_Pos (20U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< HSE Clock security System enable */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready flag */ +#define RCC_CR_PLL2ON_Pos (26U) +#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ +#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */ +#define RCC_CR_PLL2RDY_Pos (27U) +#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ +#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready flag */ +#define RCC_CR_PLL3ON_Pos (28U) +#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ +#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */ +#define RCC_CR_PLL3RDY_Pos (29U) +#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ +#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready flag */ + +/******************** Bit definition for RCC_HSICFGR register ***************/ +/*!< HSICAL configuration */ +#define RCC_HSICFGR_HSICAL_Pos (0U) +#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */ + +/*!< HSITRIM configuration */ +#define RCC_HSICFGR_HSITRIM_Pos (24U) +#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */ +#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ +#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */ +#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CRRCR register *****************/ +/*!< HSI48CAL configuration */ +#define RCC_CRRCR_HSI48CAL_Pos (0U) +#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */ +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */ +#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */ +#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */ +#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */ +#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */ +#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */ +#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */ +#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */ +#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */ +#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */ +#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */ + +/******************** Bit definition for RCC_CSICFGR register ***************/ +/*!< CSICAL configuration */ +#define RCC_CSICFGR_CSICAL_Pos (0U) +#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */ +#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */ +#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */ +#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */ +#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */ +#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */ +#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */ +#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */ +#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */ +#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */ + +/*!< CSITRIM configuration */ +#define RCC_CSICFGR_CSITRIM_Pos (24U) +#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */ +#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */ +#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */ +#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */ +#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */ +#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */ +#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */ +#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CFGR register ******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW_Pos (0U) +#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */ +#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock switch) */ +#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_Pos (3U) +#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */ +#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System clock switch status) */ +#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ +#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ + +#define RCC_CFGR_STOPWUCK_Pos (6U) +#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */ +#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK_Pos (7U) +#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */ +#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from Stop */ + +/*!< RTCPRE configuration */ +#define RCC_CFGR_RTCPRE_Pos (8U) +#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00003F00 */ +#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< RTCPRE[5:0] bits (HSE division factor for RTC clock) */ +#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */ +#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */ +#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */ +#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */ +#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */ +#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */ + +#define RCC_CFGR_TIMPRE_Pos (15U) +#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos) /*!< 0x00008000 */ +#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< TIMPRE configuration */ + +#define RCC_CFGR_MCO1PRE_Pos (18U) +#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x003C0000 */ +#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< MCO1 configuration */ +#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */ +#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */ + +#define RCC_CFGR_MCO1SEL_Pos (22U) +#define RCC_CFGR_MCO1SEL_Msk (0x7UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01C00000 */ +#define RCC_CFGR_MCO1SEL RCC_CFGR_MCO1SEL_Msk /*!< MCO1SEL [2:0] bits (MCO1 clock output selection) */ +#define RCC_CFGR_MCO1SEL_0 (0x1UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00400000 */ +#define RCC_CFGR_MCO1SEL_1 (0x2UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_MCO1SEL_2 (0x4UL << RCC_CFGR_MCO1SEL_Pos) /*!< 0x01000000 */ + +#define RCC_CFGR_MCO2PRE_Pos (25U) +#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x1E000000 */ +#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO2 configuration */ +#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */ +#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */ +#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ +#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ + +#define RCC_CFGR_MCO2SEL_Pos (29U) +#define RCC_CFGR_MCO2SEL_Msk (0x7UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0xE0000000 */ +#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [2:0] bits (MCO2 clock output selection) */ +#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x20000000 */ +#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x40000000 */ +#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for RCC_CDCFGR register ****************/ +/*!< CPRE configuration */ +#define RCC_CDCFGR_CPRE_Pos (0U) +#define RCC_CDCFGR_CPRE_Msk (0xFUL << RCC_CDCFGR_CPRE_Pos) /*!< 0x0000000F */ +#define RCC_CDCFGR_CPRE RCC_CDCFGR_CPRE_Msk /*!< CPRE[3:0] bits */ +#define RCC_CDCFGR_CPRE_0 (0x1UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000001 */ +#define RCC_CDCFGR_CPRE_1 (0x2UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000002 */ +#define RCC_CDCFGR_CPRE_2 (0x4UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000004 */ +#define RCC_CDCFGR_CPRE_3 (0x8UL << RCC_CDCFGR_CPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_BMCFGR register ****************/ +/*!< BMPRE configuration */ +#define RCC_BMCFGR_BMPRE_Pos (0U) +#define RCC_BMCFGR_BMPRE_Msk (0xFUL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x0000000F */ +#define RCC_BMCFGR_BMPRE RCC_BMCFGR_BMPRE_Msk /*!< BMPRE[3:0] bits */ +#define RCC_BMCFGR_BMPRE_0 (0x1UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000001 */ +#define RCC_BMCFGR_BMPRE_1 (0x2UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000002 */ +#define RCC_BMCFGR_BMPRE_2 (0x4UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000004 */ +#define RCC_BMCFGR_BMPRE_3 (0x8UL << RCC_BMCFGR_BMPRE_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for RCC_APBCFGR register ***************/ +/*!< APB1 prescaler configuration */ +#define RCC_APBCFGR_PPRE1_Pos (0U) +#define RCC_APBCFGR_PPRE1_Msk (0x7UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000007 */ +#define RCC_APBCFGR_PPRE1 RCC_APBCFGR_PPRE1_Msk /*!< PPRE1[2:0] bits */ +#define RCC_APBCFGR_PPRE1_0 (0x1UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000001 */ +#define RCC_APBCFGR_PPRE1_1 (0x2UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000002 */ +#define RCC_APBCFGR_PPRE1_2 (0x4UL << RCC_APBCFGR_PPRE1_Pos) /*!< 0x00000004 */ + +/*!< APB2 prescaler configuration */ +#define RCC_APBCFGR_PPRE2_Pos (4U) +#define RCC_APBCFGR_PPRE2_Msk (0x7UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000070 */ +#define RCC_APBCFGR_PPRE2 RCC_APBCFGR_PPRE2_Msk /*!< PPRE2[2:0] bits */ +#define RCC_APBCFGR_PPRE2_0 (0x1UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000010 */ +#define RCC_APBCFGR_PPRE2_1 (0x2UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000020 */ +#define RCC_APBCFGR_PPRE2_2 (0x4UL << RCC_APBCFGR_PPRE2_Pos) /*!< 0x00000040 */ + +/*!< APB4 prescaler configuration */ +#define RCC_APBCFGR_PPRE4_Pos (8U) +#define RCC_APBCFGR_PPRE4_Msk (0x7UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000700 */ +#define RCC_APBCFGR_PPRE4 RCC_APBCFGR_PPRE4_Msk /*!< PPRE4[2:0] bits */ +#define RCC_APBCFGR_PPRE4_0 (0x1UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000100 */ +#define RCC_APBCFGR_PPRE4_1 (0x2UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000200 */ +#define RCC_APBCFGR_PPRE4_2 (0x4UL << RCC_APBCFGR_PPRE4_Pos) /*!< 0x00000400 */ + +/*!< APB5 prescaler configuration */ +#define RCC_APBCFGR_PPRE5_Pos (12U) +#define RCC_APBCFGR_PPRE5_Msk (0x7UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00007000 */ +#define RCC_APBCFGR_PPRE5 RCC_APBCFGR_PPRE5_Msk /*!< PPRE5[2:0] bits */ +#define RCC_APBCFGR_PPRE5_0 (0x1UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00001000 */ +#define RCC_APBCFGR_PPRE5_1 (0x2UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00002000 */ +#define RCC_APBCFGR_PPRE5_2 (0x4UL << RCC_APBCFGR_PPRE5_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_PLLCKSELR register *************/ +#define RCC_PLLCKSELR_PLLSRC_Pos (0U) +#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ +#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk /*!< DIVMx and PLLs clock source selection */ +#define RCC_PLLCKSELR_PLLSRC_0 (0x01UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_PLLSRC_1 (0x02UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000020 */ + +#define RCC_PLLCKSELR_DIVM1_Pos (4U) +#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */ +#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk /*!< DIVM1[5:0] bits */ +#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */ +#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */ +#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */ +#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */ +#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */ +#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */ + +#define RCC_PLLCKSELR_DIVM2_Pos (12U) +#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */ +#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk /*!< DIVM2[5:0] bits */ +#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */ +#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */ +#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */ +#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */ +#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */ +#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */ + +#define RCC_PLLCKSELR_DIVM3_Pos (20U) +#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */ +#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk /*!< DIVM3[5:0] bits */ +#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */ +#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */ +#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */ +#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */ +#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */ +#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_PLLCFGR register ***************/ +#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U) +#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */ +#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk /*!< PLL1 fractional latch enable */ +#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U) +#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */ +#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk /*!< PLL1 VCO selection */ +#define RCC_PLLCFGR_PLL1SSCGEN_Pos (2U) +#define RCC_PLLCFGR_PLL1SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SSCGEN_Pos) /*!< 0x00000004 */ +#define RCC_PLLCFGR_PLL1SSCGEN RCC_PLLCFGR_PLL1SSCGEN_Msk /*!< PLL1 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL1RGE_Pos (3U) +#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000018 */ +#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk /*!< PLL1RGE[1:0] bits: PLL1 input frequency range */ +#define RCC_PLLCFGR_PLL1RGE_0 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLLCFGR_PLL1RGE_1 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000010 */ + +#define RCC_PLLCFGR_PLL1PEN_Pos (5U) +#define RCC_PLLCFGR_PLL1PEN_Msk (0x1UL << RCC_PLLCFGR_PLL1PEN_Pos) /*!< 0x00000020 */ +#define RCC_PLLCFGR_PLL1PEN RCC_PLLCFGR_PLL1PEN_Msk /*!< PLL1 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL1QEN_Pos (6U) +#define RCC_PLLCFGR_PLL1QEN_Msk (0x1UL << RCC_PLLCFGR_PLL1QEN_Pos) /*!< 0x00000040 */ +#define RCC_PLLCFGR_PLL1QEN RCC_PLLCFGR_PLL1QEN_Msk /*!< PLL1 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL1REN_Pos (7U) +#define RCC_PLLCFGR_PLL1REN_Msk (0x1UL << RCC_PLLCFGR_PLL1REN_Pos) /*!< 0x00000080 */ +#define RCC_PLLCFGR_PLL1REN RCC_PLLCFGR_PLL1REN_Msk /*!< PLL1 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL1SEN_Pos (8U) +#define RCC_PLLCFGR_PLL1SEN_Msk (0x1UL << RCC_PLLCFGR_PLL1SEN_Pos) /*!< 0x00000100 */ +#define RCC_PLLCFGR_PLL1SEN RCC_PLLCFGR_PLL1SEN_Msk /*!< PLL1 DIVS divider output enable */ + +#define RCC_PLLCFGR_PLL2FRACEN_Pos (11U) +#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000800 */ +#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk /*!< PLL2 fractional latch enable */ +#define RCC_PLLCFGR_PLL2VCOSEL_Pos (12U) +#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00001000 */ +#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk /*!< PLL2 VCO selection */ +#define RCC_PLLCFGR_PLL2SSCGEN_Pos (13U) +#define RCC_PLLCFGR_PLL2SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SSCGEN_Pos) /*!< 0x00002000 */ +#define RCC_PLLCFGR_PLL2SSCGEN RCC_PLLCFGR_PLL2SSCGEN_Msk /*!< PLL2 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL2RGE_Pos (14U) +#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x0000C000 */ +#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk /*!< PLL2RGE[1:0] bits: PLL2 input frequency range */ +#define RCC_PLLCFGR_PLL2RGE_0 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00004000 */ +#define RCC_PLLCFGR_PLL2RGE_1 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00008000 */ + +#define RCC_PLLCFGR_PLL2PEN_Pos (16U) +#define RCC_PLLCFGR_PLL2PEN_Msk (0x1UL << RCC_PLLCFGR_PLL2PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLLCFGR_PLL2PEN RCC_PLLCFGR_PLL2PEN_Msk /*!< PLL2 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL2QEN_Pos (17U) +#define RCC_PLLCFGR_PLL2QEN_Msk (0x1UL << RCC_PLLCFGR_PLL2QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLLCFGR_PLL2QEN RCC_PLLCFGR_PLL2QEN_Msk /*!< PLL2 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL2REN_Pos (18U) +#define RCC_PLLCFGR_PLL2REN_Msk (0x1UL << RCC_PLLCFGR_PLL2REN_Pos) /*!< 0x00040000 */ +#define RCC_PLLCFGR_PLL2REN RCC_PLLCFGR_PLL2REN_Msk /*!< PLL2 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL2SEN_Pos (19U) +#define RCC_PLLCFGR_PLL2SEN_Msk (0x1UL << RCC_PLLCFGR_PLL2SEN_Pos) /*!< 0x00080000 */ +#define RCC_PLLCFGR_PLL2SEN RCC_PLLCFGR_PLL2SEN_Msk /*!< PLL2 DIVS divider output enable */ +#define RCC_PLLCFGR_PLL2TEN_Pos (20U) +#define RCC_PLLCFGR_PLL2TEN_Msk (0x1UL << RCC_PLLCFGR_PLL2TEN_Pos) /*!< 0x00100000 */ +#define RCC_PLLCFGR_PLL2TEN RCC_PLLCFGR_PLL2TEN_Msk /*!< PLL2 DIVT divider output enable */ + +#define RCC_PLLCFGR_PLL3FRACEN_Pos (22U) +#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00400000 */ +#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk /*!< PLL3 fractional latch enable */ +#define RCC_PLLCFGR_PLL3VCOSEL_Pos (23U) +#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00800000 */ +#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk /*!< PLL3 VCO selection */ +#define RCC_PLLCFGR_PLL3SSCGEN_Pos (24U) +#define RCC_PLLCFGR_PLL3SSCGEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SSCGEN_Pos) /*!< 0x01000000 */ +#define RCC_PLLCFGR_PLL3SSCGEN RCC_PLLCFGR_PLL3SSCGEN_Msk /*!< PLL3 Spread Spectrum Clock Generator enable */ +#define RCC_PLLCFGR_PLL3RGE_Pos (25U) +#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x06000000 */ +#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk /*!< PLL3RGE[1:0] bits: PLL3 input frequency range */ +#define RCC_PLLCFGR_PLL3RGE_0 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x02000000 */ +#define RCC_PLLCFGR_PLL3RGE_1 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x04000000 */ + +#define RCC_PLLCFGR_PLL3PEN_Pos (27U) +#define RCC_PLLCFGR_PLL3PEN_Msk (0x1UL << RCC_PLLCFGR_PLL3PEN_Pos) /*!< 0x08000000 */ +#define RCC_PLLCFGR_PLL3PEN RCC_PLLCFGR_PLL3PEN_Msk /*!< PLL3 DIVP divider output enable */ +#define RCC_PLLCFGR_PLL3QEN_Pos (28U) +#define RCC_PLLCFGR_PLL3QEN_Msk (0x1UL << RCC_PLLCFGR_PLL3QEN_Pos) /*!< 0x10000000 */ +#define RCC_PLLCFGR_PLL3QEN RCC_PLLCFGR_PLL3QEN_Msk /*!< PLL3 DIVQ divider output enable */ +#define RCC_PLLCFGR_PLL3REN_Pos (29U) +#define RCC_PLLCFGR_PLL3REN_Msk (0x1UL << RCC_PLLCFGR_PLL3REN_Pos) /*!< 0x20000000 */ +#define RCC_PLLCFGR_PLL3REN RCC_PLLCFGR_PLL3REN_Msk /*!< PLL3 DIVR divider output enable */ +#define RCC_PLLCFGR_PLL3SEN_Pos (30U) +#define RCC_PLLCFGR_PLL3SEN_Msk (0x1UL << RCC_PLLCFGR_PLL3SEN_Pos) /*!< 0x40000000 */ +#define RCC_PLLCFGR_PLL3SEN RCC_PLLCFGR_PLL3SEN_Msk /*!< PLL3 DIVS divider output enable */ + +/******************** Bit definition for RCC_PLL1DIVR1 register *************/ +#define RCC_PLL1DIVR1_DIVN_Pos (0U) +#define RCC_PLL1DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR1_DIVN RCC_PLL1DIVR1_DIVN_Msk /*!< DIVN1[8:0] bits: PLL1 DIVN division factor */ +#define RCC_PLL1DIVR1_DIVN_0 (0x001UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR1_DIVN_1 (0x002UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR1_DIVN_2 (0x004UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR1_DIVN_3 (0x008UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR1_DIVN_4 (0x010UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR1_DIVN_5 (0x020UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR1_DIVN_6 (0x040UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR1_DIVN_7 (0x080UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR1_DIVN_8 (0x100UL << RCC_PLL1DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL1DIVR1_DIVP_Pos (9U) +#define RCC_PLL1DIVR1_DIVP_Msk (0x7FUL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR1_DIVP RCC_PLL1DIVR1_DIVP_Msk /*!< DIVP1[6:0] bits: PLL1 DIVP division factor */ +#define RCC_PLL1DIVR1_DIVP_0 (0x001UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR1_DIVP_1 (0x002UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR1_DIVP_2 (0x004UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR1_DIVP_3 (0x008UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR1_DIVP_4 (0x010UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR1_DIVP_5 (0x020UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR1_DIVP_6 (0x040UL << RCC_PLL1DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL1DIVR1_DIVQ_Pos (16U) +#define RCC_PLL1DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR1_DIVQ RCC_PLL1DIVR1_DIVQ_Msk /*!< DIVQ1[6:0] bits: PLL1 DIVQ division factor */ +#define RCC_PLL1DIVR1_DIVQ_0 (0x001UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR1_DIVQ_1 (0x002UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR1_DIVQ_2 (0x004UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR1_DIVQ_3 (0x008UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR1_DIVQ_4 (0x010UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR1_DIVQ_5 (0x020UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL1DIVR1_DIVQ_6 (0x040UL << RCC_PLL1DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL1DIVR1_DIVR_Pos (24U) +#define RCC_PLL1DIVR1_DIVR_Msk (0x7FUL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR1_DIVR RCC_PLL1DIVR1_DIVR_Msk /*!< DIVR1[6:0] bits: PLL1 DIVR division factor */ +#define RCC_PLL1DIVR1_DIVR_0 (0x001UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR1_DIVR_1 (0x002UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR1_DIVR_2 (0x004UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR1_DIVR_3 (0x008UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR1_DIVR_4 (0x010UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR1_DIVR_5 (0x020UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR1_DIVR_6 (0x040UL << RCC_PLL1DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register *************/ +#define RCC_PLL1FRACR_FRACN_Pos (3U) +#define RCC_PLL1FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_FRACN RCC_PLL1FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL2DIVR1 register *************/ +#define RCC_PLL2DIVR1_DIVN_Pos (0U) +#define RCC_PLL2DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL2DIVR1_DIVN RCC_PLL2DIVR1_DIVN_Msk /*!< DIVN2[8:0] bits: PLL2 DIVN division factor */ +#define RCC_PLL2DIVR1_DIVN_0 (0x001UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR1_DIVN_1 (0x002UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR1_DIVN_2 (0x004UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL2DIVR1_DIVN_3 (0x008UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL2DIVR1_DIVN_4 (0x010UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL2DIVR1_DIVN_5 (0x020UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL2DIVR1_DIVN_6 (0x040UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL2DIVR1_DIVN_7 (0x080UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL2DIVR1_DIVN_8 (0x100UL << RCC_PLL2DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL2DIVR1_DIVP_Pos (9U) +#define RCC_PLL2DIVR1_DIVP_Msk (0x7FUL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL2DIVR1_DIVP RCC_PLL2DIVR1_DIVP_Msk /*!< DIVP2[6:0] bits: PLL2 DIVP division factor */ +#define RCC_PLL2DIVR1_DIVP_0 (0x001UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR1_DIVP_1 (0x002UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL2DIVR1_DIVP_2 (0x004UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL2DIVR1_DIVP_3 (0x008UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL2DIVR1_DIVP_4 (0x010UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL2DIVR1_DIVP_5 (0x020UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL2DIVR1_DIVP_6 (0x040UL << RCC_PLL2DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL2DIVR1_DIVQ_Pos (16U) +#define RCC_PLL2DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL2DIVR1_DIVQ RCC_PLL2DIVR1_DIVQ_Msk /*!< DIVQ2[6:0] bits: PLL2 DIVQ division factor */ +#define RCC_PLL2DIVR1_DIVQ_0 (0x001UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL2DIVR1_DIVQ_1 (0x002UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL2DIVR1_DIVQ_2 (0x004UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL2DIVR1_DIVQ_3 (0x008UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL2DIVR1_DIVQ_4 (0x010UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL2DIVR1_DIVQ_5 (0x020UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL2DIVR1_DIVQ_6 (0x040UL << RCC_PLL2DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL2DIVR1_DIVR_Pos (24U) +#define RCC_PLL2DIVR1_DIVR_Msk (0x7FUL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL2DIVR1_DIVR RCC_PLL2DIVR1_DIVR_Msk /*!< DIVR2[6:0] bits: PLL2 DIVR division factor */ +#define RCC_PLL2DIVR1_DIVR_0 (0x001UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL2DIVR1_DIVR_1 (0x002UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL2DIVR1_DIVR_2 (0x004UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL2DIVR1_DIVR_3 (0x008UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL2DIVR1_DIVR_4 (0x010UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL2DIVR1_DIVR_5 (0x020UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL2DIVR1_DIVR_6 (0x040UL << RCC_PLL2DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2FRACR register *************/ +#define RCC_PLL2FRACR_FRACN_Pos (3U) +#define RCC_PLL2FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL2FRACR_FRACN RCC_PLL2FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_PLL3DIVR1 register *************/ +#define RCC_PLL3DIVR1_DIVN_Pos (0U) +#define RCC_PLL3DIVR1_DIVN_Msk (0x1FFUL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x000001FF */ +#define RCC_PLL3DIVR1_DIVN RCC_PLL3DIVR1_DIVN_Msk /*!< DIVN3[8:0] bits: PLL3 DIVN division factor */ +#define RCC_PLL3DIVR1_DIVN_0 (0x001UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR1_DIVN_1 (0x002UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR1_DIVN_2 (0x004UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000004 */ +#define RCC_PLL3DIVR1_DIVN_3 (0x008UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000008 */ +#define RCC_PLL3DIVR1_DIVN_4 (0x010UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000010 */ +#define RCC_PLL3DIVR1_DIVN_5 (0x020UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000020 */ +#define RCC_PLL3DIVR1_DIVN_6 (0x040UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000040 */ +#define RCC_PLL3DIVR1_DIVN_7 (0x080UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000080 */ +#define RCC_PLL3DIVR1_DIVN_8 (0x100UL << RCC_PLL3DIVR1_DIVN_Pos) /*!< 0x00000100 */ + +#define RCC_PLL3DIVR1_DIVP_Pos (9U) +#define RCC_PLL3DIVR1_DIVP_Msk (0x7FUL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL3DIVR1_DIVP RCC_PLL3DIVR1_DIVP_Msk /*!< DIVP3[6:0] bits: PLL3 DIVP division factor */ +#define RCC_PLL3DIVR1_DIVP_0 (0x001UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000200 */ +#define RCC_PLL3DIVR1_DIVP_1 (0x002UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000400 */ +#define RCC_PLL3DIVR1_DIVP_2 (0x004UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00000800 */ +#define RCC_PLL3DIVR1_DIVP_3 (0x008UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00001000 */ +#define RCC_PLL3DIVR1_DIVP_4 (0x010UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00002000 */ +#define RCC_PLL3DIVR1_DIVP_5 (0x020UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00004000 */ +#define RCC_PLL3DIVR1_DIVP_6 (0x040UL << RCC_PLL3DIVR1_DIVP_Pos) /*!< 0x00008000 */ + +#define RCC_PLL3DIVR1_DIVQ_Pos (16U) +#define RCC_PLL3DIVR1_DIVQ_Msk (0x7FUL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x007F0000 */ +#define RCC_PLL3DIVR1_DIVQ RCC_PLL3DIVR1_DIVQ_Msk /*!< DIVQ3[6:0] bits: PLL3 DIVQ division factor */ +#define RCC_PLL3DIVR1_DIVQ_0 (0x001UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00010000 */ +#define RCC_PLL3DIVR1_DIVQ_1 (0x002UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00020000 */ +#define RCC_PLL3DIVR1_DIVQ_2 (0x004UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00040000 */ +#define RCC_PLL3DIVR1_DIVQ_3 (0x008UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00080000 */ +#define RCC_PLL3DIVR1_DIVQ_4 (0x010UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00100000 */ +#define RCC_PLL3DIVR1_DIVQ_5 (0x020UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00200000 */ +#define RCC_PLL3DIVR1_DIVQ_6 (0x040UL << RCC_PLL3DIVR1_DIVQ_Pos) /*!< 0x00400000 */ + +#define RCC_PLL3DIVR1_DIVR_Pos (24U) +#define RCC_PLL3DIVR1_DIVR_Msk (0x7FUL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x7F000000 */ +#define RCC_PLL3DIVR1_DIVR RCC_PLL3DIVR1_DIVR_Msk /*!< DIVR3[6:0] bits: PLL3 DIVR division factor */ +#define RCC_PLL3DIVR1_DIVR_0 (0x001UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x01000000 */ +#define RCC_PLL3DIVR1_DIVR_1 (0x002UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x02000000 */ +#define RCC_PLL3DIVR1_DIVR_2 (0x004UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x04000000 */ +#define RCC_PLL3DIVR1_DIVR_3 (0x008UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x08000000 */ +#define RCC_PLL3DIVR1_DIVR_4 (0x010UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x10000000 */ +#define RCC_PLL3DIVR1_DIVR_5 (0x020UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x20000000 */ +#define RCC_PLL3DIVR1_DIVR_6 (0x040UL << RCC_PLL3DIVR1_DIVR_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3FRACR register *************/ +#define RCC_PLL3FRACR_FRACN_Pos (3U) +#define RCC_PLL3FRACR_FRACN_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL3FRACR_FRACN RCC_PLL3FRACR_FRACN_Msk /*!< FRACN[12:0] bits */ + +/******************** Bit definition for RCC_CCIPR1 register **************/ +#define RCC_CCIPR1_FMCSEL_Pos (0U) +#define RCC_CCIPR1_FMCSEL_Msk (0x3UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_FMCSEL RCC_CCIPR1_FMCSEL_Msk +#define RCC_CCIPR1_FMCSEL_0 (0x1UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_FMCSEL_1 (0x2UL << RCC_CCIPR1_FMCSEL_Pos) /*!< 0x00000002 */ + +#define RCC_CCIPR1_SDMMC12SEL_Pos (2U) +#define RCC_CCIPR1_SDMMC12SEL_Msk (0x1UL << RCC_CCIPR1_SDMMC12SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_SDMMC12SEL RCC_CCIPR1_SDMMC12SEL_Msk + +#define RCC_CCIPR1_XSPI1SEL_Pos (4U) +#define RCC_CCIPR1_XSPI1SEL_Msk (0x3UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000030 */ +#define RCC_CCIPR1_XSPI1SEL RCC_CCIPR1_XSPI1SEL_Msk +#define RCC_CCIPR1_XSPI1SEL_0 (0x1UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR1_XSPI1SEL_1 (0x2UL << RCC_CCIPR1_XSPI1SEL_Pos) /*!< 0x00000020 */ + +#define RCC_CCIPR1_XSPI2SEL_Pos (6U) +#define RCC_CCIPR1_XSPI2SEL_Msk (0x3UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR1_XSPI2SEL RCC_CCIPR1_XSPI2SEL_Msk +#define RCC_CCIPR1_XSPI2SEL_0 (0x1UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR1_XSPI2SEL_1 (0x2UL << RCC_CCIPR1_XSPI2SEL_Pos) /*!< 0x00000080 */ + +#define RCC_CCIPR1_USBREFCKSEL_Pos (8U) +#define RCC_CCIPR1_USBREFCKSEL_Msk (0xFUL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000F00 */ +#define RCC_CCIPR1_USBREFCKSEL RCC_CCIPR1_USBREFCKSEL_Msk +#define RCC_CCIPR1_USBREFCKSEL_0 (0x1UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR1_USBREFCKSEL_1 (0x2UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR1_USBREFCKSEL_2 (0x4UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_USBREFCKSEL_3 (0x8UL << RCC_CCIPR1_USBREFCKSEL_Pos) /*!< 0x00000800 */ + +#define RCC_CCIPR1_USBPHYCSEL_Pos (12U) +#define RCC_CCIPR1_USBPHYCSEL_Msk (0x3UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR1_USBPHYCSEL RCC_CCIPR1_USBPHYCSEL_Msk +#define RCC_CCIPR1_USBPHYCSEL_0 (0x1UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR1_USBPHYCSEL_1 (0x2UL << RCC_CCIPR1_USBPHYCSEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR1_OTGFSSEL_Pos (14U) +#define RCC_CCIPR1_OTGFSSEL_Msk (0x3UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x0000C000 */ +#define RCC_CCIPR1_OTGFSSEL RCC_CCIPR1_OTGFSSEL_Msk +#define RCC_CCIPR1_OTGFSSEL_0 (0x1UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00004000 */ +#define RCC_CCIPR1_OTGFSSEL_1 (0x2UL << RCC_CCIPR1_OTGFSSEL_Pos) /*!< 0x00008000 */ + +#define RCC_CCIPR1_ETH1REFCKSEL_Pos (16U) +#define RCC_CCIPR1_ETH1REFCKSEL_Msk (0x3UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00030000 */ +#define RCC_CCIPR1_ETH1REFCKSEL RCC_CCIPR1_ETH1REFCKSEL_Msk +#define RCC_CCIPR1_ETH1REFCKSEL_0 (0x1UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR1_ETH1REFCKSEL_1 (0x2UL << RCC_CCIPR1_ETH1REFCKSEL_Pos) /*!< 0x00020000 */ + +#define RCC_CCIPR1_ETH1PHYCKSEL_Pos (18U) +#define RCC_CCIPR1_ETH1PHYCKSEL_Msk (0x1UL << RCC_CCIPR1_ETH1PHYCKSEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_ETH1PHYCKSEL RCC_CCIPR1_ETH1PHYCKSEL_Msk + +#define RCC_CCIPR1_ADF1SEL_Pos (20U) +#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk +#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00400000 */ + +#define RCC_CCIPR1_ADCSEL_Pos (24U) +#define RCC_CCIPR1_ADCSEL_Msk (0x3UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR1_ADCSEL RCC_CCIPR1_ADCSEL_Msk +#define RCC_CCIPR1_ADCSEL_0 (0x1UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR1_ADCSEL_1 (0x2UL << RCC_CCIPR1_ADCSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR1_PSSISEL_Pos (27U) +#define RCC_CCIPR1_PSSISEL_Msk (0x1UL << RCC_CCIPR1_PSSISEL_Pos) /*!< 0x08000000 */ +#define RCC_CCIPR1_PSSISEL RCC_CCIPR1_PSSISEL_Msk + +#define RCC_CCIPR1_CKPERSEL_Pos (28U) +#define RCC_CCIPR1_CKPERSEL_Msk (0x3UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x30000000 */ +#define RCC_CCIPR1_CKPERSEL RCC_CCIPR1_CKPERSEL_Msk +#define RCC_CCIPR1_CKPERSEL_0 (0x1UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x10000000 */ +#define RCC_CCIPR1_CKPERSEL_1 (0x2UL << RCC_CCIPR1_CKPERSEL_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for RCC_CCIPR2 register *************/ +#define RCC_CCIPR2_UART234578SEL_Pos (0U) +#define RCC_CCIPR2_UART234578SEL_Msk (0x7UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR2_UART234578SEL RCC_CCIPR2_UART234578SEL_Msk +#define RCC_CCIPR2_UART234578SEL_0 (0x1UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR2_UART234578SEL_1 (0x2UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR2_UART234578SEL_2 (0x4UL << RCC_CCIPR2_UART234578SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR2_SPI23SEL_Pos (4U) +#define RCC_CCIPR2_SPI23SEL_Msk (0x7UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR2_SPI23SEL RCC_CCIPR2_SPI23SEL_Msk +#define RCC_CCIPR2_SPI23SEL_0 (0x1UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR2_SPI23SEL_1 (0x2UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SPI23SEL_2 (0x4UL << RCC_CCIPR2_SPI23SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR2_I2C23SEL_Pos (8U) +#define RCC_CCIPR2_I2C23SEL_Msk (0x3UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000300 */ +#define RCC_CCIPR2_I2C23SEL RCC_CCIPR2_I2C23SEL_Msk +#define RCC_CCIPR2_I2C23SEL_0 (0x1UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR2_I2C23SEL_1 (0x2UL << RCC_CCIPR2_I2C23SEL_Pos) /*!< 0x00000200 */ + +#define RCC_CCIPR2_I2C1_I3C1SEL_Pos (12U) +#define RCC_CCIPR2_I2C1_I3C1SEL_Msk (0x3UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00003000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL RCC_CCIPR2_I2C1_I3C1SEL_Msk +#define RCC_CCIPR2_I2C1_I3C1SEL_0 (0x1UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR2_I2C1_I3C1SEL_1 (0x2UL << RCC_CCIPR2_I2C1_I3C1SEL_Pos) /*!< 0x00002000 */ + +#define RCC_CCIPR2_LPTIM1SEL_Pos (16U) +#define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR2_LPTIM1SEL RCC_CCIPR2_LPTIM1SEL_Msk +#define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR2_FDCANSEL_Pos (22U) +#define RCC_CCIPR2_FDCANSEL_Msk (0x3UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR2_FDCANSEL RCC_CCIPR2_FDCANSEL_Msk +#define RCC_CCIPR2_FDCANSEL_0 (0x1UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR2_FDCANSEL_1 (0x2UL << RCC_CCIPR2_FDCANSEL_Pos) /*!< 0x00800000 */ + +#define RCC_CCIPR2_SPDIFRXSEL_Pos (24U) +#define RCC_CCIPR2_SPDIFRXSEL_Msk (0x3UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_SPDIFRXSEL RCC_CCIPR2_SPDIFRXSEL_Msk +#define RCC_CCIPR2_SPDIFRXSEL_0 (0x1UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_SPDIFRXSEL_1 (0x2UL << RCC_CCIPR2_SPDIFRXSEL_Pos) /*!< 0x02000000 */ + +#define RCC_CCIPR2_CECSEL_Pos (28U) +#define RCC_CCIPR2_CECSEL_Msk (0x3UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x03000000 */ +#define RCC_CCIPR2_CECSEL RCC_CCIPR2_CECSEL_Msk +#define RCC_CCIPR2_CECSEL_0 (0x1UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x01000000 */ +#define RCC_CCIPR2_CECSEL_1 (0x2UL << RCC_CCIPR2_CECSEL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for RCC_CCIPR3 register *************/ +#define RCC_CCIPR3_USART1SEL_Pos (0U) +#define RCC_CCIPR3_USART1SEL_Msk (0x7UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR3_USART1SEL RCC_CCIPR3_USART1SEL_Msk +#define RCC_CCIPR3_USART1SEL_0 (0x1UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_USART1SEL_1 (0x2UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_USART1SEL_2 (0x4UL << RCC_CCIPR3_USART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR3_SPI45SEL_Pos (4U) +#define RCC_CCIPR3_SPI45SEL_Msk (0x7UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR3_SPI45SEL RCC_CCIPR3_SPI45SEL_Msk +#define RCC_CCIPR3_SPI45SEL_0 (0x1UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_SPI45SEL_1 (0x2UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR3_SPI45SEL_2 (0x4UL << RCC_CCIPR3_SPI45SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR3_SPI1SEL_Pos (8U) +#define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR3_SPI1SEL RCC_CCIPR3_SPI1SEL_Msk +#define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR3_SAI1SEL_Pos (16U) +#define RCC_CCIPR3_SAI1SEL_Msk (0x7UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00070000 */ +#define RCC_CCIPR3_SAI1SEL RCC_CCIPR3_SAI1SEL_Msk +#define RCC_CCIPR3_SAI1SEL_0 (0x1UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00010000 */ +#define RCC_CCIPR3_SAI1SEL_1 (0x2UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00020000 */ +#define RCC_CCIPR3_SAI1SEL_2 (0x4UL << RCC_CCIPR3_SAI1SEL_Pos) /*!< 0x00040000 */ + +#define RCC_CCIPR3_SAI2SEL_Pos (20U) +#define RCC_CCIPR3_SAI2SEL_Msk (0x7UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00700000 */ +#define RCC_CCIPR3_SAI2SEL RCC_CCIPR3_SAI2SEL_Msk +#define RCC_CCIPR3_SAI2SEL_0 (0x1UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR3_SAI2SEL_1 (0x2UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR3_SAI2SEL_2 (0x4UL << RCC_CCIPR3_SAI2SEL_Pos) /*!< 0x00400000 */ + +/******************** Bit definition for RCC_CCIPR4 register ************/ +#define RCC_CCIPR4_LPUART1SEL_Pos (0U) +#define RCC_CCIPR4_LPUART1SEL_Msk (0x7UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000007 */ +#define RCC_CCIPR4_LPUART1SEL RCC_CCIPR4_LPUART1SEL_Msk +#define RCC_CCIPR4_LPUART1SEL_0 (0x1UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR4_LPUART1SEL_1 (0x2UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR4_LPUART1SEL_2 (0x4UL << RCC_CCIPR4_LPUART1SEL_Pos) /*!< 0x00000004 */ + +#define RCC_CCIPR4_SPI6SEL_Pos (4U) +#define RCC_CCIPR4_SPI6SEL_Msk (0x7UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000070 */ +#define RCC_CCIPR4_SPI6SEL RCC_CCIPR4_SPI6SEL_Msk +#define RCC_CCIPR4_SPI6SEL_0 (0x1UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR4_SPI6SEL_1 (0x2UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR4_SPI6SEL_2 (0x4UL << RCC_CCIPR4_SPI6SEL_Pos) /*!< 0x00000040 */ + +#define RCC_CCIPR4_LPTIM23SEL_Pos (8U) +#define RCC_CCIPR4_LPTIM23SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000700 */ +#define RCC_CCIPR4_LPTIM23SEL RCC_CCIPR4_LPTIM23SEL_Msk +#define RCC_CCIPR4_LPTIM23SEL_0 (0x1UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000100 */ +#define RCC_CCIPR4_LPTIM23SEL_1 (0x2UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000200 */ +#define RCC_CCIPR4_LPTIM23SEL_2 (0x4UL << RCC_CCIPR4_LPTIM23SEL_Pos) /*!< 0x00000400 */ + +#define RCC_CCIPR4_LPTIM45SEL_Pos (12U) +#define RCC_CCIPR4_LPTIM45SEL_Msk (0x7UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR4_LPTIM45SEL RCC_CCIPR4_LPTIM45SEL_Msk +#define RCC_CCIPR4_LPTIM45SEL_0 (0x1UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR4_LPTIM45SEL_1 (0x2UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR4_LPTIM45SEL_2 (0x4UL << RCC_CCIPR4_LPTIM45SEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSIRDYIE_Pos (0U) +#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (2U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (3U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_CSIRDYIE_Pos (4U) +#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk +#define RCC_CIER_HSI48RDYIE_Pos (5U) +#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */ +#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_PLL2RDYIE_Pos (7U) +#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */ +#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk +#define RCC_CIER_PLL3RDYIE_Pos (8U) +#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */ +#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk +#define RCC_CIER_LSECSSIE_Pos (9U) +#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ +#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk + +/******************** Bit definition for RCC_CIFR register ******************/ +#define RCC_CIFR_LSIRDYF_Pos (0U) +#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (2U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (3U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_CSIRDYF_Pos (4U) +#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk +#define RCC_CIFR_HSI48RDYF_Pos (5U) +#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */ +#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_PLL2RDYF_Pos (7U) +#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */ +#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk +#define RCC_CIFR_PLL3RDYF_Pos (8U) +#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */ +#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk +#define RCC_CIFR_LSECSSF_Pos (9U) +#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ +#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ******************/ +#define RCC_CICR_LSIRDYC_Pos (0U) +#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (2U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (3U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_CSIRDYC_Pos (4U) +#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk +#define RCC_CICR_HSI48RDYC_Pos (5U) +#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */ +#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_PLL2RDYC_Pos (7U) +#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */ +#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk +#define RCC_CICR_PLL3RDYC_Pos (8U) +#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */ +#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk +#define RCC_CICR_LSECSSC_Pos (9U) +#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ +#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk + +/******************** Bit definition for RCC_BDCR register ******************/ +#define RCC_BDCR_LSEON_Pos (0U) +#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk +#define RCC_BDCR_LSERDY_Pos (1U) +#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk +#define RCC_BDCR_LSEBYP_Pos (2U) +#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk +#define RCC_BDCR_LSEDRV_Pos (3U) +#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk +#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ + +#define RCC_BDCR_LSECSSON_Pos (5U) +#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk +#define RCC_BDCR_LSECSSD_Pos (6U) +#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk +#define RCC_BDCR_LSEEXT_Pos (7U) +#define RCC_BDCR_LSEEXT_Msk (0x1UL << RCC_BDCR_LSEEXT_Pos) /*!< 0x00000080 */ +#define RCC_BDCR_LSEEXT RCC_BDCR_LSEEXT_Msk +#define RCC_BDCR_RTCSEL_Pos (8U) +#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk +#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR_LSECSSRA_Pos (12U) +#define RCC_BDCR_LSECSSRA_Msk (0x1UL << RCC_BDCR_LSECSSRA_Pos) /*!< 0x00001000 */ +#define RCC_BDCR_LSECSSRA RCC_BDCR_LSECSSRA_Msk + +#define RCC_BDCR_RTCEN_Pos (15U) +#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ +#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk +#define RCC_BDCR_VSWRST_Pos (16U) +#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_LSION_Pos (0U) +#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ +#define RCC_CSR_LSION RCC_CSR_LSION_Msk +#define RCC_CSR_LSIRDY_Pos (1U) +#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ +#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (4U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_ADC12RST_Pos (5U) +#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk +#define RCC_AHB1RSTR_ETH1RST_Pos (15U) +#define RCC_AHB1RSTR_ETH1RST_Msk (0x1UL << RCC_AHB1RSTR_ETH1RST_Pos) /*!< 0x00008000 */ +#define RCC_AHB1RSTR_ETH1RST RCC_AHB1RSTR_ETH1RST_Msk +#define RCC_AHB1RSTR_OTGHSRST_Pos (25U) +#define RCC_AHB1RSTR_OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHSRST_Pos) /*!< 0x02000000 */ +#define RCC_AHB1RSTR_OTGHSRST RCC_AHB1RSTR_OTGHSRST_Msk +#define RCC_AHB1RSTR_USBPHYCRST_Pos (26U) +#define RCC_AHB1RSTR_USBPHYCRST_Msk (0x1UL << RCC_AHB1RSTR_USBPHYCRST_Pos) /*!< 0x04000000 */ +#define RCC_AHB1RSTR_USBPHYCRST RCC_AHB1RSTR_USBPHYCRST_Msk +#define RCC_AHB1RSTR_OTGFSRST_Pos (27U) +#define RCC_AHB1RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_OTGFSRST_Pos) /*!< 0x08000000 */ +#define RCC_AHB1RSTR_OTGFSRST RCC_AHB1RSTR_OTGFSRST_Msk +#define RCC_AHB1RSTR_ADF1RST_Pos (31U) +#define RCC_AHB1RSTR_ADF1RST_Msk (0x1UL << RCC_AHB1RSTR_ADF1RST_Pos) /*!< 0x80000000 */ +#define RCC_AHB1RSTR_ADF1RST RCC_AHB1RSTR_ADF1RST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_PSSIRST_Pos (1U) +#define RCC_AHB2RSTR_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_PSSIRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_PSSIRST RCC_AHB2RSTR_PSSIRST_Msk +#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U) +#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */ +#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk +#define RCC_AHB2RSTR_CORDICRST_Pos (14U) +#define RCC_AHB2RSTR_CORDICRST_Msk (0x1UL << RCC_AHB2RSTR_CORDICRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB2RSTR_CORDICRST RCC_AHB2RSTR_CORDICRST_Msk + +/******************** Bit definition for RCC_AHB3RSTR register **************/ +#define RCC_AHB3RSTR_RNGRST_Pos (0U) +#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */ +#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk +#define RCC_AHB3RSTR_HASHRST_Pos (1U) +#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk +#define RCC_AHB3RSTR_CRYPRST_Pos (2U) +#define RCC_AHB3RSTR_CRYPRST_Msk (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB3RSTR_CRYPRST RCC_AHB3RSTR_CRYPRST_Msk +#define RCC_AHB3RSTR_SAESRST_Pos (4U) +#define RCC_AHB3RSTR_SAESRST_Msk (0x1UL << RCC_AHB3RSTR_SAESRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB3RSTR_SAESRST RCC_AHB3RSTR_SAESRST_Msk +#define RCC_AHB3RSTR_PKARST_Pos (6U) +#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000040 */ +#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_GPIOARST_Pos (0U) +#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk +#define RCC_AHB4RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk +#define RCC_AHB4RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk +#define RCC_AHB4RSTR_GPIODRST_Pos (3U) +#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk +#define RCC_AHB4RSTR_GPIOERST_Pos (4U) +#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */ +#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk +#define RCC_AHB4RSTR_GPIOFRST_Pos (5U) +#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk +#define RCC_AHB4RSTR_GPIOGRST_Pos (6U) +#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ +#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk +#define RCC_AHB4RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk +#define RCC_AHB4RSTR_GPIOMRST_Pos (12U) +#define RCC_AHB4RSTR_GPIOMRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOMRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB4RSTR_GPIOMRST RCC_AHB4RSTR_GPIOMRST_Msk +#define RCC_AHB4RSTR_GPIONRST_Pos (13U) +#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */ +#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk +#define RCC_AHB4RSTR_GPIOORST_Pos (14U) +#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */ +#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk +#define RCC_AHB4RSTR_GPIOPRST_Pos (15U) +#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */ +#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk +#define RCC_AHB4RSTR_CRCRST_Pos (19U) +#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_HPDMA1RST_Pos (0U) +#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk +#define RCC_AHB5RSTR_DMA2DRST_Pos (1U) +#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk +#define RCC_AHB5RSTR_JPEGRST_Pos (3U) +#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */ +#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk +#define RCC_AHB5RSTR_FMCRST_Pos (4U) +#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */ +#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk +#define RCC_AHB5RSTR_XSPI1RST_Pos (5U) +#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk +#define RCC_AHB5RSTR_SDMMC1RST_Pos (8U) +#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */ +#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk +#define RCC_AHB5RSTR_XSPI2RST_Pos (12U) +#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */ +#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk +#define RCC_AHB5RSTR_XSPIMRST_Pos (14U) +#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00004000 */ +#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk +#define RCC_AHB5RSTR_GFXMMURST_Pos (19U) +#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */ +#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register *************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_TIM4RST_Pos (2U) +#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ +#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk +#define RCC_APB1RSTR1_TIM5RST_Pos (3U) +#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ +#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk +#define RCC_APB1RSTR1_TIM6RST_Pos (4U) +#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ +#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk +#define RCC_APB1RSTR1_TIM7RST_Pos (5U) +#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk +#define RCC_APB1RSTR1_TIM12RST_Pos (6U) +#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */ +#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk +#define RCC_APB1RSTR1_TIM13RST_Pos (7U) +#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */ +#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk +#define RCC_APB1RSTR1_TIM14RST_Pos (8U) +#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk +#define RCC_APB1RSTR1_LPTIM1RST_Pos (9U) +#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x00000200 */ +#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk +#define RCC_APB1RSTR1_SPI2RST_Pos (14U) +#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ +#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk +#define RCC_APB1RSTR1_SPI3RST_Pos (15U) +#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ +#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk +#define RCC_APB1RSTR1_SPDIFRXRST_Pos (16U) +#define RCC_APB1RSTR1_SPDIFRXRST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRXRST_Pos) /*!< 0x00010000 */ +#define RCC_APB1RSTR1_SPDIFRXRST RCC_APB1RSTR1_SPDIFRXRST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_USART3RST_Pos (18U) +#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */ +#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk +#define RCC_APB1RSTR1_UART4RST_Pos (19U) +#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ +#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk +#define RCC_APB1RSTR1_UART5RST_Pos (20U) +#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk +#define RCC_APB1RSTR1_I2C1_I3C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1_I3C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1_I3C1RST RCC_APB1RSTR1_I2C1_I3C1RST_Msk +#define RCC_APB1RSTR1_I2C2RST_Pos (22U) +#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ +#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk +#define RCC_APB1RSTR1_I2C3RST_Pos (23U) +#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ +#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk +#define RCC_APB1RSTR1_CECRST_Pos (27U) +#define RCC_APB1RSTR1_CECRST_Msk (0x1UL << RCC_APB1RSTR1_CECRST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR1_CECRST RCC_APB1RSTR1_CECRST_Msk +#define RCC_APB1RSTR1_UART7RST_Pos (30U) +#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */ +#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk +#define RCC_APB1RSTR1_UART8RST_Pos (31U) +#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */ +#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register *************/ +#define RCC_APB1RSTR2_CRSRST_Pos (1U) +#define RCC_APB1RSTR2_CRSRST_Msk (0x1UL << RCC_APB1RSTR2_CRSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR2_CRSRST RCC_APB1RSTR2_CRSRST_Msk +#define RCC_APB1RSTR2_MDIOSRST_Pos (5U) +#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk +#define RCC_APB1RSTR2_FDCANRST_Pos (8U) +#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */ +#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk +#define RCC_APB1RSTR2_UCPD1RST_Pos (27U) +#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x08000000 */ +#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (0U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (4U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_SPI4RST_Pos (13U) +#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ +#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk +#define RCC_APB2RSTR_TIM15RST_Pos (16U) +#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ +#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_TIM9RST_Pos (19U) +#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */ +#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk +#define RCC_APB2RSTR_SPI5RST_Pos (20U) +#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ +#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (22U) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk +#define RCC_APB2RSTR_SAI2RST_Pos (23U) +#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */ +#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk + +/******************** Bit definition for RCC_APB4RSTR register **************/ +#define RCC_APB4RSTR_SBSRST_Pos (1U) +#define RCC_APB4RSTR_SBSRST_Msk (0x1UL << RCC_APB4RSTR_SBSRST_Pos) /*!< 0x00000002 */ +#define RCC_APB4RSTR_SBSRST RCC_APB4RSTR_SBSRST_Msk +#define RCC_APB4RSTR_LPUART1RST_Pos (3U) +#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */ +#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk +#define RCC_APB4RSTR_SPI6RST_Pos (5U) +#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */ +#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk +#define RCC_APB4RSTR_LPTIM2RST_Pos (9U) +#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */ +#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk +#define RCC_APB4RSTR_LPTIM3RST_Pos (10U) +#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */ +#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk +#define RCC_APB4RSTR_LPTIM4RST_Pos (11U) +#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */ +#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk +#define RCC_APB4RSTR_LPTIM5RST_Pos (12U) +#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */ +#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk +#define RCC_APB4RSTR_VREFRST_Pos (15U) +#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */ +#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk +#define RCC_APB4RSTR_DTSRST_Pos (26U) +#define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */ +#define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk + +/******************** Bit definition for RCC_APB5RSTR register **************/ +#define RCC_APB5RSTR_DCMIPPRST_Pos (2U) +#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */ +#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk +#define RCC_APB5RSTR_GFXTIMRST_Pos (4U) +#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */ +#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk + +/******************** Bit definition for RCC_CKGDISR register ***************/ +#define RCC_CKGDISR_AXICKG_Pos (0U) +#define RCC_CKGDISR_AXICKG_Msk (0x1UL << RCC_CKGDISR_AXICKG_Pos) /*!< 0x00000001 */ +#define RCC_CKGDISR_AXICKG RCC_CKGDISR_AXICKG_Msk +#define RCC_CKGDISR_AHBMCKG_Pos (1U) +#define RCC_CKGDISR_AHBMCKG_Msk (0x1UL << RCC_CKGDISR_AHBMCKG_Pos) /*!< 0x00000002 */ +#define RCC_CKGDISR_AHBMCKG RCC_CKGDISR_AHBMCKG_Msk +#define RCC_CKGDISR_SDMMC1CKG_Pos (2U) +#define RCC_CKGDISR_SDMMC1CKG_Msk (0x1UL << RCC_CKGDISR_SDMMC1CKG_Pos) /*!< 0x00000004 */ +#define RCC_CKGDISR_SDMMC1CKG RCC_CKGDISR_SDMMC1CKG_Msk +#define RCC_CKGDISR_HPDMA1CKG_Pos (3U) +#define RCC_CKGDISR_HPDMA1CKG_Msk (0x1UL << RCC_CKGDISR_HPDMA1CKG_Pos) /*!< 0x00000008 */ +#define RCC_CKGDISR_HPDMA1CKG RCC_CKGDISR_HPDMA1CKG_Msk +#define RCC_CKGDISR_CPUCKG_Pos (4U) +#define RCC_CKGDISR_CPUCKG_Msk (0x1UL << RCC_CKGDISR_CPUCKG_Pos) /*!< 0x00000010 */ +#define RCC_CKGDISR_CPUCKG RCC_CKGDISR_CPUCKG_Msk +#define RCC_CKGDISR_DCMIPPCKG_Pos (8U) +#define RCC_CKGDISR_DCMIPPCKG_Msk (0x1UL << RCC_CKGDISR_DCMIPPCKG_Pos) /*!< 0x00000100 */ +#define RCC_CKGDISR_DCMIPPCKG RCC_CKGDISR_DCMIPPCKG_Msk +#define RCC_CKGDISR_DMA2DCKG_Pos (9U) +#define RCC_CKGDISR_DMA2DCKG_Msk (0x1UL << RCC_CKGDISR_DMA2DCKG_Pos) /*!< 0x00000200 */ +#define RCC_CKGDISR_DMA2DCKG RCC_CKGDISR_DMA2DCKG_Msk +#define RCC_CKGDISR_GFXMMUSCKG_Pos (10U) +#define RCC_CKGDISR_GFXMMUSCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUSCKG_Pos) /*!< 0x00000400 */ +#define RCC_CKGDISR_GFXMMUSCKG RCC_CKGDISR_GFXMMUSCKG_Msk +#define RCC_CKGDISR_GFXMMUMCKG_Pos (12U) +#define RCC_CKGDISR_GFXMMUMCKG_Msk (0x1UL << RCC_CKGDISR_GFXMMUMCKG_Pos) /*!< 0x00001000 */ +#define RCC_CKGDISR_GFXMMUMCKG RCC_CKGDISR_GFXMMUMCKG_Msk +#define RCC_CKGDISR_AHBSCKG_Pos (13U) +#define RCC_CKGDISR_AHBSCKG_Msk (0x1UL << RCC_CKGDISR_AHBSCKG_Pos) /*!< 0x00002000 */ +#define RCC_CKGDISR_AHBSCKG RCC_CKGDISR_AHBSCKG_Msk +#define RCC_CKGDISR_FMCCKG_Pos (14U) +#define RCC_CKGDISR_FMCCKG_Msk (0x1UL << RCC_CKGDISR_FMCCKG_Pos) /*!< 0x00004000 */ +#define RCC_CKGDISR_FMCCKG RCC_CKGDISR_FMCCKG_Msk +#define RCC_CKGDISR_XSPI1CKG_Pos (15U) +#define RCC_CKGDISR_XSPI1CKG_Msk (0x1UL << RCC_CKGDISR_XSPI1CKG_Pos) /*!< 0x00008000 */ +#define RCC_CKGDISR_XSPI1CKG RCC_CKGDISR_XSPI1CKG_Msk +#define RCC_CKGDISR_XSPI2CKG_Pos (16U) +#define RCC_CKGDISR_XSPI2CKG_Msk (0x1UL << RCC_CKGDISR_XSPI2CKG_Pos) /*!< 0x00010000 */ +#define RCC_CKGDISR_XSPI2CKG RCC_CKGDISR_XSPI2CKG_Msk +#define RCC_CKGDISR_AXISRAM4CKG_Pos (17U) +#define RCC_CKGDISR_AXISRAM4CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM4CKG_Pos) /*!< 0x00020000 */ +#define RCC_CKGDISR_AXISRAM4CKG RCC_CKGDISR_AXISRAM4CKG_Msk +#define RCC_CKGDISR_AXISRAM3CKG_Pos (18U) +#define RCC_CKGDISR_AXISRAM3CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM3CKG_Pos) /*!< 0x00040000 */ +#define RCC_CKGDISR_AXISRAM3CKG RCC_CKGDISR_AXISRAM3CKG_Msk +#define RCC_CKGDISR_AXISRAM2CKG_Pos (19U) +#define RCC_CKGDISR_AXISRAM2CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM2CKG_Pos) /*!< 0x00080000 */ +#define RCC_CKGDISR_AXISRAM2CKG RCC_CKGDISR_AXISRAM2CKG_Msk +#define RCC_CKGDISR_AXISRAM1CKG_Pos (20U) +#define RCC_CKGDISR_AXISRAM1CKG_Msk (0x1UL << RCC_CKGDISR_AXISRAM1CKG_Pos) /*!< 0x00100000 */ +#define RCC_CKGDISR_AXISRAM1CKG RCC_CKGDISR_AXISRAM1CKG_Msk +#define RCC_CKGDISR_FLASHCKG_Pos (21U) +#define RCC_CKGDISR_FLASHCKG_Msk (0x1UL << RCC_CKGDISR_FLASHCKG_Pos) /*!< 0x00200000 */ +#define RCC_CKGDISR_FLASHCKG RCC_CKGDISR_FLASHCKG_Msk +#define RCC_CKGDISR_EXTICKG_Pos (30U) +#define RCC_CKGDISR_EXTICKG_Msk (0x1UL << RCC_CKGDISR_EXTICKG_Pos) /*!< 0x40000000 */ +#define RCC_CKGDISR_EXTICKG RCC_CKGDISR_EXTICKG_Msk +#define RCC_CKGDISR_JTAGCKG_Pos (31U) +#define RCC_CKGDISR_JTAGCKG_Msk (0x1UL << RCC_CKGDISR_JTAGCKG_Pos) /*!< 0x80000000 */ +#define RCC_CKGDISR_JTAGCKG RCC_CKGDISR_JTAGCKG_Msk + +/******************** Bit definition for RCC_PLL1DIVR2 register *************/ +#define RCC_PLL1DIVR2_DIVS_Pos (0U) +#define RCC_PLL1DIVR2_DIVS_Msk (0x7UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL1DIVR2_DIVS RCC_PLL1DIVR2_DIVS_Msk /*!< DIVS1[2:0] bits: PLL1 DIVS division factor */ +#define RCC_PLL1DIVR2_DIVS_0 (0x1UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR2_DIVS_1 (0x2UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR2_DIVS_2 (0x4UL << RCC_PLL1DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL2DIVR2 register *************/ +#define RCC_PLL2DIVR2_DIVS_Pos (0U) +#define RCC_PLL2DIVR2_DIVS_Msk (0x7UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL2DIVR2_DIVS RCC_PLL2DIVR2_DIVS_Msk /*!< DIVS2[2:0] bits: PLL2 DIVS division factor */ +#define RCC_PLL2DIVR2_DIVS_0 (0x1UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL2DIVR2_DIVS_1 (0x2UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL2DIVR2_DIVS_2 (0x4UL << RCC_PLL2DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +#define RCC_PLL2DIVR2_DIVT_Pos (8U) +#define RCC_PLL2DIVR2_DIVT_Msk (0x7UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000700 */ +#define RCC_PLL2DIVR2_DIVT RCC_PLL2DIVR2_DIVT_Msk /*!< DIVT2[2:0] bits: PLL2 DIVT division factor */ +#define RCC_PLL2DIVR2_DIVT_0 (0x1UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000100 */ +#define RCC_PLL2DIVR2_DIVT_1 (0x2UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000200 */ +#define RCC_PLL2DIVR2_DIVT_2 (0x4UL << RCC_PLL2DIVR2_DIVT_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_PLL3DIVR2 register *************/ +#define RCC_PLL3DIVR2_DIVS_Pos (0U) +#define RCC_PLL3DIVR2_DIVS_Msk (0x7UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000007 */ +#define RCC_PLL3DIVR2_DIVS RCC_PLL3DIVR2_DIVS_Msk /*!< DIVS3[2:0] bits: PLL3 DIVS division factor */ +#define RCC_PLL3DIVR2_DIVS_0 (0x1UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000001 */ +#define RCC_PLL3DIVR2_DIVS_1 (0x2UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000002 */ +#define RCC_PLL3DIVR2_DIVS_2 (0x4UL << RCC_PLL3DIVR2_DIVS_Pos) /*!< 0x00000004 */ + +/******************** Bit definition for RCC_PLL1SSCGR register *************/ +#define RCC_PLL1SSCGR_MODPER_Pos (0U) +#define RCC_PLL1SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL1SSCGR_MODPER RCC_PLL1SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL1SSCGR_MODPER_0 (0x0001UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL1SSCGR_MODPER_1 (0x0002UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL1SSCGR_MODPER_2 (0x0004UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL1SSCGR_MODPER_3 (0x0008UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL1SSCGR_MODPER_4 (0x0010UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL1SSCGR_MODPER_5 (0x0020UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL1SSCGR_MODPER_6 (0x0040UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL1SSCGR_MODPER_7 (0x0080UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL1SSCGR_MODPER_8 (0x0100UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL1SSCGR_MODPER_9 (0x0200UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL1SSCGR_MODPER_10 (0x0400UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL1SSCGR_MODPER_11 (0x0800UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL1SSCGR_MODPER_12 (0x1000UL << RCC_PLL1SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL1SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL1SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL1SSCGR_TPDFNDIS RCC_PLL1SSCGR_TPDFNDIS_Msk +#define RCC_PLL1SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL1SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL1SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL1SSCGR_RPDFNDIS RCC_PLL1SSCGR_RPDFNDIS_Msk +#define RCC_PLL1SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL1SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL1SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL1SSCGR_SPREADSEL RCC_PLL1SSCGR_SPREADSEL_Msk +#define RCC_PLL1SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL1SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL1SSCGR_INCSTEP RCC_PLL1SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL1SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL1SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL1SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL1SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL1SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL1SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL1SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL1SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL1SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL1SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL1SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL1SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL1SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL1SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL1SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL2SSCGR register *************/ +#define RCC_PLL2SSCGR_MODPER_Pos (0U) +#define RCC_PLL2SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL2SSCGR_MODPER RCC_PLL2SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL2SSCGR_MODPER_0 (0x0001UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL2SSCGR_MODPER_1 (0x0002UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL2SSCGR_MODPER_2 (0x0004UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL2SSCGR_MODPER_3 (0x0008UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL2SSCGR_MODPER_4 (0x0010UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL2SSCGR_MODPER_5 (0x0020UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL2SSCGR_MODPER_6 (0x0040UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL2SSCGR_MODPER_7 (0x0080UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL2SSCGR_MODPER_8 (0x0100UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL2SSCGR_MODPER_9 (0x0200UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL2SSCGR_MODPER_10 (0x0400UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL2SSCGR_MODPER_11 (0x0800UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL2SSCGR_MODPER_12 (0x1000UL << RCC_PLL2SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL2SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL2SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL2SSCGR_TPDFNDIS RCC_PLL2SSCGR_TPDFNDIS_Msk +#define RCC_PLL2SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL2SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL2SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL2SSCGR_RPDFNDIS RCC_PLL2SSCGR_RPDFNDIS_Msk +#define RCC_PLL2SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL2SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL2SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL2SSCGR_SPREADSEL RCC_PLL2SSCGR_SPREADSEL_Msk +#define RCC_PLL2SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL2SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL2SSCGR_INCSTEP RCC_PLL2SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL2SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL2SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL2SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL2SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL2SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL2SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL2SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL2SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL2SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL2SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL2SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL2SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL2SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL2SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL2SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL2SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL3SSCGR register *************/ +#define RCC_PLL3SSCGR_MODPER_Pos (0U) +#define RCC_PLL3SSCGR_MODPER_Msk (0x1FFFUL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001FFF */ +#define RCC_PLL3SSCGR_MODPER RCC_PLL3SSCGR_MODPER_Msk /*!< MODPER[12:0] bits: Modulation Period Adjustment */ +#define RCC_PLL3SSCGR_MODPER_0 (0x0001UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000001 */ +#define RCC_PLL3SSCGR_MODPER_1 (0x0002UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000002 */ +#define RCC_PLL3SSCGR_MODPER_2 (0x0004UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000004 */ +#define RCC_PLL3SSCGR_MODPER_3 (0x0008UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000008 */ +#define RCC_PLL3SSCGR_MODPER_4 (0x0010UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000010 */ +#define RCC_PLL3SSCGR_MODPER_5 (0x0020UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000020 */ +#define RCC_PLL3SSCGR_MODPER_6 (0x0040UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000040 */ +#define RCC_PLL3SSCGR_MODPER_7 (0x0080UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000080 */ +#define RCC_PLL3SSCGR_MODPER_8 (0x0100UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000100 */ +#define RCC_PLL3SSCGR_MODPER_9 (0x0200UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000200 */ +#define RCC_PLL3SSCGR_MODPER_10 (0x0400UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000400 */ +#define RCC_PLL3SSCGR_MODPER_11 (0x0800UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00000800 */ +#define RCC_PLL3SSCGR_MODPER_12 (0x1000UL << RCC_PLL3SSCGR_MODPER_Pos) /*!< 0x00001000 */ +#define RCC_PLL3SSCGR_TPDFNDIS_Pos (13U) +#define RCC_PLL3SSCGR_TPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_TPDFNDIS_Pos) /*!< 0x00002000 */ +#define RCC_PLL3SSCGR_TPDFNDIS RCC_PLL3SSCGR_TPDFNDIS_Msk +#define RCC_PLL3SSCGR_RPDFNDIS_Pos (14U) +#define RCC_PLL3SSCGR_RPDFNDIS_Msk (0x1UL << RCC_PLL3SSCGR_RPDFNDIS_Pos) /*!< 0x00004000 */ +#define RCC_PLL3SSCGR_RPDFNDIS RCC_PLL3SSCGR_RPDFNDIS_Msk +#define RCC_PLL3SSCGR_SPREADSEL_Pos (15U) +#define RCC_PLL3SSCGR_SPREADSEL_Msk (0x1UL << RCC_PLL3SSCGR_SPREADSEL_Pos) /*!< 0x00008000 */ +#define RCC_PLL3SSCGR_SPREADSEL RCC_PLL3SSCGR_SPREADSEL_Msk +#define RCC_PLL3SSCGR_INCSTEP_Pos (16U) +#define RCC_PLL3SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x7FFF0000 */ +#define RCC_PLL3SSCGR_INCSTEP RCC_PLL3SSCGR_INCSTEP_Msk /*!< INCSTEP[14:0] bits: Modulation Depth Adjustment */ +#define RCC_PLL3SSCGR_INCSTEP_0 (0x0001UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00010000 */ +#define RCC_PLL3SSCGR_INCSTEP_1 (0x0002UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00020000 */ +#define RCC_PLL3SSCGR_INCSTEP_2 (0x0004UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00040000 */ +#define RCC_PLL3SSCGR_INCSTEP_3 (0x0008UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00080000 */ +#define RCC_PLL3SSCGR_INCSTEP_4 (0x0010UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00100000 */ +#define RCC_PLL3SSCGR_INCSTEP_5 (0x0020UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL3SSCGR_INCSTEP_6 (0x0040UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00400000 */ +#define RCC_PLL3SSCGR_INCSTEP_7 (0x0080UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x00800000 */ +#define RCC_PLL3SSCGR_INCSTEP_8 (0x0100UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x01000000 */ +#define RCC_PLL3SSCGR_INCSTEP_9 (0x0200UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x02000000 */ +#define RCC_PLL3SSCGR_INCSTEP_10 (0x0400UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x04000000 */ +#define RCC_PLL3SSCGR_INCSTEP_11 (0x0800UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x08000000 */ +#define RCC_PLL3SSCGR_INCSTEP_12 (0x1000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x10000000 */ +#define RCC_PLL3SSCGR_INCSTEP_13 (0x2000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x20000000 */ +#define RCC_PLL3SSCGR_INCSTEP_14 (0x4000UL << RCC_PLL3SSCGR_INCSTEP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CKPROTR register ***************/ +#define RCC_CKPROTR_XSPICKP_Pos (0U) +#define RCC_CKPROTR_XSPICKP_Msk (0x1UL << RCC_CKPROTR_XSPICKP_Pos) /*!< 0x00000001 */ +#define RCC_CKPROTR_XSPICKP RCC_CKPROTR_XSPICKP_Msk +#define RCC_CKPROTR_FMCCKP_Pos (1U) +#define RCC_CKPROTR_FMCCKP_Msk (0x1UL << RCC_CKPROTR_FMCCKP_Pos) /*!< 0x00000002 */ +#define RCC_CKPROTR_FMCCKP RCC_CKPROTR_FMCCKP_Msk +#define RCC_CKPROTR_XSPI1SWP_Pos (4U) +#define RCC_CKPROTR_XSPI1SWP_Msk (0x7UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000070 */ +#define RCC_CKPROTR_XSPI1SWP RCC_CKPROTR_XSPI1SWP_Msk +#define RCC_CKPROTR_XSPI1SWP_0 (0x1UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000010 */ +#define RCC_CKPROTR_XSPI1SWP_1 (0x2UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000020 */ +#define RCC_CKPROTR_XSPI1SWP_2 (0x4UL << RCC_CKPROTR_XSPI1SWP_Pos) /*!< 0x00000040 */ +#define RCC_CKPROTR_XSPI2SWP_Pos (8U) +#define RCC_CKPROTR_XSPI2SWP_Msk (0x7UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000700 */ +#define RCC_CKPROTR_XSPI2SWP RCC_CKPROTR_XSPI2SWP_Msk +#define RCC_CKPROTR_XSPI2SWP_0 (0x1UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000100 */ +#define RCC_CKPROTR_XSPI2SWP_1 (0x2UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000200 */ +#define RCC_CKPROTR_XSPI2SWP_2 (0x4UL << RCC_CKPROTR_XSPI2SWP_Pos) /*!< 0x00000400 */ +#define RCC_CKPROTR_FMCSWP_Pos (12U) +#define RCC_CKPROTR_FMCSWP_Msk (0x7UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00007000 */ +#define RCC_CKPROTR_FMCSWP RCC_CKPROTR_FMCSWP_Msk +#define RCC_CKPROTR_FMCSWP_0 (0x1UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00001000 */ +#define RCC_CKPROTR_FMCSWP_1 (0x2UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00002000 */ +#define RCC_CKPROTR_FMCSWP_2 (0x4UL << RCC_CKPROTR_FMCSWP_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_RSR register *******************/ +#define RCC_RSR_RMVF_Pos (16U) +#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */ +#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk +#define RCC_RSR_OBLRSTF_Pos (17U) +#define RCC_RSR_OBLRSTF_Msk (0x1UL << RCC_RSR_OBLRSTF_Pos) /*!< 0x00020000 */ +#define RCC_RSR_OBLRSTF RCC_RSR_OBLRSTF_Msk +#define RCC_RSR_BORRSTF_Pos (21U) +#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */ +#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk +#define RCC_RSR_PINRSTF_Pos (22U) +#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */ +#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk +#define RCC_RSR_PORRSTF_Pos (23U) +#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */ +#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk +#define RCC_RSR_SFTRSTF_Pos (24U) +#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */ +#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk +#define RCC_RSR_IWDGRSTF_Pos (26U) +#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */ +#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk +#define RCC_RSR_WWDGRSTF_Pos (28U) +#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */ +#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk +#define RCC_RSR_LPWRRSTF_Pos (30U) +#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */ +#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_AHB1ENR register ***************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (4U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_ADC12EN_Pos (5U) +#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk +#define RCC_AHB1ENR_ETH1MACEN_Pos (15U) +#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk +#define RCC_AHB1ENR_ETH1TXEN_Pos (16U) +#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk +#define RCC_AHB1ENR_ETH1RXEN_Pos (17U) +#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk +#define RCC_AHB1ENR_OTGHSEN_Pos (25U) +#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk +#define RCC_AHB1ENR_USBPHYCEN_Pos (26U) +#define RCC_AHB1ENR_USBPHYCEN_Msk (0x1UL << RCC_AHB1ENR_USBPHYCEN_Pos) /*!< 0x04000000 */ +#define RCC_AHB1ENR_USBPHYCEN RCC_AHB1ENR_USBPHYCEN_Msk +#define RCC_AHB1ENR_OTGFSEN_Pos (27U) +#define RCC_AHB1ENR_OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_OTGFSEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1ENR_OTGFSEN RCC_AHB1ENR_OTGFSEN_Msk +#define RCC_AHB1ENR_ADF1EN_Pos (31U) +#define RCC_AHB1ENR_ADF1EN_Msk (0x1UL << RCC_AHB1ENR_ADF1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_ADF1EN RCC_AHB1ENR_ADF1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register ***************/ +#define RCC_AHB2ENR_PSSIEN_Pos (1U) +#define RCC_AHB2ENR_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_PSSIEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_PSSIEN RCC_AHB2ENR_PSSIEN_Msk +#define RCC_AHB2ENR_SDMMC2EN_Pos (9U) +#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk +#define RCC_AHB2ENR_CORDICEN_Pos (14U) +#define RCC_AHB2ENR_CORDICEN_Msk (0x1UL << RCC_AHB2ENR_CORDICEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2ENR_CORDICEN RCC_AHB2ENR_CORDICEN_Msk +#define RCC_AHB2ENR_SRAM1EN_Pos (29U) +#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB3ENR register ***************/ +#define RCC_AHB3ENR_RNGEN_Pos (0U) +#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk +#define RCC_AHB3ENR_HASHEN_Pos (1U) +#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk +#define RCC_AHB3ENR_CRYPEN_Pos (2U) +#define RCC_AHB3ENR_CRYPEN_Msk (0x1UL << RCC_AHB3ENR_CRYPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3ENR_CRYPEN RCC_AHB3ENR_CRYPEN_Msk +#define RCC_AHB3ENR_SAESEN_Pos (4U) +#define RCC_AHB3ENR_SAESEN_Msk (0x1UL << RCC_AHB3ENR_SAESEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3ENR_SAESEN RCC_AHB3ENR_SAESEN_Msk +#define RCC_AHB3ENR_PKAEN_Pos (6U) +#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk + +/******************** Bit definition for RCC_AHB4ENR register ***************/ +#define RCC_AHB4ENR_GPIOAEN_Pos (0U) +#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk +#define RCC_AHB4ENR_GPIOBEN_Pos (1U) +#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk +#define RCC_AHB4ENR_GPIOCEN_Pos (2U) +#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk +#define RCC_AHB4ENR_GPIODEN_Pos (3U) +#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk +#define RCC_AHB4ENR_GPIOEEN_Pos (4U) +#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk +#define RCC_AHB4ENR_GPIOFEN_Pos (5U) +#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk +#define RCC_AHB4ENR_GPIOGEN_Pos (6U) +#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk +#define RCC_AHB4ENR_GPIOHEN_Pos (7U) +#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk +#define RCC_AHB4ENR_GPIOMEN_Pos (12U) +#define RCC_AHB4ENR_GPIOMEN_Msk (0x1UL << RCC_AHB4ENR_GPIOMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4ENR_GPIOMEN RCC_AHB4ENR_GPIOMEN_Msk +#define RCC_AHB4ENR_GPIONEN_Pos (13U) +#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk +#define RCC_AHB4ENR_GPIOOEN_Pos (14U) +#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk +#define RCC_AHB4ENR_GPIOPEN_Pos (15U) +#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk +#define RCC_AHB4ENR_CRCEN_Pos (19U) +#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk +#define RCC_AHB4ENR_BKPRAMEN_Pos (28U) +#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk + +/******************** Bit definition for RCC_AHB5ENR register ***************/ +#define RCC_AHB5ENR_HPDMA1EN_Pos (0U) +#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk +#define RCC_AHB5ENR_DMA2DEN_Pos (1U) +#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk +#define RCC_AHB5ENR_JPEGEN_Pos (3U) +#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk +#define RCC_AHB5ENR_FMCEN_Pos (4U) +#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk +#define RCC_AHB5ENR_XSPI1EN_Pos (5U) +#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk +#define RCC_AHB5ENR_SDMMC1EN_Pos (8U) +#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk +#define RCC_AHB5ENR_XSPI2EN_Pos (12U) +#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk +#define RCC_AHB5ENR_XSPIMEN_Pos (14U) +#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk +#define RCC_AHB5ENR_GFXMMUEN_Pos (19U) +#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_TIM4EN_Pos (2U) +#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ +#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk +#define RCC_APB1ENR1_TIM5EN_Pos (3U) +#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ +#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk +#define RCC_APB1ENR1_TIM6EN_Pos (4U) +#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ +#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk +#define RCC_APB1ENR1_TIM7EN_Pos (5U) +#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk +#define RCC_APB1ENR1_TIM12EN_Pos (6U) +#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */ +#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk +#define RCC_APB1ENR1_TIM13EN_Pos (7U) +#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */ +#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk +#define RCC_APB1ENR1_TIM14EN_Pos (8U) +#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk +#define RCC_APB1ENR1_LPTIM1EN_Pos (9U) +#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */ +#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_SPI2EN_Pos (14U) +#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ +#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk +#define RCC_APB1ENR1_SPI3EN_Pos (15U) +#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ +#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk +#define RCC_APB1ENR1_SPDIFRXEN_Pos (16U) +#define RCC_APB1ENR1_SPDIFRXEN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRXEN_Pos) /*!< 0x00010000 */ +#define RCC_APB1ENR1_SPDIFRXEN RCC_APB1ENR1_SPDIFRXEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_USART3EN_Pos (18U) +#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ +#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk +#define RCC_APB1ENR1_UART4EN_Pos (19U) +#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ +#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk +#define RCC_APB1ENR1_UART5EN_Pos (20U) +#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk +#define RCC_APB1ENR1_I2C1_I3C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1_I3C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1_I3C1EN RCC_APB1ENR1_I2C1_I3C1EN_Msk +#define RCC_APB1ENR1_I2C2EN_Pos (22U) +#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ +#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk +#define RCC_APB1ENR1_I2C3EN_Pos (23U) +#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ +#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk +#define RCC_APB1ENR1_CECEN_Pos (27U) +#define RCC_APB1ENR1_CECEN_Msk (0x1UL << RCC_APB1ENR1_CECEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR1_CECEN RCC_APB1ENR1_CECEN_Msk +#define RCC_APB1ENR1_UART7EN_Pos (30U) +#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */ +#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk +#define RCC_APB1ENR1_UART8EN_Pos (31U) +#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */ +#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_CRSEN_Pos (1U) +#define RCC_APB1ENR2_CRSEN_Msk (0x1UL << RCC_APB1ENR2_CRSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR2_CRSEN RCC_APB1ENR2_CRSEN_Msk +#define RCC_APB1ENR2_MDIOSEN_Pos (5U) +#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk +#define RCC_APB1ENR2_FDCANEN_Pos (8U) +#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk +#define RCC_APB1ENR2_UCPD1EN_Pos (27U) +#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x08000000 */ +#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk + +/******************** Bit definition for RCC_APB2ENR register ***************/ +#define RCC_APB2ENR_TIM1EN_Pos (0U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (4U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_SPI4EN_Pos (13U) +#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ +#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk +#define RCC_APB2ENR_TIM15EN_Pos (16U) +#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ +#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_TIM9EN_Pos (19U) +#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */ +#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk +#define RCC_APB2ENR_SPI5EN_Pos (20U) +#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ +#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (22U) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk +#define RCC_APB2ENR_SAI2EN_Pos (23U) +#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */ +#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk + +/******************** Bit definition for RCC_APB4ENR register ***************/ +#define RCC_APB4ENR_SBSEN_Pos (1U) +#define RCC_APB4ENR_SBSEN_Msk (0x1UL << RCC_APB4ENR_SBSEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4ENR_SBSEN RCC_APB4ENR_SBSEN_Msk +#define RCC_APB4ENR_LPUART1EN_Pos (3U) +#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */ +#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk +#define RCC_APB4ENR_SPI6EN_Pos (5U) +#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */ +#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk +#define RCC_APB4ENR_LPTIM2EN_Pos (9U) +#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */ +#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk +#define RCC_APB4ENR_LPTIM3EN_Pos (10U) +#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */ +#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk +#define RCC_APB4ENR_LPTIM4EN_Pos (11U) +#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */ +#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk +#define RCC_APB4ENR_LPTIM5EN_Pos (12U) +#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */ +#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk +#define RCC_APB4ENR_VREFEN_Pos (15U) +#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk +#define RCC_APB4ENR_RTCAPBEN_Pos (16U) +#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk +#define RCC_APB4ENR_DTSEN_Pos (26U) +#define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk + +/******************** Bit definition for RCC_APB5ENR register ***************/ +#define RCC_APB5ENR_DCMIPPEN_Pos (2U) +#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk +#define RCC_APB5ENR_GFXTIMEN_Pos (4U) +#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk + +/******************** Bit definition for RCC_AHB1LPENR register *************/ +#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4U) +#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk +#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U) +#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk +#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U) +#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk +#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U) +#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk +#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U) +#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk +#define RCC_AHB1LPENR_UCPDCTRL_Pos (24U) +#define RCC_AHB1LPENR_UCPDCTRL_Msk (0x1UL << RCC_AHB1LPENR_UCPDCTRL_Pos) /*!< 0x01000000 */ +#define RCC_AHB1LPENR_UCPDCTRL RCC_AHB1LPENR_UCPDCTRL_Msk +#define RCC_AHB1LPENR_OTGHSLPEN_Pos (25U) +#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x02000000 */ +#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk +#define RCC_AHB1LPENR_USBPHYCLPEN_Pos (26U) +#define RCC_AHB1LPENR_USBPHYCLPEN_Msk (0x1UL << RCC_AHB1LPENR_USBPHYCLPEN_Pos)/*!< 0x04000000 */ +#define RCC_AHB1LPENR_USBPHYCLPEN RCC_AHB1LPENR_USBPHYCLPEN_Msk +#define RCC_AHB1LPENR_OTGFSLPEN_Pos (27U) +#define RCC_AHB1LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGFSLPEN_Pos) /*!< 0x08000000 */ +#define RCC_AHB1LPENR_OTGFSLPEN RCC_AHB1LPENR_OTGFSLPEN_Msk +#define RCC_AHB1LPENR_ADF1LPEN_Pos (31U) +#define RCC_AHB1LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADF1LPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1LPENR_ADF1LPEN RCC_AHB1LPENR_ADF1LPEN_Msk + +/******************** Bit definition for RCC_AHB2LPENR register *************/ +#define RCC_AHB2LPENR_PSSILPEN_Pos (1U) +#define RCC_AHB2LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_PSSILPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2LPENR_PSSILPEN RCC_AHB2LPENR_PSSILPEN_Msk +#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U) +#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk +#define RCC_AHB2LPENR_CORDICLPEN_Pos (14U) +#define RCC_AHB2LPENR_CORDICLPEN_Msk (0x1UL << RCC_AHB2LPENR_CORDICLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB2LPENR_CORDICLPEN RCC_AHB2LPENR_CORDICLPEN_Msk +#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U) +#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk +#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U) +#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk + +/******************** Bit definition for RCC_AHB3LPENR register *************/ +#define RCC_AHB3LPENR_RNGLPEN_Pos (0U) +#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk +#define RCC_AHB3LPENR_HASHLPEN_Pos (1U) +#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk +#define RCC_AHB3LPENR_CRYPLPEN_Pos (2U) +#define RCC_AHB3LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB3LPENR_CRYPLPEN RCC_AHB3LPENR_CRYPLPEN_Msk +#define RCC_AHB3LPENR_SAESLPEN_Pos (4U) +#define RCC_AHB3LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB3LPENR_SAESLPEN RCC_AHB3LPENR_SAESLPEN_Msk +#define RCC_AHB3LPENR_PKALPEN_Pos (6U) +#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk + +/******************** Bit definition for RCC_AHB4LPENR register *************/ +#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U) +#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk +#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U) +#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk +#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U) +#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk +#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U) +#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk +#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U) +#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk +#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U) +#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk +#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U) +#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk +#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U) +#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk +#define RCC_AHB4LPENR_GPIOMLPEN_Pos (12U) +#define RCC_AHB4LPENR_GPIOMLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOMLPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB4LPENR_GPIOMLPEN RCC_AHB4LPENR_GPIOMLPEN_Msk +#define RCC_AHB4LPENR_GPIONLPEN_Pos (13U) +#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos) /*!< 0x00002000 */ +#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk +#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14U) +#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk +#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15U) +#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos) /*!< 0x00008000 */ +#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk +#define RCC_AHB4LPENR_CRCLPEN_Pos (19U) +#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk +#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U) +#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk + +/******************** Bit definition for RCC_AHB5LPENR register *************/ +#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0U) +#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk +#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1U) +#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk +#define RCC_AHB5LPENR_FLASHLPEN_Pos (2U) +#define RCC_AHB5LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB5LPENR_FLASHLPEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB5LPENR_FLASHLPEN RCC_AHB5LPENR_FLASHLPEN_Msk +#define RCC_AHB5LPENR_JPEGLPEN_Pos (3U) +#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */ +#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk +#define RCC_AHB5LPENR_FMCLPEN_Pos (4U) +#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */ +#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk +#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5U) +#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos) /*!< 0x00000020 */ +#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk +#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8U) +#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk +#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12U) +#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk +#define RCC_AHB5LPENR_XSPIMLPEN_Pos (14U) +#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos) /*!< 0x00004000 */ +#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk +#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19U) +#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk +#define RCC_AHB5LPENR_DTCM1LPEN_Pos (28U) +#define RCC_AHB5LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */ +#define RCC_AHB5LPENR_DTCM1LPEN RCC_AHB5LPENR_DTCM1LPEN_Msk +#define RCC_AHB5LPENR_DTCM2LPEN_Pos (29U) +#define RCC_AHB5LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB5LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB5LPENR_DTCM2LPEN RCC_AHB5LPENR_DTCM2LPEN_Msk +#define RCC_AHB5LPENR_ITCMLPEN_Pos (30U) +#define RCC_AHB5LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB5LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB5LPENR_ITCMLPEN RCC_AHB5LPENR_ITCMLPEN_Msk +#define RCC_AHB5LPENR_AXISRAMLPEN_Pos (31U) +#define RCC_AHB5LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB5LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB5LPENR_AXISRAMLPEN RCC_AHB5LPENR_AXISRAMLPEN_Msk + +/******************** Bit definition for RCC_APB1LPENR1 register ************/ +#define RCC_APB1LPENR1_TIM2LPEN_Pos (0U) +#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk +#define RCC_APB1LPENR1_TIM3LPEN_Pos (1U) +#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk +#define RCC_APB1LPENR1_TIM4LPEN_Pos (2U) +#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk +#define RCC_APB1LPENR1_TIM5LPEN_Pos (3U) +#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos) /*!< 0x00000008 */ +#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk +#define RCC_APB1LPENR1_TIM6LPEN_Pos (4U) +#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk +#define RCC_APB1LPENR1_TIM7LPEN_Pos (5U) +#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk +#define RCC_APB1LPENR1_TIM12LPEN_Pos (6U) +#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */ +#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk +#define RCC_APB1LPENR1_TIM13LPEN_Pos (7U) +#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */ +#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk +#define RCC_APB1LPENR1_TIM14LPEN_Pos (8U) +#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk +#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9U) +#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos)/*!< 0x00000200 */ +#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk +#define RCC_APB1LPENR1_WWDGLPEN_Pos (11U) +#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk +#define RCC_APB1LPENR1_SPI2LPEN_Pos (14U) +#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos) /*!< 0x00004000 */ +#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk +#define RCC_APB1LPENR1_SPI3LPEN_Pos (15U) +#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk +#define RCC_APB1LPENR1_SPDIFRXLPEN_Pos (16U) +#define RCC_APB1LPENR1_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRXLPEN_Pos)/*!< 0x00010000 */ +#define RCC_APB1LPENR1_SPDIFRXLPEN RCC_APB1LPENR1_SPDIFRXLPEN_Msk +#define RCC_APB1LPENR1_USART2LPEN_Pos (17U) +#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos)/*!< 0x00020000 */ +#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk +#define RCC_APB1LPENR1_USART3LPEN_Pos (18U) +#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos)/*!< 0x00040000 */ +#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk +#define RCC_APB1LPENR1_UART4LPEN_Pos (19U) +#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk +#define RCC_APB1LPENR1_UART5LPEN_Pos (20U) +#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos (21U) +#define RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1_I3C1LPEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1LPENR1_I2C1_I3C1LPEN RCC_APB1LPENR1_I2C1_I3C1LPEN_Msk +#define RCC_APB1LPENR1_I2C2LPEN_Pos (22U) +#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk +#define RCC_APB1LPENR1_I2C3LPEN_Pos (23U) +#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk +#define RCC_APB1LPENR1_CECLPEN_Pos (27U) +#define RCC_APB1LPENR1_CECLPEN_Msk (0x1UL << RCC_APB1LPENR1_CECLPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR1_CECLPEN RCC_APB1LPENR1_CECLPEN_Msk +#define RCC_APB1LPENR1_UART7LPEN_Pos (30U) +#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */ +#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk +#define RCC_APB1LPENR1_UART8LPEN_Pos (31U) +#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */ +#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk + +/******************** Bit definition for RCC_PB1LPENR2 register ************/ +#define RCC_APB1LPENR2_CRSLPEN_Pos (1U) +#define RCC_APB1LPENR2_CRSLPEN_Msk (0x1UL << RCC_APB1LPENR2_CRSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1LPENR2_CRSLPEN RCC_APB1LPENR2_CRSLPEN_Msk +#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5U) +#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk +#define RCC_APB1LPENR2_FDCANLPEN_Pos (8U) +#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */ +#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk +#define RCC_APB1LPENR2_UCPD1LPEN_Pos (27U) +#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x08000000 */ +#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk + +/******************** Bit definition for RCC_APB2LPENR register *************/ +#define RCC_APB2LPENR_TIM1LPEN_Pos (0U) +#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ +#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk +#define RCC_APB2LPENR_USART1LPEN_Pos (4U) +#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk +#define RCC_APB2LPENR_SPI1LPEN_Pos (12U) +#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk +#define RCC_APB2LPENR_SPI4LPEN_Pos (13U) +#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ +#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk +#define RCC_APB2LPENR_TIM15LPEN_Pos (16U) +#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk +#define RCC_APB2LPENR_TIM16LPEN_Pos (17U) +#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk +#define RCC_APB2LPENR_TIM17LPEN_Pos (18U) +#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk +#define RCC_APB2LPENR_TIM9LPEN_Pos (19U) +#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */ +#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk +#define RCC_APB2LPENR_SPI5LPEN_Pos (20U) +#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ +#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk +#define RCC_APB2LPENR_SAI1LPEN_Pos (22U) +#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */ +#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk +#define RCC_APB2LPENR_SAI2LPEN_Pos (23U) +#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */ +#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk + +/******************** Bit definition for RCC_APB4LPENR register *************/ +#define RCC_APB4LPENR_SBSLPEN_Pos (1U) +#define RCC_APB4LPENR_SBSLPEN_Msk (0x1UL << RCC_APB4LPENR_SBSLPEN_Pos) /*!< 0x00000002 */ +#define RCC_APB4LPENR_SBSLPEN RCC_APB4LPENR_SBSLPEN_Msk +#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U) +#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)/*!< 0x00000008 */ +#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk +#define RCC_APB4LPENR_SPI6LPEN_Pos (5U) +#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */ +#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk +#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U) +#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */ +#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk +#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U) +#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */ +#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk +#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U) +#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */ +#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk +#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U) +#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */ +#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk +#define RCC_APB4LPENR_VREFLPEN_Pos (15U) +#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk +#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U) +#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */ +#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk +#define RCC_APB4LPENR_DTSLPEN_Pos (26U) +#define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */ +#define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk + +/******************** Bit definition for RCC_APB5LPENR register *************/ +#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2U) +#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */ +#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk +#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4U) +#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */ +#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Secure Advanced Encryption Standard (SAES) */ +/* */ +/******************************************************************************/ +/******************* Bits definition for SAES_CR register *********************/ +#define SAES_CR_EN_Pos (0U) +#define SAES_CR_EN_Msk (0x1UL << SAES_CR_EN_Pos) /*!< 0x00000001 */ +#define SAES_CR_EN SAES_CR_EN_Msk /*!< SAES Enable */ +#define SAES_CR_DATATYPE_Pos (1U) +#define SAES_CR_DATATYPE_Msk (0x3UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define SAES_CR_DATATYPE SAES_CR_DATATYPE_Msk /*!< Data type selection */ +#define SAES_CR_DATATYPE_0 (0x1UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define SAES_CR_DATATYPE_1 (0x2UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define SAES_CR_MODE_Pos (3U) +#define SAES_CR_MODE_Msk (0x3UL << SAES_CR_MODE_Pos) /*!< 0x00000018 */ +#define SAES_CR_MODE SAES_CR_MODE_Msk /*!< SAES Mode Of Operation */ +#define SAES_CR_MODE_0 (0x1UL << SAES_CR_MODE_Pos) /*!< 0x00000008 */ +#define SAES_CR_MODE_1 (0x2UL << SAES_CR_MODE_Pos) /*!< 0x00000010 */ +#define SAES_CR_CHMOD_Pos (5U) +#define SAES_CR_CHMOD_Msk (0x803UL << SAES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define SAES_CR_CHMOD SAES_CR_CHMOD_Msk /*!< SAES Chaining Mode */ +#define SAES_CR_CHMOD_0 (0x001UL << SAES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define SAES_CR_CHMOD_1 (0x002UL << SAES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define SAES_CR_CHMOD_2 (0x800UL << SAES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define SAES_CR_DMAINEN_Pos (11U) +#define SAES_CR_DMAINEN_Msk (0x1UL << SAES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define SAES_CR_DMAINEN SAES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define SAES_CR_DMAOUTEN_Pos (12U) +#define SAES_CR_DMAOUTEN_Msk (0x1UL << SAES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define SAES_CR_DMAOUTEN SAES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define SAES_CR_GCMPH_Pos (13U) +#define SAES_CR_GCMPH_Msk (0x3UL << SAES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define SAES_CR_GCMPH SAES_CR_GCMPH_Msk /*!< GCM Phase */ +#define SAES_CR_GCMPH_0 (0x1UL << SAES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define SAES_CR_GCMPH_1 (0x2UL << SAES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define SAES_CR_KEYSIZE_Pos (18U) +#define SAES_CR_KEYSIZE_Msk (0x1UL << SAES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define SAES_CR_KEYSIZE SAES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define SAES_CR_NPBLB_Pos (20U) +#define SAES_CR_NPBLB_Msk (0xFUL << SAES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define SAES_CR_NPBLB SAES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define SAES_CR_NPBLB_0 (0x1UL << SAES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define SAES_CR_NPBLB_1 (0x2UL << SAES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define SAES_CR_NPBLB_2 (0x4UL << SAES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define SAES_CR_NPBLB_3 (0x8UL << SAES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define SAES_CR_KMOD_Pos (24U) +#define SAES_CR_KMOD_Msk (0x3UL << SAES_CR_KMOD_Pos) /*!< 0x00000006 */ +#define SAES_CR_KMOD SAES_CR_KMOD_Msk /*!< Key mode selection */ +#define SAES_CR_KMOD_0 (0x1UL << SAES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define SAES_CR_KMOD_1 (0x2UL << SAES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define SAES_CR_KSHAREID_Pos (26U) +#define SAES_CR_KSHAREID_Msk (0x3UL << SAES_CR_KSHAREID_Pos) /*!< 0x00000006 */ +#define SAES_CR_KSHAREID SAES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define SAES_CR_KEYSEL_Pos (28U) +#define SAES_CR_KEYSEL_Msk (0x7UL << SAES_CR_KEYSEL_Pos) /*!< 0x00000006 */ +#define SAES_CR_KEYSEL SAES_CR_KEYSEL_Msk /*!< Key Selection */ +#define SAES_CR_KEYSEL_0 (0x1UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_KEYSEL_1 (0x2UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_KEYSEL_2 (0x4UL << SAES_CR_KEYSEL_Pos) /*!< 0x02000000 */ +#define SAES_CR_IPRST_Pos (31U) +#define SAES_CR_IPRST_Msk (0x1UL << SAES_CR_IPRST_Pos) /*!< 0x80000001 */ +#define SAES_CR_IPRST SAES_CR_IPRST_Msk /*!< SAES IP software reset */ + +/******************* Bits definition for SAES_SR register *********************/ +#define SAES_SR_CCF_Pos (0U) +#define SAES_SR_CCF_Msk (0x1UL << SAES_SR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_SR_CCF SAES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define SAES_SR_RDERR_Pos (1U) +#define SAES_SR_RDERR_Msk (0x1UL << SAES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define SAES_SR_RDERR SAES_SR_RDERR_Msk /*!< Read Error Flag */ +#define SAES_SR_WRERR_Pos (2U) +#define SAES_SR_WRERR_Msk (0x1UL << SAES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define SAES_SR_WRERR SAES_SR_WRERR_Msk /*!< Write Error Flag */ +#define SAES_SR_BUSY_Pos (3U) +#define SAES_SR_BUSY_Msk (0x1UL << SAES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define SAES_SR_BUSY SAES_SR_BUSY_Msk /*!< Busy Flag */ +#define SAES_SR_KEYVALID_Pos (7U) +#define SAES_SR_KEYVALID_Msk (0x1UL << SAES_SR_KEYVALID_Pos) /*!< 0x00000008 */ +#define SAES_SR_KEYVALID SAES_SR_KEYVALID_Msk /*!< KEYVALID Flag */ + +/******************* Bits definition for SAES_DINR register *******************/ +#define SAES_DINR_Pos (0U) +#define SAES_DINR_Msk (0xFFFFFFFFUL << SAES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DINR SAES_DINR_Msk /*!< SAES Data Input Register */ + +/******************* Bits definition for SAES_DOUTR register ******************/ +#define SAES_DOUTR_Pos (0U) +#define SAES_DOUTR_Msk (0xFFFFFFFFUL << SAES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define SAES_DOUTR SAES_DOUTR_Msk /*!< SAES Data Output Register */ + +/******************* Bits definition for SAES_KEYR0 register ******************/ +#define SAES_KEYR0_Pos (0U) +#define SAES_KEYR0_Msk (0xFFFFFFFFUL << SAES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR0 SAES_KEYR0_Msk /*!< SAES Key Register 0 */ + +/******************* Bits definition for SAES_KEYR1 register ******************/ +#define SAES_KEYR1_Pos (0U) +#define SAES_KEYR1_Msk (0xFFFFFFFFUL << SAES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR1 SAES_KEYR1_Msk /*!< SAES Key Register 1 */ + +/******************* Bits definition for SAES_KEYR2 register ******************/ +#define SAES_KEYR2_Pos (0U) +#define SAES_KEYR2_Msk (0xFFFFFFFFUL << SAES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR2 SAES_KEYR2_Msk /*!< SAES Key Register 2 */ + +/******************* Bits definition for SAES_KEYR3 register ******************/ +#define SAES_KEYR3_Pos (0U) +#define SAES_KEYR3_Msk (0xFFFFFFFFUL << SAES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR3 SAES_KEYR3_Msk /*!< SAES Key Register 3 */ + +/******************* Bits definition for SAES_KEYR4 register ******************/ +#define SAES_KEYR4_Pos (0U) +#define SAES_KEYR4_Msk (0xFFFFFFFFUL << SAES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR4 SAES_KEYR4_Msk /*!< SAES Key Register 4 */ + +/******************* Bits definition for SAES_KEYR5 register ******************/ +#define SAES_KEYR5_Pos (0U) +#define SAES_KEYR5_Msk (0xFFFFFFFFUL << SAES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR5 SAES_KEYR5_Msk /*!< SAES Key Register 5 */ + +/******************* Bits definition for SAES_KEYR6 register ******************/ +#define SAES_KEYR6_Pos (0U) +#define SAES_KEYR6_Msk (0xFFFFFFFFUL << SAES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR6 SAES_KEYR6_Msk /*!< SAES Key Register 6 */ + +/******************* Bits definition for SAES_KEYR7 register ******************/ +#define SAES_KEYR7_Pos (0U) +#define SAES_KEYR7_Msk (0xFFFFFFFFUL << SAES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define SAES_KEYR7 SAES_KEYR7_Msk /*!< SAES Key Register 7 */ + +/******************* Bits definition for SAES_IVR0 register ******************/ +#define SAES_IVR0_Pos (0U) +#define SAES_IVR0_Msk (0xFFFFFFFFUL << SAES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR0 SAES_IVR0_Msk /*!< SAES Initialization Vector Register 0 */ + +/******************* Bits definition for SAES_IVR1 register ******************/ +#define SAES_IVR1_Pos (0U) +#define SAES_IVR1_Msk (0xFFFFFFFFUL << SAES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR1 SAES_IVR1_Msk /*!< SAES Initialization Vector Register 1 */ + +/******************* Bits definition for SAES_IVR2 register ******************/ +#define SAES_IVR2_Pos (0U) +#define SAES_IVR2_Msk (0xFFFFFFFFUL << SAES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR2 SAES_IVR2_Msk /*!< SAES Initialization Vector Register 2 */ + +/******************* Bits definition for SAES_IVR3 register ******************/ +#define SAES_IVR3_Pos (0U) +#define SAES_IVR3_Msk (0xFFFFFFFFUL << SAES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define SAES_IVR3 SAES_IVR3_Msk /*!< SAES Initialization Vector Register 3 */ + +/******************* Bit definition for SAES_SUSP0R register ******************/ +#define SAES_SUSP0R_Pos (0U) +#define SAES_SUSP0R_Msk (0xFFFFFFFFUL << SAES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP0R SAES_SUSP0R_Msk /*!< SAES Suspend registers 0 */ + +/******************* Bit definition for SAES_SUSP1R register ******************/ +#define SAES_SUSP1R_Pos (0U) +#define SAES_SUSP1R_Msk (0xFFFFFFFFUL << SAES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP1R SAES_SUSP1R_Msk /*!< SAES Suspend registers 1 */ + +/******************* Bit definition for SAES_SUSP2R register ******************/ +#define SAES_SUSP2R_Pos (0U) +#define SAES_SUSP2R_Msk (0xFFFFFFFFUL << SAES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP2R SAES_SUSP2R_Msk /*!< SAES Suspend registers 2 */ + +/******************* Bit definition for SAES_SUSP3R register ******************/ +#define SAES_SUSP3R_Pos (0U) +#define SAES_SUSP3R_Msk (0xFFFFFFFFUL << SAES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP3R SAES_SUSP3R_Msk /*!< SAES Suspend registers 3 */ + +/******************* Bit definition for SAES_SUSP4R register ******************/ +#define SAES_SUSP4R_Pos (0U) +#define SAES_SUSP4R_Msk (0xFFFFFFFFUL << SAES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP4R SAES_SUSP4R_Msk /*!< SAES Suspend registers 4 */ + +/******************* Bit definition for SAES_SUSP5R register ******************/ +#define SAES_SUSP5R_Pos (0U) +#define SAES_SUSP5R_Msk (0xFFFFFFFFUL << SAES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP5R SAES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for SAES_SUSP6R register ******************/ +#define SAES_SUSP6R_Pos (0U) +#define SAES_SUSP6R_Msk (0xFFFFFFFFUL << SAES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP6R SAES_SUSP6R_Msk /*!< SAES Suspend registers 6 */ + +/******************* Bit definition for SAES_SUSP7R register ******************/ +#define SAES_SUSP7R_Pos (0U) +#define SAES_SUSP7R_Msk (0xFFFFFFFFUL << SAES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define SAES_SUSP7R SAES_SUSP7R_Msk /*!< SAES Suspend registers 7 */ + +/******************* Bits definition for SAES_IER register ******************/ +#define SAES_IER_CCFIE_Pos (0U) +#define SAES_IER_CCFIE_Msk (0x1UL << SAES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define SAES_IER_CCFIE SAES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define SAES_IER_RWEIE_Pos (1U) +#define SAES_IER_RWEIE_Msk (0x1UL << SAES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define SAES_IER_RWEIE SAES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define SAES_IER_KEIE_Pos (2U) +#define SAES_IER_KEIE_Msk (0x1UL << SAES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define SAES_IER_KEIE SAES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define SAES_IER_RNGEIE_Pos (3U) +#define SAES_IER_RNGEIE_Msk (0x1UL << SAES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define SAES_IER_RNGEIE SAES_IER_RNGEIE_Msk /*!< Rng error interrupt enable */ + +/******************* Bits definition for SAES_ISR register ******************/ +#define SAES_ISR_CCF_Pos (0U) +#define SAES_ISR_CCF_Msk (0x1UL << SAES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ISR_CCF SAES_ISR_CCF_Msk /*!< Computation complete flag */ +#define SAES_ISR_RWEIF_Pos (1U) +#define SAES_ISR_RWEIF_Msk (0x1UL << SAES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ISR_RWEIF SAES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define SAES_ISR_KEIF_Pos (2U) +#define SAES_ISR_KEIF_Msk (0x1UL << SAES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ISR_KEIF SAES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define SAES_ISR_RNGEIF_Pos (3U) +#define SAES_ISR_RNGEIF_Msk (0x1UL << SAES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ISR_RNGEIF SAES_ISR_RNGEIF_Msk /*!< Rng error interrupt flag */ + +/******************* Bits definition for SAES_ICR register ******************/ +#define SAES_ICR_CCF_Pos (0U) +#define SAES_ICR_CCF_Msk (0x1UL << SAES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define SAES_ICR_CCF SAES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define SAES_ICR_RWEIF_Pos (1U) +#define SAES_ICR_RWEIF_Msk (0x1UL << SAES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define SAES_ICR_RWEIF SAES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define SAES_ICR_KEIF_Pos (2U) +#define SAES_ICR_KEIF_Msk (0x1UL << SAES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define SAES_ICR_KEIF SAES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define SAES_ICR_RNGEIF_Pos (3U) +#define SAES_ICR_RNGEIF_Msk (0x1UL << SAES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define SAES_ICR_RNGEIF SAES_ICR_RNGEIF_Msk /*!< Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/ARM/gcc_clang/linker_scripts/stm/stm32h7s3z8.ld b/ARM/gcc_clang/linker_scripts/stm/stm32h7s3z8.ld new file mode 100644 index 000000000..16783afba --- /dev/null +++ b/ARM/gcc_clang/linker_scripts/stm/stm32h7s3z8.ld @@ -0,0 +1,208 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7Sxx Device +** 64Kbytes FLASH +** 456Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +__FLASH_BEGIN = 0x08000000; +__FLASH_SIZE = 0x00010000; + + +__RAM_BEGIN = 0x24000000; +__RAM_SIZE = 0x71C00; +__RAM_NONCACHEABLEBUFFER_SIZE = 0x400; + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = __RAM_BEGIN, LENGTH = __RAM_SIZE + RAM_NONCACHEABLEBUFFER (xrw) : ORIGIN = __RAM_BEGIN + __RAM_SIZE, LENGTH = __RAM_NONCACHEABLEBUFFER_SIZE + + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 0x00010000 + DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 + SRAMAHB (rw) : ORIGIN = 0x30000000, LENGTH = 0x00008000 + BKPSRAM (rw) : ORIGIN = 0x38800000, LENGTH = 0x00001000 + + FLASH (xrw) : ORIGIN = __FLASH_BEGIN, LENGTH = __FLASH_SIZE +} + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCM) + LENGTH(DTCM); /* end of Ram type memory */ + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + RW_NONCACHEABLE : + { + __NONCACHEABLEBUFFER_BEGIN = .;/* create symbol for start of section */ + KEEP(*(noncacheable_buffer)) + __NONCACHEABLEBUFFER_END = .; /* create symbol for start of section */ + } > RAM_NONCACHEABLEBUFFER + + /* User_heap_stack section, used to check that there is enough Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/ARM/gcc_clang/startup/stm/stm32h7s3v8.s b/ARM/gcc_clang/startup/stm/stm32h7s3v8.s new file mode 100644 index 000000000..ae3cd3487 --- /dev/null +++ b/ARM/gcc_clang/startup/stm/stm32h7s3v8.s @@ -0,0 +1,766 @@ +/** + ****************************************************************************** + * @file startup_stm32h7s3xx.s + * @author MCD Application Team + * @brief STM32H7S3xx Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + // bl SystemInit /* Removed call for Mikroe implementation. */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl clockConfig /* Added to call MikroE system clock configuration API. */ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32H7S3xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* Digital Temperature Sensor */ + .word IWDG_IRQHandler /* Internal Watchdog */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FLASH_IRQHandler /* FLASH interrupts */ + .word RAMECC_IRQHandler /* RAMECC interrupts */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word EXTI5_IRQHandler /* EXTI Line5 */ + .word EXTI6_IRQHandler /* EXTI Line6 */ + .word EXTI7_IRQHandler /* EXTI Line7 */ + .word EXTI8_IRQHandler /* EXTI Line8 */ + .word EXTI9_IRQHandler /* EXTI Line9 */ + .word EXTI10_IRQHandler /* EXTI Line10 */ + .word EXTI11_IRQHandler /* EXTI Line11 */ + .word EXTI12_IRQHandler /* EXTI Line12 */ + .word EXTI13_IRQHandler /* EXTI Line13 */ + .word EXTI14_IRQHandler /* EXTI Line14 */ + .word EXTI15_IRQHandler /* EXTI Line15 */ + .word RTC_IRQHandler /* RTC wakeup and alarm interrupts */ + .word SAES_IRQHandler /* SAES */ + .word CRYP_IRQHandler /* CRYP */ + .word PKA_IRQHandler /* PKA */ + .word HASH_IRQHandler /* HASH */ + .word RNG_IRQHandler /* RNG */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */ + .word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */ + .word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */ + .word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */ + .word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */ + .word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */ + .word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */ + .word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM9_IRQHandler /* TIM9 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word SPI3_IRQHandler /* SPI3 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */ + .word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */ + .word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */ + .word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */ + .word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */ + .word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */ + .word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */ + .word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */ + .word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */ + .word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */ + .word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */ + .word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word I2C3_EV_IRQHandler /* I2C3 Event */ + .word I2C3_ER_IRQHandler /* I2C3 Error */ + .word UART1_IRQHandler /* UART1 */ + .word UART2_IRQHandler /* UART2 */ + .word UART3_IRQHandler /* UART3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word I3C1_EV_IRQHandler /* I3C1 Event */ + .word I3C1_ER_IRQHandler /* I3C1 Error */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word ETH_IRQHandler /* Ethernet */ + .word CORDIC_IRQHandler /* CORDIC */ + .word GFXTIM_IRQHandler /* GFXTIM */ + .word DCMIPP_IRQHandler /* DCMIPP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2D_IRQHandler /* DMA2D */ + .word JPEG_IRQHandler /* JPEG */ + .word GFXMMU_IRQHandler /* GFXMMU */ + .word I3C1_WKUP_IRQHandler /* I3C1 wakeup */ + .word MCE1_IRQHandler /* MCE1 */ + .word MCE2_IRQHandler /* MCE2 */ + .word MCE3_IRQHandler /* MCE3 */ + .word XSPI1_IRQHandler /* XSPI1 */ + .word XSPI2_IRQHandler /* XSPI2 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word TIM12_IRQHandler /* TIM12 */ + .word TIM13_IRQHandler /* TIM13 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word LPTIM1_IRQHandler /* LP TIM1 */ + .word LPTIM2_IRQHandler /* LP TIM2 */ + .word LPTIM3_IRQHandler /* LP TIM3 */ + .word LPTIM4_IRQHandler /* LP TIM4 */ + .word LPTIM5_IRQHandler /* LP TIM5 */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word MDIOS_IRQHandler /* MDIOS */ + .word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */ + .word CRS_IRQHandler /* CRS */ + .word UCPD1_IRQHandler /* UCPD1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word PSSI_IRQHandler /* PSSI */ + .word LPUART1_IRQHandler /* LP UART1 */ + .word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */ + .word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */ + .word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */ + .word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */ + .word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */ + .word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */ + .word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */ + .word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */ + .word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */ + .word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */ + .word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */ + .word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */ + .word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */ + .word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */ + .word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */ + .word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */ + .word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RAMECC_IRQHandler + .thumb_set RAMECC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel0_IRQHandler + .thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler + + .weak HPDMA1_Channel1_IRQHandler + .thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler + + .weak HPDMA1_Channel2_IRQHandler + .thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler + + .weak HPDMA1_Channel3_IRQHandler + .thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler + + .weak HPDMA1_Channel4_IRQHandler + .thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler + + .weak HPDMA1_Channel5_IRQHandler + .thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler + + .weak HPDMA1_Channel6_IRQHandler + .thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel7_IRQHandler + .thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler + + .weak SAI1_A_IRQHandler + .thumb_set SAI1_A_IRQHandler,Default_Handler + + .weak SAI1_B_IRQHandler + .thumb_set SAI1_B_IRQHandler,Default_Handler + + .weak SAI2_A_IRQHandler + .thumb_set SAI2_A_IRQHandler,Default_Handler + + .weak SAI2_B_IRQHandler + .thumb_set SAI2_B_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak GFXTIM_IRQHandler + .thumb_set GFXTIM_IRQHandler,Default_Handler + + .weak DCMIPP_IRQHandler + .thumb_set DCMIPP_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak I3C1_WKUP_IRQHandler + .thumb_set I3C1_WKUP_IRQHandler,Default_Handler + + .weak MCE1_IRQHandler + .thumb_set MCE1_IRQHandler,Default_Handler + + .weak MCE2_IRQHandler + .thumb_set MCE2_IRQHandler,Default_Handler + + .weak MCE3_IRQHandler + .thumb_set MCE3_IRQHandler,Default_Handler + + .weak XSPI1_IRQHandler + .thumb_set XSPI1_IRQHandler,Default_Handler + + .weak XSPI2_IRQHandler + .thumb_set XSPI2_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak ADF1_FLT0_IRQHandler + .thumb_set ADF1_FLT0_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak PSSI_IRQHandler + .thumb_set PSSI_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak GPDMA1_Channel12_IRQHandler + .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler + + .weak GPDMA1_Channel13_IRQHandler + .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler + + .weak GPDMA1_Channel14_IRQHandler + .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler + + .weak GPDMA1_Channel15_IRQHandler + .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler + + .weak HPDMA1_Channel8_IRQHandler + .thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler + + .weak HPDMA1_Channel9_IRQHandler + .thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler + + .weak HPDMA1_Channel10_IRQHandler + .thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler + + .weak HPDMA1_Channel11_IRQHandler + .thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler + + .weak HPDMA1_Channel12_IRQHandler + .thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler + + .weak HPDMA1_Channel13_IRQHandler + .thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler + + .weak HPDMA1_Channel14_IRQHandler + .thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler + + .weak HPDMA1_Channel15_IRQHandler + .thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak SystemInit diff --git a/ARM/gcc_clang/startup/stm/stm32h7s3z8.s b/ARM/gcc_clang/startup/stm/stm32h7s3z8.s new file mode 100644 index 000000000..ae3cd3487 --- /dev/null +++ b/ARM/gcc_clang/startup/stm/stm32h7s3z8.s @@ -0,0 +1,766 @@ +/** + ****************************************************************************** + * @file startup_stm32h7s3xx.s + * @author MCD Application Team + * @brief STM32H7S3xx Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + // bl SystemInit /* Removed call for Mikroe implementation. */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl clockConfig /* Added to call MikroE system clock configuration API. */ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The STM32H7S3xx vector table. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + /* External Interrupts */ + .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* Digital Temperature Sensor */ + .word IWDG_IRQHandler /* Internal Watchdog */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word RCC_IRQHandler /* RCC global interrupts through EXTI Line detection */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FLASH_IRQHandler /* FLASH interrupts */ + .word RAMECC_IRQHandler /* RAMECC interrupts */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TAMP_IRQHandler /* Tamper and TimeStamp interrupts */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word EXTI5_IRQHandler /* EXTI Line5 */ + .word EXTI6_IRQHandler /* EXTI Line6 */ + .word EXTI7_IRQHandler /* EXTI Line7 */ + .word EXTI8_IRQHandler /* EXTI Line8 */ + .word EXTI9_IRQHandler /* EXTI Line9 */ + .word EXTI10_IRQHandler /* EXTI Line10 */ + .word EXTI11_IRQHandler /* EXTI Line11 */ + .word EXTI12_IRQHandler /* EXTI Line12 */ + .word EXTI13_IRQHandler /* EXTI Line13 */ + .word EXTI14_IRQHandler /* EXTI Line14 */ + .word EXTI15_IRQHandler /* EXTI Line15 */ + .word RTC_IRQHandler /* RTC wakeup and alarm interrupts */ + .word SAES_IRQHandler /* SAES */ + .word CRYP_IRQHandler /* CRYP */ + .word PKA_IRQHandler /* PKA */ + .word HASH_IRQHandler /* HASH */ + .word RNG_IRQHandler /* RNG */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word GPDMA1_Channel0_IRQHandler /* GPDMA1 Channel 0 */ + .word GPDMA1_Channel1_IRQHandler /* GPDMA1 Channel 1 */ + .word GPDMA1_Channel2_IRQHandler /* GPDMA1 Channel 2 */ + .word GPDMA1_Channel3_IRQHandler /* GPDMA1 Channel 3 */ + .word GPDMA1_Channel4_IRQHandler /* GPDMA1 Channel 4 */ + .word GPDMA1_Channel5_IRQHandler /* GPDMA1 Channel 5 */ + .word GPDMA1_Channel6_IRQHandler /* GPDMA1 Channel 6 */ + .word GPDMA1_Channel7_IRQHandler /* GPDMA1 Channel 7 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word TIM5_IRQHandler /* TIM5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM9_IRQHandler /* TIM9 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word SPI3_IRQHandler /* SPI3 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word HPDMA1_Channel0_IRQHandler /* HPDMA1 Channel 0 */ + .word HPDMA1_Channel1_IRQHandler /* HPDMA1 Channel 1 */ + .word HPDMA1_Channel2_IRQHandler /* HPDMA1 Channel 2 */ + .word HPDMA1_Channel3_IRQHandler /* HPDMA1 Channel 3 */ + .word HPDMA1_Channel4_IRQHandler /* HPDMA1 Channel 4 */ + .word HPDMA1_Channel5_IRQHandler /* HPDMA1 Channel 5 */ + .word HPDMA1_Channel6_IRQHandler /* HPDMA1 Channel 6 */ + .word HPDMA1_Channel7_IRQHandler /* HPDMA1 Channel 7 */ + .word SAI1_A_IRQHandler /* Serial Audio Interface 1 block A */ + .word SAI1_B_IRQHandler /* Serial Audio Interface 1 block B */ + .word SAI2_A_IRQHandler /* Serial Audio Interface 2 block A */ + .word SAI2_B_IRQHandler /* Serial Audio Interface 2 block B */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word I2C3_EV_IRQHandler /* I2C3 Event */ + .word I2C3_ER_IRQHandler /* I2C3 Error */ + .word UART1_IRQHandler /* UART1 */ + .word UART2_IRQHandler /* UART2 */ + .word UART3_IRQHandler /* UART3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word I3C1_EV_IRQHandler /* I3C1 Event */ + .word I3C1_ER_IRQHandler /* I3C1 Error */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word ETH_IRQHandler /* Ethernet */ + .word CORDIC_IRQHandler /* CORDIC */ + .word GFXTIM_IRQHandler /* GFXTIM */ + .word DCMIPP_IRQHandler /* DCMIPP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2D_IRQHandler /* DMA2D */ + .word JPEG_IRQHandler /* JPEG */ + .word GFXMMU_IRQHandler /* GFXMMU */ + .word I3C1_WKUP_IRQHandler /* I3C1 wakeup */ + .word MCE1_IRQHandler /* MCE1 */ + .word MCE2_IRQHandler /* MCE2 */ + .word MCE3_IRQHandler /* MCE3 */ + .word XSPI1_IRQHandler /* XSPI1 */ + .word XSPI2_IRQHandler /* XSPI2 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word TIM12_IRQHandler /* TIM12 */ + .word TIM13_IRQHandler /* TIM13 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word LPTIM1_IRQHandler /* LP TIM1 */ + .word LPTIM2_IRQHandler /* LP TIM2 */ + .word LPTIM3_IRQHandler /* LP TIM3 */ + .word LPTIM4_IRQHandler /* LP TIM4 */ + .word LPTIM5_IRQHandler /* LP TIM5 */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word MDIOS_IRQHandler /* MDIOS */ + .word ADF1_FLT0_IRQHandler /* ADF1 Filter 0 */ + .word CRS_IRQHandler /* CRS */ + .word UCPD1_IRQHandler /* UCPD1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word PSSI_IRQHandler /* PSSI */ + .word LPUART1_IRQHandler /* LP UART1 */ + .word WAKEUP_PIN_IRQHandler /* Wake-up pins interrupt */ + .word GPDMA1_Channel8_IRQHandler /* GPDMA1 Channel 8 */ + .word GPDMA1_Channel9_IRQHandler /* GPDMA1 Channel 9 */ + .word GPDMA1_Channel10_IRQHandler /* GPDMA1 Channel 10 */ + .word GPDMA1_Channel11_IRQHandler /* GPDMA1 Channel 11 */ + .word GPDMA1_Channel12_IRQHandler /* GPDMA1 Channel 12 */ + .word GPDMA1_Channel13_IRQHandler /* GPDMA1 Channel 13 */ + .word GPDMA1_Channel14_IRQHandler /* GPDMA1 Channel 14 */ + .word GPDMA1_Channel15_IRQHandler /* GPDMA1 Channel 15 */ + .word HPDMA1_Channel8_IRQHandler /* HPDMA1 Channel 8 */ + .word HPDMA1_Channel9_IRQHandler /* HPDMA1 Channel 9 */ + .word HPDMA1_Channel10_IRQHandler /* HPDMA1 Channel 10 */ + .word HPDMA1_Channel11_IRQHandler /* HPDMA1 Channel 11 */ + .word HPDMA1_Channel12_IRQHandler /* HPDMA1 Channel 12 */ + .word HPDMA1_Channel13_IRQHandler /* HPDMA1 Channel 13 */ + .word HPDMA1_Channel14_IRQHandler /* HPDMA1 Channel 14 */ + .word HPDMA1_Channel15_IRQHandler /* HPDMA1 Channel 15 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RAMECC_IRQHandler + .thumb_set RAMECC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel0_IRQHandler + .thumb_set HPDMA1_Channel0_IRQHandler,Default_Handler + + .weak HPDMA1_Channel1_IRQHandler + .thumb_set HPDMA1_Channel1_IRQHandler,Default_Handler + + .weak HPDMA1_Channel2_IRQHandler + .thumb_set HPDMA1_Channel2_IRQHandler,Default_Handler + + .weak HPDMA1_Channel3_IRQHandler + .thumb_set HPDMA1_Channel3_IRQHandler,Default_Handler + + .weak HPDMA1_Channel4_IRQHandler + .thumb_set HPDMA1_Channel4_IRQHandler,Default_Handler + + .weak HPDMA1_Channel5_IRQHandler + .thumb_set HPDMA1_Channel5_IRQHandler,Default_Handler + + .weak HPDMA1_Channel6_IRQHandler + .thumb_set HPDMA1_Channel6_IRQHandler,Default_Handler + + .weak HPDMA1_Channel7_IRQHandler + .thumb_set HPDMA1_Channel7_IRQHandler,Default_Handler + + .weak SAI1_A_IRQHandler + .thumb_set SAI1_A_IRQHandler,Default_Handler + + .weak SAI1_B_IRQHandler + .thumb_set SAI1_B_IRQHandler,Default_Handler + + .weak SAI2_A_IRQHandler + .thumb_set SAI2_A_IRQHandler,Default_Handler + + .weak SAI2_B_IRQHandler + .thumb_set SAI2_B_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak UART1_IRQHandler + .thumb_set UART1_IRQHandler,Default_Handler + + .weak UART2_IRQHandler + .thumb_set UART2_IRQHandler,Default_Handler + + .weak UART3_IRQHandler + .thumb_set UART3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak I3C1_EV_IRQHandler + .thumb_set I3C1_EV_IRQHandler,Default_Handler + + .weak I3C1_ER_IRQHandler + .thumb_set I3C1_ER_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak GFXTIM_IRQHandler + .thumb_set GFXTIM_IRQHandler,Default_Handler + + .weak DCMIPP_IRQHandler + .thumb_set DCMIPP_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak I3C1_WKUP_IRQHandler + .thumb_set I3C1_WKUP_IRQHandler,Default_Handler + + .weak MCE1_IRQHandler + .thumb_set MCE1_IRQHandler,Default_Handler + + .weak MCE2_IRQHandler + .thumb_set MCE2_IRQHandler,Default_Handler + + .weak MCE3_IRQHandler + .thumb_set MCE3_IRQHandler,Default_Handler + + .weak XSPI1_IRQHandler + .thumb_set XSPI1_IRQHandler,Default_Handler + + .weak XSPI2_IRQHandler + .thumb_set XSPI2_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak TIM12_IRQHandler + .thumb_set TIM12_IRQHandler,Default_Handler + + .weak TIM13_IRQHandler + .thumb_set TIM13_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak ADF1_FLT0_IRQHandler + .thumb_set ADF1_FLT0_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak PSSI_IRQHandler + .thumb_set PSSI_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak GPDMA1_Channel8_IRQHandler + .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler + + .weak GPDMA1_Channel9_IRQHandler + .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler + + .weak GPDMA1_Channel10_IRQHandler + .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler + + .weak GPDMA1_Channel11_IRQHandler + .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler + + .weak GPDMA1_Channel12_IRQHandler + .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler + + .weak GPDMA1_Channel13_IRQHandler + .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler + + .weak GPDMA1_Channel14_IRQHandler + .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler + + .weak GPDMA1_Channel15_IRQHandler + .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler + + .weak HPDMA1_Channel8_IRQHandler + .thumb_set HPDMA1_Channel8_IRQHandler,Default_Handler + + .weak HPDMA1_Channel9_IRQHandler + .thumb_set HPDMA1_Channel9_IRQHandler,Default_Handler + + .weak HPDMA1_Channel10_IRQHandler + .thumb_set HPDMA1_Channel10_IRQHandler,Default_Handler + + .weak HPDMA1_Channel11_IRQHandler + .thumb_set HPDMA1_Channel11_IRQHandler,Default_Handler + + .weak HPDMA1_Channel12_IRQHandler + .thumb_set HPDMA1_Channel12_IRQHandler,Default_Handler + + .weak HPDMA1_Channel13_IRQHandler + .thumb_set HPDMA1_Channel13_IRQHandler,Default_Handler + + .weak HPDMA1_Channel14_IRQHandler + .thumb_set HPDMA1_Channel14_IRQHandler,Default_Handler + + .weak HPDMA1_Channel15_IRQHandler + .thumb_set HPDMA1_Channel15_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak SystemInit diff --git a/ARM/gcc_clang/system/src/stm/doc_ds_193_3/init_clock.c b/ARM/gcc_clang/system/src/stm/doc_ds_193_3/init_clock.c new file mode 100644 index 000000000..cf234226c --- /dev/null +++ b/ARM/gcc_clang/system/src/stm/doc_ds_193_3/init_clock.c @@ -0,0 +1,46 @@ +/**************************************************************************** +** +** Copyright (C) 2024 MikroElektronika d.o.o. +** Contact: https://www.mikroe.com/contact +** +** Commercial License Usage +** +** Licensees holding valid commercial NECTO compilers AI licenses may use this +** file in accordance with the commercial license agreement provided with the +** Software or, alternatively, in accordance with the terms contained in +** a written agreement between you and The MikroElektronika Company. +** For licensing terms and conditions see +** https://www.mikroe.com/legal/software-license-agreement. +** For further information use the contact form at +** https://www.mikroe.com/contact. +** +** +** GNU Lesser General Public License Usage +** +** Alternatively, this file may be used for +** non-commercial projects under the terms of the GNU Lesser +** General Public License version 3 as published by the Free Software +** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html. +** +** The above copyright notice and this permission notice shall be +** included in all copies or substantial portions of the Software. +** +** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +** OF MERCHANTABILITY, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +** TO THE WARRANTIES FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, +** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT +** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +** +****************************************************************************/ +/*! + * @file init_clock.c + * @brief Mikroe clock initialization API. + */ + +#include "core_header.h" + +void clockConfig(void) { + // TODO +} diff --git a/changelog/2024-10-09.md b/changelog/2024-10-09.md new file mode 100644 index 000000000..b7a587457 --- /dev/null +++ b/changelog/2024-10-09.md @@ -0,0 +1,23 @@ +

+ MikroElektronika +

+ +--- + +# 2024-10-08 + +## Changes + ++ [2024-10-08](#2024-10-08) + + [Changes](#changes) + + [NEW HARDWARE](#new-hardware) + +### NEW HARDWARE + +Support added for following hardware: + ++ STM32H7S3V8_Z8 MCU Support package for GCC & Clang + + STM32H7S3V8 + + STM32H7S3Z8 + +--- diff --git a/resources/queries/mcus/STM32H7S3V8/Devices.json b/resources/queries/mcus/STM32H7S3V8/Devices.json new file mode 100644 index 000000000..e38be8cec --- /dev/null +++ b/resources/queries/mcus/STM32H7S3V8/Devices.json @@ -0,0 +1,17 @@ +{ + "def_file":"STM32H7S3V8.json", + "family_uid":"STM32", + "flash":"64", + "icon":"images/mcu/stm32.png", + "max_speed":"550.000", + "name":"STM32H7S3V8", + "ram":"634880", + "sdk_config":"{\"MCU_NAME\":\"STM32H7S3V8\",\"CORE_NAME\":\"M7\",\"_MSDK_HAL_LOW_LEVEL_TARGET_\":\"mikroe\",\"_MSDK_ETH_PHY_CHIP_\":\"NULL\"}", + "necto_config":"", + "uid":"STM32H7S3V8", + "vendor":"STMicroelectronics", + "compiler_flags":"", + "linker_flags":"", + "tft_socket":"1", + "sdk_support":"0" +} diff --git a/resources/queries/mcus/STM32H7S3V8/LinkerTables.json b/resources/queries/mcus/STM32H7S3V8/LinkerTables.json new file mode 100644 index 000000000..90029b737 --- /dev/null +++ b/resources/queries/mcus/STM32H7S3V8/LinkerTables.json @@ -0,0 +1,37 @@ +{ + "device_uid": "STM32H7S3V8", + "tables": [ + { + "BoardToDevice": { + "board_uid": ["GENERIC_ARM_BOARD"] + } + }, + { + "CompilerToDevice": { + "compiler_uid": [ + "clang-llvm", + "gcc_arm_none_eabi" + ] + } + }, + { + "DeviceToPackage": { + "package_uid": [ + "100/LQFP", + "100/TFBGA", + "101/WLCSP" + ] + } + }, + { + "DeviceToSocket": { + "socket_uid": ["NONE"] + } + }, + { + "SDKToDevice": { + "sdk_uid": "2.11.3+" + } + } + ] +} diff --git a/resources/queries/mcus/STM32H7S3Z8/Devices.json b/resources/queries/mcus/STM32H7S3Z8/Devices.json new file mode 100644 index 000000000..6f3ae8e41 --- /dev/null +++ b/resources/queries/mcus/STM32H7S3Z8/Devices.json @@ -0,0 +1,17 @@ +{ + "def_file":"STM32H7S3Z8.json", + "family_uid":"STM32", + "flash":"64", + "icon":"images/mcu/stm32.png", + "max_speed":"550.000", + "name":"STM32H7S3Z8", + "ram":"634880", + "sdk_config":"{\"MCU_NAME\":\"STM32H7S3Z8\",\"CORE_NAME\":\"M7\",\"_MSDK_HAL_LOW_LEVEL_TARGET_\":\"mikroe\",\"_MSDK_ETH_PHY_CHIP_\":\"NULL\"}", + "necto_config":"", + "uid":"STM32H7S3Z8", + "vendor":"STMicroelectronics", + "compiler_flags":"", + "linker_flags":"", + "tft_socket":"1", + "sdk_support":"0" +} diff --git a/resources/queries/mcus/STM32H7S3Z8/LinkerTables.json b/resources/queries/mcus/STM32H7S3Z8/LinkerTables.json new file mode 100644 index 000000000..765abc933 --- /dev/null +++ b/resources/queries/mcus/STM32H7S3Z8/LinkerTables.json @@ -0,0 +1,36 @@ +{ + "device_uid": "STM32H7S3Z8", + "tables": [ + { + "BoardToDevice": { + "board_uid": ["GENERIC_ARM_BOARD"] + } + }, + { + "CompilerToDevice": { + "compiler_uid": [ + "clang-llvm", + "gcc_arm_none_eabi" + ] + } + }, + { + "DeviceToPackage": { + "package_uid": [ + "144/UFBGA", + "144/LQFP" + ] + } + }, + { + "DeviceToSocket": { + "socket_uid": ["NONE"] + } + }, + { + "SDKToDevice": { + "sdk_uid": "2.11.3+" + } + } + ] +}