Where do syntax errors get flagged in the API? #730
kcameron4456
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You can iterate over the diagnostics returned by the diagnostics() function |
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The way I'm using the parser, it seems to accept almost anything without generating an error message.
Here's a simple example:
This produces the output:
root node = module A; ee3 endmodule
How do I get slang to fully enforce SystemVerilog syntax rules?
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