I guess I'm missing something

[kcameron4456]

Hi gang,

I'm interested to see if I can write a viable System Verilog simulator. I stumbled upon slang and it look s like it might be a good choice for me. I've been experimenting with simple test code to see if I can see some life and get accustomed to the resultant structures. Unfortunately, I haven't seen any life yet. I'm sure someone here can easily see what I'm doing wrong.

Here's my stuff:

Test.cpp:

#include <slang/driver/Driver.h>
#include <iostream>

using namespace std;
using namespace slang::driver;

int main (int argc, char **argv) {
        slang::driver::Driver Dr;
        if ((Dr.parseCommandLine(argc, argv)) != 0)
                exit (1);
        if (!Dr.parseAllSources())
                exit (2);
        return 0;
}

YYY.v:
module YYY (a, b, c);
    input  [3:0] a, b;
    output [3:0] c;
    wire c = a ^ b;
endmodule

Result:                                                                                                                                                                               
$ 
$ slang --version
slang version 2.0.220+3d991afd
$ 
$ g++ -I ~/.local/eda/slang/include -L /home/kcameron/.local/eda/slang/lib64 -o Test Test.cpp -lsvlang -lfmt
$ 
$ Test YYY.v
terminate called after throwing an instance of 'std::runtime_error'
  what():  No options defined
Abort (core dumped)

I don't understand the error. What options are missing?

[MikePopoloski]

You're calling parseCommandLine but haven't defined any arguments to be parsed. You can call addStandardArgs to get the default ones, or define some of your own, or both.

[kcameron4456]

Got it. Thanks!