Question: How to extract binds from SystemVerilog AST using slang?

[yadu-kr]

Sorry if this is the wrong place to start this thread, but I needed some pointers.

I'm currently working with slang as a dependent library on a project that needs the binds to be extracted from a SystemVerilog model and then consumed as a dictionary for further processing. Previously, the AST and binds were generated using PyVerilog. Binds are the edges of the syntax tree, but they also include operators, concat and deconcat info.

I want to switch out PyVerilog for slang for the extended language support as well as shorter run times. I have gone through the slang repo and generated the ASTs for models, the problem I have now is the extraction of binds from the syntax tree.

Could I get some help on where to start working or which class I should begin looking at?

[MikePopoloski]

I'm not sure I understand what a "bind" is; your explanation does not provide much info. If you're just operating on the syntax level then it's straightforward to walk the syntax tree in slang, visit the nodes, and do whatever you want with each node. The SyntaxVisitor class can help with that. Note that the "SyntaxTree" in slang is the concrete syntax tree.

If you need name lookup, type resolution, generates evaluated, etc then you need the abstract syntax tree. You would start by adding your parsed concrete SyntaxTrees to a Compilation object. Compilation has a getRoot() method which gives you the root of the hierarchy and from there you can walk the tree to again, find whatever you want. ASTVisitor can help with that.