Future directions and VHDL support

[Blebowski]

Hello @MikePopoloski ,

I was wondering what are your future plans for slang ? Do you want to start
writing simulation backend ? Or rather extend it to become universal "front-end"
(sort-of open-source alternative to Verific parser ?

Longer time ago, I was asking about simulation, and I have read some discussion
where you shared your plan to start writing simulation codegen with LLVM.
Seeing all the development in tools like Verilator and NVC, I realize two things:

• There is plenty of open-source simulation already
• Mixed language stuff is what is really missing in the OS domain.

Verilator has no mainline support of VHDL / Mixed language.
NVC author has started only very recently on adding Verilog support.

On the synthesis side, I have seen that Yosys started to put together yosys-slang
as a front-end. AFAIK, yosys supports VHDL only via ghdl-yosys plugin.
I am wondering if it would not be more beneficial to have VHDL parsing + elaboration
already in Slang...

What are your thoughts on adding VHDL support ?

[MikePopoloski]

I'm not against having VHDL support in slang but it's not something I'm personally very interested in working on. Additionally while I'm sure there is plenty of infrastructure in slang that would make a VHDL parser easier to write, it's not like most of slang would be reusable -- it's very specifically trying to capture SystemVerilog grammar and semantics.

I've been thinking about the next layer to add in slang (after the AST). Some kind of MLIR-based thing seems appropriate; that might be a better thing to target for the common layer than slang's AST. The guys over in the CIRCT project are doing interesting things there (and using slang as a frontend for Verilog input). I guess if you were to start adding VHDL parsing in slang it would require some substantial reorganization to deemphasize the Verilog aspects.

[Blebowski]

I currently do not plan to start working on adding VHDL due to lack of time. Although, if that was not the case,
I would really like to :)
When I have time, I try to contribute to: NVC where the author recently started
to add Verilog support.

As for the "HW IIR", I dont have clear opinion on that. On one hand, it seems good approach from compiler theory,
and is backed by how LLVM is doing it in SW. On the other hand, the variability of follow-up processing of such IIR
is much higher for HW languanges. Simulator will likely use IIR to generate some executable code. Synthesizer will
likely transform IIR to a graph and do mapping. Formal tools will translate IIR to set of formulas and run SAT
solver on that. I don't know if it is feasible to do one IIR for every possible "outcome". In SW, all backends are program
instructions executed on a machine. In HW, the outcome is much more variable. So, it seems to me that the format of
HDLs that is then usable by all the follow-up backend-applications (syn,sim,formal) is just elaborated mixed language AST
exactly as verific provides in their commercial solution. But I am a compiler rookie, so I can be completely off.

I know there exist many projects that attempt to do similar things. CIRCT, MLIR, LLHD, UHDM all seem to me to provide
the HW IIR. It is little bit disappointing that none of them is then used by an OS tool for either sim,syn or formal that would
have capabilities and usability comparable to commercial alternatives. That is why I was asking about VHDL support.
Commercial tools have good mixed language support, and eventually, it is always needed to have mixed language.
So it seemed to me, if there was something like verific, just open-source, it would be easier to integrate such frontend
by various OS EDA tools, and reaching commerical level "usability".

Btw. thanks for the fix with the timing check.