key_filter.vt

`timescale 1 ns/ 1 ps
module key_filter_vlg_tst();

reg clk;
reg key_in;
reg rst_n;
// wires                                               

wire isPress;

                        
key_filter i1 (
	.clk(clk),
	.key_in(key_in),
	.rst_n(rst_n),
    .isPress(isPress)
);
initial                                                
begin                                                  
    clk = 1'b1;
    rst_n = 1'b0;
    key_in = 1'b1;

    #50;
    rst_n = 1'b1;

    #20_000_000;
    key_in = 1'b0;
    #40_000_000;
    key_in = 1'b1;
    #20_000_000;
    $stop;                               
end                                                    
always                                                 
begin                                                  
    #10;
    clk = ~clk;                                                       
end                                                    
endmodule