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sd.c
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sd.c
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/* Driver for Realtek PCI-Express card reader
*
* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http:
*
* Author:
* wwang ([email protected])
* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
*/
#include <linux/blkdev.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include "rtsx.h"
#include "rtsx_transport.h"
#include "rtsx_scsi.h"
#include "rtsx_card.h"
#include "sd.h"
#define SD_MAX_RETRY_COUNT 3
#define RX_TUNING_CNT 3
#define TX_TUNING_CNT 3
static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
{
struct sd_info *sd_card = &(chip->sd_card);
sd_card->err_code |= err_code;
}
static inline void sd_clr_err_code(struct rtsx_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
sd_card->err_code = 0;
}
static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
{
struct sd_info *sd_card = &(chip->sd_card);
return (sd_card->err_code & err_code);
}
static int sd_check_data0_status(struct rtsx_chip *chip)
{
u8 stat;
RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
if (!(stat & SD_DAT0_STATUS)) {
sd_set_err_code(chip, SD_BUSY);
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
int timeout = 100;
u16 reg_addr;
u8 *ptr;
int stat_idx = 0;
int rty_cnt = 0;
sd_clr_err_code(chip);
RTSX_DEBUGP(("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg));
if (rsp_type == SD_RSP_TYPE_R1b) {
timeout = 3000;
}
RTY_SEND_CMD:
rtsx_init_cmd(chip);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
0x01, PINGPONG_BUFFER);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER,
0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
rtsx_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER,
SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE);
if (rsp_type == SD_RSP_TYPE_R2) {
for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr ++) {
rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
}
stat_idx = 16;
} else if (rsp_type != SD_RSP_TYPE_R0) {
for (reg_addr = SD_CMD0; reg_addr <= SD_CMD4; reg_addr ++) {
rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
}
stat_idx = 5;
}
rtsx_add_cmd(chip, READ_REG_CMD, SD_STAT1, 0, 0);
retval = rtsx_send_cmd(chip, SD_CARD, timeout);
if (retval < 0) {
u8 val;
rtsx_read_register(chip, SD_STAT1, &val);
RTSX_DEBUGP(("SD_STAT1: 0x%x\n", val));
rtsx_read_register(chip, SD_STAT2, &val);
RTSX_DEBUGP(("SD_STAT2: 0x%x\n", val));
if (val & SD_RSP_80CLK_TIMEOUT) {
rtsx_clear_sd_error(chip);
sd_set_err_code(chip, SD_RSP_TIMEOUT);
TRACE_RET(chip, STATUS_FAIL);
}
rtsx_read_register(chip, SD_BUS_STAT, &val);
RTSX_DEBUGP(("SD_BUS_STAT: 0x%x\n", val));
if (retval == -ETIMEDOUT) {
if (rsp_type & SD_WAIT_BUSY_END) {
retval = sd_check_data0_status(chip);
if (retval != STATUS_SUCCESS) {
rtsx_clear_sd_error(chip);
TRACE_RET(chip, retval);
}
} else {
sd_set_err_code(chip, SD_TO_ERR);
}
retval = STATUS_TIMEDOUT;
} else {
retval = STATUS_FAIL;
}
rtsx_clear_sd_error(chip);
TRACE_RET(chip, retval);
}
if (rsp_type == SD_RSP_TYPE_R0) {
return STATUS_SUCCESS;
}
ptr = rtsx_get_cmd_data(chip) + 1;
if ((ptr[0] & 0xC0) != 0) {
sd_set_err_code(chip, SD_STS_ERR);
TRACE_RET(chip, STATUS_FAIL);
}
if (!(rsp_type & SD_NO_CHECK_CRC7)) {
if (ptr[stat_idx] & SD_CRC7_ERR) {
if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
sd_set_err_code(chip, SD_CRC_ERR);
TRACE_RET(chip, STATUS_FAIL);
}
if (rty_cnt < SD_MAX_RETRY_COUNT) {
wait_timeout(20);
rty_cnt ++;
goto RTY_SEND_CMD;
} else {
sd_set_err_code(chip, SD_CRC_ERR);
TRACE_RET(chip, STATUS_FAIL);
}
}
}
if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
if ((cmd_idx != SEND_RELATIVE_ADDR) && (cmd_idx != SEND_IF_COND)) {
if (cmd_idx != STOP_TRANSMISSION) {
if (ptr[1] & 0x80) {
TRACE_RET(chip, STATUS_FAIL);
}
}
#ifdef SUPPORT_SD_LOCK
if (ptr[1] & 0x7D)
#else
if (ptr[1] & 0x7F)
#endif
{
RTSX_DEBUGP(("ptr[1]: 0x%02x\n", ptr[1]));
TRACE_RET(chip, STATUS_FAIL);
}
if (ptr[2] & 0xFF) {
RTSX_DEBUGP(("ptr[2]: 0x%02x\n", ptr[2]));
TRACE_RET(chip, STATUS_FAIL);
}
if (ptr[3] & 0x80) {
RTSX_DEBUGP(("ptr[3]: 0x%02x\n", ptr[3]));
TRACE_RET(chip, STATUS_FAIL);
}
if (ptr[3] & 0x01) {
sd_card->sd_data_buf_ready = 1;
} else {
sd_card->sd_data_buf_ready = 0;
}
}
}
if (rsp && rsp_len) {
memcpy(rsp, ptr, rsp_len);
}
return STATUS_SUCCESS;
}
static inline void sd_print_debug_reg(struct rtsx_chip *chip)
{
#if DBG
u8 val;
rtsx_read_register(chip, SD_STAT1, &val);
RTSX_DEBUGP(("SD_STAT1: 0x%x\n", val));
rtsx_read_register(chip, SD_STAT2, &val);
RTSX_DEBUGP(("SD_STAT2: 0x%x\n", val));
rtsx_read_register(chip, SD_BUS_STAT, &val);
RTSX_DEBUGP(("SD_BUS_STAT: 0x%x\n", val));
rtsx_read_register(chip, SD_CMD0, &val);
RTSX_DEBUGP(("SD_CMD0: 0x%02x\n", val));
rtsx_read_register(chip, SD_CMD1, &val);
RTSX_DEBUGP(("SD_CMD1: 0x%02x\n", val));
rtsx_read_register(chip, SD_CMD2, &val);
RTSX_DEBUGP(("SD_CMD2: 0x%02x\n", val));
rtsx_read_register(chip, SD_CMD3, &val);
RTSX_DEBUGP(("SD_CMD3: 0x%02x\n", val));
rtsx_read_register(chip, SD_CMD4, &val);
RTSX_DEBUGP(("SD_CMD4: 0x%02x\n", val));
rtsx_read_register(chip, SD_CMD5, &val);
RTSX_DEBUGP(("SD_CMD5: 0x%02x\n", val));
rtsx_read_register(chip, SD_TRANSFER, &val);
RTSX_DEBUGP(("SD_TRANSFER: 0x%02x\n", val));
rtsx_read_register(chip, SD_BLOCK_CNT_L, &val);
RTSX_DEBUGP(("SD_BLOCK_CNT_L: 0x%02x\n", val));
rtsx_read_register(chip, SD_BLOCK_CNT_H, &val);
RTSX_DEBUGP(("SD_BLOCK_CNT_H: 0x%02x\n", val));
#endif
}
static int sd_read_data(struct rtsx_chip *chip, u8 trans_mode, u8 *cmd, int cmd_len,
u16 byte_cnt, u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len, int timeout)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
int i;
sd_clr_err_code(chip);
if (!buf) {
buf_len = 0;
}
if (buf_len && (buf_len > PPBUF_LEN)) {
TRACE_RET(chip, STATUS_FAIL);
}
rtsx_init_cmd(chip);
if (cmd_len) {
RTSX_DEBUGP(("SD/MMC CMD %d\n", cmd[0] - 0x40));
for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
}
}
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, bus_width);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
SD_CHECK_CRC7 | SD_RSP_LEN_6);
if (trans_mode != SD_TM_AUTO_TUNING) {
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
}
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
rtsx_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
retval = rtsx_send_cmd(chip, SD_CARD, timeout);
if (retval < 0) {
sd_print_debug_reg(chip);
if (retval == -ETIMEDOUT) {
sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
}
TRACE_RET(chip, STATUS_FAIL);
}
if (buf && buf_len) {
retval = rtsx_read_ppbuf(chip, buf, buf_len);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
}
return STATUS_SUCCESS;
}
static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width,
u8 *buf, int buf_len, int timeout)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
int i;
sd_clr_err_code(chip);
if (!buf) {
buf_len = 0;
}
if (buf_len > PPBUF_LEN) {
TRACE_RET(chip, STATUS_FAIL);
}
if (buf && buf_len) {
retval = rtsx_write_ppbuf(chip, buf, buf_len);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
}
rtsx_init_cmd(chip);
if (cmd_len) {
RTSX_DEBUGP(("SD/MMC CMD %d\n", cmd[0] - 0x40));
for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
}
}
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, bus_width);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CFG2, 0xFF,
SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
SD_CHECK_CRC7 | SD_RSP_LEN_6);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
rtsx_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
retval = rtsx_send_cmd(chip, SD_CARD, timeout);
if (retval < 0) {
sd_print_debug_reg(chip);
if (retval == -ETIMEDOUT) {
sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
}
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
int i;
u8 csd_ver, trans_speed;
u8 rsp[16];
for (i = 0; i < 6; i++) {
if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
sd_set_err_code(chip, SD_NO_CARD);
TRACE_RET(chip, STATUS_FAIL);
}
retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, SD_RSP_TYPE_R2, rsp, 16);
if (retval == STATUS_SUCCESS) {
break;
}
}
if (i == 6) {
TRACE_RET(chip, STATUS_FAIL);
}
memcpy(sd_card->raw_csd, rsp + 1, 15);
RTSX_READ_REG(chip, SD_CMD5, sd_card->raw_csd + 15);
RTSX_DEBUGP(("CSD Response:\n"));
RTSX_DUMP(sd_card->raw_csd, 16);
csd_ver = (rsp[1] & 0xc0) >> 6;
RTSX_DEBUGP(("csd_ver = %d\n", csd_ver));
trans_speed = rsp[4];
if ((trans_speed & 0x07) == 0x02) {
if ((trans_speed & 0xf8) >= 0x30) {
if (chip->asic_code) {
sd_card->sd_clock = 47;
} else {
sd_card->sd_clock = CLK_50;
}
} else if ((trans_speed & 0xf8) == 0x28) {
if (chip->asic_code) {
sd_card->sd_clock = 39;
} else {
sd_card->sd_clock = CLK_40;
}
} else if ((trans_speed & 0xf8) == 0x20) {
if (chip->asic_code) {
sd_card->sd_clock = 29;
} else {
sd_card->sd_clock = CLK_30;
}
} else if ((trans_speed & 0xf8) >= 0x10) {
if (chip->asic_code) {
sd_card->sd_clock = 23;
} else {
sd_card->sd_clock = CLK_20;
}
} else if ((trans_speed & 0x08) >= 0x08) {
if (chip->asic_code) {
sd_card->sd_clock = 19;
} else {
sd_card->sd_clock = CLK_20;
}
} else {
TRACE_RET(chip, STATUS_FAIL);
}
} else {
TRACE_RET(chip, STATUS_FAIL);
}
if (CHK_MMC_SECTOR_MODE(sd_card)) {
sd_card->capacity = 0;
} else {
if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
u8 blk_size, c_size_mult;
u16 c_size;
blk_size = rsp[6] & 0x0F;
c_size = ((u16)(rsp[7] & 0x03) << 10)
+ ((u16)rsp[8] << 2)
+ ((u16)(rsp[9] & 0xC0) >> 6);
c_size_mult = (u8)((rsp[10] & 0x03) << 1);
c_size_mult += (rsp[11] & 0x80) >> 7;
sd_card->capacity = (((u32)(c_size + 1)) * (1 << (c_size_mult + 2))) << (blk_size - 9);
} else {
u32 total_sector = 0;
total_sector = (((u32)rsp[8] & 0x3f) << 16) |
((u32)rsp[9] << 8) | (u32)rsp[10];
sd_card->capacity = (total_sector + 1) << 10;
}
}
if (check_wp) {
if (rsp[15] & 0x30) {
chip->card_wp |= SD_CARD;
}
RTSX_DEBUGP(("CSD WP Status: 0x%x\n", rsp[15]));
}
return STATUS_SUCCESS;
}
static int sd_set_sample_push_timing(struct rtsx_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) {
RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
} else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) {
RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, DDR_VAR_TX_CMD_DAT,
DDR_VAR_TX_CMD_DAT);
RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
} else {
u8 val = 0;
RTSX_WRITE_REG(chip, SD_CFG1, 0x0C, SD_20_MODE);
RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_AUTO) {
val = SD20_TX_NEG_EDGE;
} else if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) {
val = SD20_TX_14_AHEAD;
} else {
val = SD20_TX_NEG_EDGE;
}
RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, SD20_TX_SEL_MASK, val);
if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
if (chip->asic_code) {
if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
val = SD20_RX_14_DELAY;
} else {
val = SD20_RX_POS_EDGE;
}
} else {
val = SD20_RX_14_DELAY;
}
} else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
val = SD20_RX_14_DELAY;
} else {
val = SD20_RX_POS_EDGE;
}
RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, SD20_RX_SEL_MASK, val);
}
return STATUS_SUCCESS;
}
static void sd_choose_proper_clock(struct rtsx_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
if (CHK_SD_SDR104(sd_card)) {
if (chip->asic_code) {
sd_card->sd_clock = chip->asic_sd_sdr104_clk;
} else {
sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
}
} else if (CHK_SD_DDR50(sd_card)) {
if (chip->asic_code) {
sd_card->sd_clock = chip->asic_sd_ddr50_clk;
} else {
sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
}
} else if (CHK_SD_SDR50(sd_card)) {
if (chip->asic_code) {
sd_card->sd_clock = chip->asic_sd_sdr50_clk;
} else {
sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
}
} else if (CHK_SD_HS(sd_card)) {
if (chip->asic_code) {
sd_card->sd_clock = chip->asic_sd_hs_clk;
} else {
sd_card->sd_clock = chip->fpga_sd_hs_clk;
}
} else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
if (chip->asic_code) {
sd_card->sd_clock = chip->asic_mmc_52m_clk;
} else {
sd_card->sd_clock = chip->fpga_mmc_52m_clk;
}
} else if (CHK_MMC_26M(sd_card)) {
if (chip->asic_code) {
sd_card->sd_clock = 48;
} else {
sd_card->sd_clock = CLK_50;
}
}
}
static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
{
RTSX_WRITE_REG(chip, SD_CFG1, SD_CLK_DIVIDE_MASK, clk_div);
return STATUS_SUCCESS;
}
static int sd_set_init_para(struct rtsx_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
retval = sd_set_sample_push_timing(chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
sd_choose_proper_clock(chip);
retval = switch_clock(chip, sd_card->sd_clock);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
int sd_select_card(struct rtsx_chip *chip, int select)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
u8 cmd_idx, cmd_type;
u32 addr;
if (select) {
cmd_idx = SELECT_CARD;
cmd_type = SD_RSP_TYPE_R1;
addr = sd_card->sd_addr;
} else {
cmd_idx = DESELECT_CARD;
cmd_type = SD_RSP_TYPE_R0;
addr = 0;
}
retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
#ifdef SUPPORT_SD_LOCK
static int sd_update_lock_status(struct rtsx_chip *chip)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
u8 rsp[5];
retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
if (rsp[1] & 0x02) {
sd_card->sd_lock_status |= SD_LOCKED;
} else {
sd_card->sd_lock_status &= ~SD_LOCKED;
}
RTSX_DEBUGP(("sd_card->sd_lock_status = 0x%x\n", sd_card->sd_lock_status));
if (rsp[1] & 0x01) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
#endif
static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, u8 data_ready, int polling_cnt)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval, i;
u8 rsp[5];
for (i = 0; i < polling_cnt; i++) {
retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
if (((rsp[3] & 0x1E) == state) && ((rsp[3] & 0x01) == data_ready)) {
return STATUS_SUCCESS;
}
}
TRACE_RET(chip, STATUS_FAIL);
}
static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
{
int retval;
if (voltage == SD_IO_3V3) {
if (chip->asic_code) {
retval = rtsx_write_phy_register(chip, 0x08, 0x4FC0 | chip->phy_voltage);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
} else {
RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
}
} else if (voltage == SD_IO_1V8) {
if (chip->asic_code) {
retval = rtsx_write_phy_register(chip, 0x08, 0x4C40 | chip->phy_voltage);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
} else {
RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, SD_IO_USING_1V8);
}
} else {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int sd_voltage_switch(struct rtsx_chip *chip)
{
int retval;
u8 stat;
RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, SD_CLK_TOGGLE_EN);
retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL, 0);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
udelay(chip->sd_voltage_switch_delay);
RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
SD_DAT1_STATUS | SD_DAT0_STATUS)) {
TRACE_RET(chip, STATUS_FAIL);
}
RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP);
retval = sd_change_bank_voltage(chip, SD_IO_1V8);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
wait_timeout(50);
RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
wait_timeout(10);
RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
(SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
SD_DAT1_STATUS | SD_DAT0_STATUS)) {
RTSX_DEBUGP(("SD_BUS_STAT: 0x%x\n", stat));
rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
TRACE_RET(chip, STATUS_FAIL);
}
RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
return STATUS_SUCCESS;
}
static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
{
if (tune_dir == TUNE_RX) {
RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX);
RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
} else {
RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX);
RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
}
return STATUS_SUCCESS;
}
static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
{
struct sd_info *sd_card = &(chip->sd_card);
u16 SD_VP_CTL, SD_DCMPS_CTL;
u8 val;
int retval;
int ddr_rx = 0;
RTSX_DEBUGP(("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
sample_point, tune_dir));
if (tune_dir == TUNE_RX) {
SD_VP_CTL = SD_VPRX_CTL;
SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
if (CHK_SD_DDR50(sd_card)) {
ddr_rx = 1;
}
} else {
SD_VP_CTL = SD_VPTX_CTL;
SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
}
if (chip->asic_code) {
RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
} else {
#if DBG
rtsx_read_register(chip, SD_VP_CTL, &val);
RTSX_DEBUGP(("SD_VP_CTL: 0x%x\n", val));
rtsx_read_register(chip, SD_DCMPS_CTL, &val);
RTSX_DEBUGP(("SD_DCMPS_CTL: 0x%x\n", val));
#endif
if (ddr_rx) {
RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, PHASE_CHANGE);
udelay(50);
RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
PHASE_CHANGE | PHASE_NOT_RESET | sample_point);
} else {
RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
udelay(50);
RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
PHASE_NOT_RESET | sample_point);
}
udelay(100);
rtsx_init_cmd(chip);
rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, DCMPS_CHANGE);
rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
retval = rtsx_send_cmd(chip, SD_CARD, 100);
if (retval != STATUS_SUCCESS) {
TRACE_GOTO(chip, Fail);
}
val = *rtsx_get_cmd_data(chip);
if (val & DCMPS_ERROR) {
TRACE_GOTO(chip, Fail);
}
if ((val & DCMPS_CURRENT_PHASE) != sample_point) {
TRACE_GOTO(chip, Fail);
}
RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
if (ddr_rx) {
RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
} else {
RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
}
udelay(50);
}
RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
return STATUS_SUCCESS;
Fail:
#if DBG
rtsx_read_register(chip, SD_VP_CTL, &val);
RTSX_DEBUGP(("SD_VP_CTL: 0x%x\n", val));
rtsx_read_register(chip, SD_DCMPS_CTL, &val);
RTSX_DEBUGP(("SD_DCMPS_CTL: 0x%x\n", val));
#endif
rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
wait_timeout(10);
sd_reset_dcm(chip, tune_dir);
return STATUS_FAIL;
}
static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
{
struct sd_info *sd_card = &(chip->sd_card);
int retval;
u8 cmd[5], buf[8];
retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
cmd[0] = 0x40 | SEND_SCR;
cmd[1] = 0;
cmd[2] = 0;
cmd[3] = 0;
cmd[4] = 0;
retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf, 8, 250);
if (retval != STATUS_SUCCESS) {
rtsx_clear_sd_error(chip);
TRACE_RET(chip, STATUS_FAIL);
}
memcpy(sd_card->raw_scr, buf, 8);
if ((buf[0] & 0x0F) == 0) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, u8 func_to_switch,
u8 *buf, int buf_len)
{
u8 support_mask = 0, query_switch = 0, switch_busy = 0;
int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
if (func_group == SD_FUNC_GROUP_1) {
support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
switch (func_to_switch) {
case HS_SUPPORT:
support_mask = HS_SUPPORT_MASK;
query_switch = HS_QUERY_SWITCH_OK;
switch_busy = HS_SWITCH_BUSY;
break;
case SDR50_SUPPORT:
support_mask = SDR50_SUPPORT_MASK;
query_switch = SDR50_QUERY_SWITCH_OK;
switch_busy = SDR50_SWITCH_BUSY;
break;
case SDR104_SUPPORT:
support_mask = SDR104_SUPPORT_MASK;
query_switch = SDR104_QUERY_SWITCH_OK;
switch_busy = SDR104_SWITCH_BUSY;
break;
case DDR50_SUPPORT:
support_mask = DDR50_SUPPORT_MASK;
query_switch = DDR50_QUERY_SWITCH_OK;
switch_busy = DDR50_SWITCH_BUSY;
break;
default:
TRACE_RET(chip, STATUS_FAIL);
}
} else if (func_group == SD_FUNC_GROUP_3) {
support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
switch (func_to_switch) {
case DRIVING_TYPE_A:
support_mask = DRIVING_TYPE_A_MASK;
query_switch = TYPE_A_QUERY_SWITCH_OK;
switch_busy = TYPE_A_SWITCH_BUSY;
break;
case DRIVING_TYPE_C:
support_mask = DRIVING_TYPE_C_MASK;
query_switch = TYPE_C_QUERY_SWITCH_OK;
switch_busy = TYPE_C_SWITCH_BUSY;
break;
case DRIVING_TYPE_D:
support_mask = DRIVING_TYPE_D_MASK;
query_switch = TYPE_D_QUERY_SWITCH_OK;
switch_busy = TYPE_D_SWITCH_BUSY;
break;
default:
TRACE_RET(chip, STATUS_FAIL);
}
} else if (func_group == SD_FUNC_GROUP_4) {
support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
switch (func_to_switch) {
case CURRENT_LIMIT_400:
support_mask = CURRENT_LIMIT_400_MASK;
query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
break;
case CURRENT_LIMIT_600:
support_mask = CURRENT_LIMIT_600_MASK;
query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
break;
case CURRENT_LIMIT_800:
support_mask = CURRENT_LIMIT_800_MASK;
query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
break;
default:
TRACE_RET(chip, STATUS_FAIL);
}