diff --git a/.gitmodules b/.gitmodules index 824e85ae0..32546e093 100644 --- a/.gitmodules +++ b/.gitmodules @@ -21,9 +21,6 @@ [submodule "hardware/deps/common_verification"] path = hardware/deps/common_verification url = https://github.com/pulp-platform/common_verification.git -[submodule "hardware/deps/cva6"] - path = hardware/deps/cva6 - url = https://github.com/pulp-platform/cva6.git [submodule "toolchain/newlib"] path = toolchain/newlib url = https://sourceware.org/git/newlib-cygwin.git @@ -35,3 +32,6 @@ [submodule "hardware/deps/apb"] path = hardware/deps/apb url = https://github.com/pulp-platform/apb.git +[submodule "hardware/deps/cva6"] + path = hardware/deps/cva6 + url = git@github.com:MaistoV/cva6_fork.git diff --git a/Bender.yml b/Bender.yml index dd9f182aa..0860ae055 100644 --- a/Bender.yml +++ b/Bender.yml @@ -10,7 +10,7 @@ package: dependencies: axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.29.1 } common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 } - cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: acc_port_rerebase } + cva6: { git: "https://github.com/MaistoV/cva6_fork.git", rev: ara_cheshire } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.1 } apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } diff --git a/hardware/deps/axi b/hardware/deps/axi index 442ff3375..bfee21757 160000 --- a/hardware/deps/axi +++ b/hardware/deps/axi @@ -1 +1 @@ -Subproject commit 442ff3375710513623f95944d66cc2bd09b2f155 +Subproject commit bfee21757bf090ec8e358456314b0b0fd3c90809 diff --git a/hardware/deps/cva6 b/hardware/deps/cva6 index 646f33cae..00d3f66ce 160000 --- a/hardware/deps/cva6 +++ b/hardware/deps/cva6 @@ -1 +1 @@ -Subproject commit 646f33caee03a4e5a5f781b935a42fe9e7d959b2 +Subproject commit 00d3f66ce60cd94b3421a9083c0e7ea1c76270c8 diff --git a/hardware/src/vlsu/vlsu.sv b/hardware/src/vlsu/vlsu.sv index aa2e05283..7505f9f6f 100644 --- a/hardware/src/vlsu/vlsu.sv +++ b/hardware/src/vlsu/vlsu.sv @@ -89,8 +89,8 @@ module vlsu import ara_pkg::*; import rvv_pkg::*; #( .aw_chan_t(axi_aw_t ), .w_chan_t (axi_w_t ), .b_chan_t (axi_b_t ), - .req_t (axi_req_t ), - .resp_t (axi_resp_t) + .axi_req_t (axi_req_t ), + .axi_resp_t(axi_resp_t) ) i_axi_cut ( .clk_i (clk_i ), .rst_ni (rst_ni ),