From 34e57826c6c4c491f74a1fc64166983f6753d05c Mon Sep 17 00:00:00 2001
From: Paul Gardner-Stephen <paul@m-e-g-a.org>
Date: Wed, 3 Apr 2024 20:09:34 +1030
Subject: [PATCH] assign all buffered uart rx lines #798

---
 src/vhdl/nexys4.vhdl | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/vhdl/nexys4.vhdl b/src/vhdl/nexys4.vhdl
index 153fbac41..2a2821957 100644
--- a/src/vhdl/nexys4.vhdl
+++ b/src/vhdl/nexys4.vhdl
@@ -582,9 +582,8 @@ begin
       uart_tx => jclo(2),
 
       buffereduart_rx(0) => jalo(1),
+      buffereduart_rx(7 downto 1) => (others => '1'),
       buffereduart_tx(0) => jalo(2),
---      buffereduart2_rx => jchi(9),
---      buffereduart2_tx => jchi(10),
       buffereduart_ringindicate => (others => '0'),
       
       slow_access_request_toggle => slow_access_request_toggle,