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For all the decoupling caps in the project, it would be good to have one or two via to GND in layer 2 to have low inductance from capacitor GND pad. This is as described in https://web.mst.edu/~jfan/slides/Archambeault1.pdf especially page 29
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Thanks for the link to the presentation. Very interesting.
I don't agree, though, that the top right one is always the best solution:
In the presentation the GND connection from the cap always goes to the GND plane and afterwards to the IC, which may be relevant for BGA packages. For packages with pins I would usually place the caps such that there is no via between the cap and the IC at all. The via is only used for topping up the cap with energy. This means that in order to make sure current for the IC only comes from the cap, the vias to supply the caps must be on the opposite side of the cap than the IC, so that the cap cannot be bypassed.
Here is an example for the CAN transceiver:
The 3V3 supply is probably ideal, whereas the 5V corresponds more to the "ugly" in the picture. However, I doubt that the "better" placement would make any difference. If it does, please let me know why.
Normally I do put vias very close to all decoupling caps, just not below the cap as this would require smaller via sizes and increase production cost. Did you spot any cap that was particularly flawed in terms of connection to GND / supply rail plane?
For all the decoupling caps in the project, it would be good to have one or two via to GND in layer 2 to have low inductance from capacitor GND pad. This is as described in https://web.mst.edu/~jfan/slides/Archambeault1.pdf especially page 29
The text was updated successfully, but these errors were encountered: