-
Notifications
You must be signed in to change notification settings - Fork 2
/
librepcb_sk.ts
17651 lines (17601 loc) · 906 KB
/
librepcb_sk.ts
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
<?xml version="1.0" ?><!DOCTYPE TS><TS version="2.1" language="sk" sourcelanguage="en">
<context>
<name>ArchiveOutputJob</name>
<message>
<location filename="../libs/librepcb/core/job/archiveoutputjob.cpp" line="42"/>
<source>Output Archive</source>
<translation>Výstupný archív</translation>
</message>
<message>
<location filename="../libs/librepcb/core/job/archiveoutputjob.h" line="71"/>
<source>Archive</source>
<translation>Archív</translation>
</message>
</context>
<context>
<name>AttributeKey</name>
<message>
<location filename="../libs/librepcb/core/attribute/attributekey.h" line="56"/>
<source>Invalid attribute key: '%1'</source>
<translation>Nesprávny kľúč atribútu: '%1'</translation>
</message>
</context>
<context>
<name>AttributeType</name>
<message>
<location filename="../libs/librepcb/core/attribute/attributetype.cpp" line="77"/>
<source>Unknown unit of attribute type "%1": "%2"</source>
<translation>Neznáma jednotka typu atribútu "%1": "%2"</translation>
</message>
<message>
<location filename="../libs/librepcb/core/attribute/attributetype.cpp" line="124"/>
<source>Invalid attribute type: "%1"</source>
<translation>Nesprávny typ atribútu: "%1"</translation>
</message>
</context>
<context>
<name>BGI_Via</name>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="248"/>
<source>Through-Hole Via</source>
<translation>Štandardný prechod</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="250"/>
<source>Blind Via</source>
<translation>Slepý prechod</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="252"/>
<source>Buried Via</source>
<translation>Pochovaný prechod</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="254"/>
<source>Net: %1</source>
<translation>Prepojenie: %1</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="256"/>
<source>Start Layer: %1</source>
<translation>Začiatočná vrstva: %1</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="257"/>
<source>End Layer: %1</source>
<translation>Koncová vrstva: %1</translation>
</message>
</context>
<context>
<name>Board3DOutputJob</name>
<message>
<location filename="../libs/librepcb/core/job/board3doutputjob.cpp" line="39"/>
<source>STEP Model</source>
<translation>Model formátu STEP</translation>
</message>
<message>
<location filename="../libs/librepcb/core/job/board3doutputjob.h" line="73"/>
<source>3D Model</source>
<translation>3D Model</translation>
</message>
</context>
<context>
<name>BoardDesignRuleCheckMessages</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="53"/>
<source>Depending on the capabilities of the PCB manufacturer, this could cause higher costs or even serious troubles during production, leading to a possibly non-functional PCB.</source>
<translation>V závislosti od možností výrobcu DPS, môže toto spôsobiť vyššie náklady alebo dokonca vážne problémy pri výrobe, čo môže viesť aj k prípadnej nefunkčnosti DPS.</translation>
</message>
</context>
<context>
<name>BomOutputJob</name>
<message>
<location filename="../libs/librepcb/core/job/bomoutputjob.cpp" line="40"/>
<source>Bill of Materials</source>
<translation>Zoznam súčiastok</translation>
</message>
<message>
<location filename="../libs/librepcb/core/job/bomoutputjob.h" line="79"/>
<source>Bill Of Materials</source>
<translation>Zoznam súčiastok</translation>
</message>
</context>
<context>
<name>BoundedUnsignedRatio</name>
<message>
<location filename="../libs/librepcb/core/types/boundedunsignedratio.cpp" line="108"/>
<source>Minimum value must not be greater than maximum value.</source>
<translation>Minimálna hodnota nesmie byť vyššia ako maximálna hodnota.</translation>
</message>
</context>
<context>
<name>CircuitIdentifier</name>
<message>
<location filename="../libs/librepcb/core/types/circuitidentifier.h" line="54"/>
<source>Invalid identifier: '%1'</source>
<translation>Nesprávny identifikátor: '%1'</translation>
</message>
</context>
<context>
<name>CmpSigPinDisplayType</name>
<message>
<location filename="../libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="95"/>
<source>None (no text)</source>
<translation>Prázdne (bez textu)</translation>
</message>
<message>
<location filename="../libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="101"/>
<source>Symbol pin name</source>
<translation>Názov vývodu sch. značky</translation>
</message>
<message>
<location filename="../libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="107"/>
<source>Component signal name</source>
<translation>Názov signálu komponentu</translation>
</message>
<message>
<location filename="../libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="113"/>
<source>Schematic net name</source>
<translation>Názov prepojenia v schéme</translation>
</message>
</context>
<context>
<name>CommandLineInterface</name>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="86"/>
<source>Open a project to execute project-related tasks.</source>
<translation>Otvoriť projekt pre vykonanie akcií v ňom.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="89"/>
<source>Open a library to execute library-related tasks.</source>
<translation>Otvoriť knižnicu pre vykonanie akcií v nej.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="92"/>
<source>Open a STEP model to execute STEP-related tasks outside of a library.</source>
<translation>Otvorte STEP model mimo knižnice pre vykonávanie STEP úloh.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="99"/>
<source>LibrePCB Command Line Interface</source>
<translation>Rozhranie príkazového riadka LibrePCB</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="102"/>
<source>Print this message.</source>
<translation>Vytlačiť túto správu.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="105"/>
<source>Displays version information.</source>
<translation>Zobraziť informácie o verzii.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="107"/>
<source>Verbose output.</source>
<translation>Podrobný výstup</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="110"/>
<source>The command to execute (see list below).</source>
<translation>Príkaz na vykonanie (pozri zoznam nižšie).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="116"/>
<source>Run the electrical rule check, print all non-approved warnings/errors and report failure (exit code = 1) if there are non-approved messages.</source>
<translation>Spustiť kontrolu elektrických pravidiel, zobraziť všetky neschválené upozornenia/chyby a zlyhania (exit code = 1) ak sú neschválené oznámenia.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="121"/>
<source>Run the design rule check, print all non-approved warnings/errors and report failure (exit code = 1) if there are non-approved messages.</source>
<translation>Spustiť kontrolu návrhových pravidiel, zobraziť všetky neschválené upozornenia/chyby a zlyhania (exit code = 1) ak sú neschválené oznámenia.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="126"/>
<source>Override DRC settings by providing a *.lp file containing custom settings. If not set, the settings from the boards will be used instead.</source>
<translation>Prepísať nastavenie DRC, užívateľským nastavením uloženým v *.lp súbore. Ak nie je zadané, použije sa nastaveniez dosky.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="129"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="141"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="152"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="158"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="164"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="181"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="187"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="194"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="200"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="282"/>
<source>file</source>
<translation>súbor</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="132"/>
<source>Run a particular output job. Can be given multiple times to run multiple jobs.</source>
<translation>Spustenie konkrétnej výstupnej úlohy. Dá sa zadať viackrát pre spustenie viacerých úloh.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="134"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="205"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="222"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="234"/>
<source>name</source>
<translation>názov</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="136"/>
<source>Run all existing output jobs.</source>
<translation>Spustenie všetkých jestvujúcich úloh pre generovanie výstupov.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="139"/>
<source>Override output jobs with a *.lp file containing custom jobs. If not set, the jobs from the project will be used instead.</source>
<translation>Prepísať výstupné úlohy nastavením zo súboru *.lp. Ak nie je zadané, použije sa nastavenie z projektu.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="144"/>
<source>Override the output base directory of jobs. If not set, the standard output directory from the project is used.</source>
<translation>Prepísať cieľovú cestu adresára, pre úlohy generovania výstupov. Ak nie je zadané, použije sa nastavenie z projektu.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="146"/>
<source>path</source>
<translation>cesta</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="149"/>
<source>Export schematics to given file(s). Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportovať schematické výkresy do príslušných súborov. Ak súbory už existujú, budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="155"/>
<source>Export generic BOM to given file(s). Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportovať všeobecný zoznam súčiastok do príslušného súboru. Ak súbor už existuje, bude prepísaný. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="161"/>
<source>Export board-specific BOM to given file(s). Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportovať zoznam súčiastok pre konkrétnu dosku do príslušného súboru. Ak súbory už existujú, budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="167"/>
<source>Comma-separated list of additional attributes to be exported to the BOM. Example: "%1"</source>
<translation>Zoznam dodatočných atribútov oddelených čiarkami, ktoré budú exportované do zoznamu súčiastok. Napríklad "%1"</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="170"/>
<source>attributes</source>
<translation>atribúty</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="173"/>
<source>Export PCB fabrication data (Gerber/Excellon) according the fabrication output settings of boards. Existing files will be overwritten.</source>
<translation>Exportovať výrobné dáta (Gerber/Excellon) na základe nastavenia dosky. Ak súbory už existujú, budú prepísané.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="178"/>
<source>Override PCB fabrication output settings by providing a *.lp file containing custom settings. If not set, the settings from the boards will be used instead.</source>
<translation>Prepísať nastavenie generovania výrobných dát dosky, pomocou užívateľského nastavenia z *.lp súboru. Ak nie je zadané, bude použité nastavenie generovania výrobných dát z dosky.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="184"/>
<source>Export pick&place file for automated assembly of the top board side. Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportuje súbor pick&place pre automatické osádzanie súčiastok, pre vrchnú stranu dosky. Jestvujúce súbory budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="190"/>
<source>Export pick&place file for automated assembly of the bottom board side. Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportuje súbor pick&place pre automatické osádzanie súčiastok, pre spodnú stranu dosky. Jestvujúce súbory budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="197"/>
<source>Export netlist file for automated PCB testing. Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportuje zoznam prepojení pre automatizované testovanie DPS. Jestvujúce súbory budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="202"/>
<source>The name of the board(s) to export. Can be given multiple times. If not set, all boards are exported.</source>
<translation>Názov exportovanej dosky/dosiek. Môže byť zadaných viacej názvov. Ak nie je zadané, všetky dosky budú exportované.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="207"/>
<source>Same as '%1', but allows to specify boards by index instead of by name.</source>
<translation>Rovnako ako '%1', ale umožňuje špecifikovať dosku podľa indexu namiesto názvu.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="210"/>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="228"/>
<source>index</source>
<translation>index</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="213"/>
<source>Remove all boards not specified with '%1' from the project before executing all the other actions. If '%1' is not passed, all boards will be removed. Pass '%2' to save the modified project to disk.</source>
<translation>Pred vykonaním ostatných akcií, odstráňte z projektu všetky nešpecifkované dosky pomocou '%1'. Ak '%1' nebolo zadané, budú odstránené všetky dosky. Zadaním '%2' bude projekt uložený na disk.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="220"/>
<source>The name of the assembly variant(s) to export. Can be given multiple times. If not set, all assembly variants are exported.</source>
<translation>Názov alternatívneho osadenia DPS na export. Môže byť zadaných viacero názvov. Ak nie je nastavený žiaden, exportujú sa všetky varianty zostavy.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="225"/>
<source>Same as '%1', but allows to specify assembly variants by index instead of by name.</source>
<translation>Rovnako ako '%1', ale umožňuje špecifikovať alternatívne osadenie dosky podľa indexu namiesto názvu.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="231"/>
<source>Move the specified assembly variant to the top before executing all the other actions. Pass '%1' to save the modified project to disk.</source>
<translation>Najskôr presuňte špecifikované alternatívne osadenie nahor pred vykonaním všetkých ostatných akcií. Ak chcete uložiť upravený projekt na disk, zadajte '%1'.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="237"/>
<source>Save project before closing it (useful to upgrade file format).</source>
<translation>Uložiť projekt pred jeho uzavretím (užitočné pre inováciu formátu súboru).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="240"/>
<source>Fail if the project files are not strictly canonical, i.e. there would be changes when saving the project. Note that this option is not available for *.lppz files.</source>
<translation>Ukončené s chybou, ak projektové súbory nie sú striktne kanonické, t.j. pri ukladaní projektu došlo k zmenám (napr. neboli uložené programom LibrePCB). Upozorňujeme, že táto možnosť nie je k dispozícii pre súbory * .lppz.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="247"/>
<source>Perform the selected action(s) on all elements contained in the opened library.</source>
<translation>Vykonať zvolenú akciu/akcie na všetky položky v otvorenej knižnici.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="251"/>
<source>Run the library element check, print all non-approved messages and report failure (exit code = 1) if there are non-approved messages.</source>
<translation>Spustenie kontroly knižničných prvkov, zobrazenie všetkých neschválených upozornení a oznámenie chýb (exit code = 1) ak jestvujú neschválené oznámenia.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="255"/>
<source>Minify the STEP models of all packages. Only works in conjunction with '--all'. Pass '--save' to write the minified files to disk.</source>
<translation>Minify the STEP models of all packages. Only works in conjunction with '--all'. Pass '--save' to write the minified files to disk.
Minimalizuje všetky STEP modely. Funguje iba v spojení s '--all'. Ak chcete zapísať minimalizované súbory na disk, zadajte „--save“.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="259"/>
<source>Save library (and contained elements if '--all' is given) before closing them (useful to upgrade file format).</source>
<translation>Uložiť knižnicu (a obsahujúce položky ak '--all' bol zadaný) pred jej uzavretím (užitočné pre inováciu formátu knižnice).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="263"/>
<source>Fail if the opened files are not strictly canonical, i.e. there would be changes when saving the library elements.</source>
<translation>Ukončené s chybou, ak otvorené súbory nie sú striktne kanonické, t.j. pri ukladaní prvkov knižnice došlo k zmenám (napr. neboli uložené programom LibrePCB).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="269"/>
<source>Minify the STEP model before validating it. Use in conjunction with '%1' to save the output of the operation.</source>
<translation>Minimalizujte STEP model pred jeho použitím. Použite v spolupráci s '%1' pre uloženie výstupu operácie.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="274"/>
<source>Tesselate the loaded STEP model to check if LibrePCB is able to render it. Reports failure (exit code = 1) if no content is detected.</source>
<translation>Rozdeľte načítaný STEP model a skontrolujte, či ho LibrePCB dokáže vykresliť. Ak sa nezistí žiadny obsah, hlásené je zlyhanie (kód ukončenia = 1).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="279"/>
<source>Write the (modified) STEP file to this output location (may be equal to the opened file path). Only makes sense in conjunction with '%1'.</source>
<translation>Zapíšte (upravený) súbor STEP do tohto výstupného umiestnenia (môže sa rovnať otvorenej ceste k súboru). Má zmysel iba v spojení s '%1'.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="286"/>
<source>Commands:</source>
<translation>Príkazy:</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="290"/>
<source>List command-specific options:</source>
<translation>Vypísať špecifické možnosti pre príkazy:</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="293"/>
<source>Help:</source>
<translation>Pomocník:</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="307"/>
<source>Path to project file (*.lpp[z]).</source>
<translation>Cesta k súboru projektu (*.lpp[z]).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="337"/>
<source>Path to library directory (*.lplib).</source>
<translation>Cesta do adresára s knižnicou (*.lplib).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="348"/>
<source>Path to the STEP file (%1).</source>
<translation>Cesta k súboru STEP (%1).</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="354"/>
<source>Unknown command '%1'.</source>
<translation>Neznámy príkaz '%1'.</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="411"/>
<source>Missing arguments:</source>
<translation>Chýbajúce argumenty:</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="417"/>
<source>Unknown arguments:</source>
<translation>Neznáme argumenty:</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="471"/>
<source>SUCCESS</source>
<translation>ÚSPEŠNÉ</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="474"/>
<source>Finished with errors!</source>
<translation>Ukončené s chybami!</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1216"/>
<source>Minify STEP model '%1'...</source>
<translation>Minimalizácia STEP modelu '%1'...</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1222"/>
<source> - Minified '%1' from %2 to %3 bytes</source>
<translation> - Minimalizovaný '%1' z %2 na %3 bytes</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1241"/>
<source>Check '%1' for non-canonical files...</source>
<translation>Kontrolovanie '%1' na ne-kanonické súbory...</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1259"/>
<source>Check '%1' for non-approved messages...</source>
<translation>Kontrolovanie '%1' na neschválené oznámenia...</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1266"/>
<source>Approved messages: %1</source>
<translation>Schválené oznámenia: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1268"/>
<source>Non-approved messages: %1</source>
<translation>Neschválené oznámenia: %1</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1279"/>
<source>Save '%1'...</source>
<translation>Ukladanie '%1'...</translation>
</message>
<message>
<location filename="../apps/librepcb-cli/commandlineinterface.cpp" line="1415"/>
<source>This application version is UNSTABLE! Option '%1' is disabled to avoid breaking projects or libraries. Please use a stable release instead.</source>
<translation>Táto verzia aplikácie je NESTABILNÁ! Možnosť '%1' je deaktivovaná, aby nedošlo k poškodeniu projektov alebo knižníc. Namiesto toho použite prosím stabilnú verziu.</translation>
</message>
</context>
<context>
<name>ComponentPrefix</name>
<message>
<location filename="../libs/librepcb/core/library/cmp/componentprefix.h" line="57"/>
<source>Invalid component prefix: '%1'</source>
<translation>Neplatný prefix komponentu: '%1'</translation>
</message>
</context>
<context>
<name>ComponentSymbolVariantItemSuffix</name>
<message>
<location filename="../libs/librepcb/core/library/cmp/componentsymbolvariantitemsuffix.h" line="58"/>
<source>Invalid component symbol suffix: '%1'</source>
<translation>Neplatný sufix sch. značky komponentu: '%1'</translation>
</message>
</context>
<context>
<name>CopyOutputJob</name>
<message>
<location filename="../libs/librepcb/core/job/copyoutputjob.cpp" line="39"/>
<source>Custom File</source>
<translation>Užívateľský súbor</translation>
</message>
<message>
<location filename="../libs/librepcb/core/job/copyoutputjob.h" line="78"/>
<source>File Copy</source>
<translation>Kópia súboru</translation>
</message>
</context>
<context>
<name>DesktopIntegration</name>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="135"/>
<source>To avoid troubles, only proceed if there are no other (installed) LibrePCB applications on this computer.</source>
<translation>Aby ste sa vyhli problémom, pokračujte iba vtedy, ak na tomto počítači nie sú žiadne iné (nainštalované) aplikácie LibrePCB.</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="148"/>
<source>Install Desktop Integration</source>
<translation>Inštalovať integráciu do pracovnej plochy</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="149"/>
<source>This installs the following files to register the executable <i>%1</i>:</source>
<translation>Týmto sa nainštalujú a budú zaregistrované ako spúšťacie, nasledujúce súbory <i>%1</i>:</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="157"/>
<source>Uninstall Desktop Integration</source>
<translation>Odinštalovať integráciu z pracovnej plochy</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="158"/>
<source>This removes the following files:</source>
<translation>Toto spôsobí odstránenie nasledujúcich súborov:</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="181"/>
<source>Error</source>
<translation>Chyba</translation>
</message>
<message>
<location filename="../libs/librepcb/editor/workspace/desktopintegration.cpp" line="264"/>
<source>Failed to run '%1'.
Please make sure this tool is available in PATH.</source>
<translation>Chyba pri spúšťaní '%1'.
Prosím skontrolujte či je tento nástroj dostupný cez premennú PATH.</translation>
</message>
</context>
<context>
<name>DirectoryLock</name>
<message>
<location filename="../libs/librepcb/core/fileio/directorylock.cpp" line="80"/>
<location filename="../libs/librepcb/core/fileio/directorylock.cpp" line="192"/>
<source>The directory "%1" does not exist.</source>
<translation>Adresár "%1" neexistuje.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/fileio/directorylock.cpp" line="98"/>
<source>The lock file "%1" has too few lines.</source>
<translation>Súbor "%1" obsahuje príliš málo riadkov.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/fileio/directorylock.cpp" line="171"/>
<source>Could not lock the directory "%1" because it is already locked by "%2". Close any application accessing this directory and try again.</source>
<translation>Adresár "%1" sa nedá uzamknúť, pretože už je uzamknutý pomocou "%2". Zatvorte aplikáciu používajúcu tento adresár a skúste to znova.</translation>
</message>
</context>
<context>
<name>DrcMsgCopperBoardClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="597"/>
<source>Clearance board outline ↔ via < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie obrysu dosky ↔ prechodu < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="600"/>
<source>The clearance between a via and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi prechodom a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="604"/>
<source>Check the DRC settings and move the via away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte prechod ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="619"/>
<source>Clearance trace ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie spoja ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="622"/>
<source>The clearance between a trace and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi spojom a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="626"/>
<source>Check the DRC settings and move the trace away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte spoj ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="641"/>
<source>Clearance pad ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie plôšky vývodu ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="644"/>
<source>The clearance between a footprint pad and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi plôškou vývodu a obrysu dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="648"/>
<source>Check the DRC settings and move the device away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte súčiastku ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="663"/>
<source>Clearance plane ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie vyplnenej plochy ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="666"/>
<source>The clearance between a plane and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi vyplnenou plochou a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="670"/>
<source>Check the DRC settings and increase the configured plane clearance if needed.</source>
<translation>Skontrolujte nastavenie DRC a zväčšite odsadenie vyplnenej plochy.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="707"/>
<source>Clearance copper circle ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie vodivej kružnice ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="710"/>
<source>The clearance between a circle and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi kružnicou a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="713"/>
<source>Check the DRC settings and move the circle away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte kružnicu ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="728"/>
<source>Clearance copper text ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie textu ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="731"/>
<source>The clearance between a stroke text and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi textom a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="735"/>
<source>Check the DRC settings and move the stroke text away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte text ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="749"/>
<source>Clearance copper polygon ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie polygónu ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="755"/>
<source>The clearance between a polygon and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi polygónom a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="759"/>
<source>Check the DRC settings and move the polygon away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte polygón ďalej od obrysu dosky.</translation>
</message>
</context>
<context>
<name>DrcMsgCopperCopperClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="464"/>
<source>Clearance on %1: %2 ↔ %3 < %4 %5</source>
<comment>Placeholders: Layer name, object name, object name, Clearance value, unit</comment>
<translation>Vzdialenosť odsadenia na %1: %2 ↔ %3 < %4 %5</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="471"/>
<source>The clearance between two copper objects of different nets is smaller than the minimum copper clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi dvoma vodivým objektami rozdielnych prepojení je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="475"/>
<source>Check the DRC settings and move the objects to increase their clearance if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte objekty tak, aby sa zväčšila vzdialenosť medzi nimi.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="497"/>
<source>%1 layers</source>
<comment>Placeholder is a number > 1.</comment>
<translation>%1 vrstiev</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="516"/>
<source>via</source>
<translation>prechod</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="518"/>
<source>trace</source>
<translation>spoj</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="520"/>
<source>plane</source>
<translation>vyplnená plocha</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="522"/>
<source>polygon</source>
<translation>polygón</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="524"/>
<source>circle</source>
<translation>oblúk</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="526"/>
<source>text</source>
<translation>text</translation>
</message>
</context>
<context>
<name>DrcMsgCopperHoleClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="793"/>
<source>Clearance copper ↔ hole < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie vodivého prvku ↔ otvoru < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="799"/>
<source>The clearance between a non-plated hole and copper objects is smaller than the hole clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi nepokovovaným otvorom a vodivým prvkom je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="802"/>
<source>Check the DRC settings and move the copper objects away from the hole if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte vodivý objekt ďalej od otvoru.</translation>
</message>
</context>
<context>
<name>DrcMsgCopperInKeepoutZone</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="816"/>
<source>Pad in copper keepout zone: '%1'</source>
<comment>Placeholder is pad name</comment>
<translation>V oblasti zakázaných vodivých prvkov sa nachádza plôška vývodu: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="833"/>
<source>Via in copper keepout zone: '%1'</source>
<comment>Placeholder is net name</comment>
<translation>V oblasti zakázaných vodivých prvkov sa nachádza prechod: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="850"/>
<source>Trace in copper keepout zone: '%1'</source>
<comment>Placeholder is net name</comment>
<translation>V oblasti zakázaných vodivých prvkov sa nachádza spoj: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="865"/>
<source>Polygon in copper keepout zone</source>
<translation>V oblasti zakázaných vodivých prvkov sa nachádza polygón</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="879"/>
<source>Polygon in copper keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation>V oblasti zakázaných vodivých prvkov sa nachádza polygón: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="896"/>
<source>Circle in copper keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation>V oblasti zakázaných vodivých prvkov sa nachádza kružnica: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="926"/>
<source>There is a copper object within a copper keepout zone.</source>
<translation>V oblasti zakázaných vodivých prvkov sa nachádza vodivý objekt.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="927"/>
<source>Move the object to outside the keepout zone.</source>
<translation>Presuňte objekt mimo zakázanej oblasti.</translation>
</message>
</context>
<context>
<name>DrcMsgDeviceInCourtyard</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1073"/>
<source>Device in courtyard: '%1' ↔ '%2'</source>
<comment>Placeholders: Device 1 name, device 2 name</comment>
<translation>Súčiastka v manipulačnej oblasti: '%1' ↔ '%2'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1079"/>
<source>A device is placed within the courtyard of another device, which might cause troubles during assembly of these parts.</source>
<translation>Súčiastka je umiestnená v manipulačnej oblasti inej súčiastky, čo môže mať za následok problémy pri osádzaní týchto súčiastok.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1082"/>
<source>Either move the devices to increase their clearance or approve this message if you're sure they can be assembled without problems.</source>
<translation>Presuňte súčiastky tak aby ste zväčšili ich vzájomné odsadenie, alebo schváľte túto správu, ak ste si istí, že sa dajú bez problémov osadiť.</translation>
</message>
</context>
<context>
<name>DrcMsgDeviceInKeepoutZone</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1140"/>
<source>Device in keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation>V zakázanej oblasti sa nachádza súčiastka: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1168"/>
<source>There is a device within a keepout zone.</source>
<translation>V zakázanej oblasti sa nachádza súčiastka</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1169"/>
<source>Move the device to outside the keepout zone.</source>
<translation>Presuňte súčiastku mimo zakázanú oblasť.</translation>
</message>
</context>
<context>
<name>DrcMsgDisabledLayer</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1710"/>
<source>Objects on disabled layer: '%1'</source>
<translation>Počet objektov na vypnutej vrstve: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1711"/>
<source>The layer contains copper objects, but it is disabled in the board setup dialog and thus will be ignored in any production data exports. Either increase the layer count to get this layer exported, or remove all objects on this layer (by temporarily enabling this layer to see them).</source>
<translation>Vrstva obsahuje vodivé objekty, ale sú zakázané v nastavení dosky, preto budú vynechané pri akomkoľvek exporte výrobných dát. Buď zvýšte počet vrstiev, aby sa táto vrstva exportovala, alebo odstráňte všetky objekty na tejto vrstve (dočasným povolením zobrazenia tejto vrstvy).</translation>
</message>
</context>
<context>
<name>DrcMsgDrillBoardClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1051"/>
<source>Clearance drill ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie otvoru ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1057"/>
<source>The clearance between a drill and the board outline is smaller than the drill clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi otvorom a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1060"/>
<source>Check the DRC settings and move the drill away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte otvor ďalej od obrysu dosky.</translation>
</message>
</context>
<context>
<name>DrcMsgDrillDrillClearanceViolation</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="939"/>
<source>Clearance drill ↔ drill < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie: otvor ↔ otvor < %1 %2</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="942"/>
<source>The clearance between two drills is smaller than the drill clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi dvoma otvormi je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="945"/>
<source>Check the DRC settings and move the drills to increase their distance if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte otvory tak, aby sa zväčšila vzdialenosť medzi nimi.</translation>
</message>
</context>
<context>
<name>DrcMsgEmptyNetSegment</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="238"/>
<source>Empty segment of net '%1': '%2'</source>
<comment>Placeholders: Net name, segment UUID</comment>
<translation>Prázdny segment v prepojení '%1': '%2'</translation>
</message>
</context>
<context>
<name>DrcMsgExposureInKeepoutZone</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1182"/>
<source>Pad in exposure keepout zone: '%1'</source>
<comment>Placeholder is pad name</comment>
<translation>Plôška vývodu v kolízii so zakázanou oblasťou: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1199"/>
<source>Via in exposure keepout zone: '%1'</source>
<comment>Placeholder is net name</comment>
<translation>Prechod v kolízii so zakázanou oblasťou: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1214"/>
<source>Polygon in exposure keepout zone</source>
<translation>Polygón v kolízii so zakázanou oblasťou</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1227"/>
<source>Polygon in exposure keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation>Polygón v kolízii so zakázanou oblasťou: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1244"/>
<source>Circle in exposure keepout zone: '%1'</source>
<comment>Placeholder is device name</comment>
<translation>Kružnica v kolízii so zakázanou oblasťou: '%1'</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1275"/>
<source>There is a solder resist opening within an exposure keepout zone.</source>
<translation>V zakázanej oblasti sa nachádza odmaskovaná časť v nespájkovateľnej maske.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1277"/>
<source>Move the object to outside the keepout zone.</source>
<translation>Presuňte objekt mimo zakázanej zóny vodivých prvkov.</translation>
</message>
</context>
<context>
<name>DrcMsgForbiddenSlot</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1571"/>
<source>Hole is a slot with curves</source>
<translation>Otvor je slot s oblúkami</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1573"/>
<source>Hole is a multi-segment slot</source>
<translation>Otvor je viacsegmentový slot</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1575"/>
<source>Hole is a slot</source>
<translation>Otvor je slot</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1582"/>
<source>Either avoid them or check if your PCB manufacturer supports them.</source>
<translation>Buď sa im vyhnite, alebo skontrolujte, či ich výrobca PCB podporuje.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1584"/>
<source>Choose the desired Excellon slot mode when generating the production data (G85 vs. G00..G03).</source>
<translation>Vyberte požadovaný Excellon režim výroby slotu pri generovaní výrobných údajov (G85 vs. G00..G03).</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1587"/>
<source>The drilled slot mode (G85) will not be available when generating production data.</source>
<translation>Režim vŕtaného slotu (G85) nebude dostupný pri generovaní výrobných údajov.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1591"/>
<source>Curved slots are a very unusual thing and may cause troubles with many PCB manufacturers.</source>
<translation>Zakrivené sloty sú veľmi nezvyčajná vec a môžu spôsobiť problémy mnohým výrobcom PCB.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1595"/>
<source>Multi-segment slots are a rather unusual thing and may cause troubles with some PCB manufacturers.</source>
<translation>Viac segmentové sloty sú pomerne nezvyčajná vec a môžu spôsobiť problémy niektorým výrobcom PCB.</translation>
</message>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1599"/>
<source>Slots may cause troubles with some PCB manufacturers.</source>
<translation>Sloty môžu u niektorých výrobcov PCB spôsobovať problémy.</translation>
</message>
</context>
<context>
<name>DrcMsgForbiddenVia</name>
<message>
<location filename="../libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="1620"/>
<source>Blind via in net '%1'</source>
<translation>Slepý prechod v prepojení '%1'</translation>