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Igloo2_TFT_Video_Out_test.prjx
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SIZE="254"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
ENDFILE
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SIZE="254"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
ENDFILE
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SIZE="254"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
ENDFILE
VALUE "<project>/component/Actel/SmartFusion2MSS/MSS_FIC32/1.0.100/MSS_FIC32.cxf,actgen_cxf"
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SIZE="255"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
ENDFILE
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STATE="utd"
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SIZE="254"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
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VALUE "<project>/component/Actel/SmartFusion2MSS/MSS_MDDR/1.0.202/MSS_MDDR.cxf,actgen_cxf"
STATE="utd"
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SIZE="254"
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ENDFILE
VALUE "<project>/component/Actel/SmartFusion2MSS/MSS_RESET/1.0.100/MSS_RESET.cxf,actgen_cxf"
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SIZE="255"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
ENDFILE
VALUE "<project>/component/Actel/SmartFusion2MSS/MSS_SECURITY/1.0.100/MSS_SECURITY.cxf,actgen_cxf"
STATE="utd"
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SIZE="258"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
ENDFILE
VALUE "<project>/component/Actel/SmartFusion2MSS/MSS_SWITCH/1.0.101/MSS_SWITCH.cxf,actgen_cxf"
STATE="utd"
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PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
ENDFILE
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PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test/Igloo2_TFT_Video_Out_Test.cxf"
ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test/CCC_0/Igloo2_TFT_Video_Out_Test_CCC_0_FCCC.vhd,hdl"
STATE="utd"
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SIZE="5598"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test/CCC_0/Igloo2_TFT_Video_Out_Test_CCC_0_FCCC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test/FABOSC_0/Igloo2_TFT_Video_Out_Test_FABOSC_0_OSC.cxf,actgen_cxf"
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TIME="1414976077"
SIZE="476"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test/Igloo2_TFT_Video_Out_Test.cxf"
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VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test/FABOSC_0/Igloo2_TFT_Video_Out_Test_FABOSC_0_OSC.vhd,hdl"
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SIZE="1559"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test/FABOSC_0/Igloo2_TFT_Video_Out_Test_FABOSC_0_OSC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test/Igloo2_TFT_Video_Out_Test.cxf,actgen_cxf"
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ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test/Igloo2_TFT_Video_Out_Test.vhd,hdl"
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PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test/Igloo2_TFT_Video_Out_Test.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf,actgen_cxf"
STATE="utd"
TIME="1414976072"
SIZE="27869"
ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.vhd,hdl"
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IS_READONLY="TRUE"
ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS_pre.vhd,hdl"
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TIME="1414976068"
SIZE="87012"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="PRECISION_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS_syn.vhd,hdl"
STATE="utd"
TIME="1414976068"
SIZE="86874"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test_top/Igloo2_TFT_Video_Out_Test_top.cxf,actgen_cxf"
STATE="utd"
TIME="1416227316"
SIZE="8782"
ENDFILE
VALUE "<project>/component/work/Igloo2_TFT_Video_Out_Test_top/Igloo2_TFT_Video_Out_Test_top.vhd,hdl"
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IS_READONLY="TRUE"
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TIME="1414646206"
SIZE="9115"
ENDFILE
VALUE "<project>/hdl/xcounter.vhd,hdl"
STATE="utd"
TIME="1414362443"
SIZE="2057"
ENDFILE
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STATE="utd"
TIME="1415035440"
SIZE="907"
ENDFILE
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STATE="utd"
TIME="1414976079"
SIZE="1462"
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ENDFILE
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STATE="utd"
TIME="1414360630"
SIZE="25928"
PARENT="<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/CoreAHBLite.cxf"
ENDFILE
VALUE "<project>/simulation/coreahblite_usertb_ahb_master1.bfm,sim"
STATE="utd"
TIME="1414360630"
SIZE="6200"
PARENT="<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/CoreAHBLite.cxf"
ENDFILE
VALUE "<project>/simulation/coreahblite_usertb_ahb_master2.bfm,sim"
STATE="utd"
TIME="1414360630"
SIZE="6200"
PARENT="<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/CoreAHBLite.cxf"
ENDFILE
VALUE "<project>/simulation/coreahblite_usertb_ahb_master3.bfm,sim"
STATE="utd"
TIME="1414360630"
SIZE="6200"
PARENT="<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/CoreAHBLite.cxf"
ENDFILE
VALUE "<project>/simulation/coreahblite_usertb_include.bfm,sim"
STATE="utd"
TIME="1414360630"
SIZE="12178"
PARENT="<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/CoreAHBLite.cxf"
ENDFILE
VALUE "<project>/simulation/peripheral_init.bfm,sim"
STATE="utd"
TIME="1414976072"
SIZE="7138"
PARENT="<project>/component/Actel/SmartFusion2MSS/MSS/1.1.209/MSS.cxf"
ENDFILE
VALUE "<project>/simulation/run.do,do"
STATE="utd"
TIME="1415035439"
SIZE="760"
ENDFILE
VALUE "<project>/simulation/subsystem.bfm,sim"
STATE="utd"
TIME="1416227316"
SIZE="1214"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_top/Igloo2_TFT_Video_Out_Test_top.cxf"
ENDFILE
VALUE "<project>/simulation/test.bfm,sim"
STATE="utd"
TIME="1414976072"
SIZE="520"
PARENT="<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.cxf"
ENDFILE
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STATE="utd"
TIME="1416227948"
SIZE="36508"
ENDFILE
VALUE "<project>/synthesis/Igloo2_TFT_Video_Out_Test_top.edn,syn_edn"
STATE="utd"
TIME="1416227898"
SIZE="12610889"
ENDFILE
VALUE "<project>/synthesis/Igloo2_TFT_Video_Out_Test_top.so,so"
STATE="utd"
TIME="1414985891"
SIZE="262"
ENDFILE
VALUE "<project>/synthesis/Igloo2_TFT_Video_Out_Test_top.vhd,syn_hdl"
STATE="utd"
TIME="1414985897"
SIZE="797708"
ENDFILE
VALUE "<project>/synthesis/Igloo2_TFT_Video_Out_Test_top_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1414985891"
SIZE="1461"
ENDFILE
VALUE "<project>/synthesis/Igloo2_TFT_Video_Out_Test_top_syn.prj,prj"
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TIME="1414985894"
SIZE="4540"
ENDFILE
VALUE "<project>/synthesis/synwork/Igloo2_TFT_Video_Out_Test_top_comp.so,so"
STATE="utd"
TIME="1414909846"
SIZE="154"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "Igloo2_TFT_Video_Out_Test::work"
FILE "<project>/component/work/Igloo2_TFT_Video_Out_Test/Igloo2_TFT_Video_Out_Test.vhd,hdl"
LIST Other_Association
VALUE "<project>/simulation/bfmtovec_compile.tcl,sim"
VALUE "<project>/simulation/coreahblite_usertb_include.bfm,sim"
VALUE "<project>/simulation/coreahblite_usertb_ahb_master0.bfm,sim"
VALUE "<project>/simulation/coreahblite_usertb_ahb_master1.bfm,sim"
VALUE "<project>/simulation/coreahblite_usertb_ahb_master2.bfm,sim"
VALUE "<project>/simulation/coreahblite_usertb_ahb_master3.bfm,sim"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/coreparameters.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/misc.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/textio.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_package.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_main.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbl.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/test/user/testbench.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/mti/scripts/wave_user.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/coreparameters.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/misc.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/textio.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_package.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_main.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbl.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/test/user/testbench.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "Igloo2_TFT_Video_Out_Test_HPMS::work"
FILE "<project>/component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS.vhd,hdl"
LIST Other_Association
VALUE "<project>/simulation/test.bfm,sim"
VALUE "<project>/simulation/peripheral_init.bfm,sim"
ENDLIST
ENDLIST
LIST "Igloo2_TFT_Video_Out_Test_top::work"
FILE "<project>/component/work/Igloo2_TFT_Video_Out_Test_top/Igloo2_TFT_Video_Out_Test_top.vhd,hdl"
LIST Other_Association
VALUE "<project>/simulation/subsystem.bfm,sim"
ENDLIST
LIST UserCustomizedFileList
LIST "ideSIMULATION"
USE_LIST=TRUE
FILELIST
ENDFILELIST
ENDLIST
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>/synthesis/Igloo2_TFT_Video_Out_Test_top.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST PinReports
VALUE "<project>/designer/Igloo2_TFT_Video_Out_Test_top/Igloo2_TFT_Video_Out_Test_top_pinrpt_name.rpt,log"
VALUE "<project>/designer/Igloo2_TFT_Video_Out_Test_top/Igloo2_TFT_Video_Out_Test_top_pinrpt_number.rpt,log"
VALUE "<project>/designer/Igloo2_TFT_Video_Out_Test_top/Igloo2_TFT_Video_Out_Test_top_bankrpt.rpt,log"
VALUE "<project>/designer/Igloo2_TFT_Video_Out_Test_top/Igloo2_TFT_Video_Out_Test_top_ioff.xml,log"
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST Igloo2_TFT_Video_Out_Test
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/coreparameters.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/misc.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/textio.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_package.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_main.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbl.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/test/user/testbench.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST Igloo2_TFT_Video_Out_Test_top
VALUE "<project>/simulation/subsystem.bfm,sim"
ENDLIST
LIST Igloo2_TFT_Video_Out_Test
VALUE "<project>/simulation/bfmtovec_compile.tcl,sim"
VALUE "<project>/simulation/coreahblite_usertb_include.bfm,sim"
VALUE "<project>/simulation/coreahblite_usertb_ahb_master0.bfm,sim"
VALUE "<project>/simulation/coreahblite_usertb_ahb_master1.bfm,sim"
VALUE "<project>/simulation/coreahblite_usertb_ahb_master2.bfm,sim"
VALUE "<project>/simulation/coreahblite_usertb_ahb_master3.bfm,sim"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/coreparameters.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/misc.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/textio.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_package.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_main.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbl.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslaveext.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslave.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/test/user/testbench.vhd,tb_hdl"
VALUE "<project>/component/Actel/DirectCore/CoreAHBLite/5.0.100/mti/scripts/wave_user.do,do"
ENDLIST
LIST Igloo2_TFT_Video_Out_Test_HPMS
VALUE "<project>/simulation/test.bfm,sim"
VALUE "<project>/simulation/peripheral_init.bfm,sim"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1fs
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
PeriInitStandalone=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=FALSE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Synplify Pro ME"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="/opt/microsemi/Libero_v11.4/Synplify/bin/synplify_pro"
PARAM="-licensetype synplifypro_actel -batch -log synplify.log"
BATCH=1
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSim ME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="/opt/microsemi/Libero_v11.4/Model/modeltech/linuxacoem/vsim"
PARAM="-l testbench_postsynth_simulation.log -c"
BATCH=1
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FlashPro"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="/opt/microsemi/Libero_v11.4/Libero/bin/flashpro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Identify Debugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "Igloo2_TFT_Video_Out_Test::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "Igloo2_TFT_Video_Out_Test_top::work"
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS(<project>/synthesis/Igloo2_TFT_Video_Out_Test_top.edn,syn_edn)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
LIST "Igloo2_TFT_Video_Out_Test_top"
LIST "ideSIMULATION"
USE_LIST=TRUE
FILELIST
ENDFILELIST
ENDLIST
ENDLIST
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Verify Power:Igloo2_TFT_Video_Out_Test_top_power_report.xml
SmartDesign;Igloo2_TFT_Video_Out_Test_top;0
StartPage;StartPage;0
ACTIVEVIEW;Reports
ENDLIST
LIST ModuleSubBlockList
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ENDLIST
LIST "coreconfigmaster_support::work","component/Actel/DirectCore/CoreConfigMaster/2.1.102/rtl/vhdl/core/coreconfigmaster.vhd","FALSE","FALSE"
ENDLIST
LIST "CoreConfigP::work","component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vhdl/core/coreconfigp.vhd","FALSE","FALSE"
ENDLIST
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SUBBLOCK "coreresetp_pcie_hotreset::work","component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vhdl/core/coreresetp_pcie_hotreset.vhd","FALSE","FALSE"
ENDLIST
LIST "coreresetp_pcie_hotreset::work","component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vhdl/core/coreresetp_pcie_hotreset.vhd","FALSE","FALSE"
ENDLIST
LIST "DEBOUNCE::work","hdl/Debounce.vhd","FALSE","FALSE"
ENDLIST
LIST "frameBuffer::work","hdl/frameBuffer.vhd","FALSE","FALSE"
ENDLIST
LIST "Igloo2_TFT_Video_Out_Test::work","component/work/Igloo2_TFT_Video_Out_Test/Igloo2_TFT_Video_Out_Test.vhd","TRUE","FALSE"
SUBBLOCK "Igloo2_TFT_Video_Out_Test_CCC_0_FCCC::work","component/work/Igloo2_TFT_Video_Out_Test/CCC_0/Igloo2_TFT_Video_Out_Test_CCC_0_FCCC.vhd","FALSE","FALSE"
SUBBLOCK "CoreConfigMaster::work","component/Actel/DirectCore/CoreConfigMaster/2.1.102/rtl/vhdl/core/coreconfigmaster.vhd","FALSE","FALSE"
SUBBLOCK "CoreConfigP::work","component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vhdl/core/coreconfigp.vhd","FALSE","FALSE"
SUBBLOCK "CoreResetP::work","component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vhdl/core/coreresetp.vhd","FALSE","FALSE"
SUBBLOCK "Igloo2_TFT_Video_Out_Test_FABOSC_0_OSC::work","component/work/Igloo2_TFT_Video_Out_Test/FABOSC_0/Igloo2_TFT_Video_Out_Test_FABOSC_0_OSC.vhd","FALSE","FALSE"
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SUBBLOCK "CoreAHBLite::COREAHBLITE_LIB::components","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/core/coreahblite.vhd","FALSE","FALSE"
ENDLIST
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ENDLIST
LIST "Igloo2_TFT_Video_Out_Test_FABOSC_0_OSC::work","component/work/Igloo2_TFT_Video_Out_Test/FABOSC_0/Igloo2_TFT_Video_Out_Test_FABOSC_0_OSC.vhd","FALSE","FALSE"
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SUBBLOCK "RCOSC_25_50MHZ::work","component/Actel/SgCore/OSC/1.0.102/osc_comps.vhd","FALSE","FALSE"
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ENDLIST
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SUBBLOCK "Igloo2_TFT_Video_Out_Test::work","component/work/Igloo2_TFT_Video_Out_Test/Igloo2_TFT_Video_Out_Test.vhd","TRUE","FALSE"
SUBBLOCK "lineBuffer::work","hdl/lineBuffer.vhd","FALSE","FALSE"
SUBBLOCK "patternGen::work","hdl/patternGen.vhd","FALSE","FALSE"
ENDLIST
LIST "lineBuffer::work","hdl/lineBuffer.vhd","FALSE","FALSE"
ENDLIST
LIST "MSS_010::work","component/work/Igloo2_TFT_Video_Out_Test_HPMS/Igloo2_TFT_Video_Out_Test_HPMS_syn.vhd","FALSE","FALSE"
ENDLIST
LIST "patternGen::work","hdl/patternGen.vhd","FALSE","FALSE"
SUBBLOCK "xcounter::work","hdl/xcounter.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ::work","component/Actel/SgCore/OSC/1.0.102/osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ_FAB::work","component/Actel/SgCore/OSC/1.0.102/osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ::work","component/Actel/SgCore/OSC/1.0.102/osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ_FAB::work","component/Actel/SgCore/OSC/1.0.102/osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "xcounter::work","hdl/xcounter.vhd","FALSE","FALSE"
ENDLIST
LIST "XTLOSC::work","component/Actel/SgCore/OSC/1.0.102/osc_comps.vhd","FALSE","FALSE"
ENDLIST
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ENDLIST
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SUBBLOCK "CoreAHBLite::COREAHBLITE_LIB::components","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/core/coreahblite.vhd","FALSE","FALSE"
ENDLIST
LIST "CoreAHBLite::COREAHBLITE_LIB::components","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/core/coreahblite.vhd","FALSE","FALSE"
SUBBLOCK "COREAHBLITE_MATRIX4X16::COREAHBLITE_LIB","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/core/coreahblite_matrix4x16.vhd","FALSE","FALSE"
ENDLIST
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ENDLIST
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ENDLIST
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ENDLIST
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SUBBLOCK "COREAHBLITE_MASTERSTAGE::COREAHBLITE_LIB","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/core/coreahblite_masterstage.vhd","FALSE","FALSE"
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ENDLIST
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ENDLIST
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ENDLIST
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ENDLIST
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SUBBLOCK "bfm_Main::COREAHBLITE_LIB::bfM_packAGE","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_main.vhd","FALSE","TRUE"
ENDLIST
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ENDLIST
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SUBBLOCK "Bfm_aHBSlavEEXt::COREAHBLITE_LIB::bfM_packAGE","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslaveext.vhd","FALSE","TRUE"
ENDLIST
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ENDLIST
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ENDLIST
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ENDLIST
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ENDLIST
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ENDLIST
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ENDLIST
LIST "bfm_misc::COREAHBLITE_LIB","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/misc.vhd","FALSE","TRUE"
ENDLIST
LIST "bfM_packAGE::COREAHBLITE_LIB","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_package.vhd","FALSE","TRUE"
SUBBLOCK "bfm_Main::COREAHBLITE_LIB::bfM_packAGE","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_main.vhd","FALSE","TRUE"
SUBBLOCK "Bfm_aHBSlavEEXt::COREAHBLITE_LIB::bfM_packAGE","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslaveext.vhd","FALSE","TRUE"
SUBBLOCK "BFM_ahbSLAve::COREAHBLITE_LIB::bfM_packAGE","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslave.vhd","FALSE","TRUE"
SUBBLOCK "BFm_apBSLaveEXT::COREAHBLITE_LIB","","FALSE","FALSE"
SUBBLOCK "BFM_apbSLAve::COREAHBLITE_LIB","","FALSE","FALSE"
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ENDLIST
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ENDLIST
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ENDLIST
LIST "BFMA1i1lI::COREAHBLITE_LIB","","FALSE","FALSE"
ENDLIST
LIST "coreparameters::COREAHBLITE_LIB","component/Actel/DirectCore/CoreAHBLite/5.0.100/coreparameters.vhd","FALSE","TRUE"
ENDLIST
LIST "testbench::COREAHBLITE_LIB","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/test/user/testbench.vhd","FALSE","TRUE"
SUBBLOCK "CoreAHBLite::COREAHBLITE_LIB::components","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/core/coreahblite.vhd","FALSE","FALSE"
SUBBLOCK "bfM_Ahbl::COREAHBLITE_LIB::bfM_packAGE","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbl.vhd","FALSE","TRUE"
SUBBLOCK "BFM_ahbSLAve::COREAHBLITE_LIB::bfM_packAGE","component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vhdl/amba_bfm/bfm_ahbslave.vhd","FALSE","TRUE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
ENDLIST