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cpu.vcd
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$version Generated by VerilatedVcd $end
$date Mon Nov 24 17:42:58 2014
$end
$timescale 1ns $end
$scope module TOP $end
$var wire 4 ? a [3:0] $end
$var wire 1 < clk $end
$var wire 8 > instruction [7:0] $end
$var wire 1 = rst $end
$scope module v $end
$var wire 32 D DECODE [31:0] $end
$var wire 32 E EXECUTE [31:0] $end
$var wire 32 C FETCH [31:0] $end
$var wire 32 B START [31:0] $end
$var wire 32 @ WAIT [31:0] $end
$var wire 4 ? a [3:0] $end
$var wire 32 E addaxx [31:0] $end
$var wire 4 6 addr [3:0] $end
$var wire 32 @ addr_width [31:0] $end
$var wire 32 D andaxx [31:0] $end
$var wire 1 < clk $end
$var wire 4 ; currentState [3:0] $end
$var wire 32 @ data_width [31:0] $end
$var wire 4 5 datain [3:0] $end
$var wire 4 : dataout [3:0] $end
$var wire 1 9 dir $end
$var wire 8 > instruction [7:0] $end
$var wire 8 8 ir [7:0] $end
$var wire 32 G jmpxx [31:0] $end
$var wire 32 F jzxx [31:0] $end
$var wire 32 B ldaxx [31:0] $end
$var wire 32 C ldxxa [31:0] $end
$var wire 32 A movaxx [31:0] $end
$var wire 32 I nandaxx [31:0] $end
$var wire 4 # nextState [3:0] $end
$var wire 32 H nop [31:0] $end
$var wire 32 K noraxx [31:0] $end
$var wire 32 N nota [31:0] $end
$var wire 32 @ op_param [31:0] $end
$var wire 32 @ op_width [31:0] $end
$var wire 32 J oraxx [31:0] $end
$var wire 8 7 pc [7:0] $end
$var wire 32 A pc_width [31:0] $end
$var wire 1 = rst $end
$var wire 32 @ subaxx [31:0] $end
$var wire 32 M xnoraxx [31:0] $end
$var wire 32 L xoraxx [31:0] $end
$scope module cpu_mem $end
$var wire 32 B READ [31:0] $end
$var wire 32 C WRITE [31:0] $end
$var wire 4 6 addr [3:0] $end
$var wire 32 @ addr_width [31:0] $end
$var wire 1 < clk $end
$var wire 4 $ data(0) [3:0] $end
$var wire 4 % data(1) [3:0] $end
$var wire 4 . data(10) [3:0] $end
$var wire 4 / data(11) [3:0] $end
$var wire 4 0 data(12) [3:0] $end
$var wire 4 1 data(13) [3:0] $end
$var wire 4 2 data(14) [3:0] $end
$var wire 4 3 data(15) [3:0] $end
$var wire 4 & data(2) [3:0] $end
$var wire 4 ' data(3) [3:0] $end
$var wire 4 ( data(4) [3:0] $end
$var wire 4 ) data(5) [3:0] $end
$var wire 4 * data(6) [3:0] $end
$var wire 4 + data(7) [3:0] $end
$var wire 4 , data(8) [3:0] $end
$var wire 4 - data(9) [3:0] $end
$var wire 32 @ data_width [31:0] $end
$var wire 4 5 datain [3:0] $end
$var wire 4 : dataout [3:0] $end
$var wire 4 4 i [3:0] $end
$var wire 1 = rst $end
$var wire 1 9 rw $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b0000 #
b0000 $
b0000 %
b0000 &
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b00000000000000000000000000001000 A
b00000000000000000000000000000010 D
b00000000000000000000000000000011 E
b00000000000000000000000000000101 F
b00000000000000000000000000000110 G
b00000000000000000000000000000111 H
b00000000000000000000000000001001 I
b00000000000000000000000000001010 J
b00000000000000000000000000001011 K
b00000000000000000000000000001100 L
b00000000000000000000000000001101 M
b00000000000000000000000000001110 N
b00000000000000000000000000000100 @
b00000000000000000000000000000001 C
b00000000000000000000000000000000 B
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b0000 6
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b0000 :
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b0000 ?
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b0001 ;
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b0011 #
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b10000001 >
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b0010 #
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b0011 #
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b0001 #
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b0010 #
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b0011 #
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b0100 #
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1<
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b0001 #
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1<
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0<
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b0010 #
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1<
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b0011 #
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b0100 #
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b0001 #
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b0010 #
b0001 ;
1<
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0<
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b0011 #
b00001110 7
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1<
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b0100 #
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b0001 #
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1<
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1<
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b0011 #
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b01101010 8
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b0100 #
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b0001 #
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1<
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b0010 #
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b0011 #
b0101 6
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b0100 #
b0001 :
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#175
b0001 #
b0100 ;
b0101 ?
1<
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0<
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b0010 #
b0001 ;
1<
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0<
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b0011 #
b0000 6
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b00010000 8
b0010 ;
1<
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0<
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b0100 #
b0000 :
b0011 ;
1<
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0<
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b0001 #
b0101 5
19
b0100 ;
1<
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b10000001 >
0<
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b0010 #
b0101 $
b0101 :
b0001 ;
1<
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0<
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b0011 #
b0001 6
b00001101 7
b10000001 8
09
b0010 ;
1<
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0<
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b0100 #
b0000 :
b0011 ;
1<
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0<
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b0001 #
b0100 ;
b0001 ?
1<
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b00100000 >
0<
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b0010 #
b0001 ;
1<
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0<
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b0011 #
b0000 6
b00001110 7
b00100000 8
b0010 ;
1<
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0<
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b0100 #
b0101 :
b0011 ;
1<
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0<
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b0001 #
b0100 ;
1<
#200
b10010101 >
0<
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b0010 #
b0001 ;
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#202
0<
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b0011 #
b0101 6
b00001111 7
b10010101 8
b0010 ;
1<
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0<
#205
b0100 #
b0001 :
b0011 ;
1<
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0<
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b0001 #
b0100 ;
b1110 ?
1<
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b10110000 >
0<
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b0010 #
b0001 ;
1<
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0<
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b0011 #
b0000 6
b00010000 7
b10110000 8
b0010 ;
1<
#212
0<
#213
b0100 #
b0101 :
b0011 ;
1<
#214
0<
#215
b0001 #
b0100 ;
b0000 ?
1<
#216
b10100100 >
0<
#217
b0010 #
b0001 ;
1<
#218
0<
#219
b0011 #
b0100 6
b00010001 7
b10100100 8
b0010 ;
1<
#220
0<
#221
b0100 #
b0010 :
b0011 ;
1<
#222
0<
#223
b0001 #
b0100 ;
b0010 ?
1<
#224
b11000000 >
0<
#225
b0010 #
b0001 ;
1<
#226
0<
#227
b0011 #
b0000 6
b00010010 7
b11000000 8
b0010 ;
1<
#228
0<
#229
b0100 #
b0101 :
b0011 ;
1<
#230
0<
#231
b0001 #
b0100 ;
b0111 ?
1<
#232
b11010000 >
0<
#233
b0010 #
b0001 ;
1<
#234
0<
#235
b0011 #
b00010011 7
b11010000 8
b0010 ;
1<
#236
0<