Add check of silkscreen clearance to exposed copper (F5.1)

[diegoherranz]

It would be good to have this checked automatically.

Thanks!

[evanshultz]

This clearance is specified at http://kicad-pcb.org/libraries/klc/F5.1/.

While KLC mentions 0.2mm of clearance, recent IPC 7351 docs say the line width (for us it's 0.12mm) is acceptable and in fact we have done this on footprints already. So KLC really needs an update.

With that out of the way, this is already checked. See checkIntersections() at https://github.com/KiCad/kicad-library-utils/blob/master/pcb/rules/F5_1.py. The code is quite basic, though, so I suspect you found a false negative (clearance violations weren't caught by the script). If you point out the footprint and location where this was a problem perhaps it will lead clearly to some improvement of the script?

[poeschlr]

I would allow smaller clearance for small parts. (Edit: Is smaller than 0603 reasonable here? That would put the rules to something similar as with the courtyard clearance.)
The vast majority of parts can easily use larger silk to pad clearance allowing the footprints to be used at cheaper fab houses.

[diegoherranz]

Thank you both. It seems that the KLC needs an update on this aspect, then.

If this is already checked (I had a quick look at the F5_1.py file before submitting this but I assumed that checkIntersections() was for actual clashes and not clearance checks), then I think I found a false negative here:
KiCad/kicad-footprints#1388

Thanks!

[poeschlr]

Silk is not really checked right now. There are some primitive checks but that is it. (It is normally quite obvious from the screenshot if something is not right with the silk layer. But you are right proper checks could help us.)

[diegoherranz]

Yes, it's an easy one to spot. But the more automated it is, the better :)
Low priority, obviously.