diff --git a/FABulous/FABulous_CLI/FABulous.py b/FABulous/FABulous_CLI/FABulous.py
index a6bc5a79..990e0bc5 100644
--- a/FABulous/FABulous_CLI/FABulous.py
+++ b/FABulous/FABulous_CLI/FABulous.py
@@ -1064,8 +1064,10 @@ def main():
 
         if os.getenv("FAB_PROJ_LANG") == "vhdl":
             writer = VHDLWriter()
+            logger.debug("VHDL writer selected")
         elif os.getenv("FAB_PROJ_LANG") == "verilog":
             writer = VerilogWriter()
+            logger.debug("Verilog writer selected")
         else:
             logger.error(
                 f"Invalid projct language specified: {os.getenv('FAB_PROJ_LANG')}"
diff --git a/FABulous/FABulous_CLI/helper.py b/FABulous/FABulous_CLI/helper.py
index 450651ca..a1007162 100644
--- a/FABulous/FABulous_CLI/helper.py
+++ b/FABulous/FABulous_CLI/helper.py
@@ -119,7 +119,10 @@ def setup_project_env_vars(args: argparse.Namespace) -> None:
         logger.warning("No project .env file found")
 
     # Overwrite project language param, if writer is specified as command line argument
-    if args.writer:
+    if args.writer and args.writer != os.getenv("FAB_PROJ_LANG"):
+        logger.warning(
+            f"Overwriting project language for current run, from {os.getenv('FAB_PROJ_LANG')} to {args.writer}, which was specified as command line argument"
+        )
         os.environ["FAB_PROJ_LANG"] = args.writer
 
 
@@ -163,6 +166,10 @@ def create_project(project_dir, type: Literal["verilog", "vhdl"] = "verilog"):
     else:
         os.mkdir(f"{project_dir}")
 
+    # set default type, since "None" overwrites the default value
+    if not type:
+        type = "verilog"
+
     os.mkdir(f"{project_dir}/.FABulous")
     fabulousRoot = os.getenv("FAB_ROOT")
 
@@ -182,6 +189,8 @@ def create_project(project_dir, type: Literal["verilog", "vhdl"] = "verilog"):
 
     adjust_directory_in_verilog_tb(project_dir)
 
+    logger.info(f"New FABulous project created in {project_dir} with {type} language.")
+
 
 def copy_verilog_files(src: Path, dst: Path):
     """Copies all Verilog files from source directory to the destination directory.