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ASIPVectorial.qsf
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ASIPVectorial.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 21:27:55 October 26, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# ASIPVectorial_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC7C7F23C8
set_global_assignment -name TOP_LEVEL_ENTITY CPU_top_TB
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:55 OCTOBER 26, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/control_limit_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/control_limit.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/CPU_Datapath_ID.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/instr_decoder.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/control_unit.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/CPU_vector_TB.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/CPU_vector.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/CPU_top_TB.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/CPU_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/instr_decoder_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/control_unit_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/instr_decoder.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/control_unit.sv
set_global_assignment -name SYSTEMVERILOG_FILE testbenchCPU.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/multiplier_fp_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/multiplier_fp.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/adder_fp_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/adder_fp.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/mux16_1.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/mux8_1.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/mux4_1.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/mux2_1.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/ALU.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/adder.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/top.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/regMemWB.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/regfile.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/regFetchDecode.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/regExeMem.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/regDecodeExe.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/imem.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/floprneg.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/flopr.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/flopenr.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/extend.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/dmem.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/datapath.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/cpu.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/controller.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/condlogic.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/condcheck.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/dmem_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/ALU_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/vector_top.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/vector_cpu.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/vector_datapath.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/vector_top_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/scalar_reg_bank.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/scalar_reg_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/fp_reg_bank.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/vector_reg_bank.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/vector_reg_bank_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/lanes.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/lanes_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/scalar_reg_bank_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/out_vector.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/out_vector_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/vector_mux.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/vector_mux_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/zero_ext_32.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU/eq.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/eq_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE ALU/ALU_scalar.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/vector_cpu_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/alu_scalar_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/IF/CPU_Datapath_IF.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/IF/CPU_vector_TB.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/TB/instr_decoder_ID_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/TB/control_unit_ID_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/address_calculator.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/address_calc_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/mult_mem.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/TB/mult_mem_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/const_mem.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/addr_updater.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/TB/addr_updater_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/sum_mem.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/TB/sum_mem_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/vector_data_mux.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/TB/vector_data_mux_tb.sv
set_global_assignment -name SYSTEMVERILOG_FILE PlanB/ID/pc_reg.sv
set_global_assignment -name SYSTEMVERILOG_FILE tb/imem_tb.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top