ram_dp_32x2048_sim.v

/*
 * Copyright (C) 2019  Jeroen Domburg <jeroen@spritesmods.com>
 * All rights reserved.
 *
 * BSD 3-clause, see LICENSE.bsd
 *
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 * modification, are permitted provided that the following conditions are met:
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 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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 */

module ram_dp_32x2048 (
	input wire ClockA,
	input wire ClockB,
	input wire ClockEnA,
	input wire ClockEnB,
	input wire ResetA,
	input wire ResetB,
	input wire [31:0] DataInA,
	input wire [31:0] DataInB,
	input wire [10:0] AddressA,
	input wire [10:0] AddressB,
	input wire WrA,
	input wire WrB,
	output reg [31:0] QA,
	output reg [31:0] QB
);

reg [31:0] mem[0:2047];


always @(posedge ClockA) begin
	if (ResetA) begin
		QA <= 0;
	end else begin
		QA <= mem[AddressA];
		if (WrA) begin
			mem[AddressA] <= DataInA;
		end
	end
end


always @(posedge ClockB) begin
	if (ResetB) begin
		QB <= 0;
	end else begin
		QB <= mem[AddressB];
		if (WrB) begin
			mem[AddressB] <= DataInB;
		end
	end
end

endmodule;