synth_ro_top.v

/* Generated by Yosys 0.43+22 (git sha1 118b2829d, g++ 12.2.0-14 -fPIC -Os) */

(* dynports =  1  *)
(* top =  1  *)
(* src = "generic_ro.v:5.1-22.10" *)
module generic_ro(en, ro_out);
  (* src = "generic_ro.v:6.11-6.13" *)
  input en;
  wire en;
  (* src = "generic_ro.v:10.20-10.32" *)
  wire [4:0] interm_wires;
  (* src = "generic_ro.v:7.12-7.18" *)
  output ro_out;
  wire ro_out;
  assign interm_wires[0] = ~(en & ro_out);
  (* module_not_derived = 32'd1 *)
  (* src = "generic_ro.v:18.21-18.58" *)
  notGate \genblk1[1].n  (
    .a(interm_wires[0]),
    .inversedA(interm_wires[1])
  );
  (* module_not_derived = 32'd1 *)
  (* src = "generic_ro.v:18.21-18.58" *)
  notGate \genblk1[2].n  (
    .a(interm_wires[1]),
    .inversedA(interm_wires[2])
  );
  (* module_not_derived = 32'd1 *)
  (* src = "generic_ro.v:18.21-18.58" *)
  notGate \genblk1[3].n  (
    .a(interm_wires[2]),
    .inversedA(interm_wires[3])
  );
  (* module_not_derived = 32'd1 *)
  (* src = "generic_ro.v:18.21-18.58" *)
  notGate \genblk1[4].n  (
    .a(interm_wires[3]),
    .inversedA(ro_out)
  );
  assign interm_wires[4] = ro_out;
endmodule

(* src = "notModule.v:1.1-9.10" *)
module notGate(a, inversedA);
  (* src = "notModule.v:3.7-3.8" *)
  input a;
  wire a;
  (* src = "notModule.v:4.8-4.17" *)
  output inversedA;
  wire inversedA;
  assign inversedA = ~a;
endmodule