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XOR.circ
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XOR.circ
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.7.1" version="1.0">
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
<lib desc="#Wiring" name="0"/>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#Base" name="6">
<tool name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
</lib>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="6" map="Button2" name="Menu Tool"/>
<tool lib="6" map="Button3" name="Menu Tool"/>
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="6" name="Poke Tool"/>
<tool lib="6" name="Edit Tool"/>
<tool lib="6" name="Text Tool">
<a name="text" val=""/>
<a name="font" val="SansSerif plain 12"/>
<a name="halign" val="center"/>
<a name="valign" val="base"/>
</tool>
<sep/>
<tool lib="0" name="Pin">
<a name="tristate" val="false"/>
</tool>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</tool>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
</toolbar>
<circuit name="main">
<a name="circuit" val="main"/>
<a name="clabel" val=""/>
<a name="clabelup" val="east"/>
<a name="clabelfont" val="SansSerif plain 12"/>
<wire from="(140,250)" to="(170,250)"/>
<wire from="(480,190)" to="(510,190)"/>
<wire from="(170,250)" to="(230,250)"/>
<wire from="(260,250)" to="(280,250)"/>
<wire from="(160,230)" to="(280,230)"/>
<wire from="(330,120)" to="(380,120)"/>
<wire from="(330,240)" to="(380,240)"/>
<wire from="(380,180)" to="(430,180)"/>
<wire from="(380,200)" to="(430,200)"/>
<wire from="(380,200)" to="(380,240)"/>
<wire from="(140,110)" to="(160,110)"/>
<wire from="(260,110)" to="(280,110)"/>
<wire from="(170,130)" to="(280,130)"/>
<wire from="(160,110)" to="(230,110)"/>
<wire from="(380,120)" to="(380,180)"/>
<wire from="(160,110)" to="(160,230)"/>
<wire from="(170,130)" to="(170,250)"/>
<comp lib="1" loc="(260,250)" name="NOT Gate"/>
<comp lib="1" loc="(330,120)" name="AND Gate"/>
<comp lib="1" loc="(480,190)" name="OR Gate"/>
<comp lib="0" loc="(510,190)" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
<a name="labelloc" val="east"/>
</comp>
<comp lib="6" loc="(271,67)" name="Text">
<a name="text" val="XOR Circuit"/>
</comp>
<comp lib="1" loc="(330,240)" name="AND Gate"/>
<comp lib="0" loc="(140,250)" name="Pin">
<a name="tristate" val="false"/>
</comp>
<comp lib="1" loc="(260,110)" name="NOT Gate"/>
<comp lib="0" loc="(140,110)" name="Pin">
<a name="tristate" val="false"/>
</comp>
</circuit>
</project>