From a6ce5c44b0361c9f104613833a03bbadf53ed5bd Mon Sep 17 00:00:00 2001 From: Christian Fruth Date: Fri, 20 Jul 2018 19:58:21 +0200 Subject: [PATCH] Upgrade to Quartus 18.0 --- audio_pll.bsf | 2 +- audio_pll.qip | 20 +++++++++---------- audio_pll.sip | 2 +- audio_pll.vhd | 6 +++--- audio_pll_sim/aldec/rivierapro_setup.tcl | 4 ++-- audio_pll_sim/audio_pll.vho | 4 ++-- audio_pll_sim/cadence/ncsim_setup.sh | 6 +++--- audio_pll_sim/mentor/msim_setup.tcl | 4 ++-- audio_pll_sim/synopsys/vcsmx/vcsmx_setup.sh | 6 +++--- datamem.cmp | 2 +- datamem.qip | 2 +- datamem.vhd | 4 ++-- frmmem.cmp | 2 +- frmmem.qip | 2 +- frmmem.vhd | 4 ++-- master_pll.bsf | 2 +- master_pll.qip | 20 +++++++++---------- master_pll.sip | 2 +- master_pll.vhd | 6 +++--- master_pll_sim/aldec/rivierapro_setup.tcl | 4 ++-- master_pll_sim/cadence/ncsim_setup.sh | 6 +++--- master_pll_sim/master_pll.vho | 4 ++-- master_pll_sim/mentor/msim_setup.tcl | 4 ++-- master_pll_sim/synopsys/vcsmx/vcsmx_setup.sh | 6 +++--- master_reconfig.bsf | 2 +- master_reconfig.qip | 20 +++++++++---------- master_reconfig.sip | 2 +- master_reconfig.vhd | 6 +++--- master_reconfig/altera_pll_reconfig_core.v | 2 +- master_reconfig/altera_pll_reconfig_top.v | 2 +- master_reconfig/altera_std_synchronizer.v | 8 ++++---- .../aldec/rivierapro_setup.tcl | 4 ++-- .../altera_pll_reconfig_core.v | 2 +- .../altera_pll_reconfig_top.v | 2 +- .../altera_std_synchronizer.v | 8 ++++---- master_reconfig_sim/cadence/ncsim_setup.sh | 6 +++--- master_reconfig_sim/master_reconfig.vhd | 2 +- master_reconfig_sim/mentor/msim_setup.tcl | 4 ++-- .../synopsys/vcsmx/vcsmx_setup.sh | 6 +++--- nes.qsf | 8 ++++---- progmem.cmp | 2 +- progmem.qip | 2 +- progmem.vhd | 4 ++-- soamem.cmp | 2 +- soamem.qip | 2 +- soamem.vhd | 4 ++-- spritemem.cmp | 2 +- spritemem.qip | 2 +- spritemem.vhd | 4 ++-- vga_pll.bsf | 2 +- vga_pll.qip | 20 +++++++++---------- vga_pll.sip | 2 +- vga_pll.vhd | 6 +++--- vga_pll_sim/aldec/rivierapro_setup.tcl | 4 ++-- vga_pll_sim/cadence/ncsim_setup.sh | 6 +++--- vga_pll_sim/mentor/msim_setup.tcl | 4 ++-- vga_pll_sim/synopsys/vcsmx/vcsmx_setup.sh | 6 +++--- vga_pll_sim/vga_pll.vho | 4 ++-- videomem.cmp | 2 +- videomem.qip | 2 +- videomem.vhd | 4 ++-- videorom.cmp | 2 +- videorom.qip | 2 +- videorom.vhd | 4 ++-- 64 files changed, 151 insertions(+), 151 deletions(-) diff --git a/audio_pll.bsf b/audio_pll.bsf index c1bdd2c..c1722dd 100644 --- a/audio_pll.bsf +++ b/audio_pll.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 2017 Intel Corporation. All rights reserved. +Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing diff --git a/audio_pll.qip b/audio_pll.qip index 58b11ff..7b3a7ac 100644 --- a/audio_pll.qip +++ b/audio_pll.qip @@ -1,5 +1,5 @@ set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "audio_pll" -name MISC_FILE [file join $::quartus(qip_path) "audio_pll.cmp"] set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" @@ -7,19 +7,19 @@ set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_GENERATE set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_QSYS_MODE "UNKNOWN" set_global_assignment -name SYNTHESIS_ONLY_QIP ON set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_NAME "YXVkaW9fcGxs" -set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_VERSION "MTcuMQ==" -set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "audio_pll" -library "audio_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_NAME "YXVkaW9fcGxsXzAwMDI=" -set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_VERSION "MTcuMQ==" -set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl" @@ -334,5 +334,5 @@ set_global_assignment -library "audio_pll" -name VERILOG_FILE [file join $::quar set_global_assignment -library "audio_pll" -name QIP_FILE [file join $::quartus(qip_path) "audio_pll/audio_pll_0002.qip"] set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "audio_pll_0002" -library "audio_pll" -name IP_TOOL_ENV "mwpim" diff --git a/audio_pll.sip b/audio_pll.sip index 7af2aff..0317425 100644 --- a/audio_pll.sip +++ b/audio_pll.sip @@ -1,5 +1,5 @@ set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "audio_pll" -library "lib_audio_pll" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "lib_audio_pll" -name SPD_FILE [file join $::quartus(sip_path) "audio_pll.spd"] diff --git a/audio_pll.vhd b/audio_pll.vhd index c9b46be..7ba428f 100644 --- a/audio_pll.vhd +++ b/audio_pll.vhd @@ -1,8 +1,8 @@ --- megafunction wizard: %Altera PLL v17.1% +-- megafunction wizard: %PLL Intel FPGA IP v18.0% -- GENERATION: XML -- audio_pll.vhd --- Generated using ACDS version 17.1 590 +-- Generated using ACDS version 18.0 614 library IEEE; use IEEE.std_logic_1164.all; @@ -64,7 +64,7 @@ end architecture rtl; -- of audio_pll -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> --- Retrieval info: +-- Retrieval info: -- Retrieval info: -- Retrieval info: -- Retrieval info: diff --git a/audio_pll_sim/aldec/rivierapro_setup.tcl b/audio_pll_sim/aldec/rivierapro_setup.tcl index fd08095..6918842 100644 --- a/audio_pll_sim/aldec/rivierapro_setup.tcl +++ b/audio_pll_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:39:30 +# ACDS 18.0 614 win32 2018.07.18.19:32:54 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- @@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] { } if ![info exists QUARTUS_INSTALL_DIR] { - set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/" + set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/" } if ![info exists USER_DEFINED_COMPILE_OPTIONS] { diff --git a/audio_pll_sim/audio_pll.vho b/audio_pll_sim/audio_pll.vho index 6abbe16..c95d530 100644 --- a/audio_pll_sim/audio_pll.vho +++ b/audio_pll_sim/audio_pll.vho @@ -1,8 +1,8 @@ --IP Functional Simulation Model ---VERSION_BEGIN 17.1 cbx_mgl 2017:10:25:18:08:29:SJ cbx_simgen 2017:10:25:18:06:53:SJ VERSION_END +--VERSION_BEGIN 18.0 cbx_mgl 2018:04:24:18:08:49:SJ cbx_simgen 2018:04:24:18:04:18:SJ VERSION_END --- Copyright (C) 2017 Intel Corporation. All rights reserved. +-- Copyright (C) 2018 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing diff --git a/audio_pll_sim/cadence/ncsim_setup.sh b/audio_pll_sim/cadence/ncsim_setup.sh index bc780ab..f3ad8a6 100644 --- a/audio_pll_sim/cadence/ncsim_setup.sh +++ b/audio_pll_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:39:30 +# ACDS 18.0 614 win32 2018.07.18.19:32:54 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,12 +106,12 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:39:30 +# ACDS 18.0 614 win32 2018.07.18.19:32:54 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="audio_pll" QSYS_SIMDIR="./../" -QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/" +QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/" SKIP_FILE_COPY=0 SKIP_DEV_COM=0 SKIP_COM=0 diff --git a/audio_pll_sim/mentor/msim_setup.tcl b/audio_pll_sim/mentor/msim_setup.tcl index 46781d2..2806633 100644 --- a/audio_pll_sim/mentor/msim_setup.tcl +++ b/audio_pll_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:39:30 +# ACDS 18.0 614 win32 2018.07.18.19:32:54 # ---------------------------------------- # Initialize variables @@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] { } if ![info exists QUARTUS_INSTALL_DIR] { - set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/" + set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/" } if ![info exists USER_DEFINED_COMPILE_OPTIONS] { diff --git a/audio_pll_sim/synopsys/vcsmx/vcsmx_setup.sh b/audio_pll_sim/synopsys/vcsmx/vcsmx_setup.sh index 6728021..6b3173a 100644 --- a/audio_pll_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/audio_pll_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:39:30 +# ACDS 18.0 614 win32 2018.07.18.19:32:54 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,12 +107,12 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:39:30 +# ACDS 18.0 614 win32 2018.07.18.19:32:54 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="audio_pll" QSYS_SIMDIR="./../../" -QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/" +QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/" SKIP_FILE_COPY=0 SKIP_DEV_COM=0 SKIP_COM=0 diff --git a/datamem.cmp b/datamem.cmp index ea1b2e0..2a199de 100644 --- a/datamem.cmp +++ b/datamem.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/datamem.qip b/datamem.qip index 371fa68..0a4ed18 100644 --- a/datamem.qip +++ b/datamem.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "18.0" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "datamem.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "datamem.cmp"] diff --git a/datamem.vhd b/datamem.vhd index ac66201..37e62fa 100644 --- a/datamem.vhd +++ b/datamem.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 17.1.0 Build 590 10/25/2017 SJ Lite Edition +-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition -- ************************************************************ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/frmmem.cmp b/frmmem.cmp index b7bc067..a6559b1 100644 --- a/frmmem.cmp +++ b/frmmem.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/frmmem.qip b/frmmem.qip index aba4244..d6558ad 100644 --- a/frmmem.qip +++ b/frmmem.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "18.0" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "frmmem.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "frmmem.cmp"] diff --git a/frmmem.vhd b/frmmem.vhd index 9ef13f2..ab65d39 100644 --- a/frmmem.vhd +++ b/frmmem.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 17.1.0 Build 590 10/25/2017 SJ Lite Edition +-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition -- ************************************************************ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/master_pll.bsf b/master_pll.bsf index d06d926..055135e 100644 --- a/master_pll.bsf +++ b/master_pll.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 2017 Intel Corporation. All rights reserved. +Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing diff --git a/master_pll.qip b/master_pll.qip index 0fd75a6..8a7479f 100644 --- a/master_pll.qip +++ b/master_pll.qip @@ -1,5 +1,5 @@ set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "master_pll" -name MISC_FILE [file join $::quartus(qip_path) "master_pll.cmp"] set_global_assignment -entity "master_pll" -library "master_pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" @@ -7,19 +7,19 @@ set_global_assignment -entity "master_pll" -library "master_pll" -name IP_GENERA set_global_assignment -entity "master_pll" -library "master_pll" -name IP_QSYS_MODE "UNKNOWN" set_global_assignment -name SYNTHESIS_ONLY_QIP ON set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_NAME "bWFzdGVyX3BsbA==" -set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_VERSION "MTcuMQ==" -set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "master_pll" -library "master_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_NAME "bWFzdGVyX3BsbF8wMDAy" -set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_VERSION "MTcuMQ==" -set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl" @@ -480,5 +480,5 @@ set_global_assignment -library "master_pll" -name VERILOG_FILE [file join $::qua set_global_assignment -library "master_pll" -name QIP_FILE [file join $::quartus(qip_path) "master_pll/master_pll_0002.qip"] set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "master_pll_0002" -library "master_pll" -name IP_TOOL_ENV "mwpim" diff --git a/master_pll.sip b/master_pll.sip index d658d89..ee1d6e9 100644 --- a/master_pll.sip +++ b/master_pll.sip @@ -1,5 +1,5 @@ set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "master_pll" -library "lib_master_pll" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "lib_master_pll" -name SPD_FILE [file join $::quartus(sip_path) "master_pll.spd"] diff --git a/master_pll.vhd b/master_pll.vhd index 2824212..d3d74bd 100644 --- a/master_pll.vhd +++ b/master_pll.vhd @@ -1,8 +1,8 @@ --- megafunction wizard: %Altera PLL v17.1% +-- megafunction wizard: %PLL Intel FPGA IP v18.0% -- GENERATION: XML -- master_pll.vhd --- Generated using ACDS version 17.1 590 +-- Generated using ACDS version 18.0 614 library IEEE; use IEEE.std_logic_1164.all; @@ -70,7 +70,7 @@ end architecture rtl; -- of master_pll -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> --- Retrieval info: +-- Retrieval info: -- Retrieval info: -- Retrieval info: -- Retrieval info: diff --git a/master_pll_sim/aldec/rivierapro_setup.tcl b/master_pll_sim/aldec/rivierapro_setup.tcl index 9746e48..13519a1 100644 --- a/master_pll_sim/aldec/rivierapro_setup.tcl +++ b/master_pll_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:38:59 +# ACDS 18.0 614 win32 2018.07.18.19:32:25 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- @@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] { } if ![info exists QUARTUS_INSTALL_DIR] { - set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/" + set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/" } if ![info exists USER_DEFINED_COMPILE_OPTIONS] { diff --git a/master_pll_sim/cadence/ncsim_setup.sh b/master_pll_sim/cadence/ncsim_setup.sh index c48e29c..5e0beb1 100644 --- a/master_pll_sim/cadence/ncsim_setup.sh +++ b/master_pll_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:38:59 +# ACDS 18.0 614 win32 2018.07.18.19:32:25 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,12 +106,12 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:38:59 +# ACDS 18.0 614 win32 2018.07.18.19:32:25 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="master_pll" QSYS_SIMDIR="./../" -QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/" +QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/" SKIP_FILE_COPY=0 SKIP_DEV_COM=0 SKIP_COM=0 diff --git a/master_pll_sim/master_pll.vho b/master_pll_sim/master_pll.vho index 0347de2..d5e7d5c 100644 --- a/master_pll_sim/master_pll.vho +++ b/master_pll_sim/master_pll.vho @@ -1,8 +1,8 @@ --IP Functional Simulation Model ---VERSION_BEGIN 17.1 cbx_mgl 2017:10:25:18:08:29:SJ cbx_simgen 2017:10:25:18:06:53:SJ VERSION_END +--VERSION_BEGIN 18.0 cbx_mgl 2018:04:24:18:08:49:SJ cbx_simgen 2018:04:24:18:04:18:SJ VERSION_END --- Copyright (C) 2017 Intel Corporation. All rights reserved. +-- Copyright (C) 2018 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing diff --git a/master_pll_sim/mentor/msim_setup.tcl b/master_pll_sim/mentor/msim_setup.tcl index c9aabcc..daef149 100644 --- a/master_pll_sim/mentor/msim_setup.tcl +++ b/master_pll_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:38:59 +# ACDS 18.0 614 win32 2018.07.18.19:32:25 # ---------------------------------------- # Initialize variables @@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] { } if ![info exists QUARTUS_INSTALL_DIR] { - set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/" + set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/" } if ![info exists USER_DEFINED_COMPILE_OPTIONS] { diff --git a/master_pll_sim/synopsys/vcsmx/vcsmx_setup.sh b/master_pll_sim/synopsys/vcsmx/vcsmx_setup.sh index fc2fa9d..3af9805 100644 --- a/master_pll_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/master_pll_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:38:59 +# ACDS 18.0 614 win32 2018.07.18.19:32:25 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,12 +107,12 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:38:59 +# ACDS 18.0 614 win32 2018.07.18.19:32:25 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="master_pll" QSYS_SIMDIR="./../../" -QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/" +QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/" SKIP_FILE_COPY=0 SKIP_DEV_COM=0 SKIP_COM=0 diff --git a/master_reconfig.bsf b/master_reconfig.bsf index f90c499..5d5e680 100644 --- a/master_reconfig.bsf +++ b/master_reconfig.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 2017 Intel Corporation. All rights reserved. +Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing diff --git a/master_reconfig.qip b/master_reconfig.qip index b98b187..3fd2bea 100644 --- a/master_reconfig.qip +++ b/master_reconfig.qip @@ -1,5 +1,5 @@ set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" -set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "master_reconfig" -name MISC_FILE [file join $::quartus(qip_path) "master_reconfig.cmp"] set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" @@ -7,12 +7,12 @@ set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_QSYS_MODE "UNKNOWN" set_global_assignment -name SYNTHESIS_ONLY_QIP ON set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_NAME "bWFzdGVyX3JlY29uZmln" -set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw==" +set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_DISPLAY_NAME "UExMIFJlY29uZmlnIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_VERSION "MTcuMQ==" -set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ==" +set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3AgUmVjb25maWd1cmF0aW9uIEJsb2Nr" set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" @@ -20,12 +20,12 @@ set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" set_global_assignment -entity "master_reconfig" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A=" -set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_DISPLAY_NAME "UExMIFJlY29uZmlnIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_VERSION "MTcuMQ==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3AgUmVjb25maWd1cmF0aW9uIEJsb2Nr" set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ==" set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc=" set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" @@ -41,5 +41,5 @@ set_global_assignment -library "master_reconfig" -name VERILOG_FILE [file join $ set_global_assignment -library "master_reconfig" -name VERILOG_FILE [file join $::quartus(qip_path) "master_reconfig/altera_std_synchronizer.v"] set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" -set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "altera_pll_reconfig_top" -library "master_reconfig" -name IP_TOOL_ENV "mwpim" diff --git a/master_reconfig.sip b/master_reconfig.sip index 8de53cd..31bb5fb 100644 --- a/master_reconfig.sip +++ b/master_reconfig.sip @@ -1,5 +1,5 @@ set_global_assignment -entity "master_reconfig" -library "lib_master_reconfig" -name IP_TOOL_NAME "altera_pll_reconfig" -set_global_assignment -entity "master_reconfig" -library "lib_master_reconfig" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "master_reconfig" -library "lib_master_reconfig" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "master_reconfig" -library "lib_master_reconfig" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "lib_master_reconfig" -name SPD_FILE [file join $::quartus(sip_path) "master_reconfig.spd"] diff --git a/master_reconfig.vhd b/master_reconfig.vhd index 381763c..95ec519 100644 --- a/master_reconfig.vhd +++ b/master_reconfig.vhd @@ -1,8 +1,8 @@ --- megafunction wizard: %Altera PLL Reconfig v17.1% +-- megafunction wizard: %PLL Reconfig Intel FPGA IP v18.0% -- GENERATION: XML -- master_reconfig.vhd --- Generated using ACDS version 17.1 590 +-- Generated using ACDS version 18.0 614 library IEEE; use IEEE.std_logic_1164.all; @@ -114,7 +114,7 @@ end architecture rtl; -- of master_reconfig -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> --- Retrieval info: +-- Retrieval info: -- Retrieval info: -- Retrieval info: -- Retrieval info: diff --git a/master_reconfig/altera_pll_reconfig_core.v b/master_reconfig/altera_pll_reconfig_core.v index 9e34543..dde188b 100644 --- a/master_reconfig/altera_pll_reconfig_core.v +++ b/master_reconfig/altera_pll_reconfig_core.v @@ -1,4 +1,4 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. +// (C) 2001-2018 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files from any of the foregoing (including device programming or simulation diff --git a/master_reconfig/altera_pll_reconfig_top.v b/master_reconfig/altera_pll_reconfig_top.v index f308567..652de18 100644 --- a/master_reconfig/altera_pll_reconfig_top.v +++ b/master_reconfig/altera_pll_reconfig_top.v @@ -1,4 +1,4 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. +// (C) 2001-2018 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files from any of the foregoing (including device programming or simulation diff --git a/master_reconfig/altera_std_synchronizer.v b/master_reconfig/altera_std_synchronizer.v index b7b61ca..1c060eb 100644 --- a/master_reconfig/altera_std_synchronizer.v +++ b/master_reconfig/altera_std_synchronizer.v @@ -1,4 +1,4 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. +// (C) 2001-2018 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files from any of the foregoing (including device programming or simulation @@ -11,10 +11,10 @@ // agreement for further details. -// $Id: //acds/rel/17.1std/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#1 $ +// $Id: //acds/rel/18.0std/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#1 $ // $Revision: #1 $ -// $Date: 2017/07/30 $ -// $Author: swbranch $ +// $Date: 2018/01/31 $ +// $Author: psgswbuild $ //----------------------------------------------------------------------------- // // File: altera_std_synchronizer.v diff --git a/master_reconfig_sim/aldec/rivierapro_setup.tcl b/master_reconfig_sim/aldec/rivierapro_setup.tcl index dfe7199..7ce2a75 100644 --- a/master_reconfig_sim/aldec/rivierapro_setup.tcl +++ b/master_reconfig_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:40:12 +# ACDS 18.0 614 win32 2018.07.18.19:33:35 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- @@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] { } if ![info exists QUARTUS_INSTALL_DIR] { - set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/" + set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/" } if ![info exists USER_DEFINED_COMPILE_OPTIONS] { diff --git a/master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_core.v b/master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_core.v index 9e34543..dde188b 100644 --- a/master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_core.v +++ b/master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_core.v @@ -1,4 +1,4 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. +// (C) 2001-2018 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files from any of the foregoing (including device programming or simulation diff --git a/master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_top.v b/master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_top.v index f308567..652de18 100644 --- a/master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_top.v +++ b/master_reconfig_sim/altera_pll_reconfig/altera_pll_reconfig_top.v @@ -1,4 +1,4 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. +// (C) 2001-2018 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files from any of the foregoing (including device programming or simulation diff --git a/master_reconfig_sim/altera_pll_reconfig/altera_std_synchronizer.v b/master_reconfig_sim/altera_pll_reconfig/altera_std_synchronizer.v index b7b61ca..1c060eb 100644 --- a/master_reconfig_sim/altera_pll_reconfig/altera_std_synchronizer.v +++ b/master_reconfig_sim/altera_pll_reconfig/altera_std_synchronizer.v @@ -1,4 +1,4 @@ -// (C) 2001-2017 Intel Corporation. All rights reserved. +// (C) 2001-2018 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files from any of the foregoing (including device programming or simulation @@ -11,10 +11,10 @@ // agreement for further details. -// $Id: //acds/rel/17.1std/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#1 $ +// $Id: //acds/rel/18.0std/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#1 $ // $Revision: #1 $ -// $Date: 2017/07/30 $ -// $Author: swbranch $ +// $Date: 2018/01/31 $ +// $Author: psgswbuild $ //----------------------------------------------------------------------------- // // File: altera_std_synchronizer.v diff --git a/master_reconfig_sim/cadence/ncsim_setup.sh b/master_reconfig_sim/cadence/ncsim_setup.sh index 69f07be..f639691 100644 --- a/master_reconfig_sim/cadence/ncsim_setup.sh +++ b/master_reconfig_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:40:12 +# ACDS 18.0 614 win32 2018.07.18.19:33:35 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,12 +106,12 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:40:12 +# ACDS 18.0 614 win32 2018.07.18.19:33:35 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="master_reconfig" QSYS_SIMDIR="./../" -QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/" +QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/" SKIP_FILE_COPY=0 SKIP_DEV_COM=0 SKIP_COM=0 diff --git a/master_reconfig_sim/master_reconfig.vhd b/master_reconfig_sim/master_reconfig.vhd index 2a8fd3c..eaceb3a 100644 --- a/master_reconfig_sim/master_reconfig.vhd +++ b/master_reconfig_sim/master_reconfig.vhd @@ -1,6 +1,6 @@ -- master_reconfig.vhd --- Generated using ACDS version 17.1 590 +-- Generated using ACDS version 18.0 614 library IEEE; use IEEE.std_logic_1164.all; diff --git a/master_reconfig_sim/mentor/msim_setup.tcl b/master_reconfig_sim/mentor/msim_setup.tcl index 54865f5..bffce7f 100644 --- a/master_reconfig_sim/mentor/msim_setup.tcl +++ b/master_reconfig_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:40:12 +# ACDS 18.0 614 win32 2018.07.18.19:33:35 # ---------------------------------------- # Initialize variables @@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] { } if ![info exists QUARTUS_INSTALL_DIR] { - set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/" + set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/" } if ![info exists USER_DEFINED_COMPILE_OPTIONS] { diff --git a/master_reconfig_sim/synopsys/vcsmx/vcsmx_setup.sh b/master_reconfig_sim/synopsys/vcsmx/vcsmx_setup.sh index 0811229..3397bb8 100644 --- a/master_reconfig_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/master_reconfig_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:40:12 +# ACDS 18.0 614 win32 2018.07.18.19:33:35 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,12 +107,12 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:40:12 +# ACDS 18.0 614 win32 2018.07.18.19:33:35 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="master_reconfig" QSYS_SIMDIR="./../../" -QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/" +QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/" SKIP_FILE_COPY=0 SKIP_DEV_COM=0 SKIP_COM=0 diff --git a/nes.qsf b/nes.qsf index c3880b8..6c67b93 100644 --- a/nes.qsf +++ b/nes.qsf @@ -42,7 +42,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:38:44 FEBRUARY 12, 2016" -set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name SMART_RECOMPILE ON @@ -263,7 +263,7 @@ set_location_assignment PIN_M9 -to UART_RX # ========================== set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON # Analysis & Synthesis Assignments # ================================ @@ -677,5 +677,5 @@ set_global_assignment -name SIP_FILE master_reconfig.sip set_global_assignment -name HEX_FILE test_videorom.hex set_global_assignment -name HEX_FILE test_progmem.hex set_global_assignment -name SIGNALTAP_FILE stp.stp -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name SLD_FILE db/stp_auto_stripped.stp \ No newline at end of file +set_global_assignment -name SLD_FILE db/stp_auto_stripped.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/progmem.cmp b/progmem.cmp index 7066150..d19e4e0 100644 --- a/progmem.cmp +++ b/progmem.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/progmem.qip b/progmem.qip index e9fb8a1..801ef37 100644 --- a/progmem.qip +++ b/progmem.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "18.0" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "progmem.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "progmem.cmp"] diff --git a/progmem.vhd b/progmem.vhd index 9b88aeb..b37e244 100644 --- a/progmem.vhd +++ b/progmem.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 17.1.0 Build 590 10/25/2017 SJ Lite Edition +-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition -- ************************************************************ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/soamem.cmp b/soamem.cmp index b932dd2..a2f6ade 100644 --- a/soamem.cmp +++ b/soamem.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/soamem.qip b/soamem.qip index 9e07439..6177c75 100644 --- a/soamem.qip +++ b/soamem.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "18.0" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "soamem.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "soamem.cmp"] diff --git a/soamem.vhd b/soamem.vhd index b5261bf..2a15ed1 100644 --- a/soamem.vhd +++ b/soamem.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 17.1.0 Build 590 10/25/2017 SJ Lite Edition +-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition -- ************************************************************ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/spritemem.cmp b/spritemem.cmp index 197d573..ab4b128 100644 --- a/spritemem.cmp +++ b/spritemem.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/spritemem.qip b/spritemem.qip index da46f41..8f0818a 100644 --- a/spritemem.qip +++ b/spritemem.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "18.0" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "spritemem.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spritemem.cmp"] diff --git a/spritemem.vhd b/spritemem.vhd index f9872d1..7799b4e 100644 --- a/spritemem.vhd +++ b/spritemem.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 17.1.0 Build 590 10/25/2017 SJ Lite Edition +-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition -- ************************************************************ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/vga_pll.bsf b/vga_pll.bsf index 635694f..7a2c511 100644 --- a/vga_pll.bsf +++ b/vga_pll.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 2017 Intel Corporation. All rights reserved. +Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing diff --git a/vga_pll.qip b/vga_pll.qip index c90e716..9b899a0 100644 --- a/vga_pll.qip +++ b/vga_pll.qip @@ -1,5 +1,5 @@ set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "vga_pll" -name MISC_FILE [file join $::quartus(qip_path) "vga_pll.cmp"] set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" @@ -7,19 +7,19 @@ set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_GENERATED_DE set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_QSYS_MODE "UNKNOWN" set_global_assignment -name SYNTHESIS_ONLY_QIP ON set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_NAME "dmdhX3BsbA==" -set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_VERSION "MTcuMQ==" -set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "vga_pll" -library "vga_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_NAME "dmdhX3BsbF8wMDAy" -set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_VERSION "MTcuMQ==" -set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl" @@ -334,5 +334,5 @@ set_global_assignment -library "vga_pll" -name VERILOG_FILE [file join $::quartu set_global_assignment -library "vga_pll" -name QIP_FILE [file join $::quartus(qip_path) "vga_pll/vga_pll_0002.qip"] set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "vga_pll_0002" -library "vga_pll" -name IP_TOOL_ENV "mwpim" diff --git a/vga_pll.sip b/vga_pll.sip index c308dbe..9ec01a0 100644 --- a/vga_pll.sip +++ b/vga_pll.sip @@ -1,5 +1,5 @@ set_global_assignment -entity "vga_pll" -library "lib_vga_pll" -name IP_TOOL_NAME "altera_pll" -set_global_assignment -entity "vga_pll" -library "lib_vga_pll" -name IP_TOOL_VERSION "17.1" +set_global_assignment -entity "vga_pll" -library "lib_vga_pll" -name IP_TOOL_VERSION "18.0" set_global_assignment -entity "vga_pll" -library "lib_vga_pll" -name IP_TOOL_ENV "mwpim" set_global_assignment -library "lib_vga_pll" -name SPD_FILE [file join $::quartus(sip_path) "vga_pll.spd"] diff --git a/vga_pll.vhd b/vga_pll.vhd index 0d553c5..fd15f5e 100644 --- a/vga_pll.vhd +++ b/vga_pll.vhd @@ -1,8 +1,8 @@ --- megafunction wizard: %Altera PLL v17.1% +-- megafunction wizard: %PLL Intel FPGA IP v18.0% -- GENERATION: XML -- vga_pll.vhd --- Generated using ACDS version 17.1 590 +-- Generated using ACDS version 18.0 614 library IEEE; use IEEE.std_logic_1164.all; @@ -64,7 +64,7 @@ end architecture rtl; -- of vga_pll -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. ----> --- Retrieval info: +-- Retrieval info: -- Retrieval info: -- Retrieval info: -- Retrieval info: diff --git a/vga_pll_sim/aldec/rivierapro_setup.tcl b/vga_pll_sim/aldec/rivierapro_setup.tcl index a52e382..78075dd 100644 --- a/vga_pll_sim/aldec/rivierapro_setup.tcl +++ b/vga_pll_sim/aldec/rivierapro_setup.tcl @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:40:00 +# ACDS 18.0 614 win32 2018.07.18.19:33:23 # ---------------------------------------- # Auto-generated simulation script rivierapro_setup.tcl # ---------------------------------------- @@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] { } if ![info exists QUARTUS_INSTALL_DIR] { - set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/" + set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/" } if ![info exists USER_DEFINED_COMPILE_OPTIONS] { diff --git a/vga_pll_sim/cadence/ncsim_setup.sh b/vga_pll_sim/cadence/ncsim_setup.sh index 7c000e4..244d8d6 100644 --- a/vga_pll_sim/cadence/ncsim_setup.sh +++ b/vga_pll_sim/cadence/ncsim_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:40:00 +# ACDS 18.0 614 win32 2018.07.18.19:33:23 # ---------------------------------------- # ncsim - auto-generated simulation script @@ -106,12 +106,12 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:40:00 +# ACDS 18.0 614 win32 2018.07.18.19:33:23 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="vga_pll" QSYS_SIMDIR="./../" -QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/" +QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/" SKIP_FILE_COPY=0 SKIP_DEV_COM=0 SKIP_COM=0 diff --git a/vga_pll_sim/mentor/msim_setup.tcl b/vga_pll_sim/mentor/msim_setup.tcl index e3433b6..a672009 100644 --- a/vga_pll_sim/mentor/msim_setup.tcl +++ b/vga_pll_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:40:00 +# ACDS 18.0 614 win32 2018.07.18.19:33:23 # ---------------------------------------- # Initialize variables @@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] { } if ![info exists QUARTUS_INSTALL_DIR] { - set QUARTUS_INSTALL_DIR "C:/intelfpga/17.1/quartus/" + set QUARTUS_INSTALL_DIR "C:/intelfpga/18.0/quartus/" } if ![info exists USER_DEFINED_COMPILE_OPTIONS] { diff --git a/vga_pll_sim/synopsys/vcsmx/vcsmx_setup.sh b/vga_pll_sim/synopsys/vcsmx/vcsmx_setup.sh index 7dd0b30..c1edd80 100644 --- a/vga_pll_sim/synopsys/vcsmx/vcsmx_setup.sh +++ b/vga_pll_sim/synopsys/vcsmx/vcsmx_setup.sh @@ -12,7 +12,7 @@ # or its authorized distributors. Please refer to the applicable # agreement for further details. -# ACDS 17.1 590 win32 2018.01.10.18:40:00 +# ACDS 18.0 614 win32 2018.07.18.19:33:23 # ---------------------------------------- # vcsmx - auto-generated simulation script @@ -107,12 +107,12 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 17.1 590 win32 2018.01.10.18:40:00 +# ACDS 18.0 614 win32 2018.07.18.19:33:23 # ---------------------------------------- # initialize variables TOP_LEVEL_NAME="vga_pll" QSYS_SIMDIR="./../../" -QUARTUS_INSTALL_DIR="C:/intelfpga/17.1/quartus/" +QUARTUS_INSTALL_DIR="C:/intelfpga/18.0/quartus/" SKIP_FILE_COPY=0 SKIP_DEV_COM=0 SKIP_COM=0 diff --git a/vga_pll_sim/vga_pll.vho b/vga_pll_sim/vga_pll.vho index f477cd8..3623de6 100644 --- a/vga_pll_sim/vga_pll.vho +++ b/vga_pll_sim/vga_pll.vho @@ -1,8 +1,8 @@ --IP Functional Simulation Model ---VERSION_BEGIN 17.1 cbx_mgl 2017:10:25:18:08:29:SJ cbx_simgen 2017:10:25:18:06:53:SJ VERSION_END +--VERSION_BEGIN 18.0 cbx_mgl 2018:04:24:18:08:49:SJ cbx_simgen 2018:04:24:18:04:18:SJ VERSION_END --- Copyright (C) 2017 Intel Corporation. All rights reserved. +-- Copyright (C) 2018 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing diff --git a/videomem.cmp b/videomem.cmp index 6c6473a..f093c04 100644 --- a/videomem.cmp +++ b/videomem.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/videomem.qip b/videomem.qip index 84be361..fc72cbc 100644 --- a/videomem.qip +++ b/videomem.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "18.0" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "videomem.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "videomem.cmp"] diff --git a/videomem.vhd b/videomem.vhd index 54b9b6d..eb96ede 100644 --- a/videomem.vhd +++ b/videomem.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 17.1.0 Build 590 10/25/2017 SJ Lite Edition +-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition -- ************************************************************ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/videorom.cmp b/videorom.cmp index f7b35e8..fe07521 100644 --- a/videorom.cmp +++ b/videorom.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/videorom.qip b/videorom.qip index 6174970..21f6d7c 100644 --- a/videorom.qip +++ b/videorom.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" -set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_TOOL_VERSION "18.0" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "videorom.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "videorom.cmp"] diff --git a/videorom.vhd b/videorom.vhd index 1098d3a..21f4dd4 100644 --- a/videorom.vhd +++ b/videorom.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 17.1.0 Build 590 10/25/2017 SJ Lite Edition +-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition -- ************************************************************ ---Copyright (C) 2017 Intel Corporation. All rights reserved. +--Copyright (C) 2018 Intel Corporation. All rights reserved. --Your use of Intel Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing