From 9b19ad61b224aacb9e73794ab30c4cfc1d8270f2 Mon Sep 17 00:00:00 2001 From: "Jonas K." Date: Mon, 28 Oct 2024 18:58:35 +0100 Subject: [PATCH] FABulous: Fix default project language Verilog was still set as default project language for the commandline args, which could cause some problems. Add warning when default project language is overwritten by commandline argument. Add debug message, which language is set for the current project. Add info message about project creation. Signed-off-by: Jonas K. --- FABulous/FABulous.py | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/FABulous/FABulous.py b/FABulous/FABulous.py index 47da71b4..38dc5552 100644 --- a/FABulous/FABulous.py +++ b/FABulous/FABulous.py @@ -155,7 +155,10 @@ def setup_project_env_vars(args: argparse.Namespace) -> None: logger.warning("No project .env file found") # Overwrite project language param, if writer is specified as command line argument - if args.writer: + if args.writer and args.writer != os.getenv("FAB_PROJ_LANG"): + logger.warning( + f"Overwriting project language for current run, from {os.getenv('FAB_PROJ_LANG')} to {args.writer}, which was specified as command line argument" + ) os.environ["FAB_PROJ_LANG"] = args.writer @@ -180,6 +183,10 @@ def create_project(project_dir, type: Literal["verilog", "vhdl"] = "verilog"): else: os.mkdir(f"{project_dir}") + # set default type, since "None" overwrites the default value + if not type: + type = "verilog" + os.mkdir(f"{project_dir}/.FABulous") fabulousRoot = os.getenv("FAB_ROOT") @@ -199,6 +206,8 @@ def create_project(project_dir, type: Literal["verilog", "vhdl"] = "verilog"): adjust_directory_in_verilog_tb(project_dir) + logger.info(f"New FABulous project created in {project_dir} with {type} language.") + def copy_verilog_files(src, dst): """Copies all Verilog files from source directory to the destination directory. @@ -1672,7 +1681,6 @@ def main(): parser.add_argument( "-w", "--writer", - default="verilog", choices=["verilog", "vhdl"], help="Set the type of HDL code generated by the tool. Currently support Verilog and VHDL (Default using Verilog)", ) @@ -1727,8 +1735,10 @@ def main(): if os.getenv("FAB_PROJ_LANG") == "vhdl": writer = VHDLWriter() + logger.debug("VHDL writer selected") elif os.getenv("FAB_PROJ_LANG") == "verilog": writer = VerilogWriter() + logger.debug("Verilog writer selected") else: logger.error( f"Invalid projct language specified: {os.getenv('FAB_PROJ_LANG')}"