From d55d056180da8d91828af76be17a4575aabe8f7d Mon Sep 17 00:00:00 2001 From: Kelvin Chung Date: Mon, 26 Feb 2024 14:09:34 +0000 Subject: [PATCH] ever more formatting --- docs/source/conf.py | 43 +- .../top_wrapper_generator.py | 282 +++-- .../top_wrapper_generator_with_BRAM.py | 1045 ++++++++++++----- .../top_wrapper_generator_with_BRAM_vhdl.py | 573 ++++++--- 4 files changed, 1322 insertions(+), 621 deletions(-) diff --git a/docs/source/conf.py b/docs/source/conf.py index 4f4cd127..1af7b03e 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -1,36 +1,37 @@ import os import sys + # Configuration file for the Sphinx documentation builder. # -- Project information -project = 'FABulous Documentation' -copyright = '2021, University of Manchester' -author = 'Jing, Nguyen, Bea, Bardia, Dirk' +project = "FABulous Documentation" +copyright = "2021, University of Manchester" +author = "Jing, Nguyen, Bea, Bardia, Dirk" -release = '0.1' -version = '0.1.0' +release = "0.1" +version = "0.1.0" # -- General configuration extensions = [ - 'sphinx.ext.duration', - 'sphinx.ext.doctest', - 'sphinx.ext.autodoc', - 'sphinx.ext.autosummary', - 'sphinx.ext.intersphinx', - 'sphinxcontrib.bibtex', - 'sphinx.ext.napoleon', - 'sphinx-prompt' + "sphinx.ext.duration", + "sphinx.ext.doctest", + "sphinx.ext.autodoc", + "sphinx.ext.autosummary", + "sphinx.ext.intersphinx", + "sphinxcontrib.bibtex", + "sphinx.ext.napoleon", + "sphinx-prompt", ] intersphinx_mapping = { - 'python': ('https://docs.python.org/3/', None), - 'sphinx': ('https://www.sphinx-doc.org/en/master/', None), + "python": ("https://docs.python.org/3/", None), + "sphinx": ("https://www.sphinx-doc.org/en/master/", None), } -intersphinx_disabled_domains = ['std'] +intersphinx_disabled_domains = ["std"] -templates_path = ['_templates'] +templates_path = ["_templates"] sys.path.append(os.getcwd() + "/../../") @@ -52,12 +53,12 @@ # -- Options for HTML output -html_theme = 'sphinx_materialdesign_theme' +html_theme = "sphinx_materialdesign_theme" -html_logo = 'figs/FAB_logo.png' +html_logo = "figs/FAB_logo.png" # -- Options for EPUB output -epub_show_urls = 'footnote' +epub_show_urls = "footnote" -bibtex_bibfiles = ['publications.bib'] +bibtex_bibfiles = ["publications.bib"] diff --git a/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator.py b/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator.py index da293354..fab8b609 100644 --- a/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator.py +++ b/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator.py @@ -4,6 +4,7 @@ import sys, getopt import csv + def split_port(p): # split a port according to how we want to sort ports: # ((y, x), (indices...), basename) @@ -40,31 +41,47 @@ def split_port(p): # Y is in reverse order return ((-y, x), tuple(indices), basename) + def main(argv): - NumberOfRows = 16; - NumberOfCols = 19; - FrameBitsPerRow = 32; - MaxFramesPerCol = 20; - desync_flag = 20; - FrameSelectWidth = 5; - RowSelectWidth = 5; - NumberOfBRAMs = 4; + NumberOfRows = 16 + NumberOfCols = 19 + FrameBitsPerRow = 32 + MaxFramesPerCol = 20 + desync_flag = 20 + FrameSelectWidth = 5 + RowSelectWidth = 5 + NumberOfBRAMs = 4 fabric = None - + try: - opts, args = getopt.getopt(argv,"hr:c:b:f:d:t:",["NumberOfRows=","NumberOfCols=","FrameBitsPerRow=","MaxFramesPerCol=","desync_flag=","fabric="]) + opts, args = getopt.getopt( + argv, + "hr:c:b:f:d:t:", + [ + "NumberOfRows=", + "NumberOfCols=", + "FrameBitsPerRow=", + "MaxFramesPerCol=", + "desync_flag=", + "fabric=", + ], + ) except getopt.GetoptError: - print ('top_wrapper_generator.py -r -c -b -f -d -t ') + print( + "top_wrapper_generator.py -r -c -b -f -d -t " + ) sys.exit(2) for opt, arg in opts: - if opt == '-h': - print ('top_wrapper_generator.py -r -c -b -f -d -t ') + if opt == "-h": + print( + "top_wrapper_generator.py -r -c -b -f -d -t " + ) sys.exit() elif opt in ("-r", "--NumberOfRows"): NumberOfRows = int(arg) elif opt in ("-c", "--NumberOfCols"): - NumberOfCols = int(arg)+2 + NumberOfCols = int(arg) + 2 elif opt in ("-b", "--FrameBitsPerRow"): FrameBitsPerRow = int(arg) elif opt in ("-f", "--MaxFramesPerCol"): @@ -74,14 +91,14 @@ def main(argv): elif opt in ("-t", "--fabric"): fabric = arg - print ('NumberOfRows :', NumberOfRows) - print ('NumberOfCols :', NumberOfCols-2) - print ('FrameBitsPerRow :', FrameBitsPerRow) - print ('MaxFramesPerCol :', MaxFramesPerCol) - print ('desync_flag :', desync_flag) - print ('FrameSelectWidth :', FrameSelectWidth) - print ('RowSelectWidth :', RowSelectWidth) - print ('') + print("NumberOfRows :", NumberOfRows) + print("NumberOfCols :", NumberOfCols - 2) + print("FrameBitsPerRow :", FrameBitsPerRow) + print("MaxFramesPerCol :", MaxFramesPerCol) + print("desync_flag :", desync_flag) + print("FrameSelectWidth :", FrameSelectWidth) + print("RowSelectWidth :", RowSelectWidth) + print("") wrapper_top_str = "" config_str = "" @@ -89,7 +106,7 @@ def main(argv): data_reg_modules = "" strobe_reg_modules = "" testbench_str = "" - #data_reg_module_temp = "" + # data_reg_module_temp = "" if fabric is None: print("Path to generated fabric.v must be specified with -t fabric.v") @@ -97,33 +114,36 @@ def main(argv): # Determine the set of external ports port_groups = dict() - with open(fabric, 'r') as file: + with open(fabric, "r") as file: for line in file: - if m := re.match(r'(input|output)\s+(Tile_X\d+Y\d+_[A-Z0-9a-z_]+);\s*//EXTERNAL', line.strip()): + if m := re.match( + r"(input|output)\s+(Tile_X\d+Y\d+_[A-Z0-9a-z_]+);\s*//EXTERNAL", + line.strip(), + ): yx, indices, port = split_port(m.group(2)) if port not in port_groups: port_groups[port] = (m.group(1), []) port_groups[port][1].append(m.group(2)) # sort port groups according to vectorisation order for name, g in port_groups.items(): - g[1].sort(key=lambda x:split_port(x)) + g[1].sort(key=lambda x: split_port(x)) try: - with open("fabulous_top_wrapper_temp/eFPGA_top_template.v", 'r') as file : + with open("fabulous_top_wrapper_temp/eFPGA_top_template.v", "r") as file: wrapper_top_str = file.read() except IOError: print("eFPGA_top_template.v not accessible") sys.exit(1) - + try: - with open("fabulous_top_wrapper_temp/Config_template.v", 'r') as file : + with open("fabulous_top_wrapper_temp/Config_template.v", "r") as file: config_str = file.read() except IOError: print("Config_template.v not accessible") sys.exit(1) - + try: - with open("fabulous_top_wrapper_temp/ConfigFSM_template.v", 'r') as file : + with open("fabulous_top_wrapper_temp/ConfigFSM_template.v", "r") as file: configfsm_str = file.read() except IOError: print("ConfigFSM_template.v not accessible") @@ -140,124 +160,174 @@ def main(argv): # extra IO wires uio_wires = "" - for name, group in sorted(port_groups.items(), key=lambda x:x[0]): + for name, group in sorted(port_groups.items(), key=lambda x: x[0]): uio_wires += f"\t{group[0]} wire [{len(group[1])-1}:0] {name};\n" wrapper_top_str = wrapper_top_str.replace("${uio_wires}", uio_wires) - #config_str = config_str.replace("parameter NumberOfRows = 16", "parameter NumberOfRows = "+str(NumberOfRows)) - config_str = config_str.replace("parameter RowSelectWidth = 5", "parameter RowSelectWidth = "+str(RowSelectWidth)) - config_str = config_str.replace("parameter FrameBitsPerRow = 32", "parameter FrameBitsPerRow = "+str(FrameBitsPerRow)) - #config_str = config_str.replace("parameter desync_flag = 20", "parameter desync_flag = "+str(desync_flag)) - - configfsm_str = configfsm_str.replace("parameter NumberOfRows = 16", "parameter NumberOfRows = "+str(NumberOfRows)) - configfsm_str = configfsm_str.replace("parameter RowSelectWidth = 5", "parameter RowSelectWidth = "+str(RowSelectWidth)) - configfsm_str = configfsm_str.replace("parameter FrameBitsPerRow = 32", "parameter FrameBitsPerRow = "+str(FrameBitsPerRow)) - configfsm_str = configfsm_str.replace("parameter desync_flag = 20", "parameter desync_flag = "+str(desync_flag)) - + # config_str = config_str.replace("parameter NumberOfRows = 16", "parameter NumberOfRows = "+str(NumberOfRows)) + config_str = config_str.replace( + "parameter RowSelectWidth = 5", + "parameter RowSelectWidth = " + str(RowSelectWidth), + ) + config_str = config_str.replace( + "parameter FrameBitsPerRow = 32", + "parameter FrameBitsPerRow = " + str(FrameBitsPerRow), + ) + # config_str = config_str.replace("parameter desync_flag = 20", "parameter desync_flag = "+str(desync_flag)) + + configfsm_str = configfsm_str.replace( + "parameter NumberOfRows = 16", "parameter NumberOfRows = " + str(NumberOfRows) + ) + configfsm_str = configfsm_str.replace( + "parameter RowSelectWidth = 5", + "parameter RowSelectWidth = " + str(RowSelectWidth), + ) + configfsm_str = configfsm_str.replace( + "parameter FrameBitsPerRow = 32", + "parameter FrameBitsPerRow = " + str(FrameBitsPerRow), + ) + configfsm_str = configfsm_str.replace( + "parameter desync_flag = 20", "parameter desync_flag = " + str(desync_flag) + ) + for row in range(NumberOfRows): - data_reg_module_temp ="" - - data_reg_name = 'Frame_Data_Reg_'+str(row) - wrapper_top_str+='\t'+data_reg_name+' Inst_'+data_reg_name+' (\n' - wrapper_top_str+='\t.FrameData_I(LocalWriteData),\n' - wrapper_top_str+='\t.FrameData_O(FrameRegister['+str(row)+'*FrameBitsPerRow+:FrameBitsPerRow]),\n' - wrapper_top_str+='\t.RowSelect(RowSelect),\n' - wrapper_top_str+='\t.CLK(CLK)\n' - wrapper_top_str+='\t);\n\n' - #data_reg_modules += 'module '+data_reg_name+' (FrameData_I, FrameData_O, RowSelect, CLK);' + data_reg_module_temp = "" + + data_reg_name = "Frame_Data_Reg_" + str(row) + wrapper_top_str += "\t" + data_reg_name + " Inst_" + data_reg_name + " (\n" + wrapper_top_str += "\t.FrameData_I(LocalWriteData),\n" + wrapper_top_str += ( + "\t.FrameData_O(FrameRegister[" + + str(row) + + "*FrameBitsPerRow+:FrameBitsPerRow]),\n" + ) + wrapper_top_str += "\t.RowSelect(RowSelect),\n" + wrapper_top_str += "\t.CLK(CLK)\n" + wrapper_top_str += "\t);\n\n" + # data_reg_modules += 'module '+data_reg_name+' (FrameData_I, FrameData_O, RowSelect, CLK);' try: - with open("fabulous_top_wrapper_temp/Frame_Data_Reg_template.v", 'r') as file : + with open( + "fabulous_top_wrapper_temp/Frame_Data_Reg_template.v", "r" + ) as file: data_reg_module_temp = file.read() except IOError: print("Frame_Data_Reg_template.v not accessible") break - data_reg_module_temp=data_reg_module_temp.replace("Frame_Data_Reg", data_reg_name) - data_reg_module_temp=data_reg_module_temp.replace("parameter FrameBitsPerRow = 32", "parameter FrameBitsPerRow = "+str(FrameBitsPerRow)) - data_reg_module_temp=data_reg_module_temp.replace("parameter RowSelectWidth = 5", "parameter RowSelectWidth = "+str(RowSelectWidth)) - data_reg_module_temp=data_reg_module_temp.replace("parameter Row = 1", "parameter Row = "+str(row+1)) - data_reg_modules += data_reg_module_temp+'\n\n' - #with open("verilog_output/"+data_reg_name+".v", 'w') as file: + data_reg_module_temp = data_reg_module_temp.replace( + "Frame_Data_Reg", data_reg_name + ) + data_reg_module_temp = data_reg_module_temp.replace( + "parameter FrameBitsPerRow = 32", + "parameter FrameBitsPerRow = " + str(FrameBitsPerRow), + ) + data_reg_module_temp = data_reg_module_temp.replace( + "parameter RowSelectWidth = 5", + "parameter RowSelectWidth = " + str(RowSelectWidth), + ) + data_reg_module_temp = data_reg_module_temp.replace( + "parameter Row = 1", "parameter Row = " + str(row + 1) + ) + data_reg_modules += data_reg_module_temp + "\n\n" + # with open("verilog_output/"+data_reg_name+".v", 'w') as file: # file.write(data_reg_module_temp) - + for col in range(NumberOfCols): - strobe_reg_module_temp ="" - - strobe_reg_name = 'Frame_Select_'+str(col) - wrapper_top_str+='\t'+strobe_reg_name+' Inst_'+strobe_reg_name+' (\n' - wrapper_top_str+='\t.FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),\n' - wrapper_top_str+='\t.FrameStrobe_O(FrameSelect['+str(col)+'*MaxFramesPerCol +: MaxFramesPerCol]),\n' - wrapper_top_str+='\t.FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),\n' - wrapper_top_str+='\t.FrameStrobe(LongFrameStrobe)\n' - wrapper_top_str+='\t);\n\n' + strobe_reg_module_temp = "" + + strobe_reg_name = "Frame_Select_" + str(col) + wrapper_top_str += "\t" + strobe_reg_name + " Inst_" + strobe_reg_name + " (\n" + wrapper_top_str += ( + "\t.FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),\n" + ) + wrapper_top_str += ( + "\t.FrameStrobe_O(FrameSelect[" + + str(col) + + "*MaxFramesPerCol +: MaxFramesPerCol]),\n" + ) + wrapper_top_str += "\t.FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),\n" + wrapper_top_str += "\t.FrameStrobe(LongFrameStrobe)\n" + wrapper_top_str += "\t);\n\n" try: - with open("fabulous_top_wrapper_temp/Frame_Select_template.v", 'r') as file : + with open("fabulous_top_wrapper_temp/Frame_Select_template.v", "r") as file: strobe_reg_module_temp = file.read() except IOError: print("Frame_Select_template.v not accessible") break - strobe_reg_module_temp=strobe_reg_module_temp.replace("Frame_Select", strobe_reg_name) - strobe_reg_module_temp=strobe_reg_module_temp.replace("parameter MaxFramesPerCol = 20", "parameter MaxFramesPerCol = "+str(MaxFramesPerCol)) - strobe_reg_module_temp=strobe_reg_module_temp.replace("parameter FrameSelectWidth = 5", "parameter FrameSelectWidth = "+str(FrameSelectWidth)) - strobe_reg_module_temp=strobe_reg_module_temp.replace("parameter Col = 18", "parameter Col = "+str(col)) - strobe_reg_modules += strobe_reg_module_temp+'\n\n' - #with open("verilog_output/"+strobe_reg_name+".v", 'w') as file: + strobe_reg_module_temp = strobe_reg_module_temp.replace( + "Frame_Select", strobe_reg_name + ) + strobe_reg_module_temp = strobe_reg_module_temp.replace( + "parameter MaxFramesPerCol = 20", + "parameter MaxFramesPerCol = " + str(MaxFramesPerCol), + ) + strobe_reg_module_temp = strobe_reg_module_temp.replace( + "parameter FrameSelectWidth = 5", + "parameter FrameSelectWidth = " + str(FrameSelectWidth), + ) + strobe_reg_module_temp = strobe_reg_module_temp.replace( + "parameter Col = 18", "parameter Col = " + str(col) + ) + strobe_reg_modules += strobe_reg_module_temp + "\n\n" + # with open("verilog_output/"+strobe_reg_name+".v", 'w') as file: # file.write(strobe_reg_module_temp) - #wrapper_top_str+='\twire ['+str(NumberOfRows-1)+':0] dump;\n\n' - wrapper_top_str+='\teFPGA Inst_eFPGA(\n' + # wrapper_top_str+='\twire ['+str(NumberOfRows-1)+':0] dump;\n\n' + wrapper_top_str += "\teFPGA Inst_eFPGA(\n" # external IO connectivity - for name, group in sorted(port_groups.items(), key=lambda x:x[0]): + for name, group in sorted(port_groups.items(), key=lambda x: x[0]): for i, sig in enumerate(group[1]): wrapper_top_str += f"\t.{sig}({name}[{i}]),\n" - wrapper_top_str+='\t//declarations\n' - wrapper_top_str+='\t.UserCLK(CLK),\n' - wrapper_top_str+='\t.FrameData(FrameData),\n' - wrapper_top_str+='\t.FrameStrobe(FrameSelect)\n' - wrapper_top_str+='\t);\n\n' - - wrapper_top_str+="\tassign FrameData = {32'h12345678,FrameRegister,32'h12345678};\n\n" - wrapper_top_str+='endmodule\n\n' + wrapper_top_str += "\t//declarations\n" + wrapper_top_str += "\t.UserCLK(CLK),\n" + wrapper_top_str += "\t.FrameData(FrameData),\n" + wrapper_top_str += "\t.FrameStrobe(FrameSelect)\n" + wrapper_top_str += "\t);\n\n" + + wrapper_top_str += ( + "\tassign FrameData = {32'h12345678,FrameRegister,32'h12345678};\n\n" + ) + wrapper_top_str += "endmodule\n\n" if wrapper_top_str: - with open("eFPGA_top.v", 'w') as file: + with open("eFPGA_top.v", "w") as file: file.write(wrapper_top_str) if data_reg_modules: - with open("Frame_Data_Reg_Pack.v", 'w') as file: + with open("Frame_Data_Reg_Pack.v", "w") as file: file.write(data_reg_modules) if strobe_reg_modules: - with open("Frame_Select_Pack.v", 'w') as file: + with open("Frame_Select_Pack.v", "w") as file: file.write(strobe_reg_modules) - + if config_str: - with open("Config.v", 'w') as file: + with open("Config.v", "w") as file: file.write(config_str) - + if configfsm_str: - with open("ConfigFSM.v", 'w') as file: + with open("ConfigFSM.v", "w") as file: file.write(configfsm_str) - - #if testbench_str: + + # if testbench_str: # with open("tb_bitbang.vhd", 'w') as file: # file.write(testbench_str) - + print("Finish") + if __name__ == "__main__": main(sys.argv[1:]) -#argv = "/home/ise/shared_folder/diffeq1/LC_on/netgen/synthesis/diffeq_paj_convert_synthesis.v" - +# argv = "/home/ise/shared_folder/diffeq1/LC_on/netgen/synthesis/diffeq_paj_convert_synthesis.v" -#if words[i+1] == "critical": -#number1.append(words[i+3]) -#elif x == "Total": -#if words[i+1] == "used": -#number2.append(words[i+5]) -#print(number1) -#print(number2) +# if words[i+1] == "critical": +# number1.append(words[i+3]) +# elif x == "Total": +# if words[i+1] == "used": +# number2.append(words[i+5]) +# print(number1) +# print(number2) diff --git a/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM.py b/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM.py index b067cc95..db3d9479 100644 --- a/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM.py +++ b/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM.py @@ -7,12 +7,12 @@ import os import argparse -FABulous_root = os.getenv('FABulous_root') +FABulous_root = os.getenv("FABulous_root") if FABulous_root is None: - print('FABulous_root is not set!') - print('Set FABulous_root with the following command:') - print('export FABulous_root=') + print("FABulous_root is not set!") + print("Set FABulous_root with the following command:") + print("export FABulous_root=") sys.exit() NumberOfRows = 16 @@ -27,17 +27,17 @@ def main(): - NumberOfBRAMs = int(NumberOfRows/2) - - print('NumberOfRows :', NumberOfRows) - print('NumberOfCols :', NumberOfCols-2) - print('FrameBitsPerRow :', FrameBitsPerRow) - print('MaxFramesPerCol :', MaxFramesPerCol) - print('desync_flag :', desync_flag) - print('FrameSelectWidth :', FrameSelectWidth) - print('RowSelectWidth :', RowSelectWidth) - print('NumberOfBRAMs :', NumberOfBRAMs) - print('') + NumberOfBRAMs = int(NumberOfRows / 2) + + print("NumberOfRows :", NumberOfRows) + print("NumberOfCols :", NumberOfCols - 2) + print("FrameBitsPerRow :", FrameBitsPerRow) + print("MaxFramesPerCol :", MaxFramesPerCol) + print("desync_flag :", desync_flag) + print("FrameSelectWidth :", FrameSelectWidth) + print("RowSelectWidth :", RowSelectWidth) + print("NumberOfBRAMs :", NumberOfBRAMs) + print("") wrapper_top_str = "" config_str = "" @@ -45,97 +45,138 @@ def main(): data_reg_modules = "" strobe_reg_modules = "" testbench_str = "" - #data_reg_module_temp = "" + # data_reg_module_temp = "" try: - with open("fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.v", 'r') as file : + with open( + "fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.v", "r" + ) as file: wrapper_top_str = file.read() except IOError: print("eFPGA_v3_top_sky130_with_BRAM_template.v not accessible") exit(-1) try: - with open("fabulous_top_wrapper_temp/Config_template.v", 'r') as file : + with open("fabulous_top_wrapper_temp/Config_template.v", "r") as file: config_str = file.read() except IOError: print("Config_template.v not accessible") exit(-1) try: - with open("fabulous_top_wrapper_temp/ConfigFSM_template.v", 'r') as file : + with open("fabulous_top_wrapper_temp/ConfigFSM_template.v", "r") as file: configfsm_str = file.read() except IOError: print("ConfigFSM_template.v not accessible") exit(-1) try: - with open("fabulous_top_wrapper_temp/tb_bitbang_template.vhd", 'r') as file : + with open("fabulous_top_wrapper_temp/tb_bitbang_template.vhd", "r") as file: testbench_str = file.read() except IOError: print("tb_bitbang_template.vhd not accessible") exit(-1) wrapper_top_str = wrapper_top_str.replace( - "[30:0] io_in", '['+str(NumberOfRows*2+7)+'-1:0] io_in') + "[30:0] io_in", "[" + str(NumberOfRows * 2 + 7) + "-1:0] io_in" + ) wrapper_top_str = wrapper_top_str.replace( - "[30:0] io_out", '['+str(NumberOfRows*2+7)+'-1:0] io_out') + "[30:0] io_out", "[" + str(NumberOfRows * 2 + 7) + "-1:0] io_out" + ) wrapper_top_str = wrapper_top_str.replace( - "[30:0] io_oeb", '['+str(NumberOfRows*2+7)+'-1:0] io_oeb') + "[30:0] io_oeb", "[" + str(NumberOfRows * 2 + 7) + "-1:0] io_oeb" + ) wrapper_top_str = wrapper_top_str.replace( - "[32-1:0] I_top", '['+str(NumberOfRows*2)+'-1:0] I_top') + "[32-1:0] I_top", "[" + str(NumberOfRows * 2) + "-1:0] I_top" + ) wrapper_top_str = wrapper_top_str.replace( - "[32-1:0] T_top", '['+str(NumberOfRows*2)+'-1:0] T_top') + "[32-1:0] T_top", "[" + str(NumberOfRows * 2) + "-1:0] T_top" + ) wrapper_top_str = wrapper_top_str.replace( - "[32-1:0] O_top", '['+str(NumberOfRows*2)+'-1:0] O_top') + "[32-1:0] O_top", "[" + str(NumberOfRows * 2) + "-1:0] O_top" + ) wrapper_top_str = wrapper_top_str.replace( - "[64-1:0] A_config_C", '['+str(NumberOfRows*4)+'-1:0] A_config_C') + "[64-1:0] A_config_C", "[" + str(NumberOfRows * 4) + "-1:0] A_config_C" + ) wrapper_top_str = wrapper_top_str.replace( - "[64-1:0] B_config_C", '['+str(NumberOfRows*4)+'-1:0] B_config_C') + "[64-1:0] B_config_C", "[" + str(NumberOfRows * 4) + "-1:0] B_config_C" + ) wrapper_top_str = wrapper_top_str.replace( - "[64-1:0] RAM2FAB_D", '['+str(NumberOfRows*4*4)+'-1:0] RAM2FAB_D') + "[64-1:0] RAM2FAB_D", "[" + str(NumberOfRows * 4 * 4) + "-1:0] RAM2FAB_D" + ) wrapper_top_str = wrapper_top_str.replace( - "[64-1:0] FAB2RAM_D", '['+str(NumberOfRows*4*4)+'-1:0] FAB2RAM_D') + "[64-1:0] FAB2RAM_D", "[" + str(NumberOfRows * 4 * 4) + "-1:0] FAB2RAM_D" + ) wrapper_top_str = wrapper_top_str.replace( - "[64-1:0] FAB2RAM_A", '['+str(NumberOfRows*4*2)+'-1:0] FAB2RAM_A') + "[64-1:0] FAB2RAM_A", "[" + str(NumberOfRows * 4 * 2) + "-1:0] FAB2RAM_A" + ) wrapper_top_str = wrapper_top_str.replace( - "[64-1:0] FAB2RAM_C", '['+str(NumberOfRows*4)+'-1:0] FAB2RAM_C') + "[64-1:0] FAB2RAM_C", "[" + str(NumberOfRows * 4) + "-1:0] FAB2RAM_C" + ) wrapper_top_str = wrapper_top_str.replace( - "[64-1:0] Config_accessC", '['+str(NumberOfRows*4)+'-1:0] Config_accessC') + "[64-1:0] Config_accessC", "[" + str(NumberOfRows * 4) + "-1:0] Config_accessC" + ) wrapper_top_str = wrapper_top_str.replace( - "localparam NumberOfRows = 16", "localparam NumberOfRows = "+str(NumberOfRows)) + "localparam NumberOfRows = 16", "localparam NumberOfRows = " + str(NumberOfRows) + ) wrapper_top_str = wrapper_top_str.replace( - "localparam NumberOfCols = 19", "localparam NumberOfCols = "+str(NumberOfCols)) + "localparam NumberOfCols = 19", "localparam NumberOfCols = " + str(NumberOfCols) + ) - wrapper_top_str = wrapper_top_str.replace("O_top[23:18] = io_in[30:25]", "O_top["+str( - NumberOfRows*2-1)+":18] = io_in["+str(NumberOfRows*2+7-1)+":25]") wrapper_top_str = wrapper_top_str.replace( - "io_out[30:7] = I_top", "io_out["+str(NumberOfRows*2+7-1)+":7] = I_top") + "O_top[23:18] = io_in[30:25]", + "O_top[" + + str(NumberOfRows * 2 - 1) + + ":18] = io_in[" + + str(NumberOfRows * 2 + 7 - 1) + + ":25]", + ) wrapper_top_str = wrapper_top_str.replace( - "io_oeb[30:7] = T_top", "io_oeb["+str(NumberOfRows*2+7-1)+":7] = T_top") + "io_out[30:7] = I_top", + "io_out[" + str(NumberOfRows * 2 + 7 - 1) + ":7] = I_top", + ) + wrapper_top_str = wrapper_top_str.replace( + "io_oeb[30:7] = T_top", + "io_oeb[" + str(NumberOfRows * 2 + 7 - 1) + ":7] = T_top", + ) - #config_str = config_str.replace("parameter NumberOfRows = 16", "parameter NumberOfRows = "+str(NumberOfRows)) + # config_str = config_str.replace("parameter NumberOfRows = 16", "parameter NumberOfRows = "+str(NumberOfRows)) config_str = config_str.replace( - "parameter RowSelectWidth = 5", "parameter RowSelectWidth = "+str(RowSelectWidth)) + "parameter RowSelectWidth = 5", + "parameter RowSelectWidth = " + str(RowSelectWidth), + ) config_str = config_str.replace( - "parameter FrameBitsPerRow = 32", "parameter FrameBitsPerRow = "+str(FrameBitsPerRow)) - #config_str = config_str.replace("parameter desync_flag = 20", "parameter desync_flag = "+str(desync_flag)) + "parameter FrameBitsPerRow = 32", + "parameter FrameBitsPerRow = " + str(FrameBitsPerRow), + ) + # config_str = config_str.replace("parameter desync_flag = 20", "parameter desync_flag = "+str(desync_flag)) configfsm_str = configfsm_str.replace( - "parameter NumberOfRows = 16", "parameter NumberOfRows = "+str(NumberOfRows)) + "parameter NumberOfRows = 16", "parameter NumberOfRows = " + str(NumberOfRows) + ) configfsm_str = configfsm_str.replace( - "parameter RowSelectWidth = 5", "parameter RowSelectWidth = "+str(RowSelectWidth)) + "parameter RowSelectWidth = 5", + "parameter RowSelectWidth = " + str(RowSelectWidth), + ) configfsm_str = configfsm_str.replace( - "parameter FrameBitsPerRow = 32", "parameter FrameBitsPerRow = "+str(FrameBitsPerRow)) + "parameter FrameBitsPerRow = 32", + "parameter FrameBitsPerRow = " + str(FrameBitsPerRow), + ) configfsm_str = configfsm_str.replace( - "parameter desync_flag = 20", "parameter desync_flag = "+str(desync_flag)) + "parameter desync_flag = 20", "parameter desync_flag = " + str(desync_flag) + ) testbench_str = testbench_str.replace( - " STD_LOGIC_VECTOR (32 -1 downto 0)", " STD_LOGIC_VECTOR ("+str(NumberOfRows*2)+" -1 downto 0)") + " STD_LOGIC_VECTOR (32 -1 downto 0)", + " STD_LOGIC_VECTOR (" + str(NumberOfRows * 2) + " -1 downto 0)", + ) testbench_str = testbench_str.replace( - "STD_LOGIC_VECTOR (64 -1 downto 0)", "STD_LOGIC_VECTOR ("+str(NumberOfRows*4)+" -1 downto 0)") + "STD_LOGIC_VECTOR (64 -1 downto 0)", + "STD_LOGIC_VECTOR (" + str(NumberOfRows * 4) + " -1 downto 0)", + ) # I_top_buf_str = "" # T_top_buf_str = "" @@ -160,84 +201,109 @@ def main(): for row in range(NumberOfRows): data_reg_module_temp = "" - data_reg_name = 'Frame_Data_Reg_'+str(row) - wrapper_top_str += '\t'+data_reg_name+' Inst_'+data_reg_name+' (\n' - wrapper_top_str += '\t.FrameData_I(LocalWriteData),\n' - wrapper_top_str += '\t.FrameData_O(FrameRegister['+str( - row)+'*FrameBitsPerRow+:FrameBitsPerRow]),\n' - wrapper_top_str += '\t.RowSelect(RowSelect),\n' - wrapper_top_str += '\t.CLK(CLK)\n' - wrapper_top_str += '\t)\n\n' - #data_reg_modules += 'module '+data_reg_name+' (FrameData_I, FrameData_O, RowSelect, CLK)' + data_reg_name = "Frame_Data_Reg_" + str(row) + wrapper_top_str += "\t" + data_reg_name + " Inst_" + data_reg_name + " (\n" + wrapper_top_str += "\t.FrameData_I(LocalWriteData),\n" + wrapper_top_str += ( + "\t.FrameData_O(FrameRegister[" + + str(row) + + "*FrameBitsPerRow+:FrameBitsPerRow]),\n" + ) + wrapper_top_str += "\t.RowSelect(RowSelect),\n" + wrapper_top_str += "\t.CLK(CLK)\n" + wrapper_top_str += "\t)\n\n" + # data_reg_modules += 'module '+data_reg_name+' (FrameData_I, FrameData_O, RowSelect, CLK)' try: - with open("fabulous_top_wrapper_temp/Frame_Data_Reg_template.v", 'r') as file : + with open( + "fabulous_top_wrapper_temp/Frame_Data_Reg_template.v", "r" + ) as file: data_reg_module_temp = file.read() except IOError: print("Frame_Data_Reg_template.v not accessible") exit(-1) break data_reg_module_temp = data_reg_module_temp.replace( - "Frame_Data_Reg", data_reg_name) + "Frame_Data_Reg", data_reg_name + ) data_reg_module_temp = data_reg_module_temp.replace( - "parameter FrameBitsPerRow = 32", "parameter FrameBitsPerRow = "+str(FrameBitsPerRow)) + "parameter FrameBitsPerRow = 32", + "parameter FrameBitsPerRow = " + str(FrameBitsPerRow), + ) data_reg_module_temp = data_reg_module_temp.replace( - "parameter RowSelectWidth = 5", "parameter RowSelectWidth = "+str(RowSelectWidth)) + "parameter RowSelectWidth = 5", + "parameter RowSelectWidth = " + str(RowSelectWidth), + ) data_reg_module_temp = data_reg_module_temp.replace( - "parameter Row = 1", "parameter Row = "+str(row+1)) - data_reg_modules += data_reg_module_temp+'\n\n' + "parameter Row = 1", "parameter Row = " + str(row + 1) + ) + data_reg_modules += data_reg_module_temp + "\n\n" # with open("verilog_output/"+data_reg_name+".v", 'w') as file: # file.write(data_reg_module_temp) for col in range(NumberOfCols): strobe_reg_module_temp = "" - strobe_reg_name = 'Frame_Select_'+str(col) - wrapper_top_str += '\t'+strobe_reg_name+' Inst_'+strobe_reg_name+' (\n' - wrapper_top_str += '\t.FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),\n' - wrapper_top_str += '\t.FrameStrobe_O(FrameSelect['+str( - col)+'*MaxFramesPerCol +: MaxFramesPerCol]),\n' - wrapper_top_str += '\t.FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),\n' - wrapper_top_str += '\t.FrameStrobe(LongFrameStrobe)\n' - wrapper_top_str += '\t)\n\n' + strobe_reg_name = "Frame_Select_" + str(col) + wrapper_top_str += "\t" + strobe_reg_name + " Inst_" + strobe_reg_name + " (\n" + wrapper_top_str += ( + "\t.FrameStrobe_I(FrameAddressRegister[MaxFramesPerCol-1:0]),\n" + ) + wrapper_top_str += ( + "\t.FrameStrobe_O(FrameSelect[" + + str(col) + + "*MaxFramesPerCol +: MaxFramesPerCol]),\n" + ) + wrapper_top_str += "\t.FrameSelect(FrameAddressRegister[FrameBitsPerRow-1:FrameBitsPerRow-(FrameSelectWidth)]),\n" + wrapper_top_str += "\t.FrameStrobe(LongFrameStrobe)\n" + wrapper_top_str += "\t)\n\n" try: - with open("fabulous_top_wrapper_temp/Frame_Select_template.v", 'r') as file : + with open("fabulous_top_wrapper_temp/Frame_Select_template.v", "r") as file: strobe_reg_module_temp = file.read() except IOError: print("Frame_Select_template.v not accessible") exit(-1) break strobe_reg_module_temp = strobe_reg_module_temp.replace( - "Frame_Select", strobe_reg_name) + "Frame_Select", strobe_reg_name + ) strobe_reg_module_temp = strobe_reg_module_temp.replace( - "parameter MaxFramesPerCol = 20", "parameter MaxFramesPerCol = "+str(MaxFramesPerCol)) + "parameter MaxFramesPerCol = 20", + "parameter MaxFramesPerCol = " + str(MaxFramesPerCol), + ) strobe_reg_module_temp = strobe_reg_module_temp.replace( - "parameter FrameSelectWidth = 5", "parameter FrameSelectWidth = "+str(FrameSelectWidth)) + "parameter FrameSelectWidth = 5", + "parameter FrameSelectWidth = " + str(FrameSelectWidth), + ) strobe_reg_module_temp = strobe_reg_module_temp.replace( - "parameter Col = 18", "parameter Col = "+str(col)) - strobe_reg_modules += strobe_reg_module_temp+'\n\n' + "parameter Col = 18", "parameter Col = " + str(col) + ) + strobe_reg_modules += strobe_reg_module_temp + "\n\n" # with open("verilog_output/"+strobe_reg_name+".v", 'w') as file: # file.write(strobe_reg_module_temp) - #wrapper_top_str+='\twire ['+str(NumberOfRows-1)+':0] dump\n\n' - wrapper_top_str += '\teFPGA Inst_eFPGA(\n' + # wrapper_top_str+='\twire ['+str(NumberOfRows-1)+':0] dump\n\n' + wrapper_top_str += "\teFPGA Inst_eFPGA(\n" I_top_str = "" T_top_str = "" O_top_str = "" count = 0 - for i in range(NumberOfRows*2-1, -1, -2): + for i in range(NumberOfRows * 2 - 1, -1, -2): count += 1 - I_top_str += '\t.Tile_X0Y'+str(count)+'_A_I_top(I_top['+str(i)+']),\n' - I_top_str += '\t.Tile_X0Y' + \ - str(count)+'_B_I_top(I_top['+str(i-1)+']),\n' + I_top_str += "\t.Tile_X0Y" + str(count) + "_A_I_top(I_top[" + str(i) + "]),\n" + I_top_str += ( + "\t.Tile_X0Y" + str(count) + "_B_I_top(I_top[" + str(i - 1) + "]),\n" + ) - T_top_str += '\t.Tile_X0Y'+str(count)+'_A_T_top(T_top['+str(i)+']),\n' - T_top_str += '\t.Tile_X0Y' + \ - str(count)+'_B_T_top(T_top['+str(i-1)+']),\n' + T_top_str += "\t.Tile_X0Y" + str(count) + "_A_T_top(T_top[" + str(i) + "]),\n" + T_top_str += ( + "\t.Tile_X0Y" + str(count) + "_B_T_top(T_top[" + str(i - 1) + "]),\n" + ) - O_top_str += '\t.Tile_X0Y'+str(count)+'_A_O_top(O_top['+str(i)+']),\n' - O_top_str += '\t.Tile_X0Y' + \ - str(count)+'_B_O_top(O_top['+str(i-1)+']),\n' + O_top_str += "\t.Tile_X0Y" + str(count) + "_A_O_top(O_top[" + str(i) + "]),\n" + O_top_str += ( + "\t.Tile_X0Y" + str(count) + "_B_O_top(O_top[" + str(i - 1) + "]),\n" + ) A_config_C_str = "" B_config_C_str = "" @@ -246,51 +312,139 @@ def main(): Config_accessC_str = "" count = 0 - for i in range(NumberOfRows*4-1, -1, -4): + for i in range(NumberOfRows * 4 - 1, -1, -4): count += 1 - A_config_C_str += '\t.Tile_X0Y' + \ - str(count)+'_A_config_C_bit0(A_config_C['+str(i)+']),\n' - A_config_C_str += '\t.Tile_X0Y' + \ - str(count)+'_A_config_C_bit1(A_config_C['+str(i-1)+']),\n' - A_config_C_str += '\t.Tile_X0Y' + \ - str(count)+'_A_config_C_bit2(A_config_C['+str(i-2)+']),\n' - A_config_C_str += '\t.Tile_X0Y' + \ - str(count)+'_A_config_C_bit3(A_config_C['+str(i-3)+']),\n' - - B_config_C_str += '\t.Tile_X0Y' + \ - str(count)+'_B_config_C_bit0(B_config_C['+str(i)+']),\n' - B_config_C_str += '\t.Tile_X0Y' + \ - str(count)+'_B_config_C_bit1(B_config_C['+str(i-1)+']),\n' - B_config_C_str += '\t.Tile_X0Y' + \ - str(count)+'_B_config_C_bit2(B_config_C['+str(i-2)+']),\n' - B_config_C_str += '\t.Tile_X0Y' + \ - str(count)+'_B_config_C_bit3(B_config_C['+str(i-3)+']),\n' - - FAB2RAM_C_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_C_O0(FAB2RAM_C['+str(i)+']),\n' - FAB2RAM_C_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_C_O1(FAB2RAM_C['+str(i-1)+']),\n' - FAB2RAM_C_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_C_O2(FAB2RAM_C['+str(i-2)+']),\n' - FAB2RAM_C_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_C_O3(FAB2RAM_C['+str(i-3)+']),\n' - - Config_accessC_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_Config_accessC_bit0(Config_accessC['+str(i)+']),\n' - Config_accessC_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_Config_accessC_bit1(Config_accessC['+str(i-1)+']),\n' - Config_accessC_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_Config_accessC_bit2(Config_accessC['+str(i-2)+']),\n' - Config_accessC_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_Config_accessC_bit3(Config_accessC['+str(i-3)+']),\n' + A_config_C_str += ( + "\t.Tile_X0Y" + + str(count) + + "_A_config_C_bit0(A_config_C[" + + str(i) + + "]),\n" + ) + A_config_C_str += ( + "\t.Tile_X0Y" + + str(count) + + "_A_config_C_bit1(A_config_C[" + + str(i - 1) + + "]),\n" + ) + A_config_C_str += ( + "\t.Tile_X0Y" + + str(count) + + "_A_config_C_bit2(A_config_C[" + + str(i - 2) + + "]),\n" + ) + A_config_C_str += ( + "\t.Tile_X0Y" + + str(count) + + "_A_config_C_bit3(A_config_C[" + + str(i - 3) + + "]),\n" + ) + + B_config_C_str += ( + "\t.Tile_X0Y" + + str(count) + + "_B_config_C_bit0(B_config_C[" + + str(i) + + "]),\n" + ) + B_config_C_str += ( + "\t.Tile_X0Y" + + str(count) + + "_B_config_C_bit1(B_config_C[" + + str(i - 1) + + "]),\n" + ) + B_config_C_str += ( + "\t.Tile_X0Y" + + str(count) + + "_B_config_C_bit2(B_config_C[" + + str(i - 2) + + "]),\n" + ) + B_config_C_str += ( + "\t.Tile_X0Y" + + str(count) + + "_B_config_C_bit3(B_config_C[" + + str(i - 3) + + "]),\n" + ) + + FAB2RAM_C_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_C_O0(FAB2RAM_C[" + + str(i) + + "]),\n" + ) + FAB2RAM_C_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_C_O1(FAB2RAM_C[" + + str(i - 1) + + "]),\n" + ) + FAB2RAM_C_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_C_O2(FAB2RAM_C[" + + str(i - 2) + + "]),\n" + ) + FAB2RAM_C_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_C_O3(FAB2RAM_C[" + + str(i - 3) + + "]),\n" + ) + + Config_accessC_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_Config_accessC_bit0(Config_accessC[" + + str(i) + + "]),\n" + ) + Config_accessC_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_Config_accessC_bit1(Config_accessC[" + + str(i - 1) + + "]),\n" + ) + Config_accessC_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_Config_accessC_bit2(Config_accessC[" + + str(i - 2) + + "]),\n" + ) + Config_accessC_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_Config_accessC_bit3(Config_accessC[" + + str(i - 3) + + "]),\n" + ) RAM2FAB_D_str = "" FAB2RAM_D_str = "" @@ -316,181 +470,443 @@ def main(): # RAM2FAB_D_str+='\t.Tile_X'+str(NumberOfCols-1)+'Y'+str(count)+'_RAM2FAB_D3_I3(RAM2FAB_D['+str(i-14)+']),\n' # count = 0 - for i in range(NumberOfRows*4*4-1, -1, -16): + for i in range(NumberOfRows * 4 * 4 - 1, -1, -16): count += 1 - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D0_I0(RAM2FAB_D['+str(i)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D0_I1(RAM2FAB_D['+str(i-1)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D0_I2(RAM2FAB_D['+str(i-2)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D0_I3(RAM2FAB_D['+str(i-3)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D1_I0(RAM2FAB_D['+str(i-4)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D1_I1(RAM2FAB_D['+str(i-5)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D1_I2(RAM2FAB_D['+str(i-6)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D1_I3(RAM2FAB_D['+str(i-7)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D2_I0(RAM2FAB_D['+str(i-8)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D2_I1(RAM2FAB_D['+str(i-9)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D2_I2(RAM2FAB_D['+str(i-10)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D2_I3(RAM2FAB_D['+str(i-11)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D3_I0(RAM2FAB_D['+str(i-12)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D3_I1(RAM2FAB_D['+str(i-13)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D3_I2(RAM2FAB_D['+str(i-14)+']),\n' - RAM2FAB_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_RAM2FAB_D3_I3(RAM2FAB_D['+str(i-15)+']),\n' - - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D0_O0(FAB2RAM_D['+str(i)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D0_O1(FAB2RAM_D['+str(i-1)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D0_O2(FAB2RAM_D['+str(i-2)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D0_O3(FAB2RAM_D['+str(i-3)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D1_O0(FAB2RAM_D['+str(i-4)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D1_O1(FAB2RAM_D['+str(i-5)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D1_O2(FAB2RAM_D['+str(i-6)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D1_O3(FAB2RAM_D['+str(i-7)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D2_O0(FAB2RAM_D['+str(i-8)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D2_O1(FAB2RAM_D['+str(i-9)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D2_O2(FAB2RAM_D['+str(i-10)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D2_O3(FAB2RAM_D['+str(i-11)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D3_O0(FAB2RAM_D['+str(i-12)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D3_O1(FAB2RAM_D['+str(i-13)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D3_O2(FAB2RAM_D['+str(i-14)+']),\n' - FAB2RAM_D_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_D3_O3(FAB2RAM_D['+str(i-15)+']),\n' + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D0_I0(RAM2FAB_D[" + + str(i) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D0_I1(RAM2FAB_D[" + + str(i - 1) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D0_I2(RAM2FAB_D[" + + str(i - 2) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D0_I3(RAM2FAB_D[" + + str(i - 3) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D1_I0(RAM2FAB_D[" + + str(i - 4) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D1_I1(RAM2FAB_D[" + + str(i - 5) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D1_I2(RAM2FAB_D[" + + str(i - 6) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D1_I3(RAM2FAB_D[" + + str(i - 7) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D2_I0(RAM2FAB_D[" + + str(i - 8) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D2_I1(RAM2FAB_D[" + + str(i - 9) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D2_I2(RAM2FAB_D[" + + str(i - 10) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D2_I3(RAM2FAB_D[" + + str(i - 11) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D3_I0(RAM2FAB_D[" + + str(i - 12) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D3_I1(RAM2FAB_D[" + + str(i - 13) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D3_I2(RAM2FAB_D[" + + str(i - 14) + + "]),\n" + ) + RAM2FAB_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_RAM2FAB_D3_I3(RAM2FAB_D[" + + str(i - 15) + + "]),\n" + ) + + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D0_O0(FAB2RAM_D[" + + str(i) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D0_O1(FAB2RAM_D[" + + str(i - 1) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D0_O2(FAB2RAM_D[" + + str(i - 2) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D0_O3(FAB2RAM_D[" + + str(i - 3) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D1_O0(FAB2RAM_D[" + + str(i - 4) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D1_O1(FAB2RAM_D[" + + str(i - 5) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D1_O2(FAB2RAM_D[" + + str(i - 6) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D1_O3(FAB2RAM_D[" + + str(i - 7) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D2_O0(FAB2RAM_D[" + + str(i - 8) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D2_O1(FAB2RAM_D[" + + str(i - 9) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D2_O2(FAB2RAM_D[" + + str(i - 10) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D2_O3(FAB2RAM_D[" + + str(i - 11) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D3_O0(FAB2RAM_D[" + + str(i - 12) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D3_O1(FAB2RAM_D[" + + str(i - 13) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D3_O2(FAB2RAM_D[" + + str(i - 14) + + "]),\n" + ) + FAB2RAM_D_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_D3_O3(FAB2RAM_D[" + + str(i - 15) + + "]),\n" + ) FAB2RAM_A_str = "" count = 0 - for i in range(NumberOfRows*4*2-1, -1, -8): + for i in range(NumberOfRows * 4 * 2 - 1, -1, -8): count += 1 - FAB2RAM_A_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_A0_O0(FAB2RAM_A['+str(i)+']),\n' - FAB2RAM_A_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_A0_O1(FAB2RAM_A['+str(i-1)+']),\n' - FAB2RAM_A_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_A0_O2(FAB2RAM_A['+str(i-2)+']),\n' - FAB2RAM_A_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_A0_O3(FAB2RAM_A['+str(i-3)+']),\n' - FAB2RAM_A_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_A1_O0(FAB2RAM_A['+str(i-4)+']),\n' - FAB2RAM_A_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_A1_O1(FAB2RAM_A['+str(i-5)+']),\n' - FAB2RAM_A_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_A1_O2(FAB2RAM_A['+str(i-6)+']),\n' - FAB2RAM_A_str += '\t.Tile_X' + \ - str(NumberOfCols-1)+'Y'+str(count) + \ - '_FAB2RAM_A1_O3(FAB2RAM_A['+str(i-7)+']),\n' - - wrapper_top_str += I_top_str+'\n' - wrapper_top_str += T_top_str+'\n' - wrapper_top_str += O_top_str+'\n' - wrapper_top_str += A_config_C_str+'\n' - wrapper_top_str += B_config_C_str+'\n' - - wrapper_top_str += RAM2FAB_D_str+'\n' - wrapper_top_str += FAB2RAM_D_str+'\n' - wrapper_top_str += FAB2RAM_A_str+'\n' - wrapper_top_str += FAB2RAM_C_str+'\n' - wrapper_top_str += Config_accessC_str+'\n' - - wrapper_top_str += '\t//declarations\n' - wrapper_top_str += '\t.UserCLK(CLK),\n' - wrapper_top_str += '\t.FrameData(FrameData),\n' - wrapper_top_str += '\t.FrameStrobe(FrameSelect)\n' - wrapper_top_str += '\t)\n\n' + FAB2RAM_A_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_A0_O0(FAB2RAM_A[" + + str(i) + + "]),\n" + ) + FAB2RAM_A_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_A0_O1(FAB2RAM_A[" + + str(i - 1) + + "]),\n" + ) + FAB2RAM_A_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_A0_O2(FAB2RAM_A[" + + str(i - 2) + + "]),\n" + ) + FAB2RAM_A_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_A0_O3(FAB2RAM_A[" + + str(i - 3) + + "]),\n" + ) + FAB2RAM_A_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_A1_O0(FAB2RAM_A[" + + str(i - 4) + + "]),\n" + ) + FAB2RAM_A_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_A1_O1(FAB2RAM_A[" + + str(i - 5) + + "]),\n" + ) + FAB2RAM_A_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_A1_O2(FAB2RAM_A[" + + str(i - 6) + + "]),\n" + ) + FAB2RAM_A_str += ( + "\t.Tile_X" + + str(NumberOfCols - 1) + + "Y" + + str(count) + + "_FAB2RAM_A1_O3(FAB2RAM_A[" + + str(i - 7) + + "]),\n" + ) + + wrapper_top_str += I_top_str + "\n" + wrapper_top_str += T_top_str + "\n" + wrapper_top_str += O_top_str + "\n" + wrapper_top_str += A_config_C_str + "\n" + wrapper_top_str += B_config_C_str + "\n" + + wrapper_top_str += RAM2FAB_D_str + "\n" + wrapper_top_str += FAB2RAM_D_str + "\n" + wrapper_top_str += FAB2RAM_A_str + "\n" + wrapper_top_str += FAB2RAM_C_str + "\n" + wrapper_top_str += Config_accessC_str + "\n" + + wrapper_top_str += "\t//declarations\n" + wrapper_top_str += "\t.UserCLK(CLK),\n" + wrapper_top_str += "\t.FrameData(FrameData),\n" + wrapper_top_str += "\t.FrameStrobe(FrameSelect)\n" + wrapper_top_str += "\t)\n\n" BRAM_str = "" - data_cap = int((NumberOfRows*4*4)/NumberOfBRAMs) - addr_cap = int((NumberOfRows*4*2)/NumberOfBRAMs) - config_cap = int((NumberOfRows*4)/NumberOfBRAMs) + data_cap = int((NumberOfRows * 4 * 4) / NumberOfBRAMs) + addr_cap = int((NumberOfRows * 4 * 2) / NumberOfBRAMs) + config_cap = int((NumberOfRows * 4) / NumberOfBRAMs) for i in range(NumberOfBRAMs): - BRAM_str += '\tBlockRAM_1KB Inst_BlockRAM_'+str(i)+' (\n' - BRAM_str += '\t.clk(CLK),\n' - BRAM_str += '\t.rd_addr(FAB2RAM_A[' + \ - str(addr_cap*i+8-1)+':'+str(addr_cap*i)+']),\n' - BRAM_str += '\t.rd_data(RAM2FAB_D[' + \ - str(data_cap*i+32-1)+':'+str(data_cap*i)+']),\n' - BRAM_str += '\t.wr_addr(FAB2RAM_A['+str(addr_cap * - i+16-1)+':'+str(addr_cap*i+8)+']),\n' - BRAM_str += '\t.wr_data(FAB2RAM_D[' + \ - str(data_cap*i+32-1)+':'+str(data_cap*i)+']),\n' - BRAM_str += '\t.C0(FAB2RAM_C['+str(config_cap*i)+']),\n' - BRAM_str += '\t.C1(FAB2RAM_C['+str(config_cap*i+1)+']),\n' - BRAM_str += '\t.C2(FAB2RAM_C['+str(config_cap*i+2)+']),\n' - BRAM_str += '\t.C3(FAB2RAM_C['+str(config_cap*i+3)+']),\n' - BRAM_str += '\t.C4(FAB2RAM_C['+str(config_cap*i+4)+']),\n' - BRAM_str += '\t.C5(FAB2RAM_C['+str(config_cap*i+5)+'])\n' - BRAM_str += '\t)\n\n' + BRAM_str += "\tBlockRAM_1KB Inst_BlockRAM_" + str(i) + " (\n" + BRAM_str += "\t.clk(CLK),\n" + BRAM_str += ( + "\t.rd_addr(FAB2RAM_A[" + + str(addr_cap * i + 8 - 1) + + ":" + + str(addr_cap * i) + + "]),\n" + ) + BRAM_str += ( + "\t.rd_data(RAM2FAB_D[" + + str(data_cap * i + 32 - 1) + + ":" + + str(data_cap * i) + + "]),\n" + ) + BRAM_str += ( + "\t.wr_addr(FAB2RAM_A[" + + str(addr_cap * i + 16 - 1) + + ":" + + str(addr_cap * i + 8) + + "]),\n" + ) + BRAM_str += ( + "\t.wr_data(FAB2RAM_D[" + + str(data_cap * i + 32 - 1) + + ":" + + str(data_cap * i) + + "]),\n" + ) + BRAM_str += "\t.C0(FAB2RAM_C[" + str(config_cap * i) + "]),\n" + BRAM_str += "\t.C1(FAB2RAM_C[" + str(config_cap * i + 1) + "]),\n" + BRAM_str += "\t.C2(FAB2RAM_C[" + str(config_cap * i + 2) + "]),\n" + BRAM_str += "\t.C3(FAB2RAM_C[" + str(config_cap * i + 3) + "]),\n" + BRAM_str += "\t.C4(FAB2RAM_C[" + str(config_cap * i + 4) + "]),\n" + BRAM_str += "\t.C5(FAB2RAM_C[" + str(config_cap * i + 5) + "])\n" + BRAM_str += "\t)\n\n" wrapper_top_str += BRAM_str - wrapper_top_str += "\tassign FrameData = {32'h12345678,FrameRegister,32'h12345678}\n\n" - wrapper_top_str += 'endmodule\n\n' + wrapper_top_str += ( + "\tassign FrameData = {32'h12345678,FrameRegister,32'h12345678}\n\n" + ) + wrapper_top_str += "endmodule\n\n" # wrapper_top_str+='module sky130_fd_sc_hd__inv (\n' # wrapper_top_str+='\tY,\n' @@ -505,23 +921,23 @@ def main(): # wrapper_top_str+=strobe_reg_modules if wrapper_top_str: - with open(f"{output_dir}/eFPGA_top.v", 'w') as file: + with open(f"{output_dir}/eFPGA_top.v", "w") as file: file.write(wrapper_top_str) if data_reg_modules: - with open(f"{output_dir}/Frame_Data_Reg_Pack.v", 'w') as file: + with open(f"{output_dir}/Frame_Data_Reg_Pack.v", "w") as file: file.write(data_reg_modules) if strobe_reg_modules: - with open(f"{output_dir}/Frame_Select_Pack.v", 'w') as file: + with open(f"{output_dir}/Frame_Select_Pack.v", "w") as file: file.write(strobe_reg_modules) if config_str: - with open(f"{output_dir}/Config.v", 'w') as file: + with open(f"{output_dir}/Config.v", "w") as file: file.write(config_str) if configfsm_str: - with open(f"{output_dir}/ConfigFSM.v", 'w') as file: + with open(f"{output_dir}/ConfigFSM.v", "w") as file: file.write(configfsm_str) # if testbench_str: @@ -536,28 +952,33 @@ def main(): if sys.version_info <= (3, 5, 0): print("Need Python 3.5 or above to run FABulous") exit(-1) - parser = argparse.ArgumentParser(description='') + parser = argparse.ArgumentParser(description="") parser.add_argument( - "-o", "--output_dir", help="The directory to the project folder") + "-o", "--output_dir", help="The directory to the project folder" + ) parser.add_argument( - "-r", "--NumberOfRows", help="The directory to the project folder") + "-r", "--NumberOfRows", help="The directory to the project folder" + ) parser.add_argument( - "-c", "--NumberOfCols", help="The directory to the project folder") + "-c", "--NumberOfCols", help="The directory to the project folder" + ) parser.add_argument( - "-b", "--FrameBitsPerRow", help="The directory to the project folder") + "-b", "--FrameBitsPerRow", help="The directory to the project folder" + ) parser.add_argument( - "-f", "--MaxFramesPerCol", help="The directory to the project folder") + "-f", "--MaxFramesPerCol", help="The directory to the project folder" + ) parser.add_argument( - "-d", "--desync_flag", help="The directory to the project folder") + "-d", "--desync_flag", help="The directory to the project folder" + ) - parser.add_argument( - "-m", "--block_ram", help="The directory to the project folder") + parser.add_argument("-m", "--block_ram", help="The directory to the project folder") args = parser.parse_args() @@ -584,7 +1005,7 @@ def main(): main() -#argv = "/home/ise/shared_folder/diffeq1/LC_on/netgen/synthesis/diffeq_paj_convert_synthesis.v" +# argv = "/home/ise/shared_folder/diffeq1/LC_on/netgen/synthesis/diffeq_paj_convert_synthesis.v" # if words[i+1] == "critical": diff --git a/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM_vhdl.py b/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM_vhdl.py index 609edd92..320885ad 100644 --- a/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM_vhdl.py +++ b/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM_vhdl.py @@ -7,12 +7,12 @@ import os import argparse -FABulous_root = os.getenv('FABulous_root') +FABulous_root = os.getenv("FABulous_root") if FABulous_root is None: - print('FABulous_root is not set!') - print('Set FABulous_root with the following command:') - print('export FABulous_root=') + print("FABulous_root is not set!") + print("Set FABulous_root with the following command:") + print("export FABulous_root=") sys.exit(1) NumberOfRows = 16 @@ -27,17 +27,17 @@ def main(): - NumberOfBRAMs = int(NumberOfRows/2) - - print('NumberOfRows :', NumberOfRows) - print('NumberOfCols :', NumberOfCols-2) - print('FrameBitsPerRow :', FrameBitsPerRow) - print('MaxFramesPerCol :', MaxFramesPerCol) - print('desync_flag :', desync_flag) - print('FrameSelectWidth :', FrameSelectWidth) - print('RowSelectWidth :', RowSelectWidth) - print('NumberOfBRAMs :', NumberOfBRAMs) - print('') + NumberOfBRAMs = int(NumberOfRows / 2) + + print("NumberOfRows :", NumberOfRows) + print("NumberOfCols :", NumberOfCols - 2) + print("FrameBitsPerRow :", FrameBitsPerRow) + print("MaxFramesPerCol :", MaxFramesPerCol) + print("desync_flag :", desync_flag) + print("FrameSelectWidth :", FrameSelectWidth) + print("RowSelectWidth :", RowSelectWidth) + print("NumberOfBRAMs :", NumberOfBRAMs) + print("") wrapper_top_str = "" config_str = "" @@ -45,44 +45,73 @@ def main(): data_reg_modules = "" strobe_reg_modules = "" testbench_str = "" - #data_reg_module_temp = "" + # data_reg_module_temp = "" try: - with open(f"{FABulous_root}/fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.vhdl", 'r') as file: + with open( + f"{FABulous_root}/fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.vhdl", + "r", + ) as file: wrapper_top_str = file.read() except IOError: print("eFPGA_v3_top_sky130_with_BRAM_template.v not accessible") exit(-1) try: - with open(f"{FABulous_root}/fabric_generator/fabulous_top_wrapper_temp/Config_template.vhdl", 'r') as file: + with open( + f"{FABulous_root}/fabric_generator/fabulous_top_wrapper_temp/Config_template.vhdl", + "r", + ) as file: config_str = file.read() except IOError: print("Config_template.v not accessible") exit(-1) try: - with open(f"{FABulous_root}/fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.vhdl", 'r') as file: + with open( + f"{FABulous_root}/fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.vhdl", + "r", + ) as file: configfsm_str = file.read() except IOError: print("ConfigFSM_template.v not accessible") exit(-1) try: - with open(f"{FABulous_root}/fabric_generator/fabulous_top_wrapper_temp/tb_bitbang_template.vhd", 'r') as file: + with open( + f"{FABulous_root}/fabric_generator/fabulous_top_wrapper_temp/tb_bitbang_template.vhd", + "r", + ) as file: testbench_str = file.read() except IOError: print("tb_bitbang_template.vhd not accessible") exit(-1) - wrapper_top_str = wrapper_top_str.replace("FrameBitsPerRow : integer := 32;", f"FrameBitsPerRow : integer := {FrameBitsPerRow};") - wrapper_top_str = wrapper_top_str.replace("FrameSelectWidth : integer := 5;", f"FrameSelectWidth : integer := {FrameSelectWidth};") - wrapper_top_str = wrapper_top_str.replace("MaxFramesPerCol : integer := 20;", f"MaxFramesPerCol : integer := {MaxFramesPerCol};") - wrapper_top_str = wrapper_top_str.replace("NumberOfCols : integer := 19;", f"NumberOfCols : integer := {NumberOfCols};") - wrapper_top_str = wrapper_top_str.replace("NumberOfRows : integer := 16;", f"NumberOfRows : integer := {NumberOfRows};") - wrapper_top_str = wrapper_top_str.replace("RowSelectWidth : integer := 5;", f"RowSelectWidth : integer := {RowSelectWidth};") - wrapper_top_str = wrapper_top_str.replace("desync_flag : integer := 20;", f"desync_flag : integer := {desync_flag};") - + wrapper_top_str = wrapper_top_str.replace( + "FrameBitsPerRow : integer := 32;", + f"FrameBitsPerRow : integer := {FrameBitsPerRow};", + ) + wrapper_top_str = wrapper_top_str.replace( + "FrameSelectWidth : integer := 5;", + f"FrameSelectWidth : integer := {FrameSelectWidth};", + ) + wrapper_top_str = wrapper_top_str.replace( + "MaxFramesPerCol : integer := 20;", + f"MaxFramesPerCol : integer := {MaxFramesPerCol};", + ) + wrapper_top_str = wrapper_top_str.replace( + "NumberOfCols : integer := 19;", f"NumberOfCols : integer := {NumberOfCols};" + ) + wrapper_top_str = wrapper_top_str.replace( + "NumberOfRows : integer := 16;", f"NumberOfRows : integer := {NumberOfRows};" + ) + wrapper_top_str = wrapper_top_str.replace( + "RowSelectWidth : integer := 5;", + f"RowSelectWidth : integer := {RowSelectWidth};", + ) + wrapper_top_str = wrapper_top_str.replace( + "desync_flag : integer := 20;", f"desync_flag : integer := {desync_flag};" + ) # wrapper_top_str = wrapper_top_str.replace( # "I_top : out unsigned(31 downto 0)", f"I_top : out unsigned({NumberOfRows*2}-1 downto 0)") @@ -91,13 +120,11 @@ def main(): # wrapper_top_str = wrapper_top_str.replace( # "O_top : in unsigned(31 downto 0)", f"O_top : in unsigned({NumberOfRows*2}-1 downto 0)") - # wrapper_top_str = wrapper_top_str.replace( # "A_config_C : out unsigned(63 downto 0)", f"A_config_C : out unsigned({NumberOfRows*4}-1 downto 0)") # wrapper_top_str = wrapper_top_str.replace( # "B_config_C : out unsigned(63 downto 0)", f"B_config_C : out unsigned({NumberOfRows*4}-1 downto 0)") - # wrapper_top_str = wrapper_top_str.replace( # "RAM2FAB_D : out unsigned(63 downto 0)", f"RAM2FAB_D : out unsigned({NumberOfRows*4*4}-1 downto 0)") # wrapper_top_str = wrapper_top_str.replace( @@ -111,32 +138,46 @@ def main(): # wrapper_top_str = wrapper_top_str.replace( # "Config_accessC : out unsigned(63 downto 0)", f"Config_accessC : out unsigned({NumberOfRows*4}-1 downto 0)") - wrapper_top_str = wrapper_top_str.replace( - "localparam NumberOfRows = 16", "localparam NumberOfRows = "+str(NumberOfRows)) + "localparam NumberOfRows = 16", "localparam NumberOfRows = " + str(NumberOfRows) + ) wrapper_top_str = wrapper_top_str.replace( - "localparam NumberOfCols = 19", "localparam NumberOfCols = "+str(NumberOfCols)) + "localparam NumberOfCols = 19", "localparam NumberOfCols = " + str(NumberOfCols) + ) - #config_str = config_str.replace("parameter NumberOfRows = 16", "parameter NumberOfRows = "+str(NumberOfRows)) + # config_str = config_str.replace("parameter NumberOfRows = 16", "parameter NumberOfRows = "+str(NumberOfRows)) config_str = config_str.replace( - "RowSelectWidth : integer := 5", f"RowSelectWidth : integer := {RowSelectWidth}") + "RowSelectWidth : integer := 5", f"RowSelectWidth : integer := {RowSelectWidth}" + ) config_str = config_str.replace( - "FrameBitsPerRow : integer := 32;", f"FrameBitsPerRow : integer := {FrameBitsPerRow};") - #config_str = config_str.replace("parameter desync_flag = 20", "parameter desync_flag = "+str(desync_flag)) + "FrameBitsPerRow : integer := 32;", + f"FrameBitsPerRow : integer := {FrameBitsPerRow};", + ) + # config_str = config_str.replace("parameter desync_flag = 20", "parameter desync_flag = "+str(desync_flag)) configfsm_str = configfsm_str.replace( - "NumberOfRows : integer := 16;", f"NumberOfRows : integer := {NumberOfRows};") + "NumberOfRows : integer := 16;", f"NumberOfRows : integer := {NumberOfRows};" + ) configfsm_str = configfsm_str.replace( - "RowSelectWidth : integer := 5;", f"RowSelectWidth : integer := {RowSelectWidth};") + "RowSelectWidth : integer := 5;", + f"RowSelectWidth : integer := {RowSelectWidth};", + ) configfsm_str = configfsm_str.replace( - "FrameBitsPerRow : integer := 32;", f"FrameBitsPerRow : integer := {FrameBitsPerRow};") + "FrameBitsPerRow : integer := 32;", + f"FrameBitsPerRow : integer := {FrameBitsPerRow};", + ) configfsm_str = configfsm_str.replace( - "desync_flag : integer := 20", f"desync_flag : integer := {desync_flag}") + "desync_flag : integer := 20", f"desync_flag : integer := {desync_flag}" + ) testbench_str = testbench_str.replace( - " STD_LOGIC_VECTOR (32 -1 downto 0)", " STD_LOGIC_VECTOR ("+str(NumberOfRows*2)+" -1 downto 0)") + " STD_LOGIC_VECTOR (32 -1 downto 0)", + " STD_LOGIC_VECTOR (" + str(NumberOfRows * 2) + " -1 downto 0)", + ) testbench_str = testbench_str.replace( - "STD_LOGIC_VECTOR (64 -1 downto 0)", "STD_LOGIC_VECTOR ("+str(NumberOfRows*4)+" -1 downto 0)") + "STD_LOGIC_VECTOR (64 -1 downto 0)", + "STD_LOGIC_VECTOR (" + str(NumberOfRows * 4) + " -1 downto 0)", + ) # I_top_buf_str = "" # T_top_buf_str = "" @@ -159,55 +200,67 @@ def main(): # wrapper_top_str+=B_config_C_buf_str+'\n' for row in range(NumberOfRows): - data_reg_name = 'Frame_Data_Reg_'+str(row) - - wrapper_top_str += f" Inst_{data_reg_name}: Frame_Data_Reg""\n" - wrapper_top_str += f" generic map (""\n" - wrapper_top_str += f" FrameBitsPerRow => {FrameBitsPerRow},""\n" - wrapper_top_str += f" RowSelectWidth => {RowSelectWidth},""\n" - wrapper_top_str += f" Row => {row+1}""\n" - wrapper_top_str += f" )""\n" - wrapper_top_str += f" port map (""\n" - wrapper_top_str += f" FrameData_I => LocalWriteData,""\n" - wrapper_top_str += f" FrameData_O => FrameRegister( {row}*FrameBitsPerRow + FrameBitsPerRow - 1 downto {row}*FrameBitsPerRow ),""\n" - wrapper_top_str += f" RowSelect => RowSelect,""\n" - wrapper_top_str += f" CLK => CLK""\n" - wrapper_top_str += f" );""\n\n" + data_reg_name = "Frame_Data_Reg_" + str(row) + + wrapper_top_str += f" Inst_{data_reg_name}: Frame_Data_Reg" "\n" + wrapper_top_str += f" generic map (" "\n" + wrapper_top_str += f" FrameBitsPerRow => {FrameBitsPerRow}," "\n" + wrapper_top_str += f" RowSelectWidth => {RowSelectWidth}," "\n" + wrapper_top_str += f" Row => {row+1}" "\n" + wrapper_top_str += f" )" "\n" + wrapper_top_str += f" port map (" "\n" + wrapper_top_str += f" FrameData_I => LocalWriteData," "\n" + wrapper_top_str += ( + f" FrameData_O => FrameRegister( {row}*FrameBitsPerRow + FrameBitsPerRow - 1 downto {row}*FrameBitsPerRow )," + "\n" + ) + wrapper_top_str += f" RowSelect => RowSelect," "\n" + wrapper_top_str += f" CLK => CLK" "\n" + wrapper_top_str += f" );" "\n\n" for col in range(NumberOfCols): - strobe_reg_name = 'Frame_Select_'+str(col) - - wrapper_top_str += f" Inst_{strobe_reg_name}: Frame_Select""\n" - wrapper_top_str += f" generic map (""\n" - wrapper_top_str += f" FrameSelectWidth => {FrameSelectWidth},""\n" - wrapper_top_str += f" MaxFramesPerCol => {MaxFramesPerCol},""\n" - wrapper_top_str += f" Col => {col}""\n" - wrapper_top_str += f" )""\n" - wrapper_top_str += f" port map (""\n" - wrapper_top_str += f" FrameStrobe_I => FrameAddressRegister(MaxFramesPerCol-1 downto 0),""\n" - wrapper_top_str += f" FrameStrobe_O => FrameSelect( MaxFramesPerCol*{col} + MaxFramesPerCol - 1 downto MaxFramesPerCol*{col} ),""\n" - wrapper_top_str += f" FrameSelect => FrameAddressRegister(FrameBitsPerRow-1 downto FrameBitsPerRow-(FrameSelectWidth)),""\n" - wrapper_top_str += f" FrameStrobe => LongFrameStrobe""\n" - wrapper_top_str += f" );""\n\n" - - #wrapper_top_str+='\twire ['+str(NumberOfRows-1)+':0] dump\n\n' - wrapper_top_str += '\tInst_eFPGA: eFPGA\n' + strobe_reg_name = "Frame_Select_" + str(col) + + wrapper_top_str += f" Inst_{strobe_reg_name}: Frame_Select" "\n" + wrapper_top_str += f" generic map (" "\n" + wrapper_top_str += f" FrameSelectWidth => {FrameSelectWidth}," "\n" + wrapper_top_str += f" MaxFramesPerCol => {MaxFramesPerCol}," "\n" + wrapper_top_str += f" Col => {col}" "\n" + wrapper_top_str += f" )" "\n" + wrapper_top_str += f" port map (" "\n" + wrapper_top_str += ( + f" FrameStrobe_I => FrameAddressRegister(MaxFramesPerCol-1 downto 0)," + "\n" + ) + wrapper_top_str += ( + f" FrameStrobe_O => FrameSelect( MaxFramesPerCol*{col} + MaxFramesPerCol - 1 downto MaxFramesPerCol*{col} )," + "\n" + ) + wrapper_top_str += ( + f" FrameSelect => FrameAddressRegister(FrameBitsPerRow-1 downto FrameBitsPerRow-(FrameSelectWidth))," + "\n" + ) + wrapper_top_str += f" FrameStrobe => LongFrameStrobe" "\n" + wrapper_top_str += f" );" "\n\n" + + # wrapper_top_str+='\twire ['+str(NumberOfRows-1)+':0] dump\n\n' + wrapper_top_str += "\tInst_eFPGA: eFPGA\n" wrapper_top_str += " port map (\n" I_top_str = "" T_top_str = "" O_top_str = "" count = 0 - for i in range(NumberOfRows*2-1, -1, -2): + for i in range(NumberOfRows * 2 - 1, -1, -2): count += 1 - I_top_str += f" Tile_X0Y{count}_A_I_top => I_top({i}),""\n" - I_top_str += f" Tile_X0Y{count}_B_I_top => I_top({i-1}),""\n" + I_top_str += f" Tile_X0Y{count}_A_I_top => I_top({i})," "\n" + I_top_str += f" Tile_X0Y{count}_B_I_top => I_top({i-1})," "\n" - T_top_str += f" Tile_X0Y{count}_A_T_top => T_top({i}),""\n" - T_top_str += f" Tile_X0Y{count}_B_T_top => T_top({i-1}),""\n" + T_top_str += f" Tile_X0Y{count}_A_T_top => T_top({i})," "\n" + T_top_str += f" Tile_X0Y{count}_B_T_top => T_top({i-1})," "\n" - O_top_str += f" Tile_X0Y{count}_A_O_top => O_top({i}),""\n" - O_top_str += f" Tile_X0Y{count}_B_O_top => O_top({i-1}),""\n" + O_top_str += f" Tile_X0Y{count}_A_O_top => O_top({i})," "\n" + O_top_str += f" Tile_X0Y{count}_B_O_top => O_top({i-1})," "\n" A_config_C_str = "" B_config_C_str = "" @@ -216,28 +269,64 @@ def main(): Config_accessC_str = "" count = 0 - for i in range(NumberOfRows*4-1, -1, -4): + for i in range(NumberOfRows * 4 - 1, -1, -4): count += 1 - A_config_C_str += f" Tile_X0Y{count}_A_config_C_bit0 => A_config_C({i}),""\n" - A_config_C_str += f" Tile_X0Y{count}_A_config_C_bit1 => A_config_C({i-1}),""\n" - A_config_C_str += f" Tile_X0Y{count}_A_config_C_bit2 => A_config_C({i-2}),""\n" - A_config_C_str += f" Tile_X0Y{count}_A_config_C_bit3 => A_config_C({i-3}),""\n" - - B_config_C_str += f" Tile_X0Y{count}_B_config_C_bit0 => B_config_C({i}),""\n" - B_config_C_str += f" Tile_X0Y{count}_B_config_C_bit1 => B_config_C({i-1}),""\n" - B_config_C_str += f" Tile_X0Y{count}_B_config_C_bit2 => B_config_C({i-2}),""\n" - B_config_C_str += f" Tile_X0Y{count}_B_config_C_bit3 => B_config_C({i-3}),""\n" - - FAB2RAM_C_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_C_O0 => FAB2RAM_C({i}),""\n" - FAB2RAM_C_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_C_O1 => FAB2RAM_C({i-1}),""\n" - FAB2RAM_C_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_C_O2 => FAB2RAM_C({i-2}),""\n" - FAB2RAM_C_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_C_O3 => FAB2RAM_C({i-3}),""\n" - - Config_accessC_str += f" Tile_X{NumberOfCols-1}Y{count}_Config_accessC_bit0 => Config_accessC({i}),""\n" - Config_accessC_str += f" Tile_X{NumberOfCols-1}Y{count}_Config_accessC_bit1 => Config_accessC({i-1}),""\n" - Config_accessC_str += f" Tile_X{NumberOfCols-1}Y{count}_Config_accessC_bit2 => Config_accessC({i-2}),""\n" - Config_accessC_str += f" Tile_X{NumberOfCols-1}Y{count}_Config_accessC_bit3 => Config_accessC({i-3}),""\n" + A_config_C_str += ( + f" Tile_X0Y{count}_A_config_C_bit0 => A_config_C({i})," "\n" + ) + A_config_C_str += ( + f" Tile_X0Y{count}_A_config_C_bit1 => A_config_C({i-1})," "\n" + ) + A_config_C_str += ( + f" Tile_X0Y{count}_A_config_C_bit2 => A_config_C({i-2})," "\n" + ) + A_config_C_str += ( + f" Tile_X0Y{count}_A_config_C_bit3 => A_config_C({i-3})," "\n" + ) + + B_config_C_str += ( + f" Tile_X0Y{count}_B_config_C_bit0 => B_config_C({i})," "\n" + ) + B_config_C_str += ( + f" Tile_X0Y{count}_B_config_C_bit1 => B_config_C({i-1})," "\n" + ) + B_config_C_str += ( + f" Tile_X0Y{count}_B_config_C_bit2 => B_config_C({i-2})," "\n" + ) + B_config_C_str += ( + f" Tile_X0Y{count}_B_config_C_bit3 => B_config_C({i-3})," "\n" + ) + + FAB2RAM_C_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_C_O0 => FAB2RAM_C({i})," "\n" + ) + FAB2RAM_C_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_C_O1 => FAB2RAM_C({i-1})," "\n" + ) + FAB2RAM_C_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_C_O2 => FAB2RAM_C({i-2})," "\n" + ) + FAB2RAM_C_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_C_O3 => FAB2RAM_C({i-3})," "\n" + ) + + Config_accessC_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_Config_accessC_bit0 => Config_accessC({i})," + "\n" + ) + Config_accessC_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_Config_accessC_bit1 => Config_accessC({i-1})," + "\n" + ) + Config_accessC_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_Config_accessC_bit2 => Config_accessC({i-2})," + "\n" + ) + Config_accessC_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_Config_accessC_bit3 => Config_accessC({i-3})," + "\n" + ) RAM2FAB_D_str = "" FAB2RAM_D_str = "" @@ -263,80 +352,196 @@ def main(): # RAM2FAB_D_str+='\t.Tile_X'+str(NumberOfCols-1)+'Y'+str(count)+'_RAM2FAB_D3_I3(RAM2FAB_D['+str(i-14)+']),\n' # count = 0 - for i in range(NumberOfRows*4*4-1, -1, -16): + for i in range(NumberOfRows * 4 * 4 - 1, -1, -16): count += 1 - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D0_I0 => RAM2FAB_D_Readable({i}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D0_I1 => RAM2FAB_D_Readable({i-1}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D0_I2 => RAM2FAB_D_Readable({i-2}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D0_I3 => RAM2FAB_D_Readable({i-3}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D1_I0 => RAM2FAB_D_Readable({i-4}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D1_I1 => RAM2FAB_D_Readable({i-5}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D1_I2 => RAM2FAB_D_Readable({i-6}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D1_I3 => RAM2FAB_D_Readable({i-7}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D2_I0 => RAM2FAB_D_Readable({i-8}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D2_I1 => RAM2FAB_D_Readable({i-9}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D2_I2 => RAM2FAB_D_Readable({i-10}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D2_I3 => RAM2FAB_D_Readable({i-11}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D3_I0 => RAM2FAB_D_Readable({i-12}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D3_I1 => RAM2FAB_D_Readable({i-13}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D3_I2 => RAM2FAB_D_Readable({i-14}),""\n" - RAM2FAB_D_str += f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D3_I3 => RAM2FAB_D_Readable({i-15}),""\n" - - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D0_O0 => FAB2RAM_D({i}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D0_O1 => FAB2RAM_D({i-1}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D0_O2 => FAB2RAM_D({i-2}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D0_O3 => FAB2RAM_D({i-3}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D1_O0 => FAB2RAM_D({i-4}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D1_O1 => FAB2RAM_D({i-5}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D1_O2 => FAB2RAM_D({i-6}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D1_O3 => FAB2RAM_D({i-7}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D2_O0 => FAB2RAM_D({i-8}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D2_O1 => FAB2RAM_D({i-9}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D2_O2 => FAB2RAM_D({i-10}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D2_O3 => FAB2RAM_D({i-11}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D3_O0 => FAB2RAM_D({i-12}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D3_O1 => FAB2RAM_D({i-13}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D3_O2 => FAB2RAM_D({i-14}),""\n" - FAB2RAM_D_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D3_O3 => FAB2RAM_D({i-15}),""\n" - + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D0_I0 => RAM2FAB_D_Readable({i})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D0_I1 => RAM2FAB_D_Readable({i-1})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D0_I2 => RAM2FAB_D_Readable({i-2})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D0_I3 => RAM2FAB_D_Readable({i-3})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D1_I0 => RAM2FAB_D_Readable({i-4})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D1_I1 => RAM2FAB_D_Readable({i-5})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D1_I2 => RAM2FAB_D_Readable({i-6})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D1_I3 => RAM2FAB_D_Readable({i-7})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D2_I0 => RAM2FAB_D_Readable({i-8})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D2_I1 => RAM2FAB_D_Readable({i-9})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D2_I2 => RAM2FAB_D_Readable({i-10})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D2_I3 => RAM2FAB_D_Readable({i-11})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D3_I0 => RAM2FAB_D_Readable({i-12})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D3_I1 => RAM2FAB_D_Readable({i-13})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D3_I2 => RAM2FAB_D_Readable({i-14})," + "\n" + ) + RAM2FAB_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_RAM2FAB_D3_I3 => RAM2FAB_D_Readable({i-15})," + "\n" + ) + + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D0_O0 => FAB2RAM_D({i})," "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D0_O1 => FAB2RAM_D({i-1})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D0_O2 => FAB2RAM_D({i-2})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D0_O3 => FAB2RAM_D({i-3})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D1_O0 => FAB2RAM_D({i-4})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D1_O1 => FAB2RAM_D({i-5})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D1_O2 => FAB2RAM_D({i-6})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D1_O3 => FAB2RAM_D({i-7})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D2_O0 => FAB2RAM_D({i-8})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D2_O1 => FAB2RAM_D({i-9})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D2_O2 => FAB2RAM_D({i-10})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D2_O3 => FAB2RAM_D({i-11})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D3_O0 => FAB2RAM_D({i-12})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D3_O1 => FAB2RAM_D({i-13})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D3_O2 => FAB2RAM_D({i-14})," + "\n" + ) + FAB2RAM_D_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_D3_O3 => FAB2RAM_D({i-15})," + "\n" + ) FAB2RAM_A_str = "" count = 0 - for i in range(NumberOfRows*4*2-1, -1, -8): + for i in range(NumberOfRows * 4 * 2 - 1, -1, -8): count += 1 - FAB2RAM_A_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A0_O0 => FAB2RAM_A({i}),""\n" - FAB2RAM_A_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A0_O1 => FAB2RAM_A({i-1}),""\n" - FAB2RAM_A_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A0_O2 => FAB2RAM_A({i-2}),""\n" - FAB2RAM_A_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A0_O3 => FAB2RAM_A({i-3}),""\n" - FAB2RAM_A_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A1_O0 => FAB2RAM_A({i-4}),""\n" - FAB2RAM_A_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A1_O1 => FAB2RAM_A({i-5}),""\n" - FAB2RAM_A_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A1_O2 => FAB2RAM_A({i-6}),""\n" - FAB2RAM_A_str += f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A1_O3 => FAB2RAM_A({i-7}),""\n" - - - wrapper_top_str += I_top_str+'\n' - wrapper_top_str += T_top_str+'\n' - wrapper_top_str += O_top_str+'\n' - wrapper_top_str += A_config_C_str+'\n' - wrapper_top_str += B_config_C_str+'\n' - - wrapper_top_str += RAM2FAB_D_str+'\n' - wrapper_top_str += FAB2RAM_D_str+'\n' - wrapper_top_str += FAB2RAM_A_str+'\n' - wrapper_top_str += FAB2RAM_C_str+'\n' - wrapper_top_str += Config_accessC_str+'\n' - - wrapper_top_str += ' --declarations\n' - wrapper_top_str += ' UserCLK => CLK ,\n' - wrapper_top_str += ' FrameData => FrameData,\n' - wrapper_top_str += ' FrameStrobe => FrameSelect \n' - wrapper_top_str += ' );\n' + FAB2RAM_A_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A0_O0 => FAB2RAM_A({i})," "\n" + ) + FAB2RAM_A_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A0_O1 => FAB2RAM_A({i-1})," + "\n" + ) + FAB2RAM_A_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A0_O2 => FAB2RAM_A({i-2})," + "\n" + ) + FAB2RAM_A_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A0_O3 => FAB2RAM_A({i-3})," + "\n" + ) + FAB2RAM_A_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A1_O0 => FAB2RAM_A({i-4})," + "\n" + ) + FAB2RAM_A_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A1_O1 => FAB2RAM_A({i-5})," + "\n" + ) + FAB2RAM_A_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A1_O2 => FAB2RAM_A({i-6})," + "\n" + ) + FAB2RAM_A_str += ( + f" Tile_X{NumberOfCols-1}Y{count}_FAB2RAM_A1_O3 => FAB2RAM_A({i-7})," + "\n" + ) + + wrapper_top_str += I_top_str + "\n" + wrapper_top_str += T_top_str + "\n" + wrapper_top_str += O_top_str + "\n" + wrapper_top_str += A_config_C_str + "\n" + wrapper_top_str += B_config_C_str + "\n" + + wrapper_top_str += RAM2FAB_D_str + "\n" + wrapper_top_str += FAB2RAM_D_str + "\n" + wrapper_top_str += FAB2RAM_A_str + "\n" + wrapper_top_str += FAB2RAM_C_str + "\n" + wrapper_top_str += Config_accessC_str + "\n" + + wrapper_top_str += " --declarations\n" + wrapper_top_str += " UserCLK => CLK ,\n" + wrapper_top_str += " FrameData => FrameData,\n" + wrapper_top_str += " FrameStrobe => FrameSelect \n" + wrapper_top_str += " );\n" BRAM_str = "" - data_cap = int((NumberOfRows*4*4)/NumberOfBRAMs) - addr_cap = int((NumberOfRows*4*2)/NumberOfBRAMs) - config_cap = int((NumberOfRows*4)/NumberOfBRAMs) + data_cap = int((NumberOfRows * 4 * 4) / NumberOfBRAMs) + addr_cap = int((NumberOfRows * 4 * 2) / NumberOfBRAMs) + config_cap = int((NumberOfRows * 4) / NumberOfBRAMs) # for i in range(NumberOfBRAMs): # BRAM_str += f" Inst_BlockRAM_{i}: BlockRAM_1KB""\n" @@ -357,12 +562,11 @@ def main(): # BRAM_str += f" C5 => FAB2RAM_C({config_cap*i+5})""\n" # BRAM_str += f" );""\n\n" - wrapper_top_str += BRAM_str # wrapper_top_str += "FrameData <= 16#12345678# & FrameRegister & 16#12345678#;\n\n" wrapper_top_str += 'FrameData <= X"12345678" & FrameRegister & X"12345678";' - wrapper_top_str += 'end Behavioral;\n\n' + wrapper_top_str += "end Behavioral;\n\n" # wrapper_top_str+='module sky130_fd_sc_hd__inv (\n' # wrapper_top_str+='\tY,\n' @@ -377,7 +581,7 @@ def main(): # wrapper_top_str+=strobe_reg_modules if wrapper_top_str: - with open(f"{output_dir}/eFPGA_top.vhdl", 'w') as file: + with open(f"{output_dir}/eFPGA_top.vhdl", "w") as file: file.write(wrapper_top_str) # if data_reg_modules: @@ -389,11 +593,11 @@ def main(): # file.write(strobe_reg_modules) if config_str: - with open(f"{output_dir}/Config.vhdl", 'w') as file: + with open(f"{output_dir}/Config.vhdl", "w") as file: file.write(config_str) if configfsm_str: - with open(f"{output_dir}/ConfigFSM.vhdl", 'w') as file: + with open(f"{output_dir}/ConfigFSM.vhdl", "w") as file: file.write(configfsm_str) # if testbench_str: @@ -408,28 +612,33 @@ def main(): if sys.version_info <= (3, 5, 0): print("Need Python 3.5 or above to run FABulous") exit(-1) - parser = argparse.ArgumentParser(description='') + parser = argparse.ArgumentParser(description="") parser.add_argument( - "-o", "--output_dir", help="The directory to the project folder") + "-o", "--output_dir", help="The directory to the project folder" + ) parser.add_argument( - "-r", "--NumberOfRows", help="The directory to the project folder") + "-r", "--NumberOfRows", help="The directory to the project folder" + ) parser.add_argument( - "-c", "--NumberOfCols", help="The directory to the project folder") + "-c", "--NumberOfCols", help="The directory to the project folder" + ) parser.add_argument( - "-b", "--FrameBitsPerRow", help="The directory to the project folder") + "-b", "--FrameBitsPerRow", help="The directory to the project folder" + ) parser.add_argument( - "-f", "--MaxFramesPerCol", help="The directory to the project folder") + "-f", "--MaxFramesPerCol", help="The directory to the project folder" + ) parser.add_argument( - "-d", "--desync_flag", help="The directory to the project folder") + "-d", "--desync_flag", help="The directory to the project folder" + ) - parser.add_argument( - "-m", "--block_ram", help="The directory to the project folder") + parser.add_argument("-m", "--block_ram", help="The directory to the project folder") args = parser.parse_args() @@ -456,7 +665,7 @@ def main(): main() -#argv = "/home/ise/shared_folder/diffeq1/LC_on/netgen/synthesis/diffeq_paj_convert_synthesis.v" +# argv = "/home/ise/shared_folder/diffeq1/LC_on/netgen/synthesis/diffeq_paj_convert_synthesis.v" # if words[i+1] == "critical":