diff --git a/fpga/.ci/fpga-pipeline-pr.yml b/fpga/.ci/fpga-pipeline-pr.yml
index 64278c66e2..a29402b028 100644
--- a/fpga/.ci/fpga-pipeline-pr.yml
+++ b/fpga/.ci/fpga-pipeline-pr.yml
@@ -142,6 +142,7 @@ pr:
     - fpga/.ci
     - host/utils/rfnoc_image_builder.py
     - host/python/uhd/rfnoc_utils
+    - host/include/uhd/rfnoc
 
 schedules:
 - cron: "0 18 * * Sun"
diff --git a/fpga/.ci/fpga-pipeline.yml b/fpga/.ci/fpga-pipeline.yml
index e13255d734..7136399983 100644
--- a/fpga/.ci/fpga-pipeline.yml
+++ b/fpga/.ci/fpga-pipeline.yml
@@ -77,6 +77,7 @@ trigger:
     - fpga/.ci
     - host/utils/rfnoc_image_builder.py
     - host/python/uhd/rfnoc_utils
+    - host/include/uhd/rfnoc
 
 pr: none
 
diff --git a/fpga/.ci/templates/changeset_build_list.yaml b/fpga/.ci/templates/changeset_build_list.yaml
index fab10c5c1a..d8ace21a9e 100644
--- a/fpga/.ci/templates/changeset_build_list.yaml
+++ b/fpga/.ci/templates/changeset_build_list.yaml
@@ -14,23 +14,54 @@
 - re: host/python/uhd/rfnoc_utils/[^/]+py$
   add:
     - fpga.usrp3.all
+# RFNoC blocks
+- re: host/include/uhd/rfnoc/blocks/.*\.yml
+  add:
+    - fpga.usrp3.all
+# RFNoC core (the device-specific BSP files are checked below)
+- re: host/include/uhd/rfnoc/core/rfnoc_imagebuilder_args\.json
+  add:
+    - fpga.usrp3.all
+# RFNoC modules
+- re: host/include/uhd/rfnoc/modules/.*\.yml
+  add:
+    - fpga.usrp3.all
+# RFNoC transport adapters (only relevant for x4xx)
+- re: host/include/uhd/rfnoc/transport_adapters/.*\.yml
+  add:
+    - fpga.usrp3.x4xx
 
 # Device-specific changes.
 - re: fpga/usrp3/top/x400
   add:
     - fpga.usrp3.x4xx
+- re: host/include/uhd/rfnoc/core/x4.._bsp.yml
+  add:
+    - fpga.usrp3.x4xx
 - re: fpga/usrp3/top/x300
   add:
     - fpga.usrp3.x3xx
+- re: host/include/uhd/rfnoc/core/x3.._bsp.yml
+  add:
+    - fpga.usrp3.x3xx
 - re: fpga/usrp3/top/e31x
   add:
     - fpga.usrp3.e31x
+- re: host/include/uhd/rfnoc/core/e310_bsp.yml
+  add:
+    - fpga.usrp3.e31x
 - re: fpga/usrp3/top/e320
   add:
     - fpga.usrp3.e320
+- re: host/include/uhd/rfnoc/core/e320_bsp.yml
+  add:
+    - fpga.usrp3.e320
 - re: fpga/usrp3/top/n3xx
   add:
     - fpga.usrp3.n3xx
+- re: host/include/uhd/rfnoc/core/n3.._bsp.yml
+  add:
+    - fpga.usrp3.n3xx
 
 ###############################################################################
 # CI CHANGES