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controller.c
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controller.c
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/*
* MemTest86+ V5 Specific code (GPL V2.0)
* By Samuel DEMEULEMEESTER, [email protected]
* http://www.canardpc.com - http://www.memtest.org
*/
//#include "defs.h"
#include "config.h"
//#include "test.h"
#include "pci.h"
#include "controller.h"
#include "spd.h"
#include "test.h"
#include "stdint.h"
#include "cpuid.h"
#include "msr.h"
#include "dmi.h"
int col, col2;
int nhm_bus = 0x3F;
extern ulong extclock;
extern unsigned long imc_type;
extern struct cpu_ident cpu_id;
/*
#define rdmsr(msr,val1,val2) \
__asm__ __volatile__("rdmsr" \
: "=a" (val1), "=d" (val2) \
: "c" (msr) : "edi")
#define wrmsr(msr,val1,val2) \
__asm__ __volatile__("wrmsr" \
: \
: "c" (msr), "a" (val1), "d" (val2) : "edi")
*/
/* controller ECC capabilities and mode */
#define __ECC_UNEXPECTED 1 /* Unknown ECC capability present */
#define __ECC_DETECT 2 /* Can detect ECC errors */
#define __ECC_CORRECT 4 /* Can correct some ECC errors */
#define __ECC_SCRUB 8 /* Can scrub corrected ECC errors */
#define __ECC_CHIPKILL 16 /* Can corrected multi-errors */
#define ECC_UNKNOWN (~0UL) /* Unknown error correcting ability/status */
#define ECC_NONE 0 /* Doesnt support ECC (or is BIOS disabled) */
#define ECC_RESERVED __ECC_UNEXPECTED /* Reserved ECC type */
#define ECC_DETECT __ECC_DETECT
#define ECC_CORRECT (__ECC_DETECT | __ECC_CORRECT)
#define ECC_CHIPKILL (__ECC_DETECT | __ECC_CORRECT | __ECC_CHIPKILL)
#define ECC_SCRUB (__ECC_DETECT | __ECC_CORRECT | __ECC_SCRUB)
static struct ecc_info {
int index;
int poll;
unsigned bus;
unsigned dev;
unsigned fn;
unsigned cap;
unsigned mode;
} ctrl =
{
.index = 0,
/* I know of no case where the memory controller is not on the
* host bridge, and the host bridge is not on bus 0 device 0
* fn 0. But just in case leave these as variables.
*/
.bus = 0,
.dev = 0,
.fn = 0,
/* Properties of the current memory controller */
.cap = ECC_UNKNOWN,
.mode = ECC_UNKNOWN,
};
void coretemp(void)
{
unsigned int msrl, msrh;
unsigned int tjunc, tabs, tnow;
unsigned long rtcr;
double amd_raw_temp;
// Only enable coretemp if IMC is known
if(imc_type == 0) { return; }
tnow = 0;
// Intel CPU
if(cpu_id.vend_id.char_array[0] == 'G' && cpu_id.max_cpuid >= 6)
{
if(cpu_id.dts_pmp & 1){
rdmsr(MSR_IA32_THERM_STATUS, msrl, msrh);
tabs = ((msrl >> 16) & 0x7F);
rdmsr(MSR_IA32_TEMPERATURE_TARGET, msrl, msrh);
tjunc = ((msrl >> 16) & 0x7F);
if(tjunc < 50 || tjunc > 125) { tjunc = 90; } // assume Tjunc = 90°C if boggus value received.
tnow = tjunc - tabs;
dprint(LINE_CPU+1, 30, v->check_temp, 3, 0);
v->check_temp = tnow;
}
return;
}
// AMD CPU
if(cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.extendedFamily > 0)
{
pci_conf_read(0, 24, 3, 0xA4, 4, &rtcr);
amd_raw_temp = ((rtcr >> 21) & 0x7FF);
v->check_temp = (int)(amd_raw_temp / 8);
dprint(LINE_CPU+1, 30, v->check_temp, 3, 0);
}
}
void print_cpu_line(float dram_freq, float fsb_freq, int ram_type)
{
int cur_col = COL_SPEC;
cprint(LINE_CPU, cur_col, "RAM: ");
cur_col += 5;
dprint(LINE_CPU, cur_col, dram_freq, 4, 1);
cur_col += 4;
cprint(LINE_CPU, cur_col, "MHz (");
cur_col += 5;
switch(ram_type)
{
default:
case 1:
cprint(LINE_CPU, cur_col, "DDR-");
cur_col += 4;
break;
case 2:
cprint(LINE_CPU, cur_col, "DDR2-");
cur_col += 5;
break;
case 3:
cprint(LINE_CPU, cur_col, "DDR3-");
cur_col += 5;
break;
}
if(dram_freq < 500)
{
dprint(LINE_CPU, cur_col, dram_freq*2, 3, 0);
cur_col += 3;
} else {
dprint(LINE_CPU, cur_col, dram_freq*2, 4, 0);
cur_col += 4;
}
cprint(LINE_CPU, cur_col, ")");
cur_col++;
if(fsb_freq > 10)
{
cprint(LINE_CPU, cur_col, " - BCLK: ");
cur_col += 9;
dprint(LINE_CPU, cur_col, fsb_freq, 3, 0);
}
}
void print_ram_line(float cas, int rcd, int rp, int ras, int chan)
{
int cur_col = COL_SPEC;
cprint(LINE_RAM, cur_col, "Timings: CAS ");
cur_col += 13;
// CAS Latency (tCAS)
if (cas == 1.5) {
cprint(LINE_RAM, cur_col, "1.5"); cur_col += 3;
} else if (cas == 2.5) {
cprint(LINE_RAM, cur_col, "2.5"); cur_col += 3;
} else if (cas < 10) {
dprint(LINE_RAM, cur_col, cas, 1, 0); cur_col += 1;
} else {
dprint(LINE_RAM, cur_col, cas, 2, 0); cur_col += 2;
}
cprint(LINE_RAM, cur_col, "-"); cur_col += 1;
// RAS-To-CAS (tRCD)
if (rcd < 10) {
dprint(LINE_RAM, cur_col, rcd, 1, 0);
cur_col += 1;
} else {
dprint(LINE_RAM, cur_col, rcd, 2, 0);
cur_col += 2;
}
cprint(LINE_RAM, cur_col, "-"); cur_col += 1;
// RAS Precharge (tRP)
if (rp < 10) {
dprint(LINE_RAM, cur_col, rp, 1, 0);
cur_col += 1;
} else {
dprint(LINE_RAM, cur_col, rp, 2, 0);
cur_col += 2;
}
cprint(LINE_RAM, cur_col, "-"); cur_col += 1;
// RAS Active to precharge (tRAS)
if (ras < 10) {
dprint(LINE_RAM, cur_col, ras, 1, 0);
cur_col += 1;
} else {
dprint(LINE_RAM, cur_col, ras, 2, 0);
cur_col += 2;
}
switch(chan)
{
case 0:
break;
case 1:
cprint(LINE_RAM, cur_col, " @ 64-bit Mode");
break;
case 2:
cprint(LINE_RAM, cur_col, " @ 128-bit Mode");
break;
case 3:
cprint(LINE_RAM, cur_col, " @ 192-bit Mode");
break;
case 4:
cprint(LINE_RAM, cur_col, " @ 256-bit Mode");
break;
}
}
static void poll_fsb_nothing(void)
{
char *name;
/* Print the controller name */
name = controllers[ctrl.index].name;
cprint(LINE_CPU, COL_SPEC, "Chipset: ");
cprint(LINE_CPU, COL_SPEC+9, name);
return;
}
static void poll_timings_nothing(void)
{
char *ram_type;
/* Print the controller name */
ram_type = controllers[ctrl.index].ram_type;
cprint(LINE_RAM, COL_SPEC, "RAM Type: ");
cprint(LINE_RAM, COL_SPEC+10, ram_type);
return;
}
static void setup_nothing(void)
{
ctrl.cap = ECC_NONE;
ctrl.mode = ECC_NONE;
}
static void poll_nothing(void)
{
/* Code to run when we don't know how, or can't ask the memory
* controller about memory errors.
*/
return;
}
static void setup_wmr(void)
{
ulong dev0;
// Activate MMR I/O
pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
if (!(dev0 & 0x1)) {
pci_conf_write( 0, 0, 0, 0x48, 1, dev0 | 1);
}
}
static void setup_nhm(void)
{
static float possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid, mc_control, mc_ssrcontrol;
int i;
//Nehalem supports Scrubbing */
ctrl.cap = ECC_SCRUB;
ctrl.mode = ECC_NONE;
/* First, locate the PCI bus where the MCH is located */
for(i = 0; i < sizeof(possible_nhm_bus); i++) {
pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid);
pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00) {
nhm_bus = possible_nhm_bus[i];
}
}
/* Now, we have the last IMC bus number in nhm_bus */
/* Check for ECC & Scrub */
pci_conf_read(nhm_bus, 3, 0, 0x4C, 2, &mc_control);
if((mc_control >> 4) & 1) {
ctrl.mode = ECC_CORRECT;
pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);
if(mc_ssrcontrol & 3) {
ctrl.mode = ECC_SCRUB;
}
}
}
static void setup_nhm32(void)
{
static float possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid, mc_control, mc_ssrcontrol;
int i;
//Nehalem supports Scrubbing */
ctrl.cap = ECC_SCRUB;
ctrl.mode = ECC_NONE;
/* First, locate the PCI bus where the MCH is located */
for(i = 0; i < sizeof(possible_nhm_bus); i++) {
pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid);
pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00) {
nhm_bus = possible_nhm_bus[i];
}
}
/* Now, we have the last IMC bus number in nhm_bus */
/* Check for ECC & Scrub */
pci_conf_read(nhm_bus, 3, 0, 0x48, 2, &mc_control);
if((mc_control >> 1) & 1) {
ctrl.mode = ECC_CORRECT;
pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);
if(mc_ssrcontrol & 1) {
ctrl.mode = ECC_SCRUB;
}
}
}
static void setup_amd64(void)
{
static const int ddim[] = { ECC_NONE, ECC_CORRECT, ECC_RESERVED, ECC_CHIPKILL };
unsigned long nbxcfg;
unsigned int mcgsrl;
unsigned int mcgsth;
unsigned long mcanb;
unsigned long dramcl;
/* All AMD64 support Chipkill */
ctrl.cap = ECC_CHIPKILL;
/* Check First if ECC DRAM Modules are used */
pci_conf_read(0, 24, 2, 0x90, 4, &dramcl);
if (cpu_id.vers.bits.extendedModel >= 4) {
/* NEW K8 0Fh Family 90 nm */
if ((dramcl >> 19)&1){
/* Fill in the correct memory capabilites */
pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
ctrl.mode = ddim[(nbxcfg >> 22)&3];
} else {
ctrl.mode = ECC_NONE;
}
/* Enable NB ECC Logging by MSR Write */
rdmsr(0x017B, mcgsrl, mcgsth);
wrmsr(0x017B, 0x10, mcgsth);
/* Clear any previous error */
pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
} else {
/* OLD K8 130 nm */
if ((dramcl >> 17)&1){
/* Fill in the correct memory capabilites */
pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
ctrl.mode = ddim[(nbxcfg >> 22)&3];
} else {
ctrl.mode = ECC_NONE;
}
/* Enable NB ECC Logging by MSR Write */
rdmsr(0x017B, mcgsrl, mcgsth);
wrmsr(0x017B, 0x10, mcgsth);
/* Clear any previous error */
pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7F801EFC );
}
}
static void setup_k10(void)
{
static const int ddim[] = { ECC_NONE, ECC_CORRECT, ECC_CHIPKILL, ECC_CHIPKILL };
unsigned long nbxcfg;
unsigned int mcgsrl;
unsigned int mcgsth;
unsigned long mcanb;
unsigned long dramcl;
ulong msr_low, msr_high;
// All AMD64 support Chipkill */
ctrl.cap = ECC_CHIPKILL;
// Check First if ECC DRAM Modules are used */
pci_conf_read(0, 24, 2, 0x90, 4, &dramcl);
if ((dramcl >> 19)&1){
// Fill in the correct memory capabilites */
pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
ctrl.mode = ddim[(nbxcfg >> 22)&3];
} else {
ctrl.mode = ECC_NONE;
}
// Enable NB ECC Logging by MSR Write */
rdmsr(0x017B, mcgsrl, mcgsth);
wrmsr(0x017B, 0x10, mcgsth);
// Clear any previous error */
pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
/* Enable ECS */
rdmsr(0xC001001F, msr_low, msr_high);
wrmsr(0xC001001F, msr_low, (msr_high | 0x4000));
rdmsr(0xC001001F, msr_low, msr_high);
}
static void setup_apu(void)
{
ulong msr_low, msr_high;
/* Enable ECS */
rdmsr(0xC001001F, msr_low, msr_high);
wrmsr(0xC001001F, msr_low, (msr_high | 0x4000));
rdmsr(0xC001001F, msr_low, msr_high);
}
/*
static void poll_amd64(void)
{
unsigned long mcanb;
unsigned long page, offset;
unsigned long celog_syndrome;
unsigned long mcanb_add;
pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
if (((mcanb >> 31)&1) && ((mcanb >> 14)&1)) {
// Find out about the first correctable error
// Syndrome code -> bits use a complex matrix. Will add this later
// Read the error location
pci_conf_read(0, 24, 3, 0x50, 4, &mcanb_add);
// Read the syndrome
celog_syndrome = (mcanb >> 15)&0xFF;
// Parse the error location
page = (mcanb_add >> 12);
offset = (mcanb_add >> 3) & 0xFFF;
// Report the error
print_ecc_err(page, offset, 1, celog_syndrome, 0);
// Clear the error registers
pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
}
if (((mcanb >> 31)&1) && ((mcanb >> 13)&1)) {
// Found out about the first uncorrectable error
// Read the error location
pci_conf_read(0, 24, 3, 0x50, 4, &mcanb_add);
// Parse the error location
page = (mcanb_add >> 12);
offset = (mcanb_add >> 3) & 0xFFF;
// Report the error
print_ecc_err(page, offset, 0, 0, 0);
// Clear the error registers
pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFF );
}
}
*/
static void setup_amd751(void)
{
unsigned long dram_status;
/* Fill in the correct memory capabilites */
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5a, 2, &dram_status);
ctrl.cap = ECC_CORRECT;
ctrl.mode = (dram_status & (1 << 2))?ECC_CORRECT: ECC_NONE;
}
/*
static void poll_amd751(void)
{
unsigned long ecc_status;
unsigned long bank_addr;
unsigned long bank_info;
unsigned long page;
int bits;
int i;
// Read the error status
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 2, &ecc_status);
if (ecc_status & (3 << 8)) {
for(i = 0; i < 6; i++) {
if (!(ecc_status & (1 << i))) {
continue;
}
// Find the bank the error occured on
bank_addr = 0x40 + (i << 1);
// Now get the information on the erroring bank
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, bank_addr, 2, &bank_info);
// Parse the error location and error type
page = (bank_info & 0xFF80) << 4;
bits = (((ecc_status >> 8) &3) == 2)?1:2;
// Report the error
print_ecc_err(page, 0, bits==1?1:0, 0, 0);
}
// Clear the error status
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 2, 0);
}
}
// Still waiting for the CORRECT intel datasheet
static void setup_i85x(void)
{
unsigned long drc;
ctrl.cap = ECC_CORRECT;
pci_conf_read(ctrl.bus, ctrl.dev, 1, 0x70, 4, &drc);
ctrl.mode = ((drc>>20)&1)?ECC_CORRECT:ECC_NONE;
}
*/
static void setup_amd76x(void)
{
static const int ddim[] = { ECC_NONE, ECC_DETECT, ECC_CORRECT, ECC_CORRECT };
unsigned long ecc_mode_status;
/* Fill in the correct memory capabilites */
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x48, 4, &ecc_mode_status);
ctrl.cap = ECC_CORRECT;
ctrl.mode = ddim[(ecc_mode_status >> 10)&3];
}
/*
static void poll_amd76x(void)
{
unsigned long ecc_mode_status;
unsigned long bank_addr;
unsigned long bank_info;
unsigned long page;
// Read the error status
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x48, 4, &ecc_mode_status);
// Multibit error
if (ecc_mode_status & (1 << 9)) {
// Find the bank the error occured on
bank_addr = 0xC0 + (((ecc_mode_status >> 4) & 0xf) << 2);
// Now get the information on the erroring bank
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, bank_addr, 4, &bank_info);
// Parse the error location and error type
page = (bank_info & 0xFF800000) >> 12;
// Report the error
print_ecc_err(page, 0, 1, 0, 0);
}
// Singlebit error
if (ecc_mode_status & (1 << 8)) {
// Find the bank the error occured on
bank_addr = 0xC0 + (((ecc_mode_status >> 0) & 0xf) << 2);
// Now get the information on the erroring bank
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, bank_addr, 4, &bank_info);
// Parse the error location and error type
page = (bank_info & 0xFF800000) >> 12;
// Report the error
print_ecc_err(page, 0, 0, 0, 0);
}
// Clear the error status
if (ecc_mode_status & (3 << 8)) {
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x48, 4, ecc_mode_status);
}
}
*/
static void setup_cnb20(void)
{
/* Fill in the correct memory capabilites */
ctrl.cap = ECC_CORRECT;
/* FIXME add ECC error polling. I don't have the documentation
* do it right now.
*/
}
static void setup_E5400(void)
{
unsigned long mcs;
/* Read the hardware capabilities */
pci_conf_read(ctrl.bus, 16, 1, 0x40, 4, &mcs);
/* Fill in the correct memory capabilities */
ctrl.mode = 0;
ctrl.cap = ECC_SCRUB;
/* Checking and correcting enabled */
if (((mcs >> 5) & 1) == 1) {
ctrl.mode |= ECC_CORRECT;
}
/* scrub enabled */
if (((mcs >> 7) & 1) == 1) {
ctrl.mode |= __ECC_SCRUB;
}
}
static void setup_iE7xxx(void)
{
unsigned long mchcfgns;
unsigned long drc;
unsigned long device;
unsigned long dvnp;
/* Read the hardare capabilities */
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x52, 2, &mchcfgns);
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x7C, 4, &drc);
/* This is a check for E7205 */
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x02, 2, &device);
/* Fill in the correct memory capabilities */
ctrl.mode = 0;
ctrl.cap = ECC_CORRECT;
/* checking and correcting enabled */
if (((drc >> 20) & 3) == 2) {
ctrl.mode |= ECC_CORRECT;
}
/* E7205 doesn't support scrubbing */
if (device != 0x255d) {
/* scrub enabled */
/* For E7501, valid SCRUB operations is bit 0 / D0:F0:R70-73 */
ctrl.cap = ECC_SCRUB;
if (mchcfgns & 1) {
ctrl.mode |= __ECC_SCRUB;
}
/* Now, we can active Dev1/Fun1 */
/* Thanks to Tyan for providing us the board to solve this */
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE0, 2, &dvnp);
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn , 0xE0, 2, (dvnp & 0xFE));
/* Clear any routing of ECC errors to interrupts that the BIOS might have set up */
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x88, 1, 0x0);
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x8A, 1, 0x0);
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x8C, 1, 0x0);
}
/* Clear any prexisting error reports */
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 1, 3);
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 1, 3);
}
static void setup_iE7520(void)
{
unsigned long mchscrb;
unsigned long drc;
unsigned long dvnp1;
/* Read the hardare capabilities */
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x52, 2, &mchscrb);
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x7C, 4, &drc);
/* Fill in the correct memory capabilities */
ctrl.mode = 0;
ctrl.cap = ECC_CORRECT;
/* Checking and correcting enabled */
if (((drc >> 20) & 3) != 0) {
ctrl.mode |= ECC_CORRECT;
}
/* scrub enabled */
ctrl.cap = ECC_SCRUB;
if ((mchscrb & 3) == 2) {
ctrl.mode |= __ECC_SCRUB;
}
/* Now, we can activate Fun1 */
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xF4, 1, &dvnp1);
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn , 0xF4, 1, (dvnp1 | 0x20));
/* Clear any prexisting error reports */
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 2, 0x4747);
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 2, 0x4747);
}
/*
static void poll_iE7xxx(void)
{
unsigned long ferr;
unsigned long nerr;
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 1, &ferr);
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 1, &nerr);
if (ferr & 1) {
// Find out about the first correctable error
unsigned long celog_add;
unsigned long celog_syndrome;
unsigned long page;
// Read the error location
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xA0, 4, &celog_add);
// Read the syndrome
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xD0, 2, &celog_syndrome);
// Parse the error location
page = (celog_add & 0x0FFFFFC0) >> 6;
// Report the error
print_ecc_err(page, 0, 1, celog_syndrome, 0);
// Clear Bit
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 1, ferr & 3);
}
if (ferr & 2) {
// Found out about the first uncorrectable error
unsigned long uccelog_add;
unsigned long page;
// Read the error location
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xB0, 4, &uccelog_add);
// Parse the error location
page = (uccelog_add & 0x0FFFFFC0) >> 6;
// Report the error
print_ecc_err(page, 0, 0, 0, 0);
// Clear Bit
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 1, ferr & 3);
}
// Check if DRAM_NERR contains data
if (nerr & 3) {
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 1, nerr & 3);
}
}
*/
static void setup_i440gx(void)
{
static const int ddim[] = { ECC_NONE, ECC_DETECT, ECC_CORRECT, ECC_CORRECT };
unsigned long nbxcfg;
/* Fill in the correct memory capabilites */
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 4, &nbxcfg);
ctrl.cap = ECC_CORRECT;
ctrl.mode = ddim[(nbxcfg >> 7)&3];
}
/*
static void poll_i440gx(void)
{
unsigned long errsts;
unsigned long page;
int bits;
// Read the error status
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x91, 2, &errsts);
if (errsts & 0x11) {
unsigned long eap;
// Read the error location
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x80, 4, &eap);
// Parse the error location and error type
page = (eap & 0xFFFFF000) >> 12;
bits = 0;
if (eap &3) {
bits = ((eap & 3) == 1)?1:2;
}
if (bits) {
// Report the error
print_ecc_err(page, 0, bits==1?1:0, 0, 0);
}
// Clear the error status
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x91, 2, 0x11);
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x80, 4, 3);
}
}
*/
static void setup_i840(void)
{
static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_CORRECT };
unsigned long mchcfg;
/* Fill in the correct memory capabilites */
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 2, &mchcfg);
ctrl.cap = ECC_CORRECT;
ctrl.mode = ddim[(mchcfg >> 7)&3];
}
/*
static void poll_i840(void)
{
unsigned long errsts;
unsigned long page;
unsigned long syndrome;
int channel;
int bits;
// Read the error status
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts);
if (errsts & 3) {
unsigned long eap;
unsigned long derrctl_sts;
// Read the error location
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE4, 4, &eap);
pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, &derrctl_sts);
// Parse the error location and error type
page = (eap & 0xFFFFF800) >> 11;
channel = eap & 1;
syndrome = derrctl_sts & 0xFF;
bits = ((errsts & 3) == 1)?1:2;
// Report the error
print_ecc_err(page, 0, bits==1?1:0, syndrome, channel);
// Clear the error status
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, 3 << 10);
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 3);
}
}
*/
static void setup_i875(void)
{
long *ptr;
ulong dev0, dev6 ;
/* Fill in the correct memory capabilites */
ctrl.cap = ECC_CORRECT;
ctrl.mode = ECC_NONE;
/* From my article : http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm */
/* Activate Device 6 */
pci_conf_read( 0, 0, 0, 0xF4, 1, &dev0);
pci_conf_write( 0, 0, 0, 0xF4, 1, (dev0 | 0x2));
/* Activate Device 6 MMR */
pci_conf_read( 0, 6, 0, 0x04, 2, &dev6);
pci_conf_write( 0, 6, 0, 0x04, 2, (dev6 | 0x2));
/* Read the MMR Base Address & Define the pointer*/
pci_conf_read( 0, 6, 0, 0x10, 4, &dev6);
ptr=(long*)(dev6+0x68);
if (((*ptr >> 18)&1) == 1) { ctrl.mode = ECC_CORRECT; }
/* Reseting state */
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 0x81);
}
static void setup_i925(void)
{
// Activate MMR I/O
ulong dev0, drc;
unsigned long tolm;
long *ptr;
pci_conf_read( 0, 0, 0, 0x54, 4, &dev0);
dev0 = dev0 | 0x10000000;
pci_conf_write( 0, 0, 0, 0x54, 4, dev0);
// CDH start
pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
if (!(dev0 & 0xFFFFC000)) {
pci_conf_read( 0, 0, 0, 0x9C, 1, &tolm);
pci_conf_write( 0, 0, 0, 0x47, 1, tolm & 0xF8);
}
// CDH end
// ECC Checking
ctrl.cap = ECC_CORRECT;
dev0 &= 0xFFFFC000;
ptr=(long*)(dev0+0x120);
drc = *ptr & 0xFFFFFFFF;
if (((drc >> 20) & 3) == 2) {
pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 3);
ctrl.mode = ECC_CORRECT;
} else {
ctrl.mode = ECC_NONE;
}
}
static void setup_p35(void)
{
// Activate MMR I/O
ulong dev0, capid0;
pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
if (!(dev0 & 0x1)) {
pci_conf_write( 0, 0, 0, 0x48, 1, dev0 | 1);
}
// ECC Checking (No poll on X38/48 for now)
pci_conf_read( 0, 0, 0, 0xE4, 4, &capid0);
if ((capid0 >> 8) & 1) {
ctrl.cap = ECC_NONE;
} else {
ctrl.cap = ECC_CORRECT;
}
ctrl.mode = ECC_NONE;
/*
ulong toto;
pci_conf_write(0, 31, 3, 0x40, 1, 0x1);
pci_conf_read(0, 31, 3, 0x0, 4, &toto);
hprint(11,0,toto);
pci_conf_read(0, 31, 3, 0x10, 4, &toto);
hprint(11,10,toto) ;
pci_conf_read(0, 31, 3, 0x20, 4, &toto);
hprint(11,20,toto) ;
pci_conf_read(0, 28, 0, 0x0, 4, &toto);
hprint(11,30,toto);
pci_conf_read(0, 31, 0, 0x0, 4, &toto);
hprint(11,40,toto) ;
pci_conf_read(0, 31, 1, 0x0, 4, &toto);
hprint(11,50,toto) ;
pci_conf_read(0, 31, 2, 0x0, 4, &toto);
hprint(11,60,toto) ;
*/
}
/*
static void poll_i875(void)
{
unsigned long errsts;