README.md

SystemVerilog Simulation

A simple SystemVerilog simulation tool written in rust

This project is in a very early state

Project Scope

• Provide an incomplete, slightly broken SystemVerilog parser
• Provide a simple SystemVerilog parser
• Provide simple analysis tools
• Allow design verification for simple projects

Repository Contents

• src: source files
• sv: example SystemVerilog files for testing

Installation

sv-sim uses cargo for package management. If you wish to generate documentation with styling, generate_docs.sh is provided. In order to apply styling, git submodules must be initialized.

# Clone repo
git clone https://github.com/DMoore12/sv-sim.git

# Initialize submodules
cd ./sv-sim
git submodule init

# Run test file
cargo run -- ./sv/cu_top.sv none

# Generate documentation
sudo chmod +x generate_docs.sh
./generate_docs.sh

Usage

sv-sim uses clap for argument parsing. Use cargo run -- --help or sv-sim[EXE] --help to view input arguments and parameters

Arguments

• log_level
  • Log level for output. Defaults to error
• verbose
  • Gives additional build information in output