diff --git a/dependencies/opensbi/fw_payload.txt b/dependencies/opensbi/fw_payload.txt
deleted file mode 100644
index e69de29..0000000
diff --git a/src/cpu.rs b/src/cpu.rs
index bf9fdf9..2b4edf3 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -1012,9 +1012,15 @@ impl Cpu {
     }
     // 2. Decode.
     let opcode = inst & 0x0000007f;
-    let rd = self.inst.rd as u64;
-    let rs1 = self.inst.rs1 as u64;
-    let rs2 = self.inst.rs2 as u64;
+    // let rd = self.inst.rd as u64;
+    // let rs1 = self.inst.rs1 as u64;
+    // let rs2 = self.inst.rs2 as u64;
+    let rd = (inst & 0x00000f80) >> 7;
+    let rs1 = (inst & 0x000f8000) >> 15;
+    let rs2 = (inst & 0x01f00000) >> 20;
+    // assert_eq!(rd, self.inst.rd as u64);
+    // assert_eq!(rs1, self.inst.rs1 as u64);
+    // assert_eq!(rs2, self.inst.rs2 as u64);
     let funct3 = (inst & 0x00007000) >> 12;
     let funct7 = (inst & 0xfe000000) >> 25;
 
diff --git a/src/instructions.rs b/src/instructions.rs
index 2c4c66e..90ac453 100644
--- a/src/instructions.rs
+++ b/src/instructions.rs
@@ -1,7 +1,9 @@
 mod rv64i;
 mod rv64m;
+mod rv64a;
 use rv64i::rv64i;
 use rv64m::rv64m;
+use rv64a::rv64a;
 
 #[derive(Copy, Clone, Debug)]
 pub enum Instruction {
@@ -54,6 +56,32 @@ pub enum RegisterType {
   DIVUW,
   REMW,
   REMUW,
+
+  // RV32A
+  LR_W,
+  SC_W,
+  AMOSWAP_W,
+  AMOADD_W,
+  AMOXOR_W,
+  AMOAND_W,
+  AMOOR_W,
+  AMOMIN_W,
+  AMOMAX_W,
+  AMONINU_W,
+  AMOMAXU_W,
+
+  // RV64A
+  LR_D,
+  SC_D,
+  AMOSWAP_D,
+  AMOADD_D,
+  AMOXOR_D,
+  AMOAND_D,
+  AMOOR_D,
+  AMOMIN_D,
+  AMOMAX_D,
+  AMOMINU_D,
+  AMOMAXU_D,
 }
 
 #[allow(non_camel_case_types)]
@@ -170,6 +198,7 @@ impl Inst {
     let mut ipt :Vec<InstPattern>= vec![];
     ipt.extend(rv64i());
     ipt.extend(rv64m());
+    ipt.extend(rv64a());
 
     // self
     Inst {
@@ -265,97 +294,3 @@ impl InstPattern {
     InstPattern { name, pattern, itype }
   }
 }
-
-#[rustfmt::skip]
-pub fn new_ipt() -> Vec<InstPattern> {
-    vec![
-  // RegisterType
-  // rv32I 
-  InstPattern::new("add", "0000000 ????? ????? 000 ????? 01100 11", Instruction::Register(RegisterType::ADD)),
-  InstPattern::new("sub", "0100000 ????? ????? 000 ????? 01100 11", Instruction::Register(RegisterType::SUB)),
-  InstPattern::new("xor", "0000000 ????? ????? 100 ????? 01100 11", Instruction::Register(RegisterType::XOR)),
-  InstPattern::new("or", "0000000 ????? ????? 110 ????? 01100 11", Instruction::Register(RegisterType::OR)),
-  InstPattern::new("and", "0000000 ????? ????? 111 ????? 01100 11", Instruction::Register(RegisterType::AND)),
-  InstPattern::new("sll", "0000000 ????? ????? 001 ????? 01100 11", Instruction::Register(RegisterType::SLL)),
-  InstPattern::new("srl", "0000000 ????? ????? 101 ????? 01100 11", Instruction::Register(RegisterType::SRL)),
-  InstPattern::new("sra", "0100000 ????? ????? 101 ????? 01100 11", Instruction::Register(RegisterType::SRA)),
-  InstPattern::new("slt", "0000000 ????? ????? 010 ????? 01100 11", Instruction::Register(RegisterType::SLT)),
-  InstPattern::new("sltu", "0000000 ????? ????? 011 ????? 01100 11", Instruction::Register(RegisterType::SLTU)),
-  // rv32M
-  InstPattern::new("mul", "0000001 ????? ????? 000 ????? 01100 11", Instruction::Register(RegisterType::MUL)),
-  InstPattern::new("mulh", "0000001 ????? ????? 001 ????? 01100 11", Instruction::Register(RegisterType::MULH)),
-  InstPattern::new("mulhsu", "0000001 ????? ????? 010 ????? 01100 11", Instruction::Register(RegisterType::MULHSU)),
-  InstPattern::new("mulhu", "0000001 ????? ????? 011 ????? 01100 11", Instruction::Register(RegisterType::MULHU)),
-  InstPattern::new("div", "0000001 ????? ????? 100 ????? 01100 11", Instruction::Register(RegisterType::DIV)),
-  InstPattern::new("divu", "0000001 ????? ????? 101 ????? 01100 11", Instruction::Register(RegisterType::DIVU)),
-  InstPattern::new("rem", "0000001 ????? ????? 110 ????? 01100 11", Instruction::Register(RegisterType::REM)),
-  InstPattern::new("remu", "0000001 ????? ????? 111 ????? 01100 11", Instruction::Register(RegisterType::REMU)),
-  // rv64I
-  // rv64M
-  InstPattern::new("mulw", "0000001 ????? ????? 000 ????? 01110 11", Instruction::Register(RegisterType::MULW)),
-  InstPattern::new("divw", "0000001 ????? ????? 100 ????? 01110 11", Instruction::Register(RegisterType::DIVW)),
-  InstPattern::new("divuw", "0000001 ????? ????? 100 ????? 01110 11", Instruction::Register(RegisterType::DIVUW)),
-  InstPattern::new("remw", "0000001 ????? ????? 110 ????? 01110 11", Instruction::Register(RegisterType::REMW)),
-  InstPattern::new("remuw", "0000001 ????? ????? 110 ????? 01110 11", Instruction::Register(RegisterType::REMUW)),
-
-  // Immediate
-  // rv32I
-  InstPattern::new("addi", "??????? ????? ????? 000 ????? 00100 11", Instruction::Immediate(ImmediateType::ADDI)),
-  InstPattern::new("xori", "??????? ????? ????? 100 ????? 00100 11", Instruction::Immediate(ImmediateType::XORI)),
-  InstPattern::new("ori", "??????? ????? ????? 110 ????? 00100 11", Instruction::Immediate(ImmediateType::ORI)),
-  InstPattern::new("andi", "??????? ????? ????? 111 ????? 00100 11", Instruction::Immediate(ImmediateType::ANDI)),
-  InstPattern::new("slli", "000000? ????? ????? 001 ????? 00100 11", Instruction::Immediate(ImmediateType::SLLI)),
-  InstPattern::new("srli", "000000? ????? ????? 101 ????? 00100 11", Instruction::Immediate(ImmediateType::SRLI)),
-  InstPattern::new("srai", "010000? ????? ????? 101 ????? 00100 11", Instruction::Immediate(ImmediateType::SRAI)),
-  InstPattern::new("slti", "??????? ????? ????? 010 ????? 00100 11", Instruction::Immediate(ImmediateType::SLTI)),
-  InstPattern::new("sltiu", "??????? ????? ????? 011 ????? 00100 11", Instruction::Immediate(ImmediateType::SLTIU)),
-
-  InstPattern::new("lb", "??????? ????? ????? 000 ????? 00000 11", Instruction::Immediate(ImmediateType::LB)),
-  InstPattern::new("lh", "??????? ????? ????? 001 ????? 00000 11", Instruction::Immediate(ImmediateType::LH)),
-  InstPattern::new("lw", "??????? ????? ????? 010 ????? 00000 11", Instruction::Immediate(ImmediateType::LW)),
-  InstPattern::new("lbu", "??????? ????? ????? 100 ????? 00000 11", Instruction::Immediate(ImmediateType::LBU)),
-  InstPattern::new("lhu", "??????? ????? ????? 101 ????? 00000 11", Instruction::Immediate(ImmediateType::LHU)),
-
-  InstPattern::new("jalr", "??????? ????? ????? 000 ????? 11001 11", Instruction::Immediate(ImmediateType::JALR)),
-
-  InstPattern::new("ebreak", "0000000 00001 00000 000 00000 11100 11", Instruction::Immediate(ImmediateType::EBREAK)),
-  InstPattern::new("ecall", "0000000 00000 00000 000 00000 11100 11", Instruction::Immediate(ImmediateType::ECALL)),
-  InstPattern::new("fence", "0000??? ????? 00000 000 00000 00011 11", Instruction::Immediate(ImmediateType::FENCE)),
-
-  InstPattern::new("csrrw", "??????? ????? ????? 001 ????? 11100 11", Instruction::Immediate(ImmediateType::CSRRW)),
-  InstPattern::new("csrrs", "??????? ????? ????? 010 ????? 11100 11", Instruction::Immediate(ImmediateType::CSRRS)),
-  InstPattern::new("csrrc", "??????? ????? ????? 011 ????? 11100 11", Instruction::Immediate(ImmediateType::CSRRC)),
-  InstPattern::new("csrrwi", "??????? ????? ????? 101 ????? 11100 11", Instruction::Immediate(ImmediateType::CSRRWI)),
-  InstPattern::new("csrrsi", "??????? ????? ????? 110 ????? 11100 11", Instruction::Immediate(ImmediateType::CSRRSI)),
-  InstPattern::new("csrrci", "??????? ????? ????? 111 ????? 11100 11", Instruction::Immediate(ImmediateType::CSRRCI)),
-  // rv64I
-  InstPattern::new("lwu", "??????? ????? ????? 110 ????? 00000 11", Instruction::Immediate(ImmediateType::LWU)),
-  InstPattern::new("ld", "??????? ????? ????? 011 ????? 00000 11", Instruction::Immediate(ImmediateType::LD)),
-  InstPattern::new("addiw", "??????? ????? ????? 000 ????? 00110 11", Instruction::Immediate(ImmediateType::ADDIW)),
-  InstPattern::new("slliw", "000000? ????? ????? 001 ????? 00110 11", Instruction::Immediate(ImmediateType::SLLIW)),
-  InstPattern::new("srliw", "000000? ????? ????? 101 ????? 00110 11", Instruction::Immediate(ImmediateType::SRLIW)),
-  InstPattern::new("sraiw", "010000? ????? ????? 101 ????? 00110 11", Instruction::Immediate(ImmediateType::SRAIW)),
-
-  // Store
-  // rv32I
-  InstPattern::new("sb", "??????? ????? ????? 000 ????? 01000 11", Instruction::Store(StoreType::SB)),
-  InstPattern::new("sh", "??????? ????? ????? 001 ????? 01000 11", Instruction::Store(StoreType::SH)),
-  InstPattern::new("sw", "??????? ????? ????? 010 ????? 01000 11", Instruction::Store(StoreType::SW)),
-  // rv64I
-  InstPattern::new("sd", "??????? ????? ????? 011 ????? 01000 11", Instruction::Store(StoreType::SD)),
-  // Branch
-  // rv32I
-  InstPattern::new("beq", "??????? ????? ????? 000 ????? 11000 11", Instruction::Branch(BranchType::BEQ)),
-  InstPattern::new("bne", "??????? ????? ????? 001 ????? 11000 11", Instruction::Branch(BranchType::BNE)),
-  InstPattern::new("blt", "??????? ????? ????? 100 ????? 11000 11", Instruction::Branch(BranchType::BLT)),
-  InstPattern::new("bge", "??????? ????? ????? 101 ????? 11000 11", Instruction::Branch(BranchType::BGE)),
-  InstPattern::new("bltu", "??????? ????? ????? 110 ????? 11000 11", Instruction::Branch(BranchType::BLTU)),
-  InstPattern::new("bgeu", "??????? ????? ????? 111 ????? 11000 11", Instruction::Branch(BranchType::BGEU)),
-  // Jump
-  // rv32I
-  InstPattern::new("jal", "??????? ????? ????? ??? ????? 11011 11", Instruction::Jump(JumpType::JAL)),
-  // Upper
-  // rv32I
-  InstPattern::new("lui", "??????? ????? ????? ??? ????? 01101 11", Instruction::Upper(UpperType::LUI)),
-  InstPattern::new("auipc", "??????? ????? ????? ??? ????? 00101 11", Instruction::Upper(UpperType::AUIPC)),]
-}
diff --git a/src/instructions/rv64a.rs b/src/instructions/rv64a.rs
new file mode 100644
index 0000000..e00b18c
--- /dev/null
+++ b/src/instructions/rv64a.rs
@@ -0,0 +1,37 @@
+use super::*;
+
+#[rustfmt::skip]
+pub fn rv32a() -> Vec<InstPattern> {
+  vec![
+  InstPattern::new("lr.w", "00010?? 00000 ????? 010 ????? 01011 11", Instruction::Register(RegisterType::LR_W)),
+  InstPattern::new("sc.w", "00011?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::SC_W)),
+  InstPattern::new("amoswap.w", "00001?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::AMOSWAP_W)),
+  InstPattern::new("amoadd.w", "00000?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::AMOADD_W)),
+  InstPattern::new("amoxor.w", "00100?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::AMOXOR_W)),
+  InstPattern::new("amoand.w", "01100?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::AMOAND_W)),
+  InstPattern::new("amoor.w", "01000?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::AMOOR_W)),
+  InstPattern::new("amomin.w", "10000?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::AMOMIN_W)),
+  InstPattern::new("amomax.w", "10100?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::AMOMAX_W)),
+  InstPattern::new("amoninu.w", "11000?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::AMONINU_W)),
+  InstPattern::new("amomaxu.w", "11100?? ????? ????? 010 ????? 01011 11", Instruction::Register(RegisterType::AMOMAXU_W)),
+  ]
+}
+
+#[rustfmt::skip]
+pub fn rv64a() -> Vec<InstPattern> {
+  let mut a = vec![
+  InstPattern::new("lr.d", "00010?? 00000 ????? 011 ????? 01011 11", Instruction::Register(RegisterType::LR_D)),
+  InstPattern::new("sc.d", "00011?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::SC_D)),
+  InstPattern::new("amoswap.d", "00001?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::AMOSWAP_D)),
+  InstPattern::new("amoadd.d", "00000?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::AMOADD_D)),
+  InstPattern::new("amoxor.d", "00100?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::AMOXOR_D)),
+  InstPattern::new("amoand.d", "01100?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::AMOAND_D)),
+  InstPattern::new("amoor.d", "01000?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::AMOOR_D)),
+  InstPattern::new("amomin.d", "10000?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::AMOMIN_D)),
+  InstPattern::new("amomax.d", "10100?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::AMOMAX_D)),
+  InstPattern::new("amoninu.d", "11000?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::AMOMINU_D)),
+  InstPattern::new("amomaxu.d", "11100?? ????? ????? 011 ????? 01011 11", Instruction::Register(RegisterType::AMOMAXU_D)),
+  ];
+  a.extend(rv32a());
+  a
+}