From 42c14046b9924eb3fac4d845c50d25ce0a45dc1c Mon Sep 17 00:00:00 2001
From: Clo91eaf <Clo91eaf@qq.com>
Date: Sun, 10 Mar 2024 16:56:59 +0800
Subject: [PATCH] fix CI

---
 .github/workflows/test.yml | 8 ++++++++
 src/cpu.rs                 | 4 +---
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
index f435801..4fa4289 100644
--- a/.github/workflows/test.yml
+++ b/.github/workflows/test.yml
@@ -5,6 +5,14 @@ jobs:
     name: am-test
     runs-on: ubuntu-latest
     steps:
+    - name: checkout
+      uses: actions/checkout@master
+    - name: test
+      run: RUST_TEST_THREADS=1 cargo test --test am-tests
+  riscv-test:
+    name: riscv-test
+    runs-on: ubuntu-latest
+    steps:
     - name: checkout
       uses: actions/checkout@master
     - name: test
diff --git a/src/cpu.rs b/src/cpu.rs
index 9eb3246..17fea6a 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -1,4 +1,3 @@
-mod csr;
 mod instruction;
 pub mod memory;
 mod statistic;
@@ -17,7 +16,6 @@ use std::io::prelude::*;
 use std::io::BufReader;
 use std::path::PathBuf;
 
-use csr::CSR;
 use memory::{read_data, read_inst, write_data};
 use utils::{bits, decode_operand, match_inst, sext};
 
@@ -270,7 +268,7 @@ impl Cpu {
       Inst::Register(R::REMUW)  => {self.gpr[rd] = sext((self.gpr[rs1] as u32 % self.gpr[rs2] as u32) as usize, 64);}
       Inst::Register(R::REMW)   => {self.gpr[rd] = sext((self.gpr[rs1] as i32 % self.gpr[rs2] as i32) as usize, 32);}
 
-      Inst::Register(R::MRET)   => {self.dnpc = self.csr[CSR::MEPC as usize];}
+      // Inst::Register(R::MRET)   => {self.dnpc = self.csr[CSR::MEPC as usize];}
 
       Inst::Immediate(I::ECALL)  => {todo!();}
       Inst::Immediate(I::EBREAK) => {self.hemu_trap();}