From bf32b468e75a5e6f9768c22800c50f027e01c353 Mon Sep 17 00:00:00 2001
From: Justin Bassett <jbassett271@gmail.com>
Date: Thu, 24 Jun 2021 19:47:27 -0700
Subject: [PATCH] Add test utility to create a DataDepGraph

---
 unittests/Basic/CMakeLists.txt |   1 +
 unittests/Basic/ddg.h          |  45 +++++++++++++
 unittests/Basic/ddg_test.cpp   | 114 +++++++++++++++++++++++++++++++++
 3 files changed, 160 insertions(+)
 create mode 100644 unittests/Basic/ddg.h
 create mode 100644 unittests/Basic/ddg_test.cpp

diff --git a/unittests/Basic/CMakeLists.txt b/unittests/Basic/CMakeLists.txt
index 8009c25d..76cf3b16 100644
--- a/unittests/Basic/CMakeLists.txt
+++ b/unittests/Basic/CMakeLists.txt
@@ -5,4 +5,5 @@ add_optsched_unittest(OptSchedBasicTests
   LoggerTest.cpp
   UtilitiesTest.cpp
   simple_machine_model_test.cpp
+  ddg_test.cpp
   )
diff --git a/unittests/Basic/ddg.h b/unittests/Basic/ddg.h
new file mode 100644
index 00000000..49087de6
--- /dev/null
+++ b/unittests/Basic/ddg.h
@@ -0,0 +1,45 @@
+#ifndef OPTSCHED_TESTS_DDG_H
+#define OPTSCHED_TESTS_DDG_H
+
+#include "opt-sched/Scheduler/data_dep.h"
+#include "simple_machine_model.h"
+#include "gtest/gtest.h"
+#include <memory>
+#include <string>
+
+std::shared_ptr<llvm::opt_sched::DataDepGraph>
+makeDDG(const std::string &DDG,
+        llvm::opt_sched::MachineModel *Model = nullptr) {
+  using namespace llvm::opt_sched;
+
+  class SimpleDDG : public DataDepGraph {
+  public:
+    using DataDepGraph::DataDepGraph;
+
+    void convertSUnits(bool, bool) override {
+      FAIL() << "Unsupported operation convertSUnits()";
+    }
+    void convertRegFiles() override {
+      FAIL() << "Unsupported operation convertRegFile()";
+    }
+  };
+
+  struct DDGData {
+    std::unique_ptr<MachineModel> Model = nullptr;
+    SimpleDDG DDG;
+
+    DDGData(MachineModel *Model) : DDG(Model) {}
+    DDGData()
+        : Model(llvm::make_unique<MachineModel>(simpleMachineModel())),
+          DDG(Model.get()) {}
+  };
+
+  auto Result =
+      Model ? std::make_shared<DDGData>(Model) : std::make_shared<DDGData>();
+  auto Ret = Result->DDG.ReadFromString(DDG);
+  EXPECT_TRUE(Ret != RES_ERROR && Ret != RES_FAIL && Ret != RES_TIMEOUT)
+      << "Failed to parse DDG";
+  return std::shared_ptr<DataDepGraph>(Result, &Result->DDG);
+}
+
+#endif
diff --git a/unittests/Basic/ddg_test.cpp b/unittests/Basic/ddg_test.cpp
new file mode 100644
index 00000000..f76ffbdd
--- /dev/null
+++ b/unittests/Basic/ddg_test.cpp
@@ -0,0 +1,114 @@
+#include "ddg.h"
+
+#include "gtest/gtest.h"
+
+using namespace llvm::opt_sched;
+
+namespace {
+TEST(SimpleDDG, CanBeMade) {
+  std::shared_ptr<DataDepGraph> DDG = makeDDG(R"(
+dag 7 "Simple"
+{
+dag_id fake:3
+dag_weight 1.000000
+compiler LLVM
+dag_lb -1
+dag_ub -1
+nodes
+node 0 "Inst"
+    sched_order 0
+    issue_cycle 0
+node 1 "Inst"
+    sched_order 1
+    issue_cycle 1
+node 2 "Inst"
+    sched_order 2
+    issue_cycle 2
+node 3 "Inst"
+    sched_order 3
+    issue_cycle 3
+node 4 "Inst"
+    sched_order 4
+    issue_cycle 4
+node 5 "artificial"  "__optsched_entry"
+node 6 "artificial"
+dependencies
+dep 0 1 "other" 0
+dep 1 2 "other" 0
+dep 2 6 "other" 0
+dep 3 4 "data" 1
+dep 4 6 "other" 0
+dep 5 3 "other" 0
+dep 5 0 "other" 0
+}
+  )");
+
+  EXPECT_EQ(7, DDG->GetNodeCnt());
+}
+
+TEST(SimpleDDG, CanBeMadeWithRealData) {
+  MachineModel Model = simpleMachineModel();
+  {
+    InstTypeInfo Info;
+    Info.issuType = Model.getDefaultIssueType();
+    Info.name = "ATOMIC_FENCE";
+    Info.isCntxtDep = false;
+    Info.ltncy = 0;
+    Info.pipelined = true;
+    Info.sprtd = true;
+    Info.blksCycle = true;
+    Model.AddInstType(Info);
+
+    Info.name = "S_BARRIER";
+    Model.AddInstType(Info);
+
+    Info.name = "S_ADD_I32";
+    Info.ltncy = 1;
+    Model.AddInstType(Info);
+
+    Info.name = "S_CMP_LT_U32";
+    Info.ltncy = 1;
+    Model.AddInstType(Info);
+  }
+
+  std::shared_ptr<DataDepGraph> DDG = makeDDG(R"(
+dag 7 "Simple"
+{
+dag_id kernel_c18_sdk_94:3
+dag_weight 1.000000
+compiler LLVM
+dag_lb -1
+dag_ub -1
+nodes
+node 0 "ATOMIC_FENCE"
+    sched_order 0
+    issue_cycle 0
+node 1 "S_BARRIER"  "S_BARRIER"
+    sched_order 1
+    issue_cycle 1
+node 2 "ATOMIC_FENCE"  "ATOMIC_FENCE"
+    sched_order 2
+    issue_cycle 2
+node 3 "S_ADD_I32"  "S_ADD_I32"
+    sched_order 3
+    issue_cycle 3
+node 4 "S_CMP_LT_U32"  "S_CMP_LT_U32"
+    sched_order 4
+    issue_cycle 4
+node 5 "artificial"  "__optsched_entry"
+node 6 "artificial"
+dependencies
+dep 0 1 "other" 0
+dep 1 2 "other" 0
+dep 2 6 "other" 0
+dep 3 4 "data" 1
+dep 4 6 "other" 0
+dep 5 3 "other" 0
+dep 5 0 "other" 0
+}
+  )",
+                                              &Model);
+
+  EXPECT_EQ(7, DDG->GetNodeCnt());
+}
+} // namespace