From eae422eda6416b39a243294bc8323ecbe4bf4c97 Mon Sep 17 00:00:00 2001 From: nicolas Date: Sat, 20 Jul 2024 14:46:32 -0700 Subject: [PATCH] modified test cases --- test/tb.v | 2 +- test/test.py | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/test/tb.v b/test/tb.v index 2fc848c..4e10570 100644 --- a/test/tb.v +++ b/test/tb.v @@ -24,7 +24,7 @@ module tb (); wire [7:0] uio_oe; // Replace tt_um_example with your module name: - tt_um_example user_project ( + tt_um_COLVERTYETY_top user_project ( // Include power ports for the Gate Level test: `ifdef GL_TEST diff --git a/test/test.py b/test/test.py index 34d8d20..c8aa810 100644 --- a/test/test.py +++ b/test/test.py @@ -44,6 +44,13 @@ def shape_input(x): @cocotb.test() async def test_project(dut): + """Test the project.""" + + dataset = get_dataset() + print(dataset) + + + # Initialize the dut dut._log.info("Start") # Set the clock period to 10 us (100 KHz) @@ -70,7 +77,7 @@ async def test_project(dut): # The following assersion is just an example of how to check the output values. # Change it to match the actual expected output of your module: - assert dut.uo_out.value == 50 + # assert dut.uo_out.value == 50 # Keep testing the module by changing the input values, waiting for # one or more clock cycles, and asserting the expected output values.