How to compute the bandwidth according to the terminal output?

[huangzl19]

I'm new to the Ramulator, and I wonder how to compute the read/write bandwidth according to the output.
I use the default example_config.yaml and the example_inst.trace. The output is pasted at the end

Since total_num_read_requests = 6, then the data volume = 6 * 64B = 384B
Memory_system_cycles = 81306. It's DDR4-2400, so the clock frequency is 1.2GHz. The time used is 81306 * (1/1.2G) = 6.7755e-5s
Then the bandwidth = 384B / 6.7755e-5s = 5.67MB/s. It seems to be too slow compared to the theoretical DDR4-bandwidth.

I also try to generate long stream read trace file using the tracegen.py in ./verilog_verification/traces. Using the calculation method above, I find the memory bandwidth increase to about 5.8GB/s. However, it is still very low compared to the theorectical bandwidth of DDR4, which should be 19.2GB/s.

Therefore, my questions are:

1. how to compute the memory bandwidth?
2. If the above computation is correct, then how to make the simulation output more close to the theoretical bandwidth?

========== TERMINAL OUTPUTS ============

Frontend:
  impl: SimpleO3
  memory_access_cycles_recorded_core_0: 61
  cycles_recorded_core_0: 216815
  llc_mshr_unavailable: 0
  llc_read_misses: 37
  llc_read_access: 133336
  llc_write_misses: 8
  llc_write_access: 33334
  llc_eviction: 0
  num_expected_insts: 500000
  Translation:
    impl: RandomTranslation


MemorySystem:
  impl: GenericDRAM
  total_num_other_requests: 0
  total_num_write_requests: 0
  total_num_read_requests: 6
  memory_system_cycles: 81306
  DRAM:
    impl: DDR4
  AddrMapper:
    impl: RoBaRaCoCh


  Controller:
    impl: Generic
    id: Channel 0
    avg_read_latency_0: 46.5
    read_queue_len_avg_0: 0.00232455181
    write_queue_len_0: 0
    queue_len_0: 245
    num_other_reqs_0: 0
    num_write_reqs_0: 0
    read_latency_0: 279
    priority_queue_len_avg_0: 0.000688756059
    row_hits_0: 2
    priority_queue_len_0: 56
    row_misses_0: 4
    row_conflicts_0: 0
    read_row_misses_0: 4
    queue_len_avg_0: 0.00301330769
    read_row_conflicts_core_0: 0
    read_row_hits_0: 2
    write_queue_len_avg_0: 0
    read_row_conflicts_0: 0
    write_row_misses_0: 0
    write_row_conflicts_0: 0
    read_queue_len_0: 189
    write_row_hits_0: 0
    read_row_hits_core_0: 2
    read_row_misses_core_0: 4
    num_read_reqs_0: 6
    Scheduler:
      impl: FRFCFS
    RefreshManager:
      impl: AllBank


    RowPolicy:
      impl: ClosedRowPolicy
      num_close_reqs: 0
    ```