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Input file "readwriteaccessFirstTry3.trace" contains (the decimal are converted virtual addresses from Intel Pintool):
W 140736775976056,140736775976056
W 140736775976048,140736775976048
W 140736775976040,140736775976040
W 140736775976032,140736775976032
W 140736775976024,140736775976024
W 140736775975928,140736775975928
W 140736775975936,140736775975936
R 140189629292038,140189629292038
W 140189629292038,140189629292038
W 140189629291184,140189629291184
W 140189629287008,140189629287008
R 140189629288024,140189629288024
W 140189629291200,140189629291200
W 140189629291360,140189629291360
R 140189629288040,140189629288040
W 140189629291280,140189629291280
R 140189629288056,140189629288056
W 140189629291912,140189629291912
R 140189629288072,140189629288072
W 140189629291288,140189629291288
Greetings! I hope you are well. I am Sadman Sakib Akash, currently working as a GRA at University of Central Florida.
Regarding the problem above, I also used virtual addresses directly. Whatever the input the output is always same. what am I missing? Do I need to change anything in the code to process the input for calculating memory timing and power.
yaml file:
Frontend:
impl: ReadWriteTrace
path: /home/ssa/ramulator2/readwriteaccessFirstTry3.trace
clock_ratio: 3
Translation:
impl: RandomTranslation
max_addr: 1140736775975936
MemorySystem:
impl: GenericDRAM
clock_ratio: 3
DRAM:
impl: DDR4
org:
preset: DDR4_8Gb_x8
channel: 1
rank: 2
timing:
preset: DDR4_2400R
Controller:
impl: Generic
Scheduler:
impl: FRFCFS
RefreshManager:
impl: AllBank
RowPolicy:
impl: ClosedRowPolicy
cap: 4
plugins:
AddrMapper:
impl: RoBaRaCoCh
Input file "readwriteaccessFirstTry3.trace" contains (the decimal are converted virtual addresses from Intel Pintool):
W 140736775976056,140736775976056
W 140736775976048,140736775976048
W 140736775976040,140736775976040
W 140736775976032,140736775976032
W 140736775976024,140736775976024
W 140736775975928,140736775975928
W 140736775975936,140736775975936
R 140189629292038,140189629292038
W 140189629292038,140189629292038
W 140189629291184,140189629291184
W 140189629287008,140189629287008
R 140189629288024,140189629288024
W 140189629291200,140189629291200
W 140189629291360,140189629291360
R 140189629288040,140189629288040
W 140189629291280,140189629291280
R 140189629288056,140189629288056
W 140189629291912,140189629291912
R 140189629288072,140189629288072
W 140189629291288,140189629291288
Command: ./ramulator2 -f ./example_config.yaml
Output:
[Ramulator::ReadWriteTrace] [info] Loading trace file /home/ssa/ramulator2/readwriteaccessFirstTry3.trace ...
[Ramulator::ReadWriteTrace] [info] Loaded 20 lines.
Frontend:
impl: ReadWriteTrace
MemorySystem:
impl: GenericDRAM
total_num_other_requests: 0
total_num_write_requests: 1
total_num_read_requests: 0
memory_system_cycles: 0
DRAM:
impl: DDR4
AddrMapper:
impl: RoBaRaCoCh
Controller:
impl: Generic
id: Channel 0
avg_read_latency_0: .nan
read_queue_len_avg_0: .nan
write_queue_len_0: 0
queue_len_0: 0
num_other_reqs_0: 0
num_write_reqs_0: 1
read_latency_0: 0
priority_queue_len_avg_0: .nan
row_hits_0: 0
priority_queue_len_0: 0
row_misses_0: 0
row_conflicts_0: 0
read_row_misses_0: 0
queue_len_avg_0: .nan
read_row_conflicts_core_0: 0
read_row_hits_0: 0
write_queue_len_avg_0: .nan
read_row_conflicts_0: 0
write_row_misses_0: 0
write_row_conflicts_0: 0
read_queue_len_0: 0
write_row_hits_0: 0
read_row_hits_core_0: 0
read_row_misses_core_0: 0
num_read_reqs_0: 0
Scheduler:
impl: FRFCFS
RefreshManager:
impl: AllBank
Other files are not changed.
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