SimpleO3 front end show significant Cache bandwidth bound when doing sequential memory access test.

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Dear Author,
While conducting a single core sequential memory read-only test on LPDDR5 6400, I noticed that the system bandwidth is constrained by cache performance with all default settings, rather than by the DRAM. Only when I modify the Cache latency to 1, I can find the effect of different memory bandwidth configurations. I want to know why it happens since it is not likely to be cache bound in the real system to do such a test.